fwohci.c revision 1.5
1 /*- 2 * Copyright (c) 2000 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * IEEE1394 Open Host Controller Interface 39 * based on OHCI Specification 1.1 (January 6, 2000) 40 * The first version to support network interface part is wrtten by 41 * Atsushi Onoe <onoe (at) netbsd.org>. 42 */ 43 44 #include "opt_inet.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/socket.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/mbuf.h> 53 54 #include <machine/bus.h> 55 56 #include <dev/ieee1394/ieee1394reg.h> 57 #include <dev/ieee1394/fwohcireg.h> 58 59 #include <dev/ieee1394/ieee1394var.h> 60 #include <dev/ieee1394/fwohcivar.h> 61 62 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 63 64 #if 0 65 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 66 bus_dmamap_t *mapp, caddr_t *kvap, int flags); 67 #endif 68 69 static int fwohci_desc_alloc(struct fwohci_softc *); 70 71 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 72 int, int); 73 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 74 75 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 76 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 77 static void fwohci_buf_init(struct fwohci_softc *); 78 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 79 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_ctx *, 80 caddr_t *, int); 81 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 82 struct fwohci_pkt *); 83 84 static void fwohci_phy_busreset(struct fwohci_softc *); 85 86 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 87 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 88 void *); 89 90 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 91 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 92 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 93 94 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 95 struct fwohci_pkt *); 96 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *); 97 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 98 struct fwohci_pkt *); 99 100 static void fwohci_configrom_init(struct fwohci_softc *); 101 102 static void fwohci_selfid_init(struct fwohci_softc *); 103 static void fwohci_selfid_input(struct fwohci_softc *); 104 105 static void fwohci_csr_init(struct fwohci_softc *); 106 static int fwohci_csr_input(struct fwohci_softc *, void *, 107 struct fwohci_pkt *); 108 109 static void fwohci_uid_collect(struct fwohci_softc *); 110 static int fwohci_uid_input(struct fwohci_softc *, void *, 111 struct fwohci_pkt *); 112 static int fwohci_uid_lookup(struct fwohci_softc *, u_int8_t *); 113 114 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 115 void (*)(struct device *, struct mbuf *)); 116 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 117 static int fwohci_if_output(struct device *, struct mbuf *, 118 void (*)(struct device *, struct mbuf *)); 119 120 int 121 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 122 { 123 int i; 124 u_int32_t val; 125 #if 0 126 int error; 127 #endif 128 129 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 130 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 131 132 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_SoftReset); 133 /* 134 * Wait for reset completion 135 */ 136 for (i = 0; i < OHCI_LOOP; i++) { 137 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 138 if ((val & OHCI_HCControl_SoftReset) == 0) 139 break; 140 } 141 142 /* What dialect of OHCI is this device? 143 */ 144 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 145 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 146 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 147 148 /* Is the Global UID ROM present? 149 */ 150 if ((val & OHCI_Version_GUID_ROM) == 0) { 151 printf("\n%s: fatal: no global UID ROM\n", sc->sc_sc1394.sc1394_dev.dv_xname); 152 return -1; 153 } else { 154 155 /* Extract the Global UID 156 */ 157 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 158 sc->sc_sc1394.sc1394_guid[0] = (val >> 24) & 0xff; 159 sc->sc_sc1394.sc1394_guid[1] = (val >> 16) & 0xff; 160 sc->sc_sc1394.sc1394_guid[2] = (val >> 8) & 0xff; 161 sc->sc_sc1394.sc1394_guid[3] = (val >> 0) & 0xff; 162 163 val = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 164 sc->sc_sc1394.sc1394_guid[4] = (val >> 24) & 0xff; 165 sc->sc_sc1394.sc1394_guid[5] = (val >> 16) & 0xff; 166 sc->sc_sc1394.sc1394_guid[6] = (val >> 8) & 0xff; 167 sc->sc_sc1394.sc1394_guid[7] = (val >> 0) & 0xff; 168 } 169 170 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 171 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 172 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 173 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 174 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 175 176 /* Get the maximum link speed and receive size 177 */ 178 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 179 sc->sc_sc1394.sc1394_link_speed = 180 (val & OHCI_BusOptions_LinkSpd_MASK) 181 >> OHCI_BusOptions_LinkSpd_BITPOS; 182 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 183 printf(", %s", ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 184 } else { 185 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 186 } 187 188 /* MaxRec is encoded as log2(max_rec_octets)-1 189 */ 190 sc->sc_sc1394.sc1394_max_receive = 191 1 << (((val & OHCI_BusOptions_MaxRec_MASK) 192 >> OHCI_BusOptions_MaxRec_BITPOS) + 1); 193 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 194 195 /* 196 * Count how many isochronous ctx we have. 197 */ 198 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, 0xffffffff); 199 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 200 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, 0xffffffff); 201 for (i = 0; val != 0; val >>= 1) { 202 if (val & 0x1) 203 i++; 204 } 205 sc->sc_isoctx = i; 206 printf(", %d iso_ctx", sc->sc_isoctx); 207 208 printf("\n"); 209 210 #if 0 211 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, OHCI_CONFIG_ALIGNMENT, 212 &sc->sc_configrom_map, 213 (caddr_t *) &sc->sc_configrom, 214 BUS_DMA_WAITOK|BUS_DMA_COHERENT); 215 return error; 216 #endif 217 218 /* 219 * Enable Link Power 220 */ 221 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 222 if (fwohci_desc_alloc(sc)) 223 return -1; 224 225 /* 226 * Allocate DMA Context 227 */ 228 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 229 OHCI_CTX_ASYNC_RX_REQUEST); 230 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 231 OHCI_CTX_ASYNC_RX_RESPONSE); 232 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, OHCI_BUF_ATRQ_CNT, 233 OHCI_CTX_ASYNC_TX_REQUEST); 234 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, OHCI_BUF_ATRS_CNT, 235 OHCI_CTX_ASYNC_TX_RESPONSE); 236 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 237 M_DEVBUF, M_WAITOK); 238 for (i = 0; i < sc->sc_isoctx; i++) { 239 fwohci_ctx_alloc(sc, &sc->sc_ctx_ir[i], OHCI_BUF_IR_CNT, i); 240 sc->sc_ctx_ir[i]->fc_ppbmode = 1; 241 } 242 243 /* 244 * Allocate buffer for configuration ROM and SelfID buffer 245 */ 246 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 247 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 248 249 /* 250 * First, initilize CSRs to default settings. 251 */ 252 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 253 #if 0 254 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 255 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC; 256 #endif 257 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 258 for (i = 0; i < sc->sc_isoctx; i++) { 259 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 260 ~0); 261 } 262 fwohci_configrom_init(sc); 263 fwohci_selfid_init(sc); 264 fwohci_buf_init(sc); 265 fwohci_csr_init(sc); 266 267 /* 268 * Final CSR settings. 269 */ 270 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 271 OHCI_LinkControl_CycleSource); 272 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 273 OHCI_LinkControl_CycleTimerEnable | OHCI_LinkControl_RcvSelfID | 274 OHCI_LinkControl_RcvPhyPkt); 275 276 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 277 278 /* clear receive filter */ 279 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 280 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 281 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 282 283 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 284 OHCI_HCControl_NoByteSwapData); 285 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 286 287 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 288 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 289 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 290 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 291 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 292 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 293 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 294 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 295 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 296 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 297 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 298 config_defer(&sc->sc_sc1394.sc1394_dev, 299 (void (*)(struct device *))fwohci_phy_busreset); 300 301 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 302 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 303 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, 304 "fw", fwohci_print); 305 306 return 0; 307 } 308 309 int 310 fwohci_intr(void *arg) 311 { 312 struct fwohci_softc * const sc = arg; 313 int i; 314 int progress = 0; 315 u_int32_t intmask, iso; 316 317 for (;;) { 318 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 319 if (intmask == 0) 320 return progress; 321 #ifdef FW_DEBUG 322 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, intmask); 323 if (intmask & OHCI_Int_CycleTooLong) 324 printf(" CycleTooLong"); 325 if (intmask & OHCI_Int_UnrecoverableError) 326 printf(" UnrecoverableError"); 327 if (intmask & OHCI_Int_CycleInconsistent) 328 printf(" CycleInconsistent"); 329 if (intmask & OHCI_Int_BusReset) 330 printf(" BusReset"); 331 if (intmask & OHCI_Int_SelfIDComplete) 332 printf(" SelfIDComplete"); 333 if (intmask & OHCI_Int_LockRespErr) 334 printf(" LockRespErr"); 335 if (intmask & OHCI_Int_PostedWriteErr) 336 printf(" PostedWriteErr"); 337 if (intmask & OHCI_Int_ReqTxComplete) 338 printf(" ReqTxComplete(0x%08x)", 339 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 340 OHCI_SUBREG_ContextControlClear)); 341 if (intmask & OHCI_Int_RespTxComplete) 342 printf(" RespTxComplete(0x%08x)", 343 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 344 OHCI_SUBREG_ContextControlClear)); 345 if (intmask & OHCI_Int_ARRS) 346 printf(" ARRS(0x%08x)", 347 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 348 OHCI_SUBREG_ContextControlClear)); 349 if (intmask & OHCI_Int_ARRQ) 350 printf(" ARRQ(0x%08x)", 351 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 352 OHCI_SUBREG_ContextControlClear)); 353 if (intmask & OHCI_Int_IsochRx) 354 printf(" IsochRx"); 355 if (intmask & OHCI_Int_IsochTx) 356 printf(" IsochTx"); 357 if (intmask & OHCI_Int_RQPkt) 358 printf(" RQPkt"); 359 if (intmask & OHCI_Int_RSPkt) 360 printf(" RSPkt"); 361 printf("\n"); 362 #endif /* FW_DEBUG */ 363 if (intmask & OHCI_Int_BusReset) { 364 if (sc->sc_uidtbl != NULL) { 365 free(sc->sc_uidtbl, M_DEVBUF); 366 sc->sc_uidtbl = NULL; 367 } 368 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 369 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 370 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 371 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 372 fwohci_buf_init(sc); 373 } 374 if (intmask & OHCI_Int_SelfIDComplete) { 375 fwohci_selfid_input(sc); 376 fwohci_uid_collect(sc); 377 } 378 379 if (intmask & OHCI_Int_ReqTxComplete) 380 fwohci_at_done(sc, sc->sc_ctx_atrq); 381 if (intmask & OHCI_Int_RespTxComplete) 382 fwohci_at_done(sc, sc->sc_ctx_atrs); 383 if (intmask & OHCI_Int_RQPkt) 384 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 385 if (intmask & OHCI_Int_RSPkt) 386 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 387 388 if (intmask & OHCI_Int_IsochTx) { 389 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 390 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 391 } 392 if (intmask & OHCI_Int_IsochRx) { 393 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 394 for (i = 0; i < sc->sc_isoctx; i++) { 395 if (iso & (1 << i)) 396 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 397 } 398 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 399 } 400 401 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, intmask); 402 if (!progress) { 403 sc->sc_intrcnt.ev_count++; 404 progress = 1; 405 } 406 } 407 } 408 409 #if 0 410 static int 411 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 412 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 413 { 414 bus_dma_segment_t segs[1]; 415 int error, nsegs, steps; 416 417 steps = 0; 418 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 419 segs, 1, &nsegs, flags); 420 if (error) 421 goto cleanup; 422 423 steps = 1; 424 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 425 kvap, flags); 426 if (error) 427 goto cleanup; 428 429 if (error == 0) 430 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 431 size, flags, mapp); 432 if (error) 433 goto cleanup; 434 if (error == 0) 435 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, flags); 436 if (error) 437 goto cleanup; 438 439 cleanup: 440 switch (steps) { 441 case 1: 442 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 443 } 444 445 return error; 446 } 447 #endif 448 449 int 450 fwohci_print(void *aux, const char *pnp) 451 { 452 char *name = aux; 453 454 if (pnp) 455 printf("%s at %s", name, pnp); 456 457 return UNCONF; 458 } 459 460 /* 461 * COMMON FUNCTIONS 462 */ 463 464 /* 465 * Initiate Bus Reset 466 */ 467 static void 468 fwohci_phy_busreset(struct fwohci_softc *sc) 469 { 470 int i; 471 u_int8_t reg; 472 u_int32_t val; 473 474 reg = 1; 475 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 476 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 477 for (i = 0; i < OHCI_LOOP; i++) { 478 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 479 OHCI_PhyControl_RdDone) 480 break; 481 } 482 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 483 val = (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 484 val = (val & 0x80) | 0x40 | 0x3f; /* XXX: gap */ 485 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 486 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 487 (val << OHCI_PhyControl_WrData_BITPOS)); 488 for (i = 0; i < OHCI_LOOP; i++) { 489 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 490 OHCI_PhyControl_WrReg)) 491 break; 492 } 493 } 494 495 /* 496 * Descriptor for context DMA. 497 */ 498 static int 499 fwohci_desc_alloc(struct fwohci_softc *sc) 500 { 501 int error; 502 503 /* 504 * allocate descriptor buffer 505 */ 506 507 sc->sc_descsize = sizeof(struct fwohci_desc) * 508 (OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 509 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 510 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2); 511 512 if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_descsize, 513 OHCI_PAGE_SIZE, 0, &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 514 printf("%s: unable to allocate descriptor buffer, error = %d\n", 515 sc->sc_sc1394.sc1394_dev.dv_xname, error); 516 goto fail_0; 517 } 518 519 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 520 sc->sc_descsize, &sc->sc_desc, BUS_DMA_COHERENT)) != 0) { 521 printf("%s: unable to map descriptor buffer, error = %d\n", 522 sc->sc_sc1394.sc1394_dev.dv_xname, error); 523 goto fail_1; 524 } 525 526 if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_descsize, 527 sc->sc_dnseg, sc->sc_descsize, 0, 0, &sc->sc_ddmamap)) != 0) { 528 printf("%s: unable to create descriptor buffer DMA map, " 529 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 530 goto fail_2; 531 } 532 533 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 534 sc->sc_descsize, NULL, 0)) != 0) { 535 printf("%s: unable to load descriptor buffer DMA map, " 536 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 537 goto fail_3; 538 } 539 540 return 0; 541 542 fail_3: 543 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 544 fail_2: 545 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, sc->sc_descsize); 546 fail_1: 547 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 548 fail_0: 549 return error; 550 } 551 552 /* 553 * Asyncronous/Isochronous Transmit/Receive Context 554 */ 555 static int 556 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 557 int bufcnt, int ctx) 558 { 559 int i, error; 560 struct fwohci_ctx *fc; 561 struct fwohci_buf *fb; 562 struct fwohci_desc *fd; 563 564 fc = malloc(sizeof(*fc) + sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK); 565 memset(fc, 0, sizeof(*fc) + sizeof(*fb) * bufcnt); 566 LIST_INIT(&fc->fc_handler); 567 TAILQ_INIT(&fc->fc_buf); 568 TAILQ_INIT(&fc->fc_busy); 569 fc->fc_ctx = ctx; 570 fc->fc_bufcnt = bufcnt; 571 fb = (struct fwohci_buf *)&fc[1]; 572 for (i = 0; i < bufcnt; i++, fb++) { 573 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 574 goto fail; 575 fd = (struct fwohci_desc *)sc->sc_desc + sc->sc_descfree++; 576 fb->fb_desc = fd; 577 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 578 ((caddr_t)fd - sc->sc_desc); 579 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 580 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 581 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 582 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 583 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 584 } 585 *fcp = fc; 586 return 0; 587 588 fail: 589 while (i-- > 0) 590 fwohci_buf_free(sc, --fb); 591 free(fc, M_DEVBUF); 592 return error; 593 } 594 595 static void 596 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 597 { 598 struct fwohci_buf *fb, *nfb; 599 struct fwohci_desc *fd; 600 601 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 602 nfb = TAILQ_NEXT(fb, fb_list); 603 fb->fb_off = 0; 604 fd = fb->fb_desc; 605 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 606 fd->fd_rescount = fd->fd_reqcount; 607 } 608 } 609 610 /* 611 * DMA data buffer 612 */ 613 static int 614 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 615 { 616 int error; 617 618 if ((error = bus_dmamem_alloc(sc->sc_dmat, OHCI_PAGE_SIZE, 619 OHCI_PAGE_SIZE, 0, &fb->fb_seg, 1, &fb->fb_nseg, 0)) != 0) { 620 printf("%s: unable to allocate buffer, error = %d\n", 621 sc->sc_sc1394.sc1394_dev.dv_xname, error); 622 goto fail_0; 623 } 624 625 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 626 fb->fb_nseg, OHCI_PAGE_SIZE, &fb->fb_buf, 0)) != 0) { 627 printf("%s: unable to map buffer, error = %d\n", 628 sc->sc_sc1394.sc1394_dev.dv_xname, error); 629 goto fail_1; 630 } 631 632 if ((error = bus_dmamap_create(sc->sc_dmat, OHCI_PAGE_SIZE, 633 fb->fb_nseg, OHCI_PAGE_SIZE, 0, 0, &fb->fb_dmamap)) != 0) { 634 printf("%s: unable to create buffer DMA map, " 635 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 636 error); 637 goto fail_2; 638 } 639 640 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 641 fb->fb_buf, OHCI_PAGE_SIZE, NULL, 0)) != 0) { 642 printf("%s: unable to load buffer DMA map, " 643 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 644 error); 645 goto fail_3; 646 } 647 648 return 0; 649 650 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 651 fail_3: 652 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 653 fail_2: 654 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, OHCI_PAGE_SIZE); 655 fail_1: 656 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 657 fail_0: 658 return error; 659 } 660 661 static void 662 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 663 { 664 665 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 666 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 667 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, OHCI_PAGE_SIZE); 668 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 669 } 670 671 static void 672 fwohci_buf_init(struct fwohci_softc *sc) 673 { 674 int i; 675 struct fwohci_buf *fb; 676 677 /* 678 * Stop the transmitter and receiver. 679 */ 680 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 681 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 682 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 683 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 684 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 685 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 686 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 687 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 688 for (i = 0; i < sc->sc_isoctx; i++) { 689 OHCI_SYNC_RX_DMA_WRITE(sc, i, 690 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 691 } 692 693 /* 694 * Initialize for Asynchronous Transmit Request. 695 */ 696 while ((fb = TAILQ_FIRST(&sc->sc_ctx_atrq->fc_busy)) != NULL) { 697 TAILQ_REMOVE(&sc->sc_ctx_atrq->fc_busy, fb, fb_list); 698 if (fb->fb_m != NULL) { 699 if (fb->fb_callback != NULL) { 700 (*fb->fb_callback) 701 (sc->sc_sc1394.sc1394_if, fb->fb_m); 702 fb->fb_callback = NULL; 703 } else 704 m_freem(fb->fb_m); 705 fb->fb_m = NULL; 706 } 707 TAILQ_INSERT_TAIL(&sc->sc_ctx_atrq->fc_buf, fb, fb_list); 708 } 709 sc->sc_ctx_atrq->fc_branch = NULL; 710 711 /* 712 * Initialize for Asynchronous Transmit Response. 713 */ 714 while ((fb = TAILQ_FIRST(&sc->sc_ctx_atrs->fc_busy)) != NULL) { 715 TAILQ_REMOVE(&sc->sc_ctx_atrs->fc_busy, fb, fb_list); 716 if (fb->fb_m != NULL) { 717 if (fb->fb_callback != NULL) { 718 (*fb->fb_callback) 719 (sc->sc_sc1394.sc1394_if, fb->fb_m); 720 fb->fb_callback = NULL; 721 } else 722 m_freem(fb->fb_m); 723 fb->fb_m = NULL; 724 } 725 TAILQ_INSERT_TAIL(&sc->sc_ctx_atrs->fc_buf, fb, fb_list); 726 } 727 sc->sc_ctx_atrq->fc_branch = NULL; 728 729 /* 730 * Initialize for Asynchronous Receive Request. 731 */ 732 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 733 fb = TAILQ_FIRST(&sc->sc_ctx_arrq->fc_buf); 734 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 735 OHCI_SUBREG_CommandPtr, fb->fb_daddr | 1); 736 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 737 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 738 739 /* 740 * Initialize for Asynchronous Receive Response. 741 */ 742 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 743 fb = TAILQ_FIRST(&sc->sc_ctx_arrs->fc_buf); 744 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 745 OHCI_SUBREG_CommandPtr, fb->fb_daddr | 1); 746 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 747 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 748 749 /* 750 * Initialize for Isochronous Receive. 751 */ 752 for (i = 0; i < sc->sc_isoctx; i++) { 753 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 754 fb = TAILQ_FIRST(&sc->sc_ctx_ir[i]->fc_buf); 755 OHCI_SYNC_RX_DMA_WRITE(sc, 0, OHCI_SUBREG_CommandPtr, 756 fb->fb_daddr | 1); 757 OHCI_SYNC_RX_DMA_WRITE(sc, 0, OHCI_SUBREG_ContextControlClear, 758 OHCI_CTXCTL_RX_BUFFER_FILL | 759 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 760 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 761 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 762 OHCI_SYNC_RX_DMA_WRITE(sc, 0, OHCI_SUBREG_ContextControlSet, 763 OHCI_CTXCTL_RX_ISOCH_HEADER); 764 if (LIST_FIRST(&sc->sc_ctx_ir[i]->fc_handler) != NULL) { 765 OHCI_SYNC_RX_DMA_WRITE(sc, i, 766 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 767 } 768 } 769 } 770 771 static void 772 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 773 { 774 struct fwohci_buf *fb, *tfb; 775 776 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 777 if (fb->fb_off != fb->fb_desc->fd_reqcount || 778 fb->fb_desc->fd_rescount != 0) 779 break; 780 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 781 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 782 fb->fb_off = 0; 783 fb->fb_desc->fd_branch = 0; 784 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 785 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 786 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 787 } 788 } 789 790 static int 791 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_ctx *fc, caddr_t *pp, 792 int len) 793 { 794 struct fwohci_buf *fb; 795 struct fwohci_desc *fd; 796 int bufend; 797 798 fb = TAILQ_FIRST(&fc->fc_buf); 799 again: 800 fd = fb->fb_desc; 801 #ifdef FW_DEBUG 802 printf("fwohci_buf_pktget: desc %d, off %d, req %d, res %d\n", fd - (struct fwohci_desc *)sc->sc_desc, fb->fb_off, fd->fd_reqcount, fd->fd_rescount); 803 #endif 804 bufend = fd->fd_reqcount - fd->fd_rescount; 805 if (fb->fb_off >= bufend) { 806 if (fc->fc_ppbmode && fb->fb_off > 0) { 807 fb->fb_off = fd->fd_reqcount; 808 fd->fd_rescount = 0; 809 } 810 if (fd->fd_rescount == 0) { 811 if ((fb = TAILQ_NEXT(fb, fb_list)) != NULL) 812 goto again; 813 } 814 return 0; 815 } 816 if (fb->fb_off + len > bufend) 817 len = bufend - fb->fb_off; 818 *pp = fb->fb_buf + fb->fb_off; 819 fb->fb_off += roundup(len, 4); 820 return len; 821 } 822 823 static int 824 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 825 struct fwohci_pkt *pkt) 826 { 827 caddr_t p; 828 int len, count, i; 829 830 /* get first quadlet */ 831 count = 4; 832 if (fc->fc_ppbmode) { 833 /* 834 * get trailer first, may be bogus data unless status update 835 * in descriptor is set. 836 */ 837 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 838 sizeof(pkt->fp_trail)); 839 if (len <= 0) 840 return 0; 841 } 842 len = fwohci_buf_pktget(sc, fc, &p, count); 843 if (len <= 0) { 844 #ifdef FW_DEBUG 845 printf("fwohci_buf_input: no input\n"); 846 #endif 847 return 0; 848 } 849 pkt->fp_hdr[0] = *(u_int32_t *)p; 850 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 851 switch (pkt->fp_tcode) { 852 case IEEE1394_TCODE_WRITE_REQ_QUAD: 853 case IEEE1394_TCODE_READ_RESP_QUAD: 854 pkt->fp_hlen = 12; 855 pkt->fp_dlen = 4; 856 break; 857 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 858 case IEEE1394_TCODE_READ_RESP_BLOCK: 859 case IEEE1394_TCODE_LOCK_REQ: 860 case IEEE1394_TCODE_LOCK_RESP: 861 pkt->fp_hlen = 16; 862 break; 863 case IEEE1394_TCODE_STREAM_DATA: 864 pkt->fp_hlen = 4; 865 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 866 break; 867 default: 868 pkt->fp_hlen = 12; 869 pkt->fp_dlen = 0; 870 break; 871 } 872 873 /* get header */ 874 while (count < pkt->fp_hlen) { 875 len = fwohci_buf_pktget(sc, fc, &p, pkt->fp_hlen - count); 876 if (len == 0) { 877 printf("fwohci_buf_input: malformed input 1: %d\n", 878 pkt->fp_hlen - count); 879 return 0; 880 } 881 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 882 count += len; 883 } 884 if (pkt->fp_hlen == 16) 885 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 886 #ifdef FW_DEBUG 887 printf("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 888 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 889 #endif 890 891 /* get data */ 892 count = 0; 893 i = 0; 894 while (count < pkt->fp_dlen) { 895 len = fwohci_buf_pktget(sc, fc, 896 (caddr_t *)&pkt->fp_iov[i].iov_base, 897 pkt->fp_dlen - count); 898 if (len == 0) { 899 printf("fwohci_buf_input: malformed input 2: %d\n", 900 pkt->fp_hlen - count); 901 return 0; 902 } 903 pkt->fp_iov[i++].iov_len = len; 904 count += len; 905 } 906 907 if (!fc->fc_ppbmode) { 908 /* get trailer */ 909 len = fwohci_buf_pktget(sc, fc, (caddr_t *)&pkt->fp_trail, 910 sizeof(pkt->fp_trail)); 911 if (len <= 0) { 912 printf("fwohci_buf_input: malformed input 3: %d\n", 913 pkt->fp_hlen - count); 914 return 0; 915 } 916 } 917 return 1; 918 } 919 920 static int 921 fwohci_handler_set(struct fwohci_softc *sc, 922 int tcode, u_int32_t key1, u_int32_t key2, 923 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 924 void *arg) 925 { 926 struct fwohci_ctx *fc; 927 struct fwohci_handler *fh; 928 int i; 929 930 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 931 for (i = 0; ; i++) { 932 if (i == sc->sc_isoctx) { 933 /* no more free ctx */ 934 return ENOMEM; 935 } 936 fc = sc->sc_ctx_ir[i]; 937 fh = LIST_FIRST(&fc->fc_handler); 938 if (fh == NULL) 939 break; 940 if (fh->fh_tcode == tcode && fh->fh_key1 == key1 && 941 fh->fh_key2 == key2) 942 break; 943 } 944 } else { 945 switch (tcode) { 946 case IEEE1394_TCODE_WRITE_REQ_QUAD: 947 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 948 case IEEE1394_TCODE_READ_REQ_QUAD: 949 case IEEE1394_TCODE_READ_REQ_BLOCK: 950 case IEEE1394_TCODE_LOCK_REQ: 951 fc = sc->sc_ctx_arrq; 952 break; 953 case IEEE1394_TCODE_WRITE_RESP: 954 case IEEE1394_TCODE_READ_RESP_QUAD: 955 case IEEE1394_TCODE_READ_RESP_BLOCK: 956 case IEEE1394_TCODE_LOCK_RESP: 957 fc = sc->sc_ctx_arrs; 958 break; 959 default: 960 return EIO; 961 } 962 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 963 fh = LIST_NEXT(fh, fh_list)) { 964 if (fh->fh_tcode == tcode && fh->fh_key1 == key1 && 965 fh->fh_key2 == key2) 966 break; 967 } 968 } 969 if (handler == NULL) { 970 if (fh != NULL) 971 LIST_REMOVE(fh, fh_list); 972 return 0; 973 } 974 if (fh == NULL) { 975 fh = malloc(sizeof(*fh), M_DEVBUF, M_NOWAIT); 976 if (fh == NULL) 977 return ENOMEM; 978 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 979 } 980 fh->fh_tcode = tcode; 981 fh->fh_key1 = key1; 982 fh->fh_key2 = key2; 983 fh->fh_handler = handler; 984 fh->fh_handarg = arg; 985 986 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 987 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextMatch, 988 (OHCI_CTXMATCH_TAG0 << key2) | key1); 989 } 990 return 0; 991 } 992 993 /* 994 * Asyncronous Receive Requests input frontend. 995 */ 996 static void 997 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 998 { 999 int rcode; 1000 u_int32_t key1, key2; 1001 struct fwohci_handler *fh; 1002 struct fwohci_pkt pkt, res; 1003 1004 while (fwohci_buf_input(sc, fc, &pkt)) { 1005 key1 = pkt.fp_hdr[1] & 0xffff; 1006 key2 = pkt.fp_hdr[2]; 1007 memset(&res, 0, sizeof(res)); 1008 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1009 fh = LIST_NEXT(fh, fh_list)) { 1010 if (pkt.fp_tcode == fh->fh_tcode && 1011 key1 == fh->fh_key1 && 1012 key2 == fh->fh_key2) { 1013 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1014 &pkt); 1015 break; 1016 } 1017 } 1018 if (fh == NULL) { 1019 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1020 #ifdef FW_DEBUG 1021 printf("fwohci_arrq_input: no listener: tcode 0x%x, " 1022 "addr=0x%04x %08x\n", pkt.fp_tcode, 1023 key1, key2); 1024 #endif 1025 } 1026 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1027 OHCI_CTXCTL_EVENT_ACK_PENDING) 1028 continue; 1029 if (rcode != -1) 1030 fwohci_atrs_output(sc, rcode, &pkt, &res); 1031 } 1032 fwohci_buf_next(sc, fc); 1033 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1034 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1035 } 1036 1037 /* 1038 * Asynchronous Receive Response input frontend. 1039 */ 1040 static void 1041 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1042 { 1043 struct fwohci_pkt pkt; 1044 struct fwohci_handler *fh; 1045 u_int16_t srcid; 1046 int rcode, tlabel; 1047 1048 while (fwohci_buf_input(sc, fc, &pkt)) { 1049 srcid = pkt.fp_hdr[1] >> 16; 1050 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1051 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1052 #ifdef FW_DEBUG 1053 printf("fwohci_arrs_input: tcode 0x%x, from 0x%04x, tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1054 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, pkt.fp_dlen); 1055 #endif 1056 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1057 fh = LIST_NEXT(fh, fh_list)) { 1058 if (pkt.fp_tcode == fh->fh_tcode && 1059 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1060 tlabel == fh->fh_key2) { 1061 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1062 LIST_REMOVE(fh, fh_list); 1063 free(fh, M_DEVBUF); 1064 break; 1065 } 1066 } 1067 #ifdef FW_DEBUG 1068 if (fh == NULL) 1069 printf("fwohci_arrs_input: no lister\n"); 1070 #endif 1071 } 1072 fwohci_buf_next(sc, fc); 1073 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1074 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1075 } 1076 1077 /* 1078 * Isochronous Receive input frontend. 1079 */ 1080 static void 1081 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1082 { 1083 int rcode, chan, tag; 1084 struct iovec *iov; 1085 struct fwohci_handler *fh; 1086 struct fwohci_pkt pkt; 1087 1088 while (fwohci_buf_input(sc, fc, &pkt)) { 1089 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1090 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1091 #ifdef FW_DEBUG 1092 printf("fwohci_ir_input: hdr 0x%08x, tcode %d, hlen %d, dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, pkt.fp_dlen); 1093 #endif 1094 if (tag == IEEE1394_TAG_GASP) { 1095 /* 1096 * The pkt with tag=3 is GASP format. 1097 * Move GASP header to header part. 1098 */ 1099 if (pkt.fp_dlen < 8) 1100 continue; 1101 iov = pkt.fp_iov; 1102 /* assuming pkt per buffer mode */ 1103 memcpy(pkt.fp_hdr + 1, iov->iov_base, 8); 1104 iov->iov_base = (caddr_t)iov->iov_base + 8; 1105 iov->iov_len -= 8; 1106 pkt.fp_hlen += 8; 1107 pkt.fp_dlen -= 8; 1108 } 1109 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1110 fh = LIST_NEXT(fh, fh_list)) { 1111 if (pkt.fp_tcode == fh->fh_tcode && 1112 chan == fh->fh_key1 && tag == fh->fh_key2) { 1113 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1114 &pkt); 1115 break; 1116 } 1117 } 1118 #ifdef FW_DEBUG 1119 if (fh == NULL) 1120 printf("fwohci_ir_input: no handler\n"); 1121 else 1122 printf("fwohci_ir_input: rcode %d\n", rcode); 1123 #endif 1124 } 1125 fwohci_buf_next(sc, fc); 1126 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet, 1127 OHCI_CTXCTL_WAKE); 1128 } 1129 1130 /* 1131 * Asynchronous Transmit common routine. 1132 */ 1133 static int 1134 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1135 struct fwohci_pkt *pkt) 1136 { 1137 struct fwohci_buf *fb, *nfb; 1138 struct fwohci_desc *fd; 1139 struct iovec *iov; 1140 int i, ndesc; 1141 u_int32_t val; 1142 1143 #ifdef FW_DEBUG 1144 printf("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1145 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen); 1146 for (i = 0; i < pkt->fp_hlen/4; i++) 1147 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1148 printf("$"); 1149 for (ndesc = 0, iov = pkt->fp_iov; ndesc < pkt->fp_iovcnt; ndesc++, iov++) { 1150 for (i = 0; i < iov->iov_len; i++) 1151 printf("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1152 ((u_int8_t *)iov->iov_base)[i]); 1153 printf("$"); 1154 } 1155 printf("\n"); 1156 #endif 1157 1158 ndesc = 2 + pkt->fp_iovcnt; 1159 if (ndesc > 8) 1160 return ENOBUFS; 1161 1162 fb = TAILQ_FIRST(&fc->fc_buf); 1163 if (fb == NULL) 1164 return ENOBUFS; 1165 for (i = 1, fb = TAILQ_FIRST(&fc->fc_buf); i < ndesc; i++, fb = nfb) { 1166 nfb = TAILQ_NEXT(fb, fb_list); 1167 if (nfb == NULL) 1168 return ENOBUFS; 1169 if (nfb->fb_desc != fb->fb_desc + 1) { 1170 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != nfb) { 1171 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1172 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1173 } 1174 break; 1175 } 1176 } 1177 1178 fb = TAILQ_FIRST(&fc->fc_buf); 1179 fd = fb->fb_desc; 1180 fd->fd_flags = OHCI_DESC_IMMED; 1181 fd->fd_reqcount = pkt->fp_hlen; 1182 fd->fd_data = 0; 1183 fd->fd_branch = 0; 1184 fd->fd_status = 0; 1185 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1186 i = 3; /* XXX: 3 sec */ 1187 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1188 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1189 ((((val >> 25) + i) & 0x7) << 13); 1190 } else 1191 fd->fd_timestamp = 0; 1192 fb = TAILQ_NEXT(fb, fb_list); 1193 memcpy(fb->fb_desc, pkt->fp_hdr, pkt->fp_hlen); 1194 for (i = 0, iov = pkt->fp_iov; i < pkt->fp_iovcnt; i++, iov++) { 1195 fb = TAILQ_NEXT(fb, fb_list); 1196 memcpy(fb->fb_buf, iov->iov_base, iov->iov_len); /*XXX*/ 1197 fd = fb->fb_desc; 1198 fd->fd_flags = 0; 1199 fd->fd_reqcount = iov->iov_len; 1200 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1201 fd->fd_branch = 0; 1202 fd->fd_status = 0; 1203 fd->fd_timestamp = 0; 1204 } 1205 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1206 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1207 /* hang mbuf on the last buffer */ 1208 fb->fb_m = pkt->fp_m; 1209 fb->fb_callback = pkt->fp_callback; 1210 1211 fb = TAILQ_FIRST(&fc->fc_buf); 1212 #ifdef FW_DEBUG 1213 printf("fwohci_at_output: desc %d", fb->fb_desc - (struct fwohci_desc *)sc->sc_desc); 1214 for (i = 0; i < ndesc * 4; i++) 1215 printf("%s%08x", i&7?" ":"\n\t", ((u_int32_t *)fb->fb_desc)[i]); 1216 printf("\n"); 1217 #endif 1218 1219 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1220 OHCI_SUBREG_ContextControlClear); 1221 1222 if (val & OHCI_CTXCTL_RUN) { 1223 if (fc->fc_branch == NULL) { 1224 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1225 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1226 goto run; 1227 } 1228 *fc->fc_branch = fb->fb_daddr | ndesc; 1229 if ((val & OHCI_CTXCTL_ACTIVE) == 0) 1230 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1231 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1232 } else { 1233 run: 1234 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1235 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1236 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1237 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1238 } 1239 fc->fc_branch = &fd->fd_branch; 1240 1241 for (i = 0; i < ndesc; i++) { 1242 fb = TAILQ_FIRST(&fc->fc_buf); 1243 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1244 TAILQ_INSERT_TAIL(&fc->fc_busy, fb, fb_list); 1245 } 1246 return 0; 1247 } 1248 1249 static void 1250 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1251 { 1252 struct fwohci_buf *fb, *lfb; 1253 1254 while ((fb = TAILQ_FIRST(&fc->fc_busy)) != NULL) { 1255 for (lfb = fb; lfb != NULL; lfb = TAILQ_NEXT(lfb, fb_list)) { 1256 #ifdef FW_DEBUG 1257 printf("fwohci_at_done: desc %d, %08x %08x %08x %08x\n", 1258 lfb->fb_desc - (struct fwohci_desc *)sc->sc_desc, 1259 ((u_int32_t *)lfb->fb_desc)[0], 1260 ((u_int32_t *)lfb->fb_desc)[1], 1261 ((u_int32_t *)lfb->fb_desc)[2], 1262 ((u_int32_t *)lfb->fb_desc)[3]); 1263 #endif 1264 if (lfb->fb_desc->fd_flags & OHCI_DESC_LAST) 1265 break; 1266 } 1267 if (lfb == NULL) { 1268 printf("fwohci_at_done: last not found\n"); 1269 break; 1270 } 1271 if (!(lfb->fb_desc->fd_status & OHCI_CTXCTL_ACTIVE)) 1272 break; 1273 if (lfb->fb_desc->fd_flags & OHCI_DESC_IMMED) 1274 lfb = TAILQ_NEXT(lfb, fb_list); 1275 do { 1276 fb = TAILQ_FIRST(&fc->fc_busy); 1277 TAILQ_REMOVE(&fc->fc_busy, fb, fb_list); 1278 if (fb->fb_m != NULL) { 1279 if (fb->fb_callback != NULL) { 1280 (*fb->fb_callback) 1281 (sc->sc_sc1394.sc1394_if, fb->fb_m); 1282 fb->fb_callback = NULL; 1283 } else { 1284 m_freem(fb->fb_m); 1285 } 1286 fb->fb_m = NULL; 1287 } 1288 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1289 } while (fb != lfb); 1290 } 1291 } 1292 1293 /* 1294 * Asynchronous Transmit Reponse -- in response of request packet. 1295 */ 1296 static void 1297 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 1298 struct fwohci_pkt *res) 1299 { 1300 int i; 1301 1302 if (((*req->fp_trail & 0x001f0000) >> 16) != 1303 OHCI_CTXCTL_EVENT_ACK_PENDING) 1304 return; 1305 1306 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 1307 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 1308 switch (req->fp_tcode) { 1309 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1310 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1311 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 1312 res->fp_hlen = 12; 1313 break; 1314 case IEEE1394_TCODE_READ_REQ_QUAD: 1315 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 1316 res->fp_hlen = 16; 1317 res->fp_dlen = 0; 1318 if (res->fp_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 1319 res->fp_hdr[3] = 1320 *(u_int32_t *)res->fp_iov[0].iov_base; 1321 res->fp_iovcnt = 0; 1322 break; 1323 case IEEE1394_TCODE_READ_REQ_BLOCK: 1324 case IEEE1394_TCODE_LOCK_REQ: 1325 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 1326 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 1327 else 1328 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 1329 res->fp_hlen = 16; 1330 res->fp_dlen = 0; 1331 for (i = 0; i < res->fp_iovcnt; i++) 1332 res->fp_dlen += res->fp_iov[i].iov_len; 1333 res->fp_hdr[3] = res->fp_dlen << 16; 1334 break; 1335 } 1336 res->fp_hdr[0] |= (res->fp_tcode << 4); 1337 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 1338 } 1339 1340 /* 1341 * APPLICATION LAYER SERVICES 1342 */ 1343 1344 /* 1345 * Initialization for Configuration ROM (no DMA context) 1346 */ 1347 1348 #define CFR_MAXUNIT 20 1349 1350 struct configromctx { 1351 u_int32_t *ptr; 1352 int curunit; 1353 struct { 1354 u_int32_t *start; 1355 int length; 1356 u_int32_t *refer; 1357 int refunit; 1358 } unit[CFR_MAXUNIT]; 1359 }; 1360 1361 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 1362 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 1363 1364 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 1365 1366 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 1367 1368 #define CFR_PUT_CRC(cfr, n) \ 1369 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 1370 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 1371 1372 #define CFR_START_UNIT(cfr, n) \ 1373 do { \ 1374 if ((cfr)->unit[n].refer != NULL) { \ 1375 *(cfr)->unit[n].refer |= \ 1376 (cfr)->ptr - (cfr)->unit[n].refer; \ 1377 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 1378 } \ 1379 (cfr)->curunit = (n); \ 1380 (cfr)->unit[n].start = (cfr)->ptr++; \ 1381 } while (0 /* CONSTCOND */) 1382 1383 #define CFR_PUT_REFER(cfr, key, n) \ 1384 do { \ 1385 (cfr)->unit[n].refer = (cfr)->ptr; \ 1386 (cfr)->unit[n].refunit = (cfr)->curunit; \ 1387 *(cfr)->ptr++ = (key) << 24; \ 1388 } while (0 /* CONSTCOND */) 1389 1390 #define CFR_END_UNIT(cfr) \ 1391 do { \ 1392 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 1393 ((cfr)->unit[(cfr)->curunit].start + 1); \ 1394 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 1395 } while (0 /* CONSTCOND */) 1396 1397 static u_int16_t 1398 fwohci_crc16(u_int32_t *ptr, int len) 1399 { 1400 int shift; 1401 u_int32_t crc, sum, data; 1402 1403 crc = 0; 1404 while (len-- > 0) { 1405 data = *ptr++; 1406 for (shift = 28; shift >= 0; shift -= 4) { 1407 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 1408 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 1409 } 1410 crc &= 0xffff; 1411 } 1412 return crc; 1413 } 1414 1415 static void 1416 fwohci_configrom_init(struct fwohci_softc *sc) 1417 { 1418 int i; 1419 struct fwohci_buf *fb; 1420 u_int32_t *hdr; 1421 struct configromctx cfr; 1422 1423 fb = &sc->sc_buf_cnfrom; 1424 memset(&cfr, 0, sizeof(cfr)); 1425 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 1426 1427 /* headers */ 1428 CFR_START_UNIT(&cfr, 0); 1429 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 1430 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 1431 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 1432 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 1433 CFR_END_UNIT(&cfr); 1434 /* copy info_length from crc_length */ 1435 *hdr |= (*hdr & 0x00ff0000) << 8; 1436 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 1437 1438 /* root directory */ 1439 CFR_START_UNIT(&cfr, 1); 1440 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 1441 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 1442 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 1443 /* spt,64,fix,lst,drq */ 1444 #ifdef INET 1445 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 1446 #endif /* INET */ 1447 #ifdef INET6 1448 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 1449 #endif /* INET6 */ 1450 CFR_END_UNIT(&cfr); 1451 1452 CFR_START_UNIT(&cfr, 2); 1453 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1454 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1455 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 1456 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 1457 CFR_END_UNIT(&cfr); 1458 1459 #ifdef INET 1460 /* IPv4 unit directory */ 1461 CFR_START_UNIT(&cfr, 3); 1462 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1463 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 1464 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1465 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 1466 CFR_END_UNIT(&cfr); 1467 1468 CFR_START_UNIT(&cfr, 6); 1469 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1470 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1471 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1472 CFR_END_UNIT(&cfr); 1473 1474 CFR_START_UNIT(&cfr, 7); 1475 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1476 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1477 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 1478 CFR_END_UNIT(&cfr); 1479 #endif /* INET */ 1480 1481 #ifdef INET6 1482 /* IPv6 unit directory */ 1483 CFR_START_UNIT(&cfr, 4); 1484 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 1485 CFR_PUT_REFER(&cfr, 0x81, 8); /* textual descriptor offset */ 1486 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 1487 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 1488 CFR_END_UNIT(&cfr); 1489 1490 CFR_START_UNIT(&cfr, 8); 1491 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1492 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 1493 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 1494 CFR_END_UNIT(&cfr); 1495 1496 CFR_START_UNIT(&cfr, 9); 1497 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 1498 CFR_PUT_DATA1(&cfr, 0); 1499 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 1500 CFR_END_UNIT(&cfr); 1501 #endif /* INET6 */ 1502 1503 #ifdef FW_DEBUG 1504 printf("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname); 1505 for (i = 0; i < cfr.ptr - hdr; i++) 1506 printf("%s%08x", i&7?" ":"\n ", hdr[i]); 1507 printf("\n"); 1508 #endif /* FW_DEBUG */ 1509 1510 /* 1511 * Make network byte order for DMA 1512 */ 1513 for (i = 0; i < cfr.ptr - hdr; i++) 1514 NTOHL(hdr[i]); 1515 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 1516 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 1517 1518 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 1519 fb->fb_dmamap->dm_segs[0].ds_addr); 1520 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_BIBImageValid); 1521 } 1522 1523 /* 1524 * SelfID buffer (no DMA context) 1525 */ 1526 static void 1527 fwohci_selfid_init(struct fwohci_softc *sc) 1528 { 1529 struct fwohci_buf *fb; 1530 1531 fb = &sc->sc_buf_selfid; 1532 memset(fb->fb_buf, 0, OHCI_PAGE_SIZE); 1533 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, OHCI_PAGE_SIZE, 1534 BUS_DMASYNC_PREREAD); 1535 1536 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 1537 fb->fb_dmamap->dm_segs[0].ds_addr); 1538 } 1539 1540 static void 1541 fwohci_selfid_input(struct fwohci_softc *sc) 1542 { 1543 int i; 1544 u_int32_t count, val; 1545 u_int32_t *buf; 1546 1547 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 1548 if (val & OHCI_SelfID_Error) { 1549 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 1550 return; 1551 } 1552 count = (val & OHCI_SelfID_Size_MASK) >> OHCI_SelfID_Size_BITPOS; 1553 1554 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 1555 0, count << 2, BUS_DMASYNC_POSTREAD); 1556 1557 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 1558 if ((val & OHCI_SelfID_Gen_MASK) != (*buf & OHCI_SelfID_Gen_MASK)) { 1559 printf("%s: SelfID Gen mismatch (%d, %d)\n", 1560 sc->sc_sc1394.sc1394_dev.dv_xname, 1561 (val & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS, 1562 (*buf & OHCI_SelfID_Gen_MASK) >> OHCI_SelfID_Gen_BITPOS); 1563 return; 1564 } 1565 1566 #ifdef FW_DEBUG 1567 printf("\n%s: SelfID:", sc->sc_sc1394.sc1394_dev.dv_xname); 1568 for (i = 0; i < count; i++) 1569 printf("%s%08x", i&7?" ":"\n ", buf[i]); 1570 printf("\n"); 1571 #endif /* FW_DEBUG */ 1572 1573 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 1574 for (i = 1; i < count; i += 2) { 1575 if (buf[i] != ~buf[i + 1]) { 1576 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 1577 sc->sc_sc1394.sc1394_dev.dv_xname, i, 1578 buf[i], buf[i + 1]); 1579 return; 1580 } 1581 if (buf[i] & 0x00000001) 1582 continue; /* more pkt */ 1583 if (buf[i] & 0x00800000) 1584 continue; /* external id */ 1585 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 1586 if ((buf[i] & 0x00400800) == 0x00400800) 1587 sc->sc_irmid = sc->sc_rootid; 1588 } 1589 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 1590 if ((val & OHCI_NodeId_IDValid) == 0) { 1591 sc->sc_nodeid = IEEE1394_BCAST_PHY_ID; /* invalid */ 1592 return; 1593 } 1594 sc->sc_nodeid = val & 0xffff; 1595 #ifdef FW_DEBUG 1596 printf("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 1597 sc->sc_sc1394.sc1394_dev.dv_xname, 1598 sc->sc_nodeid, sc->sc_nodeid & OHCI_NodeId_NodeNumber, 1599 sc->sc_rootid, sc->sc_irmid); 1600 #endif 1601 1602 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 1603 return; 1604 1605 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 1606 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 1607 OHCI_LinkControl_CycleMaster); 1608 else 1609 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 1610 OHCI_LinkControl_CycleMaster); 1611 } 1612 1613 1614 /* 1615 * some CSRs are handled by driver. 1616 */ 1617 static void 1618 fwohci_csr_init(struct fwohci_softc *sc) 1619 { 1620 int i; 1621 static u_int32_t csr[] = { 1622 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 1623 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 1624 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 1625 CSR_SB_BROADCAST_CHANNEL 1626 }; 1627 1628 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 1629 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 1630 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 1631 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 1632 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 1633 } 1634 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 1635 } 1636 1637 static int 1638 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 1639 { 1640 struct fwohci_pkt res; 1641 u_int32_t reg; 1642 1643 /* 1644 * XXX need to do special functionality other than just r/w... 1645 */ 1646 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 1647 1648 if ((reg & 0x03) != 0) { 1649 /* alignment error */ 1650 return IEEE1394_RCODE_ADDRESS_ERROR; 1651 } 1652 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 1653 #ifdef FW_DEBUG 1654 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x -> 0x%08x\n", 1655 reg, *(u_int32_t *)(&sc->sc_csr[reg]), 1656 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base)); 1657 #endif 1658 *(u_int32_t *)&sc->sc_csr[reg] = 1659 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 1660 } else { 1661 #ifdef FW_DEBUG 1662 printf("fwohci_csr_input: CSR[0x%04x]: 0x%08x\n", 1663 reg, *(u_int32_t *)(&sc->sc_csr[reg])); 1664 #endif 1665 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 1666 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 1667 res.fp_iov[0].iov_len = 4; 1668 res.fp_iovcnt = 1; 1669 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 1670 return -1; 1671 } 1672 return IEEE1394_RCODE_COMPLETE; 1673 } 1674 1675 /* 1676 * Mapping between nodeid and unique ID (EUI-64). 1677 */ 1678 static void 1679 fwohci_uid_collect(struct fwohci_softc *sc) 1680 { 1681 int i; 1682 struct fwohci_uidtbl *fu; 1683 struct fwohci_pkt pkt; 1684 1685 if (sc->sc_uidtbl != NULL) 1686 free(sc->sc_uidtbl, M_DEVBUF); 1687 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), 1688 M_DEVBUF, M_NOWAIT); 1689 if (sc->sc_uidtbl == NULL) 1690 return; 1691 memset(sc->sc_uidtbl, 0, sizeof(*fu) * (sc->sc_rootid + 1)); 1692 1693 memset(&pkt, 0, sizeof(pkt)); 1694 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 1695 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 1696 memcpy(fu->fu_hi.fu_uid, sc->sc_sc1394.sc1394_guid, 4); 1697 memcpy(fu->fu_lo.fu_uid, sc->sc_sc1394.sc1394_guid, 4); 1698 fu->fu_hi.fu_valid = fu->fu_lo.fu_valid = 1; 1699 continue; 1700 } 1701 fu->fu_hi.fu_valid = fu->fu_lo.fu_valid = 0; 1702 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 1703 pkt.fp_hlen = 12; 1704 pkt.fp_dlen = 0; 1705 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 1706 (pkt.fp_tcode << 4); 1707 pkt.fp_hdr[1] = ((0xffc0 | i) << 16) | CSR_BASE_HI; 1708 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 1709 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 1710 sc->sc_tlabel, fwohci_uid_input, &fu->fu_hi); 1711 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 1712 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 1713 1714 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 1715 (pkt.fp_tcode << 4); 1716 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 1717 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, i, 1718 sc->sc_tlabel, fwohci_uid_input, &fu->fu_lo); 1719 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 1720 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 1721 } 1722 } 1723 1724 static int 1725 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 1726 { 1727 struct fwohci_uident *fu = arg; 1728 1729 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 1730 fu->fu_valid = 1; 1731 #ifdef FW_DEBUG 1732 printf("fwohci_uid_input: %02x%02x%02x%02x\n", 1733 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3]); 1734 #endif 1735 return 0; 1736 } 1737 1738 static int 1739 fwohci_uid_lookup(struct fwohci_softc *sc, u_int8_t *uid) 1740 { 1741 struct fwohci_uidtbl *fu; 1742 int n; 1743 static const u_int8_t bcast[] = 1744 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1745 1746 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 1747 return IEEE1394_BCAST_PHY_ID; 1748 fu = sc->sc_uidtbl; 1749 if (fu == NULL) { 1750 fwohci_uid_collect(sc); /* try to get */ 1751 return -1; 1752 } 1753 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 1754 if (fu->fu_hi.fu_valid && fu->fu_lo.fu_valid && 1755 memcmp(fu->fu_hi.fu_uid, uid, 4) == 0 && 1756 memcmp(fu->fu_lo.fu_uid, uid + 4, 4) == 0) 1757 break; 1758 } 1759 if (n > sc->sc_rootid) { 1760 fwohci_uid_collect(sc); /* try to get */ 1761 return -1; 1762 } 1763 return n; 1764 } 1765 1766 /* 1767 * functions to support network interface 1768 */ 1769 static int 1770 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 1771 void (*handler)(struct device *, struct mbuf *)) 1772 { 1773 struct fwohci_softc *sc = (struct fwohci_softc *)self; 1774 1775 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 1776 fwohci_if_input, handler); 1777 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 1778 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & OHCI_NodeId_NodeNumber, 1779 IEEE1394_TAG_GASP, fwohci_if_input, handler); 1780 return 0; 1781 } 1782 1783 static int 1784 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 1785 { 1786 int n, len; 1787 struct mbuf *m; 1788 struct iovec *iov; 1789 void (*handler)(struct device *, struct mbuf *) = arg; 1790 1791 #ifdef FW_DEBUG 1792 { int n; 1793 printf("fwohci_if_input: tcode=0x%x, dlen=%d", 1794 pkt->fp_tcode, pkt->fp_dlen); 1795 for (i = 0; i < pkt->fp_hlen/4; i++) 1796 printf("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i]); 1797 printf("$"); 1798 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++) { 1799 iov = &pkt->fp_iov[n]; 1800 for (i = 0; i < iov->iov_len; i++) 1801 printf("%s%02x", (i%32)?((i%4)?"":" "):"\n\t", 1802 ((u_int8_t *)iov->iov_base)[i]); 1803 printf("$"); 1804 } 1805 printf("\n"); 1806 } 1807 #endif /* FW_DEBUG */ 1808 len = pkt->fp_dlen; 1809 MGETHDR(m, M_DONTWAIT, MT_DATA); 1810 if (m == NULL) 1811 return IEEE1394_RCODE_COMPLETE; 1812 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) 1813 m->m_flags |= M_BCAST; 1814 m->m_pkthdr.rcvif = NULL; /* set in child */ 1815 m->m_pkthdr.len = len; 1816 m->m_len = 0; 1817 if (len > MHLEN) { 1818 MCLGET(m, M_DONTWAIT); 1819 if ((m->m_flags & M_EXT) == 0) { 1820 m_freem(m); 1821 return IEEE1394_RCODE_COMPLETE; 1822 } 1823 } 1824 /* 1825 * We may use receive buffer by external mbuf instead of copy here. 1826 * But asynchronous receive buffer must be operate in buffer fill 1827 * mode, so that each receive buffer will shared by multiple mbufs. 1828 * If upper layer doesn't free mbuf soon, e.g. application program 1829 * is suspended, buffer must be reallocated. 1830 * Isochronous buffer must be operate in packet buffer mode, and 1831 * it is easy to map receive buffer to external mbuf. But it is 1832 * used for broadcast/multicast only, and is expected not so 1833 * performance sensitive for now. 1834 * XXX: The performance may be important for multicast case, 1835 * so we should revisit here later. 1836 * -- onoe 1837 */ 1838 n = 0; 1839 iov = pkt->fp_iov; 1840 while (len > 0) { 1841 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 1842 iov->iov_len); 1843 m->m_len += iov->iov_len; 1844 len -= iov->iov_len; 1845 iov++; 1846 } 1847 (*handler)(sc->sc_sc1394.sc1394_if, m); 1848 return IEEE1394_RCODE_COMPLETE; 1849 } 1850 1851 static int 1852 fwohci_if_output(struct device *self, struct mbuf *m0, 1853 void (*callback)(struct device *, struct mbuf *)) 1854 { 1855 struct fwohci_softc *sc = (struct fwohci_softc *)self; 1856 struct mbuf *m; 1857 struct fwohci_pkt pkt; 1858 struct iovec *iov; 1859 u_int8_t *p; 1860 int n; 1861 int error; 1862 1863 memset(&pkt, 0, sizeof(pkt)); 1864 if (m0->m_flags & (M_BCAST|M_MCAST)) { 1865 m_adj(m0, 8); 1866 /* construct GASP header */ 1867 p = mtod(m0, u_int8_t *); 1868 p[0] = sc->sc_nodeid >> 8; 1869 p[1] = sc->sc_nodeid & 0xff; 1870 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 1871 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 1872 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 1873 pkt.fp_hlen = 8; 1874 pkt.fp_hdr[0] = (IEEE1394_TAG_GASP << 14) | 1875 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 1876 OHCI_NodeId_NodeNumber) << 8); 1877 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 1878 } else { 1879 p = mtod(m0, u_int8_t *); 1880 m_adj(m0, 16); 1881 n = fwohci_uid_lookup(sc, p); 1882 if (n < 0) { 1883 printf("fwohci_if_output: nodeid unknown: %08x%08x\n", 1884 htonl(((u_int32_t *)p)[0]), 1885 htonl(((u_int32_t *)p)[1])); 1886 error = EHOSTUNREACH; 1887 goto end; 1888 } 1889 if (n == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 1890 /* should not come here */ 1891 error = EIO; 1892 goto end; 1893 } 1894 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 1895 pkt.fp_hlen = 16; 1896 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 1897 (p[9] << 16); 1898 pkt.fp_hdr[1] = 1899 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 1900 (p[10] << 8) | p[11]; 1901 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 1902 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 1903 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 1904 } 1905 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 1906 pkt.fp_dlen = m0->m_pkthdr.len; 1907 for (m = m0; m != NULL; m = m->m_next) { 1908 iov = &pkt.fp_iov[pkt.fp_iovcnt++]; 1909 iov->iov_base = mtod(m, caddr_t); 1910 iov->iov_len = m->m_len; 1911 } 1912 pkt.fp_m = m0; 1913 pkt.fp_callback = callback; 1914 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 1915 end: 1916 if (error) { 1917 if (callback) 1918 (*callback)(sc->sc_sc1394.sc1394_if, m0); 1919 else 1920 m_freem(m0); 1921 } 1922 return error; 1923 } 1924
Indexes created Thu Sep 25 16:09:42 GMT 2025