fwohci.c revision 1.59
1 /* $NetBSD: fwohci.c,v 1.59 2002/11/25 02:30:38 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 /* 47 * The first version to support isochronous acquisition part is wrtten 48 * by HAYAKAWA Koichi <haya (at) netbsd.org>. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.59 2002/11/25 02:30:38 thorpej Exp $"); 53 54 #define DOUBLEBUF 1 55 #define NO_THREAD 1 56 57 #include "opt_inet.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kthread.h> 62 #include <sys/socket.h> 63 #include <sys/callout.h> 64 #include <sys/device.h> 65 #include <sys/kernel.h> 66 #include <sys/malloc.h> 67 #include <sys/mbuf.h> 68 69 #if __NetBSD_Version__ >= 105010000 70 #include <uvm/uvm_extern.h> 71 #else 72 #include <vm/vm.h> 73 #endif 74 75 #include <machine/bus.h> 76 #include <machine/intr.h> 77 78 #include <dev/ieee1394/ieee1394reg.h> 79 #include <dev/ieee1394/fwohcireg.h> 80 81 #include <dev/ieee1394/ieee1394var.h> 82 #include <dev/ieee1394/fwohcivar.h> 83 84 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 85 86 #if 0 87 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 88 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 89 #endif 90 static void fwohci_create_event_thread(void *); 91 static void fwohci_thread_init(void *); 92 93 static void fwohci_event_thread(struct fwohci_softc *); 94 static void fwohci_hw_init(struct fwohci_softc *); 95 static void fwohci_power(int, void *); 96 static void fwohci_shutdown(void *); 97 98 static int fwohci_desc_alloc(struct fwohci_softc *); 99 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 100 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 101 102 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 103 int, int, int); 104 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 105 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 106 107 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 108 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 109 static void fwohci_buf_init_rx(struct fwohci_softc *); 110 static void fwohci_buf_start_rx(struct fwohci_softc *); 111 static void fwohci_buf_stop_tx(struct fwohci_softc *); 112 static void fwohci_buf_stop_rx(struct fwohci_softc *); 113 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 114 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_buf **, 115 caddr_t *, int); 116 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 117 struct fwohci_pkt *); 118 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 119 struct fwohci_pkt *); 120 121 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 122 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 123 static void fwohci_phy_busreset(struct fwohci_softc *); 124 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 125 126 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 127 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 128 129 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 130 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 131 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 132 133 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 134 struct fwohci_pkt *); 135 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 136 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 137 struct fwohci_pkt *); 138 139 static int fwohci_guidrom_init(struct fwohci_softc *); 140 static void fwohci_configrom_init(struct fwohci_softc *); 141 static int fwohci_configrom_input(struct fwohci_softc *, void *, 142 struct fwohci_pkt *); 143 static void fwohci_selfid_init(struct fwohci_softc *); 144 static int fwohci_selfid_input(struct fwohci_softc *); 145 146 static void fwohci_csr_init(struct fwohci_softc *); 147 static int fwohci_csr_input(struct fwohci_softc *, void *, 148 struct fwohci_pkt *); 149 150 static void fwohci_uid_collect(struct fwohci_softc *); 151 static void fwohci_uid_req(struct fwohci_softc *, int); 152 static int fwohci_uid_input(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 155 static void fwohci_check_nodes(struct fwohci_softc *); 156 157 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 158 void (*)(struct device *, struct mbuf *)); 159 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 160 static int fwohci_if_input_iso(struct fwohci_softc *, void *, struct fwohci_pkt *); 161 static int fwohci_if_output(struct device *, struct mbuf *, 162 void (*)(struct device *, struct mbuf *)); 163 static int fwohci_if_setiso(struct device *, u_int32_t, u_int32_t, u_int32_t, 164 void (*)(struct device *, struct mbuf *)); 165 static int fwohci_read(struct ieee1394_abuf *); 166 static int fwohci_write(struct ieee1394_abuf *); 167 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 168 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 169 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 170 struct fwohci_pkt *); 171 static int fwohci_inreg(struct ieee1394_abuf *, int); 172 static int fwohci_unreg(struct ieee1394_abuf *, int); 173 static int fwohci_parse_input(struct fwohci_softc *, void *, 174 struct fwohci_pkt *); 175 static int fwohci_submatch(struct device *, struct cfdata *, void *); 176 177 #ifdef FW_DEBUG 178 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 179 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 180 181 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 182 183 #define DPRINTF(x) if (fwdebug) printf x 184 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 185 int fwdebug = 1; 186 #else 187 #define DPRINTF(x) 188 #define DPRINTFN(n,x) 189 #endif 190 191 int 192 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 193 { 194 int i; 195 u_int32_t val; 196 #if 0 197 int error; 198 #endif 199 200 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 201 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 202 203 evcnt_attach_dynamic(&sc->sc_isocnt, EVCNT_TYPE_MISC, ev, 204 sc->sc_sc1394.sc1394_dev.dv_xname, "iso"); 205 evcnt_attach_dynamic(&sc->sc_isopktcnt, EVCNT_TYPE_MISC, ev, 206 sc->sc_sc1394.sc1394_dev.dv_xname, "isopackets"); 207 208 /* 209 * Wait for reset completion 210 */ 211 for (i = 0; i < OHCI_LOOP; i++) { 212 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 213 if ((val & OHCI_HCControl_SoftReset) == 0) 214 break; 215 DELAY(10); 216 } 217 218 /* What dialect of OHCI is this device? 219 */ 220 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 221 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 222 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 223 224 LIST_INIT(&sc->sc_nodelist); 225 226 if (fwohci_guidrom_init(sc) != 0) { 227 printf("\n%s: fatal: no global UID ROM\n", 228 sc->sc_sc1394.sc1394_dev.dv_xname); 229 return -1; 230 } 231 232 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 233 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 234 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 235 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 236 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 237 238 /* Get the maximum link speed and receive size 239 */ 240 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 241 sc->sc_sc1394.sc1394_link_speed = 242 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 243 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 244 printf(", %s", 245 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 246 } else { 247 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 248 } 249 250 /* MaxRec is encoded as log2(max_rec_octets)-1 251 */ 252 sc->sc_sc1394.sc1394_max_receive = 253 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 254 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 255 256 /* 257 * Count how many isochronous ctx we have. 258 */ 259 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 260 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 261 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 262 for (i = 0; val != 0; val >>= 1) { 263 if (val & 0x1) 264 i++; 265 } 266 sc->sc_isoctx = i; 267 printf(", %d iso_ctx", sc->sc_isoctx); 268 269 printf("\n"); 270 271 #if 0 272 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 273 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 274 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 275 return error; 276 #endif 277 278 sc->sc_dying = 0; 279 sc->sc_nodeid = 0xffff; /* invalid */ 280 281 sc->sc_sc1394.sc1394_callback.sc1394_read = fwohci_read; 282 sc->sc_sc1394.sc1394_callback.sc1394_write = fwohci_write; 283 sc->sc_sc1394.sc1394_callback.sc1394_inreg = fwohci_inreg; 284 sc->sc_sc1394.sc1394_callback.sc1394_unreg = fwohci_unreg; 285 286 kthread_create(fwohci_create_event_thread, sc); 287 return 0; 288 } 289 290 static int 291 fwohci_if_setiso(struct device *self, u_int32_t channel, u_int32_t tag, 292 u_int32_t direction, void (*handler)(struct device *, struct mbuf *)) 293 { 294 struct fwohci_softc *sc = (struct fwohci_softc *)self; 295 int retval; 296 int s; 297 298 if (direction == 1) { 299 return EIO; 300 } 301 302 s = splnet(); 303 retval = fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 304 channel, tag, fwohci_if_input_iso, handler); 305 splx(s); 306 307 if (!retval) { 308 printf("%s: dummy iso handler set\n", 309 sc->sc_sc1394.sc1394_dev.dv_xname); 310 } else { 311 printf("%s: dummy iso handler cannot set\n", 312 sc->sc_sc1394.sc1394_dev.dv_xname); 313 } 314 315 return retval; 316 } 317 318 int 319 fwohci_intr(void *arg) 320 { 321 struct fwohci_softc * const sc = arg; 322 int progress = 0; 323 u_int32_t intmask, iso; 324 325 for (;;) { 326 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 327 328 /* 329 * On a bus reset, everything except bus reset gets 330 * cleared. That can't get cleared until the selfid 331 * phase completes (which happens outside the 332 * interrupt routines). So if just a bus reset is left 333 * in the mask and it's already in the sc_intmask, 334 * just return. 335 */ 336 337 if ((intmask == 0) || 338 (progress && (intmask == OHCI_Int_BusReset) && 339 (sc->sc_intmask & OHCI_Int_BusReset))) { 340 if (progress) 341 wakeup(fwohci_event_thread); 342 return progress; 343 } 344 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 345 intmask & ~OHCI_Int_BusReset); 346 #ifdef FW_DEBUG 347 if (fwdebug > 1) 348 fwohci_show_intr(sc, intmask); 349 #endif 350 351 if (intmask & OHCI_Int_BusReset) { 352 /* 353 * According to OHCI spec 6.1.1 "busReset", 354 * All asynchronous transmit must be stopped before 355 * clearing BusReset. Moreover, the BusReset 356 * interrupt bit should not be cleared during the 357 * SelfID phase. Thus we turned off interrupt mask 358 * bit of BusReset instead until SelfID completion 359 * or SelfID timeout. 360 */ 361 intmask &= OHCI_Int_SelfIDComplete; 362 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 363 OHCI_Int_BusReset); 364 sc->sc_intmask = OHCI_Int_BusReset; 365 } 366 sc->sc_intmask |= intmask; 367 368 if (intmask & OHCI_Int_IsochTx) { 369 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 370 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 371 } 372 if (intmask & OHCI_Int_IsochRx) { 373 #if NO_THREAD 374 int i; 375 int asyncstream = 0; 376 #endif 377 378 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 379 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 380 #if NO_THREAD 381 for (i = 0; i < sc->sc_isoctx; i++) { 382 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) { 383 if (sc->sc_ctx_ir[i]->fc_type == FWOHCI_CTX_ISO_SINGLE) { 384 asyncstream |= (1 << i); 385 continue; 386 } 387 bus_dmamap_sync(sc->sc_dmat, 388 sc->sc_ddmamap, 389 0, sizeof(struct fwohci_desc) * sc->sc_descsize, 390 BUS_DMASYNC_PREREAD); 391 sc->sc_isocnt.ev_count++; 392 393 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 394 } 395 } 396 if (asyncstream != 0) { 397 sc->sc_iso |= asyncstream; 398 } else { 399 /* all iso intr is pure isochronous */ 400 sc->sc_intmask &= ~OHCI_Int_IsochRx; 401 } 402 #else 403 sc->sc_iso |= iso; 404 #endif /* NO_THREAD */ 405 } 406 407 if (!progress) { 408 sc->sc_intrcnt.ev_count++; 409 progress = 1; 410 } 411 } 412 } 413 414 static void 415 fwohci_create_event_thread(void *arg) 416 { 417 struct fwohci_softc *sc = arg; 418 419 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 420 sc->sc_sc1394.sc1394_dev.dv_xname)) { 421 printf("%s: unable to create event thread\n", 422 sc->sc_sc1394.sc1394_dev.dv_xname); 423 panic("fwohci_create_event_thread"); 424 } 425 } 426 427 static void 428 fwohci_thread_init(void *arg) 429 { 430 struct fwohci_softc *sc = arg; 431 int i; 432 433 /* 434 * Allocate descriptors 435 */ 436 if (fwohci_desc_alloc(sc)) { 437 printf("%s: not enabling interrupts\n", 438 sc->sc_sc1394.sc1394_dev.dv_xname); 439 kthread_exit(1); 440 } 441 442 /* 443 * Enable Link Power 444 */ 445 446 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 447 448 /* 449 * Allocate DMA Context 450 */ 451 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 452 OHCI_CTX_ASYNC_RX_REQUEST, FWOHCI_CTX_ASYNC); 453 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 454 OHCI_CTX_ASYNC_RX_RESPONSE, FWOHCI_CTX_ASYNC); 455 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST, 456 FWOHCI_CTX_ASYNC); 457 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE, 458 FWOHCI_CTX_ASYNC); 459 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 460 M_DEVBUF, M_WAITOK); 461 for (i = 0; i < sc->sc_isoctx; i++) 462 sc->sc_ctx_ir[i] = NULL; 463 464 /* 465 * Allocate buffer for configuration ROM and SelfID buffer 466 */ 467 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 468 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 469 470 callout_init(&sc->sc_selfid_callout); 471 472 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 473 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 474 sc->sc_sc1394.sc1394_ifsetiso = fwohci_if_setiso; 475 476 /* 477 * establish hooks for shutdown and suspend/resume 478 */ 479 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 480 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 481 482 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 483 fwohci_print); 484 485 /* Main loop. It's not coming back normally. */ 486 487 fwohci_event_thread(sc); 488 489 kthread_exit(0); 490 } 491 492 static void 493 fwohci_event_thread(struct fwohci_softc *sc) 494 { 495 int i, s; 496 u_int32_t intmask, iso; 497 498 s = splbio(); 499 500 /* 501 * Initialize hardware registers. 502 */ 503 504 fwohci_hw_init(sc); 505 506 /* Initial Bus Reset */ 507 fwohci_phy_busreset(sc); 508 splx(s); 509 510 while (!sc->sc_dying) { 511 s = splbio(); 512 intmask = sc->sc_intmask; 513 if (intmask == 0) { 514 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 515 splx(s); 516 continue; 517 } 518 sc->sc_intmask = 0; 519 splx(s); 520 521 if (intmask & OHCI_Int_BusReset) { 522 fwohci_buf_stop_tx(sc); 523 if (sc->sc_uidtbl != NULL) { 524 free(sc->sc_uidtbl, M_DEVBUF); 525 sc->sc_uidtbl = NULL; 526 } 527 528 callout_reset(&sc->sc_selfid_callout, 529 OHCI_SELFID_TIMEOUT, 530 (void (*)(void *))fwohci_phy_busreset, sc); 531 sc->sc_nodeid = 0xffff; /* indicate invalid */ 532 sc->sc_rootid = 0; 533 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 534 } 535 if (intmask & OHCI_Int_SelfIDComplete) { 536 s = splbio(); 537 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 538 OHCI_Int_BusReset); 539 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 540 OHCI_Int_BusReset); 541 splx(s); 542 callout_stop(&sc->sc_selfid_callout); 543 if (fwohci_selfid_input(sc) == 0) { 544 fwohci_buf_start_rx(sc); 545 fwohci_uid_collect(sc); 546 } 547 } 548 if (intmask & OHCI_Int_ReqTxComplete) 549 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 550 if (intmask & OHCI_Int_RespTxComplete) 551 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 552 if (intmask & OHCI_Int_RQPkt) 553 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 554 if (intmask & OHCI_Int_RSPkt) 555 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 556 if (intmask & OHCI_Int_IsochRx) { 557 s = splbio(); 558 iso = sc->sc_iso; 559 sc->sc_iso = 0; 560 splx(s); 561 for (i = 0; i < sc->sc_isoctx; i++) { 562 if ((iso & (1 << i)) && 563 sc->sc_ctx_ir[i] != NULL) { 564 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 565 sc->sc_isocnt.ev_count++; 566 } 567 } 568 } 569 } 570 } 571 572 #if 0 573 static int 574 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 575 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 576 { 577 bus_dma_segment_t segs[1]; 578 int error, nsegs, steps; 579 580 steps = 0; 581 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 582 segs, 1, &nsegs, flags); 583 if (error) 584 goto cleanup; 585 586 steps = 1; 587 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 588 kvap, flags); 589 if (error) 590 goto cleanup; 591 592 if (error == 0) 593 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 594 size, flags, mapp); 595 if (error) 596 goto cleanup; 597 if (error == 0) 598 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 599 flags); 600 if (error) 601 goto cleanup; 602 603 cleanup: 604 switch (steps) { 605 case 1: 606 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 607 } 608 609 return error; 610 } 611 #endif 612 613 int 614 fwohci_print(void *aux, const char *pnp) 615 { 616 char *name = aux; 617 618 if (pnp) 619 printf("%s at %s", name, pnp); 620 621 return UNCONF; 622 } 623 624 static void 625 fwohci_hw_init(struct fwohci_softc *sc) 626 { 627 int i; 628 u_int32_t val; 629 630 /* 631 * Software Reset. 632 */ 633 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 634 for (i = 0; i < OHCI_LOOP; i++) { 635 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 636 if ((val & OHCI_HCControl_SoftReset) == 0) 637 break; 638 DELAY(10); 639 } 640 641 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 642 643 /* 644 * First, initilize CSRs with undefined value to default settings. 645 */ 646 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 647 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 648 #if 0 649 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 650 #else 651 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 652 #endif 653 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 654 for (i = 0; i < sc->sc_isoctx; i++) { 655 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 656 ~0); 657 } 658 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 659 660 fwohci_configrom_init(sc); 661 fwohci_selfid_init(sc); 662 fwohci_buf_init_rx(sc); 663 fwohci_csr_init(sc); 664 665 /* 666 * Final CSR settings. 667 */ 668 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 669 OHCI_LinkControl_CycleTimerEnable | 670 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 671 672 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 673 674 /* clear receive filter */ 675 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 676 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 677 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 678 679 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 680 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 681 #if BYTE_ORDER == BIG_ENDIAN 682 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 683 OHCI_HCControl_NoByteSwapData); 684 #endif 685 686 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 687 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 688 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 689 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 690 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 691 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 692 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 693 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 694 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 695 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 696 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 697 698 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 699 700 /* 701 * Start the receivers 702 */ 703 fwohci_buf_start_rx(sc); 704 } 705 706 static void 707 fwohci_power(int why, void *arg) 708 { 709 struct fwohci_softc *sc = arg; 710 int s; 711 712 s = splbio(); 713 switch (why) { 714 case PWR_SUSPEND: 715 case PWR_STANDBY: 716 fwohci_shutdown(sc); 717 break; 718 case PWR_RESUME: 719 fwohci_hw_init(sc); 720 fwohci_phy_busreset(sc); 721 break; 722 case PWR_SOFTSUSPEND: 723 case PWR_SOFTSTANDBY: 724 case PWR_SOFTRESUME: 725 break; 726 } 727 splx(s); 728 } 729 730 static void 731 fwohci_shutdown(void *arg) 732 { 733 struct fwohci_softc *sc = arg; 734 u_int32_t val; 735 736 callout_stop(&sc->sc_selfid_callout); 737 /* disable all interrupt */ 738 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 739 fwohci_buf_stop_tx(sc); 740 fwohci_buf_stop_rx(sc); 741 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 742 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 743 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 744 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 745 fwohci_phy_busreset(sc); 746 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 747 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 748 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 749 } 750 751 /* 752 * COMMON FUNCTIONS 753 */ 754 755 /* 756 * read the PHY Register. 757 */ 758 static u_int8_t 759 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 760 { 761 int i; 762 u_int32_t val; 763 764 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 765 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 766 for (i = 0; i < OHCI_LOOP; i++) { 767 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 768 OHCI_PhyControl_RdDone) 769 break; 770 DELAY(10); 771 } 772 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 773 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 774 } 775 776 /* 777 * write the PHY Register. 778 */ 779 static void 780 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 781 { 782 int i; 783 784 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 785 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 786 (val << OHCI_PhyControl_WrData_BITPOS)); 787 for (i = 0; i < OHCI_LOOP; i++) { 788 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 789 OHCI_PhyControl_WrReg)) 790 break; 791 DELAY(10); 792 } 793 } 794 795 /* 796 * Initiate Bus Reset 797 */ 798 static void 799 fwohci_phy_busreset(struct fwohci_softc *sc) 800 { 801 int s; 802 u_int8_t val; 803 804 s = splbio(); 805 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 806 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 807 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 808 callout_stop(&sc->sc_selfid_callout); 809 val = fwohci_phy_read(sc, 1); 810 val = (val & 0x80) | /* preserve RHB (force root) */ 811 0x40 | /* Initiate Bus Reset */ 812 0x3f; /* default GAP count */ 813 fwohci_phy_write(sc, 1, val); 814 splx(s); 815 } 816 817 /* 818 * PHY Packet 819 */ 820 static void 821 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 822 { 823 u_int32_t val; 824 825 val = pkt->fp_hdr[1]; 826 if (val != ~pkt->fp_hdr[2]) { 827 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 828 OHCI_CTXCTL_EVENT_BUS_RESET) { 829 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 830 pkt->fp_hdr[2])); 831 } else { 832 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 833 sc->sc_sc1394.sc1394_dev.dv_xname, val, 834 pkt->fp_hdr[2]); 835 } 836 return; 837 } 838 #ifdef FW_DEBUG 839 if (fwdebug > 1) 840 fwohci_show_phypkt(sc, val); 841 #endif 842 } 843 844 /* 845 * Descriptor for context DMA. 846 */ 847 static int 848 fwohci_desc_alloc(struct fwohci_softc *sc) 849 { 850 int error, mapsize, dsize; 851 852 /* 853 * allocate descriptor buffer 854 */ 855 856 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 857 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 858 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 859 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 860 mapsize = howmany(sc->sc_descsize, NBBY); 861 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK|M_ZERO); 862 863 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 864 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 865 printf("%s: unable to allocate descriptor buffer, error = %d\n", 866 sc->sc_sc1394.sc1394_dev.dv_xname, error); 867 goto fail_0; 868 } 869 870 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 871 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 872 != 0) { 873 printf("%s: unable to map descriptor buffer, error = %d\n", 874 sc->sc_sc1394.sc1394_dev.dv_xname, error); 875 goto fail_1; 876 } 877 878 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 879 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 880 printf("%s: unable to create descriptor buffer DMA map, " 881 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 882 goto fail_2; 883 } 884 885 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 886 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 887 printf("%s: unable to load descriptor buffer DMA map, " 888 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 889 goto fail_3; 890 } 891 892 return 0; 893 894 fail_3: 895 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 896 fail_2: 897 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 898 fail_1: 899 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 900 fail_0: 901 return error; 902 } 903 904 static struct fwohci_desc * 905 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 906 { 907 int i, n; 908 909 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 910 for (i = 0; ; i++) { 911 if (i == ndesc) { 912 for (i = 0; i < ndesc; i++) 913 setbit(sc->sc_descmap, n + i); 914 return sc->sc_desc + n; 915 } 916 if (isset(sc->sc_descmap, n + i)) 917 break; 918 } 919 } 920 return NULL; 921 } 922 923 static void 924 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 925 { 926 int i, n; 927 928 n = fd - sc->sc_desc; 929 for (i = 0; i < ndesc; i++, n++) { 930 #ifdef DIAGNOSTIC 931 if (isclr(sc->sc_descmap, n)) 932 panic("fwohci_desc_put: duplicated free"); 933 #endif 934 clrbit(sc->sc_descmap, n); 935 } 936 } 937 938 /* 939 * Asyncronous/Isochronous Transmit/Receive Context 940 */ 941 static int 942 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 943 int bufcnt, int ctx, int ctxtype) 944 { 945 int i, error; 946 struct fwohci_ctx *fc; 947 struct fwohci_buf *fb; 948 struct fwohci_desc *fd; 949 #if DOUBLEBUF 950 int buf2cnt; 951 #endif 952 953 fc = malloc(sizeof(*fc), M_DEVBUF, M_WAITOK|M_ZERO); 954 LIST_INIT(&fc->fc_handler); 955 TAILQ_INIT(&fc->fc_buf); 956 fc->fc_ctx = ctx; 957 fc->fc_buffers = fb = malloc(sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK|M_ZERO); 958 fc->fc_bufcnt = bufcnt; 959 #if DOUBLEBUF 960 TAILQ_INIT(&fc->fc_buf2); /* for isochronous */ 961 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 962 buf2cnt = bufcnt/2; 963 bufcnt -= buf2cnt; 964 if (buf2cnt == 0) { 965 panic("cannot allocate iso buffer"); 966 } 967 } 968 #endif 969 for (i = 0; i < bufcnt; i++, fb++) { 970 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 971 goto fail; 972 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 973 error = ENOBUFS; 974 goto fail; 975 } 976 fb->fb_desc = fd; 977 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 978 ((caddr_t)fd - (caddr_t)sc->sc_desc); 979 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 980 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 981 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 982 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 983 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 984 } 985 #if DOUBLEBUF 986 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 987 for (i = bufcnt; i < bufcnt + buf2cnt; i++, fb++) { 988 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 989 goto fail; 990 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 991 error = ENOBUFS; 992 goto fail; 993 } 994 fb->fb_desc = fd; 995 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 996 ((caddr_t)fd - (caddr_t)sc->sc_desc); 997 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 998 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 999 BUS_DMASYNC_PREWRITE); 1000 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1001 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1002 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1003 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1004 TAILQ_INSERT_TAIL(&fc->fc_buf2, fb, fb_list); 1005 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1006 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1007 BUS_DMASYNC_POSTWRITE); 1008 } 1009 } 1010 #endif /* DOUBLEBUF */ 1011 fc->fc_type = ctxtype; 1012 *fcp = fc; 1013 return 0; 1014 1015 fail: 1016 while (i-- > 0) { 1017 fb--; 1018 if (fb->fb_desc) 1019 fwohci_desc_put(sc, fb->fb_desc, 1); 1020 fwohci_buf_free(sc, fb); 1021 } 1022 free(fc, M_DEVBUF); 1023 return error; 1024 } 1025 1026 static void 1027 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1028 { 1029 struct fwohci_buf *fb; 1030 struct fwohci_handler *fh; 1031 1032 #if DOUBLEBUF 1033 if ((fc->fc_type == FWOHCI_CTX_ISO_MULTI) && 1034 (TAILQ_FIRST(&fc->fc_buf) > TAILQ_FIRST(&fc->fc_buf2))) { 1035 struct fwohci_buf_s fctmp; 1036 1037 fctmp = fc->fc_buf; 1038 fc->fc_buf = fc->fc_buf2; 1039 fc->fc_buf2 = fctmp; 1040 } 1041 #endif 1042 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1043 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1044 NULL, NULL); 1045 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1046 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1047 if (fb->fb_desc) 1048 fwohci_desc_put(sc, fb->fb_desc, 1); 1049 fwohci_buf_free(sc, fb); 1050 } 1051 #if DOUBLEBUF 1052 while ((fb = TAILQ_FIRST(&fc->fc_buf2)) != NULL) { 1053 TAILQ_REMOVE(&fc->fc_buf2, fb, fb_list); 1054 if (fb->fb_desc) 1055 fwohci_desc_put(sc, fb->fb_desc, 1); 1056 fwohci_buf_free(sc, fb); 1057 } 1058 #endif /* DOUBLEBUF */ 1059 free(fc->fc_buffers, M_DEVBUF); 1060 free(fc, M_DEVBUF); 1061 } 1062 1063 static void 1064 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1065 { 1066 struct fwohci_buf *fb, *nfb; 1067 struct fwohci_desc *fd; 1068 struct fwohci_handler *fh; 1069 int n; 1070 1071 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1072 nfb = TAILQ_NEXT(fb, fb_list); 1073 fb->fb_off = 0; 1074 fd = fb->fb_desc; 1075 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1076 fd->fd_rescount = fd->fd_reqcount; 1077 } 1078 1079 #if DOUBLEBUF 1080 for (fb = TAILQ_FIRST(&fc->fc_buf2); fb != NULL; fb = nfb) { 1081 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1082 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1083 BUS_DMASYNC_PREWRITE); 1084 nfb = TAILQ_NEXT(fb, fb_list); 1085 fb->fb_off = 0; 1086 fd = fb->fb_desc; 1087 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1088 fd->fd_rescount = fd->fd_reqcount; 1089 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1090 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1091 BUS_DMASYNC_POSTWRITE); 1092 } 1093 #endif /* DOUBLEBUF */ 1094 1095 n = fc->fc_ctx; 1096 fb = TAILQ_FIRST(&fc->fc_buf); 1097 if (fc->fc_type != FWOHCI_CTX_ASYNC) { 1098 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1099 fb->fb_daddr | 1); 1100 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1101 OHCI_CTXCTL_RX_BUFFER_FILL | 1102 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1103 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1104 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1105 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1106 OHCI_CTXCTL_RX_ISOCH_HEADER); 1107 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1108 OHCI_SYNC_RX_DMA_WRITE(sc, n, 1109 OHCI_SUBREG_ContextControlSet, 1110 OHCI_CTXCTL_RX_BUFFER_FILL); 1111 } 1112 fh = LIST_FIRST(&fc->fc_handler); 1113 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1114 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1115 } else { 1116 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1117 fb->fb_daddr | 1); 1118 } 1119 } 1120 1121 /* 1122 * DMA data buffer 1123 */ 1124 static int 1125 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1126 { 1127 int error; 1128 1129 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1130 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1131 printf("%s: unable to allocate buffer, error = %d\n", 1132 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1133 goto fail_0; 1134 } 1135 1136 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1137 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1138 printf("%s: unable to map buffer, error = %d\n", 1139 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1140 goto fail_1; 1141 } 1142 1143 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1144 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1145 printf("%s: unable to create buffer DMA map, " 1146 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1147 error); 1148 goto fail_2; 1149 } 1150 1151 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1152 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1153 printf("%s: unable to load buffer DMA map, " 1154 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1155 error); 1156 goto fail_3; 1157 } 1158 1159 return 0; 1160 1161 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1162 fail_3: 1163 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1164 fail_2: 1165 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1166 fail_1: 1167 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1168 fail_0: 1169 return error; 1170 } 1171 1172 static void 1173 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1174 { 1175 1176 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1177 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1178 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1179 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1180 } 1181 1182 static void 1183 fwohci_buf_init_rx(struct fwohci_softc *sc) 1184 { 1185 int i; 1186 1187 /* 1188 * Initialize for Asynchronous Receive Queue. 1189 */ 1190 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1191 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1192 1193 /* 1194 * Initialize for Isochronous Receive Queue. 1195 */ 1196 for (i = 0; i < sc->sc_isoctx; i++) { 1197 if (sc->sc_ctx_ir[i] != NULL) 1198 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1199 } 1200 } 1201 1202 static void 1203 fwohci_buf_start_rx(struct fwohci_softc *sc) 1204 { 1205 int i; 1206 1207 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1208 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1209 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1210 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1211 for (i = 0; i < sc->sc_isoctx; i++) { 1212 if (sc->sc_ctx_ir[i] != NULL) 1213 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1214 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1215 } 1216 } 1217 1218 static void 1219 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1220 { 1221 int i; 1222 1223 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1224 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1225 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1226 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1227 1228 /* 1229 * Make sure the transmitter is stopped. 1230 */ 1231 for (i = 0; i < OHCI_LOOP; i++) { 1232 DELAY(10); 1233 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1234 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1235 continue; 1236 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1237 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1238 continue; 1239 break; 1240 } 1241 1242 /* 1243 * Initialize for Asynchronous Transmit Queue. 1244 */ 1245 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1246 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1247 } 1248 1249 static void 1250 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1251 { 1252 int i; 1253 1254 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1255 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1256 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1257 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1258 for (i = 0; i < sc->sc_isoctx; i++) { 1259 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1260 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1261 } 1262 } 1263 1264 static void 1265 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1266 { 1267 struct fwohci_buf *fb, *tfb; 1268 1269 #if DOUBLEBUF 1270 if (fc->fc_type != FWOHCI_CTX_ISO_MULTI) { 1271 #endif 1272 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1273 if (fc->fc_type) { 1274 if (fb->fb_off == 0) 1275 break; 1276 } else { 1277 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1278 fb->fb_desc->fd_rescount != 0) 1279 break; 1280 } 1281 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1282 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1283 fb->fb_off = 0; 1284 fb->fb_desc->fd_branch = 0; 1285 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1286 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1287 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1288 } 1289 #if DOUBLEBUF 1290 } else { 1291 struct fwohci_buf_s fctmp; 1292 1293 /* cleaning buffer */ 1294 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; 1295 fb = TAILQ_NEXT(fb, fb_list)) { 1296 fb->fb_off = 0; 1297 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1298 } 1299 1300 /* rotating buffer */ 1301 fctmp = fc->fc_buf; 1302 fc->fc_buf = fc->fc_buf2; 1303 fc->fc_buf2 = fctmp; 1304 } 1305 #endif 1306 } 1307 1308 static int 1309 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_buf **fbp, caddr_t *pp, 1310 int len) 1311 { 1312 struct fwohci_buf *fb; 1313 struct fwohci_desc *fd; 1314 int bufend; 1315 1316 fb = *fbp; 1317 again: 1318 fd = fb->fb_desc; 1319 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1320 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1321 fd->fd_reqcount, fd->fd_rescount, len, 1322 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1323 bufend = fd->fd_reqcount - fd->fd_rescount; 1324 if (fb->fb_off >= bufend) { 1325 DPRINTFN(5, ("buf %x finish req %d res %d off %d ", 1326 fb->fb_desc->fd_data, fd->fd_reqcount, fd->fd_rescount, 1327 fb->fb_off)); 1328 if (fd->fd_rescount == 0) { 1329 *fbp = fb = TAILQ_NEXT(fb, fb_list); 1330 if (fb != NULL) 1331 goto again; 1332 } 1333 return 0; 1334 } 1335 if (fb->fb_off + len > bufend) 1336 len = bufend - fb->fb_off; 1337 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1338 BUS_DMASYNC_POSTREAD); 1339 *pp = fb->fb_buf + fb->fb_off; 1340 fb->fb_off += roundup(len, 4); 1341 return len; 1342 } 1343 1344 static int 1345 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1346 struct fwohci_pkt *pkt) 1347 { 1348 caddr_t p; 1349 struct fwohci_buf *fb; 1350 int len, count, i; 1351 1352 memset(pkt, 0, sizeof(*pkt)); 1353 pkt->fp_uio.uio_iov = pkt->fp_iov; 1354 pkt->fp_uio.uio_rw = UIO_WRITE; 1355 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1356 1357 /* get first quadlet */ 1358 fb = TAILQ_FIRST(&fc->fc_buf); 1359 count = 4; 1360 len = fwohci_buf_pktget(sc, &fb, &p, count); 1361 if (len <= 0) { 1362 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1363 fc->fc_ctx)); 1364 return 0; 1365 } 1366 pkt->fp_hdr[0] = *(u_int32_t *)p; 1367 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1368 switch (pkt->fp_tcode) { 1369 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1370 case IEEE1394_TCODE_READ_RESP_QUAD: 1371 pkt->fp_hlen = 12; 1372 pkt->fp_dlen = 4; 1373 break; 1374 case IEEE1394_TCODE_READ_REQ_BLOCK: 1375 pkt->fp_hlen = 16; 1376 pkt->fp_dlen = 0; 1377 break; 1378 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1379 case IEEE1394_TCODE_READ_RESP_BLOCK: 1380 case IEEE1394_TCODE_LOCK_REQ: 1381 case IEEE1394_TCODE_LOCK_RESP: 1382 pkt->fp_hlen = 16; 1383 break; 1384 case IEEE1394_TCODE_STREAM_DATA: 1385 #ifdef DIAGNOSTIC 1386 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) 1387 #endif 1388 { 1389 pkt->fp_hlen = 4; 1390 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1391 DPRINTFN(5, ("[%d]", pkt->fp_dlen)); 1392 break; 1393 } 1394 #ifdef DIAGNOSTIC 1395 else { 1396 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1397 return 0; 1398 } 1399 #endif 1400 default: 1401 pkt->fp_hlen = 12; 1402 pkt->fp_dlen = 0; 1403 break; 1404 } 1405 1406 /* get header */ 1407 while (count < pkt->fp_hlen) { 1408 len = fwohci_buf_pktget(sc, &fb, &p, pkt->fp_hlen - count); 1409 if (len == 0) { 1410 printf("fwohci_buf_input: malformed input 1: %d\n", 1411 pkt->fp_hlen - count); 1412 return 0; 1413 } 1414 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1415 count += len; 1416 } 1417 if (pkt->fp_hlen == 16 && 1418 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1419 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1420 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, hlen=%d, dlen=%d\n", 1421 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1422 1423 /* get data */ 1424 count = 0; 1425 i = 0; 1426 while (count < pkt->fp_dlen) { 1427 len = fwohci_buf_pktget(sc, &fb, 1428 (caddr_t *)&pkt->fp_iov[i].iov_base, 1429 pkt->fp_dlen - count); 1430 if (len == 0) { 1431 printf("fwohci_buf_input: malformed input 2: %d\n", 1432 pkt->fp_dlen - count); 1433 return 0; 1434 } 1435 pkt->fp_iov[i++].iov_len = len; 1436 count += len; 1437 } 1438 pkt->fp_uio.uio_iovcnt = i; 1439 pkt->fp_uio.uio_resid = count; 1440 1441 /* get trailer */ 1442 len = fwohci_buf_pktget(sc, &fb, (caddr_t *)&pkt->fp_trail, 1443 sizeof(*pkt->fp_trail)); 1444 if (len <= 0) { 1445 printf("fwohci_buf_input: malformed input 3: %d\n", 1446 pkt->fp_hlen - count); 1447 return 0; 1448 } 1449 return 1; 1450 } 1451 1452 static int 1453 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1454 struct fwohci_pkt *pkt) 1455 { 1456 caddr_t p; 1457 int len; 1458 struct fwohci_buf *fb; 1459 struct fwohci_desc *fd; 1460 1461 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1462 return fwohci_buf_input(sc, fc, pkt); 1463 } 1464 1465 memset(pkt, 0, sizeof(*pkt)); 1466 pkt->fp_uio.uio_iov = pkt->fp_iov; 1467 pkt->fp_uio.uio_rw = UIO_WRITE; 1468 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1469 1470 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1471 if (fb == NULL) 1472 return 0; 1473 if (fb->fb_off == 0) 1474 break; 1475 } 1476 fd = fb->fb_desc; 1477 len = fd->fd_reqcount - fd->fd_rescount; 1478 if (len == 0) 1479 return 0; 1480 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1481 BUS_DMASYNC_POSTREAD); 1482 1483 p = fb->fb_buf; 1484 fb->fb_off += roundup(len, 4); 1485 if (len < 8) { 1486 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1487 return 0; 1488 } 1489 1490 /* 1491 * get trailer first, may be bogus data unless status update 1492 * in descriptor is set. 1493 */ 1494 pkt->fp_trail = (u_int32_t *)p; 1495 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1496 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1497 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1498 #ifdef DIAGNOSTIC 1499 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1500 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1501 pkt->fp_tcode); 1502 return 0; 1503 } 1504 #endif 1505 pkt->fp_hlen = 4; 1506 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1507 p += 8; 1508 len -= 8; 1509 if (pkt->fp_dlen != len) { 1510 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1511 pkt->fp_dlen, len); 1512 return 0; 1513 } 1514 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1515 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1516 pkt->fp_iov[0].iov_base = p; 1517 pkt->fp_iov[0].iov_len = len; 1518 pkt->fp_uio.uio_iovcnt = 0; 1519 pkt->fp_uio.uio_resid = len; 1520 return 1; 1521 } 1522 1523 static int 1524 fwohci_handler_set(struct fwohci_softc *sc, 1525 int tcode, u_int32_t key1, u_int32_t key2, 1526 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1527 void *arg) 1528 { 1529 struct fwohci_ctx *fc; 1530 struct fwohci_handler *fh; 1531 int i, j; 1532 1533 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1534 int isasync = key1 & OHCI_ASYNC_STREAM; 1535 1536 key1 &= IEEE1394_ISOCH_MASK; 1537 j = sc->sc_isoctx; 1538 fh = NULL; 1539 for (i = 0; i < sc->sc_isoctx; i++) { 1540 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1541 if (j == sc->sc_isoctx) 1542 j = i; 1543 continue; 1544 } 1545 fh = LIST_FIRST(&fc->fc_handler); 1546 if (fh->fh_tcode == tcode && 1547 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1548 break; 1549 fh = NULL; 1550 } 1551 if (fh == NULL) { 1552 if (handler == NULL) 1553 return 0; 1554 if (j == sc->sc_isoctx) { 1555 DPRINTF(("fwohci_handler_set: no more free " 1556 "context\n")); 1557 return ENOMEM; 1558 } 1559 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1560 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j, 1561 isasync ? FWOHCI_CTX_ISO_SINGLE : 1562 FWOHCI_CTX_ISO_MULTI); 1563 sc->sc_ctx_ir[j] = fc; 1564 } 1565 } 1566 } else { 1567 switch (tcode) { 1568 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1569 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1570 case IEEE1394_TCODE_READ_REQ_QUAD: 1571 case IEEE1394_TCODE_READ_REQ_BLOCK: 1572 case IEEE1394_TCODE_LOCK_REQ: 1573 fc = sc->sc_ctx_arrq; 1574 break; 1575 case IEEE1394_TCODE_WRITE_RESP: 1576 case IEEE1394_TCODE_READ_RESP_QUAD: 1577 case IEEE1394_TCODE_READ_RESP_BLOCK: 1578 case IEEE1394_TCODE_LOCK_RESP: 1579 fc = sc->sc_ctx_arrs; 1580 break; 1581 default: 1582 return EIO; 1583 } 1584 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1585 fh = LIST_NEXT(fh, fh_list)) { 1586 if (fh->fh_tcode == tcode && 1587 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1588 break; 1589 } 1590 } 1591 if (handler == NULL) { 1592 if (fh != NULL) { 1593 LIST_REMOVE(fh, fh_list); 1594 free(fh, M_DEVBUF); 1595 } 1596 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1597 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1598 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1599 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1600 fwohci_ctx_free(sc, fc); 1601 } 1602 return 0; 1603 } 1604 if (fh == NULL) { 1605 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1606 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1607 } 1608 fh->fh_tcode = tcode; 1609 fh->fh_key1 = key1; 1610 fh->fh_key2 = key2; 1611 fh->fh_handler = handler; 1612 fh->fh_handarg = arg; 1613 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1614 fc->fc_ctx, tcode, key1, key2)); 1615 1616 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1617 fwohci_ctx_init(sc, fc); 1618 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1619 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1620 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1621 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1622 } 1623 return 0; 1624 } 1625 1626 /* 1627 * Asyncronous Receive Requests input frontend. 1628 */ 1629 static void 1630 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1631 { 1632 int rcode; 1633 u_int32_t key1, key2; 1634 struct fwohci_handler *fh; 1635 struct fwohci_pkt pkt, res; 1636 1637 /* 1638 * Do not return if next packet is in the buffer, or the next 1639 * packet cannot be received until the next receive interrupt. 1640 */ 1641 while (fwohci_buf_input(sc, fc, &pkt)) { 1642 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1643 fwohci_phy_input(sc, &pkt); 1644 continue; 1645 } 1646 key1 = pkt.fp_hdr[1] & 0xffff; 1647 key2 = pkt.fp_hdr[2]; 1648 memset(&res, 0, sizeof(res)); 1649 res.fp_uio.uio_rw = UIO_WRITE; 1650 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1651 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1652 fh = LIST_NEXT(fh, fh_list)) { 1653 if (pkt.fp_tcode == fh->fh_tcode && 1654 key1 == fh->fh_key1 && 1655 key2 == fh->fh_key2) { 1656 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1657 &pkt); 1658 break; 1659 } 1660 } 1661 if (fh == NULL) { 1662 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1663 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1664 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1665 key2)); 1666 } 1667 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1668 OHCI_CTXCTL_EVENT_ACK_PENDING) 1669 continue; 1670 if (rcode != -1) 1671 fwohci_atrs_output(sc, rcode, &pkt, &res); 1672 } 1673 fwohci_buf_next(sc, fc); 1674 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1675 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1676 } 1677 1678 1679 /* 1680 * Asynchronous Receive Response input frontend. 1681 */ 1682 static void 1683 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1684 { 1685 struct fwohci_pkt pkt; 1686 struct fwohci_handler *fh; 1687 u_int16_t srcid; 1688 int rcode, tlabel; 1689 1690 while (fwohci_buf_input(sc, fc, &pkt)) { 1691 srcid = pkt.fp_hdr[1] >> 16; 1692 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1693 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1694 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1695 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1696 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1697 pkt.fp_dlen)); 1698 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1699 fh = LIST_NEXT(fh, fh_list)) { 1700 if (pkt.fp_tcode == fh->fh_tcode && 1701 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1702 tlabel == fh->fh_key2) { 1703 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1704 LIST_REMOVE(fh, fh_list); 1705 free(fh, M_DEVBUF); 1706 break; 1707 } 1708 } 1709 if (fh == NULL) 1710 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1711 } 1712 fwohci_buf_next(sc, fc); 1713 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1714 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1715 } 1716 1717 /* 1718 * Isochronous Receive input frontend. 1719 */ 1720 static void 1721 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1722 { 1723 int rcode, chan, tag; 1724 struct iovec *iov; 1725 struct fwohci_handler *fh; 1726 struct fwohci_pkt pkt; 1727 1728 #if DOUBLEBUF 1729 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1730 struct fwohci_buf *fb; 1731 int i; 1732 u_int32_t reg; 1733 1734 /* stop dma engine before read buffer */ 1735 reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, 1736 OHCI_SUBREG_ContextControlClear); 1737 DPRINTFN(5, ("ir_input %08x =>", reg)); 1738 if (reg & OHCI_CTXCTL_RUN) { 1739 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1740 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1741 } 1742 DPRINTFN(5, (" %08x\n", OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlClear))); 1743 1744 i = 0; 1745 while ((reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet)) & OHCI_CTXCTL_ACTIVE) { 1746 delay(10); 1747 if (++i > 10000) { 1748 printf("cannot stop dma engine 0x%08x\n", reg); 1749 return; 1750 } 1751 } 1752 1753 /* rotate dma buffer */ 1754 fb = TAILQ_FIRST(&fc->fc_buf2); 1755 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_CommandPtr, 1756 fb->fb_daddr | 1); 1757 /* start dma engine */ 1758 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1759 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1760 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, 1761 (1 << fc->fc_ctx)); 1762 } 1763 #endif 1764 1765 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 1766 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1767 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1768 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode 0x%0x, hlen %d" 1769 ", dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1770 pkt.fp_dlen)); 1771 if (tag == IEEE1394_TAG_GASP) { 1772 /* 1773 * The pkt with tag=3 is GASP format. 1774 * Move GASP header to header part. 1775 */ 1776 if (pkt.fp_dlen < 8) 1777 continue; 1778 iov = pkt.fp_iov; 1779 /* assuming pkt per buffer mode */ 1780 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1781 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1782 iov->iov_base = (caddr_t)iov->iov_base + 8; 1783 iov->iov_len -= 8; 1784 pkt.fp_hlen += 8; 1785 pkt.fp_dlen -= 8; 1786 } 1787 sc->sc_isopktcnt.ev_count++; 1788 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1789 fh = LIST_NEXT(fh, fh_list)) { 1790 if (pkt.fp_tcode == fh->fh_tcode && 1791 chan == fh->fh_key1 && tag == fh->fh_key2) { 1792 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1793 &pkt); 1794 break; 1795 } 1796 } 1797 #ifdef FW_DEBUG 1798 if (fh == NULL) { 1799 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1800 } else { 1801 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1802 } 1803 #endif 1804 } 1805 fwohci_buf_next(sc, fc); 1806 1807 if (fc->fc_type == FWOHCI_CTX_ISO_SINGLE) { 1808 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1809 OHCI_SUBREG_ContextControlSet, 1810 OHCI_CTXCTL_WAKE); 1811 } 1812 } 1813 1814 /* 1815 * Asynchronous Transmit common routine. 1816 */ 1817 static int 1818 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1819 struct fwohci_pkt *pkt) 1820 { 1821 struct fwohci_buf *fb; 1822 struct fwohci_desc *fd; 1823 struct mbuf *m, *m0; 1824 int i, ndesc, error, off, len; 1825 u_int32_t val; 1826 #ifdef FW_DEBUG 1827 struct iovec *iov; 1828 #endif 1829 1830 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 1831 /* We can't send anything during selfid duration */ 1832 return EAGAIN; 1833 1834 #ifdef FW_DEBUG 1835 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, hlen %d, dlen %d", 1836 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1837 for (i = 0; i < pkt->fp_hlen/4; i++) 1838 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 1839 DPRINTFN(2, ("$")); 1840 for (ndesc = 0, iov = pkt->fp_iov; 1841 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1842 for (i = 0; i < iov->iov_len; i++) 1843 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 1844 ((u_int8_t *)iov->iov_base)[i])); 1845 DPRINTFN(2, ("$")); 1846 } 1847 DPRINTFN(1, ("\n")); 1848 #endif 1849 1850 if ((m = pkt->fp_m) != NULL) { 1851 for (ndesc = 2; m != NULL; m = m->m_next) 1852 ndesc++; 1853 if (ndesc > OHCI_DESC_MAX) { 1854 m0 = NULL; 1855 ndesc = 2; 1856 for (off = 0; off < pkt->fp_dlen; off += len) { 1857 if (m0 == NULL) { 1858 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1859 if (m0 != NULL) 1860 M_COPY_PKTHDR(m0, pkt->fp_m); 1861 m = m0; 1862 } else { 1863 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1864 m = m->m_next; 1865 } 1866 if (m != NULL) 1867 MCLGET(m, M_DONTWAIT); 1868 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1869 m_freem(m0); 1870 return ENOMEM; 1871 } 1872 len = pkt->fp_dlen - off; 1873 if (len > m->m_ext.ext_size) 1874 len = m->m_ext.ext_size; 1875 m_copydata(pkt->fp_m, off, len, 1876 mtod(m, caddr_t)); 1877 m->m_len = len; 1878 ndesc++; 1879 } 1880 m_freem(pkt->fp_m); 1881 pkt->fp_m = m0; 1882 } 1883 } else 1884 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1885 1886 if (ndesc > OHCI_DESC_MAX) 1887 return ENOBUFS; 1888 1889 if (fc->fc_bufcnt > 50) /*XXX*/ 1890 return ENOBUFS; 1891 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1892 fb->fb_nseg = ndesc; 1893 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1894 if (fb->fb_desc == NULL) { 1895 free(fb, M_DEVBUF); 1896 return ENOBUFS; 1897 } 1898 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1899 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1900 fb->fb_m = pkt->fp_m; 1901 fb->fb_callback = pkt->fp_callback; 1902 fb->fb_statuscb = pkt->fp_statuscb; 1903 fb->fb_statusarg = pkt->fp_statusarg; 1904 1905 if (ndesc > 2) { 1906 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1907 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1908 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1909 free(fb, M_DEVBUF); 1910 return error; 1911 } 1912 1913 if (pkt->fp_m != NULL) 1914 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1915 pkt->fp_m, BUS_DMA_WAITOK); 1916 else 1917 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1918 &pkt->fp_uio, BUS_DMA_WAITOK); 1919 if (error != 0) { 1920 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1921 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1922 free(fb, M_DEVBUF); 1923 return error; 1924 } 1925 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1926 BUS_DMASYNC_PREWRITE); 1927 } 1928 1929 fd = fb->fb_desc; 1930 fd->fd_flags = OHCI_DESC_IMMED; 1931 fd->fd_reqcount = pkt->fp_hlen; 1932 fd->fd_data = 0; 1933 fd->fd_branch = 0; 1934 fd->fd_status = 0; 1935 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1936 i = 3; /* XXX: 3 sec */ 1937 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1938 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1939 ((((val >> 25) + i) & 0x7) << 13); 1940 } else 1941 fd->fd_timestamp = 0; 1942 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1943 for (i = 0; i < ndesc - 2; i++) { 1944 fd = fb->fb_desc + 2 + i; 1945 fd->fd_flags = 0; 1946 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1947 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1948 fd->fd_branch = 0; 1949 fd->fd_status = 0; 1950 fd->fd_timestamp = 0; 1951 } 1952 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1953 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1954 1955 #ifdef FW_DEBUG 1956 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1957 (long)(fb->fb_desc - sc->sc_desc))); 1958 for (i = 0; i < ndesc * 4; i++) 1959 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1960 ((u_int32_t *)fb->fb_desc)[i])); 1961 DPRINTFN(1, ("\n")); 1962 #endif 1963 1964 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1965 OHCI_SUBREG_ContextControlClear); 1966 1967 if (val & OHCI_CTXCTL_RUN) { 1968 if (fc->fc_branch == NULL) { 1969 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1970 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1971 goto run; 1972 } 1973 *fc->fc_branch = fb->fb_daddr | ndesc; 1974 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1975 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1976 } else { 1977 run: 1978 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1979 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1980 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1981 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1982 } 1983 fc->fc_branch = &fd->fd_branch; 1984 1985 fc->fc_bufcnt++; 1986 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1987 pkt->fp_m = NULL; 1988 return 0; 1989 } 1990 1991 static void 1992 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 1993 { 1994 struct fwohci_buf *fb; 1995 struct fwohci_desc *fd; 1996 struct fwohci_pkt pkt; 1997 int i; 1998 1999 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 2000 fd = fb->fb_desc; 2001 #ifdef FW_DEBUG 2002 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 2003 force ? "force " : "", (long)(fd - sc->sc_desc), 2004 fb->fb_nseg)); 2005 for (i = 0; i < fb->fb_nseg * 4; i++) 2006 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 2007 ((u_int32_t *)fd)[i])); 2008 DPRINTFN(1, ("\n")); 2009 #endif 2010 if (fb->fb_nseg > 2) 2011 fd += fb->fb_nseg - 1; 2012 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 2013 break; 2014 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 2015 if (fc->fc_branch == &fd->fd_branch) { 2016 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2017 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2018 fc->fc_branch = NULL; 2019 for (i = 0; i < OHCI_LOOP; i++) { 2020 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 2021 OHCI_SUBREG_ContextControlClear) & 2022 OHCI_CTXCTL_ACTIVE)) 2023 break; 2024 DELAY(10); 2025 } 2026 } 2027 2028 if (fb->fb_statuscb) { 2029 memset(&pkt, 0, sizeof(pkt)); 2030 pkt.fp_status = fd->fd_status; 2031 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 2032 2033 /* Indicate this is just returning the status bits. */ 2034 pkt.fp_tcode = -1; 2035 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 2036 fb->fb_statuscb = NULL; 2037 fb->fb_statusarg = NULL; 2038 } 2039 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 2040 if (fb->fb_nseg > 2) 2041 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 2042 fc->fc_bufcnt--; 2043 if (fb->fb_callback) { 2044 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 2045 fb->fb_callback = NULL; 2046 } else if (fb->fb_m != NULL) 2047 m_freem(fb->fb_m); 2048 free(fb, M_DEVBUF); 2049 } 2050 } 2051 2052 /* 2053 * Asynchronous Transmit Reponse -- in response of request packet. 2054 */ 2055 static void 2056 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 2057 struct fwohci_pkt *res) 2058 { 2059 2060 if (((*req->fp_trail & 0x001f0000) >> 16) != 2061 OHCI_CTXCTL_EVENT_ACK_PENDING) 2062 return; 2063 2064 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 2065 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 2066 switch (req->fp_tcode) { 2067 case IEEE1394_TCODE_WRITE_REQ_QUAD: 2068 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 2069 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 2070 res->fp_hlen = 12; 2071 break; 2072 case IEEE1394_TCODE_READ_REQ_QUAD: 2073 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2074 res->fp_hlen = 16; 2075 res->fp_dlen = 0; 2076 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 2077 res->fp_hdr[3] = 2078 *(u_int32_t *)res->fp_iov[0].iov_base; 2079 res->fp_uio.uio_iovcnt = 0; 2080 break; 2081 case IEEE1394_TCODE_READ_REQ_BLOCK: 2082 case IEEE1394_TCODE_LOCK_REQ: 2083 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 2084 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 2085 else 2086 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2087 res->fp_hlen = 16; 2088 res->fp_dlen = res->fp_uio.uio_resid; 2089 res->fp_hdr[3] = res->fp_dlen << 16; 2090 break; 2091 } 2092 res->fp_hdr[0] |= (res->fp_tcode << 4); 2093 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 2094 } 2095 2096 /* 2097 * APPLICATION LAYER SERVICES 2098 */ 2099 2100 /* 2101 * Retrieve Global UID from GUID ROM 2102 */ 2103 static int 2104 fwohci_guidrom_init(struct fwohci_softc *sc) 2105 { 2106 int i, n, off; 2107 u_int32_t val1, val2; 2108 2109 /* Extract the Global UID 2110 */ 2111 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 2112 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 2113 2114 if (val1 != 0 || val2 != 0) { 2115 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 2116 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 2117 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 2118 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 2119 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 2120 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 2121 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 2122 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 2123 } else { 2124 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 2125 if ((val1 & OHCI_Version_GUID_ROM) == 0) 2126 return -1; 2127 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 2128 for (i = 0; i < OHCI_LOOP; i++) { 2129 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2130 if (!(val1 & OHCI_Guid_AddrReset)) 2131 break; 2132 DELAY(10); 2133 } 2134 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 2135 val2 = 0; 2136 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 2137 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 2138 OHCI_Guid_RdStart); 2139 for (i = 0; i < OHCI_LOOP; i++) { 2140 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2141 if (!(val1 & OHCI_Guid_RdStart)) 2142 break; 2143 DELAY(10); 2144 } 2145 if (n < off) 2146 continue; 2147 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 2148 sc->sc_sc1394.sc1394_guid[n - off] = val1; 2149 val2 |= val1; 2150 } 2151 if (val2 == 0) 2152 return -1; 2153 } 2154 return 0; 2155 } 2156 2157 /* 2158 * Initialization for Configuration ROM (no DMA context) 2159 */ 2160 2161 #define CFR_MAXUNIT 20 2162 2163 struct configromctx { 2164 u_int32_t *ptr; 2165 int curunit; 2166 struct { 2167 u_int32_t *start; 2168 int length; 2169 u_int32_t *refer; 2170 int refunit; 2171 } unit[CFR_MAXUNIT]; 2172 }; 2173 2174 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 2175 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 2176 2177 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 2178 2179 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 2180 2181 #define CFR_PUT_CRC(cfr, n) \ 2182 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 2183 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 2184 2185 #define CFR_START_UNIT(cfr, n) \ 2186 do { \ 2187 if ((cfr)->unit[n].refer != NULL) { \ 2188 *(cfr)->unit[n].refer |= \ 2189 (cfr)->ptr - (cfr)->unit[n].refer; \ 2190 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 2191 } \ 2192 (cfr)->curunit = (n); \ 2193 (cfr)->unit[n].start = (cfr)->ptr++; \ 2194 } while (0 /* CONSTCOND */) 2195 2196 #define CFR_PUT_REFER(cfr, key, n) \ 2197 do { \ 2198 (cfr)->unit[n].refer = (cfr)->ptr; \ 2199 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2200 *(cfr)->ptr++ = (key) << 24; \ 2201 } while (0 /* CONSTCOND */) 2202 2203 #define CFR_END_UNIT(cfr) \ 2204 do { \ 2205 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2206 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2207 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2208 } while (0 /* CONSTCOND */) 2209 2210 static u_int16_t 2211 fwohci_crc16(u_int32_t *ptr, int len) 2212 { 2213 int shift; 2214 u_int32_t crc, sum, data; 2215 2216 crc = 0; 2217 while (len-- > 0) { 2218 data = *ptr++; 2219 for (shift = 28; shift >= 0; shift -= 4) { 2220 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2221 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2222 } 2223 crc &= 0xffff; 2224 } 2225 return crc; 2226 } 2227 2228 static void 2229 fwohci_configrom_init(struct fwohci_softc *sc) 2230 { 2231 int i, val; 2232 struct fwohci_buf *fb; 2233 u_int32_t *hdr; 2234 struct configromctx cfr; 2235 2236 fb = &sc->sc_buf_cnfrom; 2237 memset(&cfr, 0, sizeof(cfr)); 2238 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2239 2240 /* headers */ 2241 CFR_START_UNIT(&cfr, 0); 2242 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2243 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2244 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2245 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2246 CFR_END_UNIT(&cfr); 2247 /* copy info_length from crc_length */ 2248 *hdr |= (*hdr & 0x00ff0000) << 8; 2249 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2250 2251 /* root directory */ 2252 CFR_START_UNIT(&cfr, 1); 2253 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2254 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2255 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2256 /* spt,64,fix,lst,drq */ 2257 #ifdef INET 2258 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2259 #endif /* INET */ 2260 #ifdef INET6 2261 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2262 #endif /* INET6 */ 2263 CFR_END_UNIT(&cfr); 2264 2265 CFR_START_UNIT(&cfr, 2); 2266 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2267 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2268 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2269 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2270 CFR_END_UNIT(&cfr); 2271 2272 #ifdef INET 2273 /* IPv4 unit directory */ 2274 CFR_START_UNIT(&cfr, 3); 2275 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2276 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2277 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2278 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2279 CFR_PUT_REFER(&cfr, 0x95, 8); /* Unit location */ 2280 CFR_END_UNIT(&cfr); 2281 2282 CFR_START_UNIT(&cfr, 6); 2283 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2284 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2285 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2286 CFR_END_UNIT(&cfr); 2287 2288 CFR_START_UNIT(&cfr, 7); 2289 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2290 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2291 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2292 CFR_END_UNIT(&cfr); 2293 2294 CFR_START_UNIT(&cfr, 8); /* Spec's valid addr range. */ 2295 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2296 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2297 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2298 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2299 CFR_END_UNIT(&cfr); 2300 2301 #endif /* INET */ 2302 2303 #ifdef INET6 2304 /* IPv6 unit directory */ 2305 CFR_START_UNIT(&cfr, 4); 2306 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2307 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2308 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2309 /* XXX: TBA by IANA */ 2310 CFR_PUT_REFER(&cfr, 0x81, 10); /* textual descriptor offset */ 2311 CFR_PUT_REFER(&cfr, 0x95, 11); /* Unit location */ 2312 CFR_END_UNIT(&cfr); 2313 2314 CFR_START_UNIT(&cfr, 9); 2315 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2316 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2317 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2318 CFR_END_UNIT(&cfr); 2319 2320 CFR_START_UNIT(&cfr, 10); 2321 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2322 CFR_PUT_DATA1(&cfr, 0); 2323 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2324 CFR_END_UNIT(&cfr); 2325 2326 CFR_START_UNIT(&cfr, 11); /* Spec's valid addr range. */ 2327 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2328 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2329 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2330 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2331 CFR_END_UNIT(&cfr); 2332 2333 #endif /* INET6 */ 2334 2335 fb->fb_off = cfr.ptr - hdr; 2336 #ifdef FW_DEBUG 2337 DPRINTF(("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2338 for (i = 0; i < fb->fb_off; i++) 2339 DPRINTF(("%s%08x", i&7?" ":"\n ", hdr[i])); 2340 DPRINTF(("\n")); 2341 #endif /* FW_DEBUG */ 2342 2343 /* 2344 * Make network byte order for DMA 2345 */ 2346 for (i = 0; i < fb->fb_off; i++) 2347 HTONL(hdr[i]); 2348 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2349 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2350 2351 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2352 fb->fb_dmamap->dm_segs[0].ds_addr); 2353 2354 /* This register is only valid on OHCI 1.1. */ 2355 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2356 if ((OHCI_Version_GET_Version(val) == 1) && 2357 (OHCI_Version_GET_Revision(val) == 1)) 2358 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2359 OHCI_HCControl_BIBImageValid); 2360 2361 /* Just allow quad reads of the rom. */ 2362 for (i = 0; i < fb->fb_off; i++) 2363 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2364 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2365 fwohci_configrom_input, NULL); 2366 } 2367 2368 static int 2369 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2370 struct fwohci_pkt *pkt) 2371 { 2372 struct fwohci_pkt res; 2373 u_int32_t loc, *rom; 2374 2375 /* This will be used as an array index so size accordingly. */ 2376 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2377 if ((loc & 0x03) != 0) { 2378 /* alignment error */ 2379 return IEEE1394_RCODE_ADDRESS_ERROR; 2380 } 2381 else 2382 loc /= 4; 2383 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2384 2385 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2386 ntohl(rom[loc]))); 2387 2388 memset(&res, 0, sizeof(res)); 2389 res.fp_hdr[3] = rom[loc]; 2390 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2391 return -1; 2392 } 2393 2394 /* 2395 * SelfID buffer (no DMA context) 2396 */ 2397 static void 2398 fwohci_selfid_init(struct fwohci_softc *sc) 2399 { 2400 struct fwohci_buf *fb; 2401 2402 fb = &sc->sc_buf_selfid; 2403 #ifdef DIAGNOSTIC 2404 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2405 panic("fwohci_selfid_init: not aligned: %ld (%ld) %p", 2406 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_addr, 2407 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2408 #endif 2409 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2410 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2411 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2412 2413 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2414 fb->fb_dmamap->dm_segs[0].ds_addr); 2415 } 2416 2417 static int 2418 fwohci_selfid_input(struct fwohci_softc *sc) 2419 { 2420 int i; 2421 u_int32_t count, val, gen; 2422 u_int32_t *buf; 2423 2424 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2425 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2426 again: 2427 if (val & OHCI_SelfID_Error) { 2428 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2429 return -1; 2430 } 2431 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2432 2433 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2434 0, count << 2, BUS_DMASYNC_POSTREAD); 2435 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2436 2437 #ifdef FW_DEBUG 2438 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2439 val)); 2440 for (i = 0; i < count; i++) 2441 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2442 DPRINTFN(1, ("\n")); 2443 #endif /* FW_DEBUG */ 2444 2445 for (i = 1; i < count; i += 2) { 2446 if (buf[i] != ~buf[i + 1]) 2447 break; 2448 if (buf[i] & 0x00000001) 2449 continue; /* more pkt */ 2450 if (buf[i] & 0x00800000) 2451 continue; /* external id */ 2452 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2453 if ((buf[i] & 0x00400800) == 0x00400800) 2454 sc->sc_irmid = sc->sc_rootid; 2455 } 2456 2457 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2458 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2459 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2460 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2461 goto again; 2462 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2463 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2464 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2465 return -1; 2466 } 2467 if (i != count) { 2468 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2469 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2470 #if 1 2471 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2472 /* 2473 * XXX: CXD3222 sometimes fails to DMA 2474 * selfid packet?? 2475 */ 2476 sc->sc_rootid = (count - 1) / 2 - 1; 2477 sc->sc_irmid = sc->sc_rootid; 2478 } else 2479 #endif 2480 return -1; 2481 } 2482 2483 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2484 if ((val & OHCI_NodeId_IDValid) == 0) { 2485 sc->sc_nodeid = 0xffff; /* invalid */ 2486 printf("%s: nodeid is invalid\n", 2487 sc->sc_sc1394.sc1394_dev.dv_xname); 2488 return -1; 2489 } 2490 sc->sc_nodeid = val & 0xffff; 2491 2492 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2493 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2494 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2495 sc->sc_irmid)); 2496 2497 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2498 return -1; 2499 2500 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2501 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2502 OHCI_LinkControl_CycleMaster); 2503 else 2504 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2505 OHCI_LinkControl_CycleMaster); 2506 return 0; 2507 } 2508 2509 /* 2510 * some CSRs are handled by driver. 2511 */ 2512 static void 2513 fwohci_csr_init(struct fwohci_softc *sc) 2514 { 2515 int i; 2516 static u_int32_t csr[] = { 2517 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2518 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2519 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2520 CSR_SB_BROADCAST_CHANNEL 2521 }; 2522 2523 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2524 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2525 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2526 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2527 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2528 } 2529 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2530 } 2531 2532 static int 2533 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2534 { 2535 struct fwohci_pkt res; 2536 u_int32_t reg; 2537 2538 /* 2539 * XXX need to do special functionality other than just r/w... 2540 */ 2541 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2542 2543 if ((reg & 0x03) != 0) { 2544 /* alignment error */ 2545 return IEEE1394_RCODE_ADDRESS_ERROR; 2546 } 2547 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2548 *(u_int32_t *)(&sc->sc_csr[reg]))); 2549 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2550 DPRINTFN(1, (" -> 0x%08x\n", 2551 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2552 *(u_int32_t *)&sc->sc_csr[reg] = 2553 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2554 } else { 2555 DPRINTFN(1, ("\n")); 2556 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2557 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2558 res.fp_iov[0].iov_len = 4; 2559 res.fp_uio.uio_resid = 4; 2560 res.fp_uio.uio_iovcnt = 1; 2561 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2562 return -1; 2563 } 2564 return IEEE1394_RCODE_COMPLETE; 2565 } 2566 2567 /* 2568 * Mapping between nodeid and unique ID (EUI-64). 2569 * 2570 * Track old mappings and simply update their devices with the new id's when 2571 * they match an existing EUI. This allows proper renumeration of the bus. 2572 */ 2573 static void 2574 fwohci_uid_collect(struct fwohci_softc *sc) 2575 { 2576 int i; 2577 struct fwohci_uidtbl *fu; 2578 struct ieee1394_softc *iea; 2579 2580 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2581 iea->sc1394_node_id = 0xffff; 2582 2583 if (sc->sc_uidtbl != NULL) 2584 free(sc->sc_uidtbl, M_DEVBUF); 2585 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2586 M_NOWAIT|M_ZERO); /* XXX M_WAITOK requires locks */ 2587 if (sc->sc_uidtbl == NULL) 2588 return; 2589 2590 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2591 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2592 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2593 fu->fu_valid = 3; 2594 2595 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2596 if (iea) { 2597 iea->sc1394_node_id = i; 2598 DPRINTF(("%s: Updating nodeid to %d\n", 2599 iea->sc1394_dev.dv_xname, 2600 iea->sc1394_node_id)); 2601 } 2602 } else { 2603 fu->fu_valid = 0; 2604 fwohci_uid_req(sc, i); 2605 } 2606 } 2607 if (sc->sc_rootid == 0) 2608 fwohci_check_nodes(sc); 2609 } 2610 2611 static void 2612 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 2613 { 2614 struct fwohci_pkt pkt; 2615 2616 memset(&pkt, 0, sizeof(pkt)); 2617 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2618 pkt.fp_hlen = 12; 2619 pkt.fp_dlen = 0; 2620 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2621 (pkt.fp_tcode << 4); 2622 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 2623 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2624 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2625 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2626 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2627 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2628 2629 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2630 (pkt.fp_tcode << 4); 2631 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2632 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2633 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2634 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2635 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2636 } 2637 2638 static int 2639 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2640 { 2641 struct fwohci_uidtbl *fu; 2642 struct ieee1394_softc *iea; 2643 struct ieee1394_attach_args fwa; 2644 int i, n, done, rcode, found; 2645 2646 found = 0; 2647 2648 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2649 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2650 if (rcode != IEEE1394_RCODE_COMPLETE || 2651 sc->sc_uidtbl == NULL || 2652 n > sc->sc_rootid) 2653 return 0; 2654 fu = &sc->sc_uidtbl[n]; 2655 if (arg == 0) { 2656 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2657 fu->fu_valid |= 0x1; 2658 } else { 2659 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2660 fu->fu_valid |= 0x2; 2661 } 2662 #ifdef FW_DEBUG 2663 if (fu->fu_valid == 0x3) 2664 DPRINTFN(1, ("fwohci_uid_input: " 2665 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2666 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2667 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2668 #endif 2669 if (fu->fu_valid == 0x3) { 2670 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2671 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2672 found = 1; 2673 iea->sc1394_node_id = n; 2674 DPRINTF(("%s: Updating nodeid to %d\n", 2675 iea->sc1394_dev.dv_xname, 2676 iea->sc1394_node_id)); 2677 if (iea->sc1394_callback.sc1394_reset) 2678 iea->sc1394_callback.sc1394_reset(iea, 2679 iea->sc1394_callback.sc1394_resetarg); 2680 break; 2681 } 2682 if (!found) { 2683 strcpy(fwa.name, "fwnode"); 2684 memcpy(fwa.uid, fu->fu_uid, 8); 2685 fwa.nodeid = n; 2686 iea = (struct ieee1394_softc *) 2687 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2688 fwohci_print, fwohci_submatch); 2689 if (iea != NULL) 2690 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2691 sc1394_node); 2692 } 2693 } 2694 done = 1; 2695 2696 for (i = 0; i < sc->sc_rootid + 1; i++) { 2697 fu = &sc->sc_uidtbl[i]; 2698 if (fu->fu_valid != 0x3) { 2699 done = 0; 2700 break; 2701 } 2702 } 2703 if (done) 2704 fwohci_check_nodes(sc); 2705 2706 return 0; 2707 } 2708 2709 static void 2710 fwohci_check_nodes(struct fwohci_softc *sc) 2711 { 2712 struct device *detach = NULL; 2713 struct ieee1394_softc *iea; 2714 2715 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2716 2717 /* 2718 * Have to defer detachment until the next 2719 * loop iteration since config_detach 2720 * free's the softc and the loop iterator 2721 * needs data from the softc to move 2722 * forward. 2723 */ 2724 2725 if (detach) { 2726 config_detach(detach, 0); 2727 detach = NULL; 2728 } 2729 if (iea->sc1394_node_id == 0xffff) { 2730 detach = (struct device *)iea; 2731 LIST_REMOVE(iea, sc1394_node); 2732 } 2733 } 2734 if (detach) 2735 config_detach(detach, 0); 2736 } 2737 2738 static int 2739 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2740 { 2741 struct fwohci_uidtbl *fu; 2742 int n; 2743 static const u_int8_t bcast[] = 2744 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2745 2746 fu = sc->sc_uidtbl; 2747 if (fu == NULL) { 2748 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2749 return IEEE1394_BCAST_PHY_ID; 2750 fwohci_uid_collect(sc); /* try to get */ 2751 return -1; 2752 } 2753 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 2754 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2755 return n; 2756 } 2757 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2758 return IEEE1394_BCAST_PHY_ID; 2759 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 2760 if (fu->fu_valid != 0x3) { 2761 /* 2762 * XXX: need timer before retransmission 2763 */ 2764 fwohci_uid_req(sc, n); 2765 } 2766 } 2767 return -1; 2768 } 2769 2770 /* 2771 * functions to support network interface 2772 */ 2773 static int 2774 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2775 void (*handler)(struct device *, struct mbuf *)) 2776 { 2777 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2778 2779 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2780 handler ? fwohci_if_input : NULL, handler); 2781 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2782 (sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & IEEE1394_ISOCH_MASK) | 2783 OHCI_ASYNC_STREAM, 2784 IEEE1394_TAG_GASP, handler ? fwohci_if_input : NULL, handler); 2785 return 0; 2786 } 2787 2788 static int 2789 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2790 { 2791 int n, len; 2792 struct mbuf *m; 2793 struct iovec *iov; 2794 void (*handler)(struct device *, struct mbuf *) = arg; 2795 2796 #ifdef FW_DEBUG 2797 int i; 2798 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2799 pkt->fp_dlen)); 2800 for (i = 0; i < pkt->fp_hlen/4; i++) 2801 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2802 DPRINTFN(2, ("$")); 2803 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2804 iov = &pkt->fp_iov[n]; 2805 for (i = 0; i < iov->iov_len; i++) 2806 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2807 ((u_int8_t *)iov->iov_base)[i])); 2808 DPRINTFN(2, ("$")); 2809 } 2810 DPRINTFN(1, ("\n")); 2811 #endif /* FW_DEBUG */ 2812 len = pkt->fp_dlen; 2813 MGETHDR(m, M_DONTWAIT, MT_DATA); 2814 if (m == NULL) 2815 return IEEE1394_RCODE_COMPLETE; 2816 m->m_len = 16; 2817 if (len + m->m_len > MHLEN) { 2818 MCLGET(m, M_DONTWAIT); 2819 if ((m->m_flags & M_EXT) == 0) { 2820 m_freem(m); 2821 return IEEE1394_RCODE_COMPLETE; 2822 } 2823 } 2824 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2825 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2826 sc->sc_uidtbl[n].fu_valid != 0x3) { 2827 printf("%s: packet from unknown node: phy id %d\n", 2828 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2829 m_freem(m); 2830 fwohci_uid_req(sc, n); 2831 return IEEE1394_RCODE_COMPLETE; 2832 } 2833 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2834 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2835 m->m_flags |= M_BCAST; 2836 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2837 } else { 2838 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2839 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2840 } 2841 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2842 mtod(m, u_int8_t *)[9] = 2843 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2844 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2845 2846 m->m_pkthdr.rcvif = NULL; /* set in child */ 2847 m->m_pkthdr.len = len + m->m_len; 2848 /* 2849 * We may use receive buffer by external mbuf instead of copy here. 2850 * But asynchronous receive buffer must be operate in buffer fill 2851 * mode, so that each receive buffer will shared by multiple mbufs. 2852 * If upper layer doesn't free mbuf soon, e.g. application program 2853 * is suspended, buffer must be reallocated. 2854 * Isochronous buffer must be operate in packet buffer mode, and 2855 * it is easy to map receive buffer to external mbuf. But it is 2856 * used for broadcast/multicast only, and is expected not so 2857 * performance sensitive for now. 2858 * XXX: The performance may be important for multicast case, 2859 * so we should revisit here later. 2860 * -- onoe 2861 */ 2862 n = 0; 2863 iov = pkt->fp_uio.uio_iov; 2864 while (len > 0) { 2865 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2866 iov->iov_len); 2867 m->m_len += iov->iov_len; 2868 len -= iov->iov_len; 2869 iov++; 2870 } 2871 (*handler)(sc->sc_sc1394.sc1394_if, m); 2872 return IEEE1394_RCODE_COMPLETE; 2873 } 2874 2875 static int 2876 fwohci_if_input_iso(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2877 { 2878 int n, len; 2879 int chan, tag; 2880 struct mbuf *m; 2881 struct iovec *iov; 2882 void (*handler)(struct device *, struct mbuf *) = arg; 2883 #ifdef FW_DEBUG 2884 int i; 2885 #endif 2886 2887 chan = (pkt->fp_hdr[0] & 0x00003f00) >> 8; 2888 tag = (pkt->fp_hdr[0] & 0x0000c000) >> 14; 2889 #ifdef FW_DEBUG 2890 DPRINTFN(1, ("fwohci_if_input_iso: " 2891 "tcode=0x%x, chan=%d, tag=%x, dlen=%d", 2892 pkt->fp_tcode, chan, tag, pkt->fp_dlen)); 2893 for (i = 0; i < pkt->fp_hlen/4; i++) 2894 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2895 DPRINTFN(2, ("$")); 2896 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2897 iov = &pkt->fp_iov[n]; 2898 for (i = 0; i < iov->iov_len; i++) 2899 DPRINTFN(2, ("%s%02x", 2900 (i%32)?((i%4)?"":" "):"\n\t", 2901 ((u_int8_t *)iov->iov_base)[i])); 2902 DPRINTFN(2, ("$")); 2903 } 2904 DPRINTFN(2, ("\n")); 2905 #endif /* FW_DEBUG */ 2906 len = pkt->fp_dlen; 2907 MGETHDR(m, M_DONTWAIT, MT_DATA); 2908 if (m == NULL) 2909 return IEEE1394_RCODE_COMPLETE; 2910 m->m_len = 16; 2911 if (m->m_len + len > MHLEN) { 2912 MCLGET(m, M_DONTWAIT); 2913 if ((m->m_flags & M_EXT) == 0) { 2914 m_freem(m); 2915 return IEEE1394_RCODE_COMPLETE; 2916 } 2917 } 2918 2919 m->m_flags |= M_BCAST; 2920 2921 if (tag == IEEE1394_TAG_GASP) { 2922 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2923 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2924 sc->sc_uidtbl[n].fu_valid != 0x3) { 2925 printf("%s: packet from unknown node: phy id %d\n", 2926 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2927 m_freem(m); 2928 return IEEE1394_RCODE_COMPLETE; 2929 } 2930 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2931 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2932 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2933 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2934 mtod(m, u_int8_t *)[9] = 2935 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2936 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2937 } 2938 mtod(m, u_int8_t *)[14] = chan; 2939 mtod(m, u_int8_t *)[15] = tag; 2940 2941 2942 m->m_pkthdr.rcvif = NULL; /* set in child */ 2943 m->m_pkthdr.len = len + m->m_len; 2944 /* 2945 * We may use receive buffer by external mbuf instead of copy here. 2946 * But asynchronous receive buffer must be operate in buffer fill 2947 * mode, so that each receive buffer will shared by multiple mbufs. 2948 * If upper layer doesn't free mbuf soon, e.g. application program 2949 * is suspended, buffer must be reallocated. 2950 * Isochronous buffer must be operate in packet buffer mode, and 2951 * it is easy to map receive buffer to external mbuf. But it is 2952 * used for broadcast/multicast only, and is expected not so 2953 * performance sensitive for now. 2954 * XXX: The performance may be important for multicast case, 2955 * so we should revisit here later. 2956 * -- onoe 2957 */ 2958 n = 0; 2959 iov = pkt->fp_uio.uio_iov; 2960 while (len > 0) { 2961 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2962 iov->iov_len); 2963 m->m_len += iov->iov_len; 2964 len -= iov->iov_len; 2965 iov++; 2966 } 2967 (*handler)(sc->sc_sc1394.sc1394_if, m); 2968 return IEEE1394_RCODE_COMPLETE; 2969 } 2970 2971 2972 2973 static int 2974 fwohci_if_output(struct device *self, struct mbuf *m0, 2975 void (*callback)(struct device *, struct mbuf *)) 2976 { 2977 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2978 struct fwohci_pkt pkt; 2979 u_int8_t *p; 2980 int n, error, spd, hdrlen, maxrec; 2981 #ifdef FW_DEBUG 2982 struct mbuf *m; 2983 #endif 2984 2985 p = mtod(m0, u_int8_t *); 2986 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2987 spd = IEEE1394_SPD_S100; /*XXX*/ 2988 maxrec = 512; /*XXX*/ 2989 hdrlen = 8; 2990 } else { 2991 n = fwohci_uid_lookup(sc, p); 2992 if (n < 0) { 2993 printf("%s: nodeid unknown:" 2994 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 2995 sc->sc_sc1394.sc1394_dev.dv_xname, 2996 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 2997 error = EHOSTUNREACH; 2998 goto end; 2999 } 3000 if (n == IEEE1394_BCAST_PHY_ID) { 3001 printf("%s: broadcast with !M_MCAST\n", 3002 sc->sc_sc1394.sc1394_dev.dv_xname); 3003 #ifdef FW_DEBUG 3004 DPRINTFN(2, ("packet:")); 3005 for (m = m0; m != NULL; m = m->m_next) { 3006 for (n = 0; n < m->m_len; n++) 3007 DPRINTFN(2, ("%s%02x", (n%32)? 3008 ((n%4)?"":" "):"\n ", 3009 mtod(m, u_int8_t *)[n])); 3010 DPRINTFN(2, ("$")); 3011 } 3012 DPRINTFN(2, ("\n")); 3013 #endif 3014 error = EHOSTUNREACH; 3015 goto end; 3016 } 3017 maxrec = 2 << p[8]; 3018 spd = p[9]; 3019 hdrlen = 0; 3020 } 3021 if (spd > sc->sc_sc1394.sc1394_link_speed) { 3022 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 3023 spd, sc->sc_sc1394.sc1394_link_speed)); 3024 spd = sc->sc_sc1394.sc1394_link_speed; 3025 } 3026 if (maxrec > (512 << spd)) { 3027 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 3028 "\n", maxrec, spd)); 3029 maxrec = 512 << spd; 3030 } 3031 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 3032 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 3033 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 3034 maxrec >>= 1; 3035 } 3036 if (maxrec < 512) { 3037 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 3038 "minimum\n", maxrec)); 3039 maxrec = 512; 3040 } 3041 3042 m_adj(m0, 16 - hdrlen); 3043 if (m0->m_pkthdr.len > maxrec) { 3044 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 3045 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 3046 error = E2BIG; /*XXX*/ 3047 goto end; 3048 } 3049 3050 memset(&pkt, 0, sizeof(pkt)); 3051 pkt.fp_uio.uio_iov = pkt.fp_iov; 3052 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3053 pkt.fp_uio.uio_rw = UIO_WRITE; 3054 if (m0->m_flags & (M_BCAST | M_MCAST)) { 3055 /* construct GASP header */ 3056 p = mtod(m0, u_int8_t *); 3057 p[0] = sc->sc_nodeid >> 8; 3058 p[1] = sc->sc_nodeid & 0xff; 3059 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 3060 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 3061 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 3062 pkt.fp_hlen = 8; 3063 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 3064 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 3065 OHCI_NodeId_NodeNumber) << 8); 3066 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 3067 } else { 3068 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 3069 pkt.fp_hlen = 16; 3070 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 3071 (spd << 16); 3072 pkt.fp_hdr[1] = 3073 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 3074 (p[10] << 8) | p[11]; 3075 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 3076 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 3077 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3078 } 3079 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 3080 pkt.fp_dlen = m0->m_pkthdr.len; 3081 pkt.fp_m = m0; 3082 pkt.fp_callback = callback; 3083 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3084 m0 = pkt.fp_m; 3085 end: 3086 if (m0 != NULL) { 3087 if (callback) 3088 (*callback)(sc->sc_sc1394.sc1394_if, m0); 3089 else 3090 m_freem(m0); 3091 } 3092 return error; 3093 } 3094 3095 /* 3096 * High level routines to provide abstraction to attaching layers to 3097 * send/receive data. 3098 */ 3099 3100 /* 3101 * These break down into 4 routines as follows: 3102 * 3103 * int fwohci_read(struct ieee1394_abuf *) 3104 * 3105 * This routine will attempt to read a region from the requested node. 3106 * A callback must be provided which will be called when either the completed 3107 * read is done or an unrecoverable error occurs. This is mainly a convenience 3108 * routine since it will encapsulate retrying a region as quadlet vs. block 3109 * reads and recombining all the returned data. This could also be done with a 3110 * series of write/inreg's for each packet sent. 3111 * 3112 * int fwohci_write(struct ieee1394_abuf *) 3113 * 3114 * The work horse main entry point for putting packets on the bus. This is the 3115 * generalized interface for fwnode/etc code to put packets out onto the bus. 3116 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and 3117 * optionally will callback via a func pointer to the calling code with the 3118 * resulting ACK code from the packet. If the ACK code is to be ignored (i.e. 3119 * no cb) then the write routine will take care of free'ing the abuf since the 3120 * fwnode/etc code won't have any knowledge of when to do this. This allows for 3121 * simple one-off packets to be sent from the upper-level code without worrying 3122 * about a callback for cleanup. 3123 * 3124 * int fwohci_inreg(struct ieee1394_abuf *, int) 3125 * 3126 * This is very simple. It evals the abuf passed in and registers an internal 3127 * handler as the callback for packets received for that operation. 3128 * The integer argument specifies whether on a block read/write operation to 3129 * allow sub-regions to be read/written (in block form) as well. 3130 * 3131 * XXX: This whole structure needs to be redone as a list of regions and 3132 * operations allowed on those regions. 3133 * 3134 * int fwohci_unreg(struct ieee1394_abuf *, int) 3135 * 3136 * This simply unregisters the respective callback done via inreg for items 3137 * which only need to register an area for a one-time operation (like a status 3138 * buffer a remote node will write to when the current operation is done). The 3139 * int argument specifies the same behavior as inreg, except in reverse (i.e. 3140 * it unregisters). 3141 */ 3142 3143 static int 3144 fwohci_read(struct ieee1394_abuf *ab) 3145 { 3146 struct fwohci_pkt pkt; 3147 struct ieee1394_softc *sc = ab->ab_req; 3148 struct fwohci_softc *psc = 3149 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3150 struct fwohci_cb *fcb; 3151 u_int32_t high, lo; 3152 int rv, tcode; 3153 3154 /* Have to have a callback when reading. */ 3155 if (ab->ab_cb == NULL) 3156 return -1; 3157 3158 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 3159 fcb->ab = ab; 3160 fcb->count = 0; 3161 fcb->abuf_valid = 1; 3162 3163 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3164 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3165 3166 memset(&pkt, 0, sizeof(pkt)); 3167 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3168 pkt.fp_hdr[2] = lo; 3169 pkt.fp_dlen = 0; 3170 3171 if (ab->ab_length == 4) { 3172 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3173 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 3174 pkt.fp_hlen = 12; 3175 } else { 3176 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 3177 pkt.fp_hlen = 16; 3178 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 3179 pkt.fp_hdr[3] = (ab->ab_length << 16); 3180 } 3181 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3182 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3183 3184 pkt.fp_statusarg = fcb; 3185 pkt.fp_statuscb = fwohci_read_resp; 3186 3187 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3188 psc->sc_tlabel, fwohci_read_resp, fcb); 3189 if (rv) 3190 return rv; 3191 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3192 if (rv) 3193 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3194 psc->sc_tlabel, NULL, NULL); 3195 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3196 fcb->count = 1; 3197 return rv; 3198 } 3199 3200 static int 3201 fwohci_write(struct ieee1394_abuf *ab) 3202 { 3203 struct fwohci_pkt pkt; 3204 struct ieee1394_softc *sc = ab->ab_req; 3205 struct fwohci_softc *psc = 3206 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3207 u_int32_t high, lo; 3208 int rv; 3209 3210 if (ab->ab_length > IEEE1394_MAX_REC(sc->sc1394_max_receive)) { 3211 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 3212 return E2BIG; 3213 } 3214 3215 if (ab->ab_data && ab->ab_uio) 3216 panic("Can't call with uio and data set"); 3217 if ((ab->ab_data == NULL) && (ab->ab_uio == NULL)) 3218 panic("One of either ab_data or ab_uio must be set"); 3219 3220 memset(&pkt, 0, sizeof(pkt)); 3221 3222 pkt.fp_tcode = ab->ab_tcode; 3223 if (ab->ab_data) { 3224 pkt.fp_uio.uio_iov = pkt.fp_iov; 3225 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3226 pkt.fp_uio.uio_rw = UIO_WRITE; 3227 } else 3228 memcpy(&pkt.fp_uio, ab->ab_uio, sizeof(struct uio)); 3229 3230 pkt.fp_statusarg = ab; 3231 pkt.fp_statuscb = fwohci_write_ack; 3232 3233 switch (ab->ab_tcode) { 3234 case IEEE1394_TCODE_WRITE_RESP: 3235 pkt.fp_hlen = 12; 3236 case IEEE1394_TCODE_READ_RESP_QUAD: 3237 case IEEE1394_TCODE_READ_RESP_BLOCK: 3238 if (!pkt.fp_hlen) 3239 pkt.fp_hlen = 16; 3240 high = ab->ab_retlen; 3241 ab->ab_retlen = 0; 3242 lo = 0; 3243 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3244 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 3245 break; 3246 default: 3247 pkt.fp_hlen = 16; 3248 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3249 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3250 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3251 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3252 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3253 break; 3254 } 3255 3256 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3257 pkt.fp_hdr[2] = lo; 3258 if (pkt.fp_hlen == 16) { 3259 if (ab->ab_length == 4) { 3260 pkt.fp_hdr[3] = ab->ab_data[0]; 3261 pkt.fp_dlen = 0; 3262 } else { 3263 pkt.fp_hdr[3] = (ab->ab_length << 16); 3264 pkt.fp_dlen = ab->ab_length; 3265 if (ab->ab_data) { 3266 pkt.fp_uio.uio_iovcnt = 1; 3267 pkt.fp_uio.uio_resid = ab->ab_length; 3268 pkt.fp_iov[0].iov_base = ab->ab_data; 3269 pkt.fp_iov[0].iov_len = ab->ab_length; 3270 } 3271 } 3272 } 3273 switch (ab->ab_tcode) { 3274 case IEEE1394_TCODE_WRITE_RESP: 3275 case IEEE1394_TCODE_READ_RESP_QUAD: 3276 case IEEE1394_TCODE_READ_RESP_BLOCK: 3277 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 3278 break; 3279 default: 3280 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3281 break; 3282 } 3283 return rv; 3284 } 3285 3286 static int 3287 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3288 { 3289 struct fwohci_cb *fcb = arg; 3290 struct ieee1394_abuf *ab = fcb->ab; 3291 struct fwohci_pkt newpkt; 3292 u_int32_t *cur, high, lo; 3293 int i, tcode, rcode, status, rv; 3294 3295 /* 3296 * Both the ACK handling and normal response callbacks are handled here. 3297 * The main reason for this is the various error conditions that can 3298 * occur trying to block read some areas and the ways that gets reported 3299 * back to calling station. This is a variety of ACK codes, responses, 3300 * etc which makes it much more difficult to process if both aren't 3301 * handled here. 3302 */ 3303 3304 /* Check for status packet. */ 3305 3306 if (pkt->fp_tcode == -1) { 3307 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3308 rcode = -1; 3309 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3310 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3311 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3312 DPRINTFN(2, ("Got status packet: 0x%02x\n", 3313 (unsigned int)status)); 3314 fcb->count--; 3315 3316 /* 3317 * Got all the ack's back and the buffer is invalid (i.e. the 3318 * callback has been called. Clean up. 3319 */ 3320 3321 if (fcb->abuf_valid == 0) { 3322 if (fcb->count == 0) 3323 free(fcb, M_DEVBUF); 3324 return IEEE1394_RCODE_COMPLETE; 3325 } 3326 } else { 3327 status = -1; 3328 tcode = pkt->fp_tcode; 3329 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3330 } 3331 3332 /* 3333 * Some area's (like the config rom want to be read as quadlets only. 3334 * 3335 * The current ideas to try are: 3336 * 3337 * Got an ACK_TYPE_ERROR on a block read. 3338 * 3339 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 3340 * response. 3341 * 3342 * In all cases construct a new packet for a quadlet read and let 3343 * mutli_resp handle the iteration over the space. 3344 */ 3345 3346 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 3347 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 3348 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 3349 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 3350 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 3351 3352 /* Read the area in quadlet chunks (internally track this). */ 3353 3354 memset(&newpkt, 0, sizeof(newpkt)); 3355 3356 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3357 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3358 3359 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3360 newpkt.fp_hlen = 12; 3361 newpkt.fp_dlen = 0; 3362 newpkt.fp_hdr[1] = 3363 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3364 newpkt.fp_hdr[2] = lo; 3365 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3366 (newpkt.fp_tcode << 4); 3367 3368 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3369 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3370 fwohci_read_multi_resp, fcb); 3371 if (rv) { 3372 (*ab->ab_cb)(ab, -1); 3373 goto cleanup; 3374 } 3375 newpkt.fp_statusarg = fcb; 3376 newpkt.fp_statuscb = fwohci_read_resp; 3377 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3378 if (rv) { 3379 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3380 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 3381 NULL); 3382 (*ab->ab_cb)(ab, -1); 3383 goto cleanup; 3384 } 3385 fcb->count++; 3386 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3387 return IEEE1394_RCODE_COMPLETE; 3388 } else if ((rcode != -1) || ((status != -1) && 3389 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3390 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3391 3392 /* 3393 * Recombine all the iov data into 1 chunk for higher 3394 * level code. 3395 */ 3396 3397 if (rcode != -1) { 3398 cur = ab->ab_data; 3399 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3400 /* 3401 * Make sure and don't exceed the buffer 3402 * allocated for return. 3403 */ 3404 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3405 ab->ab_length) { 3406 memcpy(cur, pkt->fp_iov[i].iov_base, 3407 (ab->ab_length - ab->ab_retlen)); 3408 ab->ab_retlen = ab->ab_length; 3409 break; 3410 } 3411 memcpy(cur, pkt->fp_iov[i].iov_base, 3412 pkt->fp_iov[i].iov_len); 3413 cur += pkt->fp_iov[i].iov_len; 3414 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3415 } 3416 } 3417 if (status != -1) 3418 /* XXX: Need a complete tlabel interface. */ 3419 for (i = 0; i < 64; i++) 3420 fwohci_handler_set(sc, 3421 IEEE1394_TCODE_READ_RESP_QUAD, 3422 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3423 (*ab->ab_cb)(ab, rcode); 3424 goto cleanup; 3425 } else 3426 /* Good ack packet. */ 3427 return IEEE1394_RCODE_COMPLETE; 3428 3429 /* Can't get here unless ab->ab_cb has been called. */ 3430 3431 cleanup: 3432 fcb->abuf_valid = 0; 3433 if (fcb->count == 0) 3434 free(fcb, M_DEVBUF); 3435 return IEEE1394_RCODE_COMPLETE; 3436 } 3437 3438 static int 3439 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3440 struct fwohci_pkt *pkt) 3441 { 3442 struct fwohci_cb *fcb = arg; 3443 struct ieee1394_abuf *ab = fcb->ab; 3444 struct fwohci_pkt newpkt; 3445 u_int32_t high, lo; 3446 int rcode, rv; 3447 3448 /* 3449 * Bad return codes from the wire, just return what's already in the 3450 * buf. 3451 */ 3452 3453 /* Make sure a response packet didn't arrive after a bad ACK. */ 3454 if (fcb->abuf_valid == 0) 3455 return IEEE1394_RCODE_COMPLETE; 3456 3457 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3458 3459 if (rcode) { 3460 (*ab->ab_cb)(ab, rcode); 3461 goto cleanup; 3462 } 3463 3464 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3465 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3466 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3467 ab->ab_retlen = ab->ab_length; 3468 } else { 3469 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3470 pkt->fp_iov[0].iov_base, 4); 3471 ab->ab_retlen += 4; 3472 } 3473 /* Still more, loop and read 4 more bytes. */ 3474 if (ab->ab_retlen < ab->ab_length) { 3475 memset(&newpkt, 0, sizeof(newpkt)); 3476 3477 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3478 lo = (ab->ab_addr & 0x00000000ffffffffULL) + ab->ab_retlen; 3479 3480 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3481 newpkt.fp_hlen = 12; 3482 newpkt.fp_dlen = 0; 3483 newpkt.fp_hdr[1] = 3484 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3485 newpkt.fp_hdr[2] = lo; 3486 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3487 (newpkt.fp_tcode << 4); 3488 3489 newpkt.fp_statusarg = fcb; 3490 newpkt.fp_statuscb = fwohci_read_resp; 3491 3492 /* 3493 * Bad return code. Just give up and return what's 3494 * come in now. 3495 */ 3496 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3497 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3498 fwohci_read_multi_resp, fcb); 3499 if (rv) 3500 (*ab->ab_cb)(ab, -1); 3501 else { 3502 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3503 if (rv) { 3504 fwohci_handler_set(sc, 3505 IEEE1394_TCODE_READ_RESP_QUAD, 3506 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3507 NULL, NULL); 3508 (*ab->ab_cb)(ab, -1); 3509 } else { 3510 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3511 fcb->count++; 3512 return IEEE1394_RCODE_COMPLETE; 3513 } 3514 } 3515 } else 3516 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3517 3518 cleanup: 3519 /* Can't get here unless ab_cb has been called. */ 3520 fcb->abuf_valid = 0; 3521 if (fcb->count == 0) 3522 free(fcb, M_DEVBUF); 3523 return IEEE1394_RCODE_COMPLETE; 3524 } 3525 3526 static int 3527 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3528 { 3529 struct ieee1394_abuf *ab = arg; 3530 u_int16_t status; 3531 3532 3533 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3534 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3535 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3536 DPRINTF(("Got status packet: 0x%02x\n", 3537 (unsigned int)status)); 3538 3539 /* No callback means this level should free the buffers. */ 3540 if (ab->ab_cb) 3541 (*ab->ab_cb)(ab, status); 3542 else { 3543 if (ab->ab_data) 3544 free(ab->ab_data, M_1394DATA); 3545 free(ab, M_1394DATA); 3546 } 3547 return IEEE1394_RCODE_COMPLETE; 3548 } 3549 3550 static int 3551 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3552 { 3553 struct ieee1394_softc *sc = ab->ab_req; 3554 struct fwohci_softc *psc = 3555 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3556 u_int32_t high, lo; 3557 int i, j, rv; 3558 3559 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3560 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3561 3562 rv = 0; 3563 switch (ab->ab_tcode) { 3564 case IEEE1394_TCODE_READ_REQ_QUAD: 3565 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3566 if (ab->ab_cb) 3567 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3568 fwohci_parse_input, ab); 3569 else 3570 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3571 NULL); 3572 break; 3573 case IEEE1394_TCODE_READ_REQ_BLOCK: 3574 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3575 if (allow) { 3576 for (i = 0; i < (ab->ab_length / 4); i++) { 3577 if (ab->ab_cb) { 3578 rv = fwohci_handler_set(psc, 3579 ab->ab_tcode, high, lo + (i * 4), 3580 fwohci_parse_input, ab); 3581 if (rv) 3582 break; 3583 } else 3584 fwohci_handler_set(psc, ab->ab_tcode, 3585 high, lo + (i * 4), NULL, NULL); 3586 } 3587 if (i != (ab->ab_length / 4)) { 3588 j = i + 1; 3589 for (i = 0; i < j; i++) 3590 fwohci_handler_set(psc, ab->ab_tcode, 3591 high, lo + (i * 4), NULL, NULL); 3592 } 3593 /* 3594 * XXX: Need something to indicate writing a smaller 3595 * amount is ok. 3596 */ 3597 if (ab->ab_cb) 3598 ab->ab_subok = 1; 3599 } else { 3600 if (ab->ab_cb) 3601 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3602 lo, fwohci_parse_input, ab); 3603 else 3604 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3605 NULL, NULL); 3606 } 3607 break; 3608 default: 3609 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3610 return -1; 3611 break; 3612 } 3613 return rv; 3614 } 3615 3616 static int 3617 fwohci_unreg(struct ieee1394_abuf *ab, int allow) 3618 { 3619 void *save; 3620 int rv; 3621 3622 save = ab->ab_cb; 3623 ab->ab_cb = NULL; 3624 rv = fwohci_inreg(ab, allow); 3625 ab->ab_cb = save; 3626 return rv; 3627 } 3628 3629 static int 3630 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3631 { 3632 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3633 u_int64_t addr; 3634 u_int32_t *cur; 3635 int i, count; 3636 3637 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3638 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3639 addr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3640 3641 /* Make sure it's always 0 in case this gets reused multiple times. */ 3642 ab->ab_retlen = 0; 3643 3644 switch (ab->ab_tcode) { 3645 case IEEE1394_TCODE_READ_REQ_QUAD: 3646 ab->ab_retlen = 4; 3647 break; 3648 case IEEE1394_TCODE_READ_REQ_BLOCK: 3649 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3650 if (ab->ab_subok) { 3651 if ((addr + ab->ab_retlen) > 3652 (ab->ab_addr + ab->ab_length)) 3653 return IEEE1394_RCODE_ADDRESS_ERROR; 3654 } else 3655 if (ab->ab_retlen != ab->ab_length) 3656 return IEEE1394_RCODE_ADDRESS_ERROR; 3657 break; 3658 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3659 ab->ab_retlen = 4; 3660 /* Fall through. */ 3661 3662 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3663 if (!ab->ab_retlen) 3664 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3665 if (ab->ab_subok) { 3666 if ((addr + ab->ab_retlen) > 3667 (ab->ab_addr + ab->ab_length)) 3668 return IEEE1394_RCODE_ADDRESS_ERROR; 3669 } else 3670 if (ab->ab_retlen != ab->ab_length) 3671 return IEEE1394_RCODE_ADDRESS_ERROR; 3672 3673 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3674 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3675 ab->ab_data[0] = pkt->fp_hdr[3]; 3676 else { 3677 count = 0; 3678 cur = ab->ab_data; 3679 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3680 memcpy(cur, pkt->fp_iov[i].iov_base, 3681 pkt->fp_iov[i].iov_len); 3682 cur += pkt->fp_iov[i].iov_len; 3683 count += pkt->fp_iov[i].iov_len; 3684 } 3685 if (ab->ab_retlen != count) 3686 panic("Packet claims %d length " 3687 "but only %d bytes returned\n", 3688 ab->ab_retlen, count); 3689 } 3690 break; 3691 default: 3692 panic("Got a callback for a tcode that wasn't requested: %d", 3693 ab->ab_tcode); 3694 break; 3695 } 3696 ab->ab_addr = addr; 3697 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3698 return -1; 3699 } 3700 3701 static int 3702 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3703 { 3704 struct ieee1394_attach_args *fwa = aux; 3705 3706 /* Both halves must be filled in for a match. */ 3707 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3708 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3709 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3710 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3711 return (config_match(parent, cf, aux)); 3712 return 0; 3713 } 3714 3715 int 3716 fwohci_detach(struct fwohci_softc *sc, int flags) 3717 { 3718 int rv = 0; 3719 3720 if (sc->sc_sc1394.sc1394_if != NULL) 3721 rv = config_detach(sc->sc_sc1394.sc1394_if, flags); 3722 if (rv != 0) 3723 return (rv); 3724 3725 callout_stop(&sc->sc_selfid_callout); 3726 3727 if (sc->sc_powerhook != NULL) 3728 powerhook_disestablish(sc->sc_powerhook); 3729 if (sc->sc_shutdownhook != NULL) 3730 shutdownhook_disestablish(sc->sc_shutdownhook); 3731 3732 return (rv); 3733 } 3734 3735 int 3736 fwohci_activate(struct device *self, enum devact act) 3737 { 3738 struct fwohci_softc *sc = (struct fwohci_softc *)self; 3739 int s, rv = 0; 3740 3741 s = splhigh(); 3742 switch (act) { 3743 case DVACT_ACTIVATE: 3744 rv = EOPNOTSUPP; 3745 break; 3746 3747 case DVACT_DEACTIVATE: 3748 if (sc->sc_sc1394.sc1394_if != NULL) 3749 rv = config_deactivate(sc->sc_sc1394.sc1394_if); 3750 break; 3751 } 3752 splx(s); 3753 3754 return (rv); 3755 } 3756 3757 #ifdef FW_DEBUG 3758 static void 3759 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3760 { 3761 3762 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3763 intmask); 3764 if (intmask & OHCI_Int_CycleTooLong) 3765 printf(" CycleTooLong"); 3766 if (intmask & OHCI_Int_UnrecoverableError) 3767 printf(" UnrecoverableError"); 3768 if (intmask & OHCI_Int_CycleInconsistent) 3769 printf(" CycleInconsistent"); 3770 if (intmask & OHCI_Int_BusReset) 3771 printf(" BusReset"); 3772 if (intmask & OHCI_Int_SelfIDComplete) 3773 printf(" SelfIDComplete"); 3774 if (intmask & OHCI_Int_LockRespErr) 3775 printf(" LockRespErr"); 3776 if (intmask & OHCI_Int_PostedWriteErr) 3777 printf(" PostedWriteErr"); 3778 if (intmask & OHCI_Int_ReqTxComplete) 3779 printf(" ReqTxComplete(0x%04x)", 3780 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3781 OHCI_SUBREG_ContextControlClear)); 3782 if (intmask & OHCI_Int_RespTxComplete) 3783 printf(" RespTxComplete(0x%04x)", 3784 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3785 OHCI_SUBREG_ContextControlClear)); 3786 if (intmask & OHCI_Int_ARRS) 3787 printf(" ARRS(0x%04x)", 3788 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3789 OHCI_SUBREG_ContextControlClear)); 3790 if (intmask & OHCI_Int_ARRQ) 3791 printf(" ARRQ(0x%04x)", 3792 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3793 OHCI_SUBREG_ContextControlClear)); 3794 if (intmask & OHCI_Int_IsochRx) 3795 printf(" IsochRx(0x%08x)", 3796 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3797 if (intmask & OHCI_Int_IsochTx) 3798 printf(" IsochTx(0x%08x)", 3799 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3800 if (intmask & OHCI_Int_RQPkt) 3801 printf(" RQPkt(0x%04x)", 3802 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3803 OHCI_SUBREG_ContextControlClear)); 3804 if (intmask & OHCI_Int_RSPkt) 3805 printf(" RSPkt(0x%04x)", 3806 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3807 OHCI_SUBREG_ContextControlClear)); 3808 printf("\n"); 3809 } 3810 3811 static void 3812 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3813 { 3814 u_int8_t key, phyid; 3815 3816 key = (val & 0xc0000000) >> 30; 3817 phyid = (val & 0x3f000000) >> 24; 3818 printf("%s: PHY packet from %d: ", 3819 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3820 switch (key) { 3821 case 0: 3822 printf("PHY Config:"); 3823 if (val & 0x00800000) 3824 printf(" ForceRoot"); 3825 if (val & 0x00400000) 3826 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3827 printf("\n"); 3828 break; 3829 case 1: 3830 printf("Link-on\n"); 3831 break; 3832 case 2: 3833 printf("SelfID:"); 3834 if (val & 0x00800000) { 3835 printf(" #%d", (val & 0x00700000) >> 20); 3836 } else { 3837 if (val & 0x00400000) 3838 printf(" LinkActive"); 3839 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3840 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3841 if (val & 0x00000800) 3842 printf(" Cont"); 3843 if (val & 0x00000002) 3844 printf(" InitiateBusReset"); 3845 } 3846 if (val & 0x00000001) 3847 printf(" +"); 3848 printf("\n"); 3849 break; 3850 default: 3851 printf("unknown: 0x%08x\n", val); 3852 break; 3853 } 3854 } 3855 #endif /* FW_DEBUG */ 3856
Indexes created Mon Sep 29 21:09:56 GMT 2025