fwohci.c revision 1.60
1 /* $NetBSD: fwohci.c,v 1.60 2002/11/30 06:09:42 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 /* 47 * The first version to support isochronous acquisition part is wrtten 48 * by HAYAKAWA Koichi <haya (at) netbsd.org>. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.60 2002/11/30 06:09:42 jmc Exp $"); 53 54 #define DOUBLEBUF 1 55 #define NO_THREAD 1 56 57 #include "opt_inet.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kthread.h> 62 #include <sys/socket.h> 63 #include <sys/callout.h> 64 #include <sys/device.h> 65 #include <sys/kernel.h> 66 #include <sys/malloc.h> 67 #include <sys/mbuf.h> 68 69 #if __NetBSD_Version__ >= 105010000 70 #include <uvm/uvm_extern.h> 71 #else 72 #include <vm/vm.h> 73 #endif 74 75 #include <machine/bus.h> 76 #include <machine/intr.h> 77 78 #include <dev/ieee1394/ieee1394reg.h> 79 #include <dev/ieee1394/fwohcireg.h> 80 81 #include <dev/ieee1394/ieee1394var.h> 82 #include <dev/ieee1394/fwohcivar.h> 83 84 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 85 86 #if 0 87 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 88 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 89 #endif 90 static void fwohci_create_event_thread(void *); 91 static void fwohci_thread_init(void *); 92 93 static void fwohci_event_thread(struct fwohci_softc *); 94 static void fwohci_hw_init(struct fwohci_softc *); 95 static void fwohci_power(int, void *); 96 static void fwohci_shutdown(void *); 97 98 static int fwohci_desc_alloc(struct fwohci_softc *); 99 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 100 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 101 102 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 103 int, int, int); 104 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 105 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 106 107 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 108 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 109 static void fwohci_buf_init_rx(struct fwohci_softc *); 110 static void fwohci_buf_start_rx(struct fwohci_softc *); 111 static void fwohci_buf_stop_tx(struct fwohci_softc *); 112 static void fwohci_buf_stop_rx(struct fwohci_softc *); 113 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 114 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_buf **, 115 caddr_t *, int); 116 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 117 struct fwohci_pkt *); 118 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 119 struct fwohci_pkt *); 120 121 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 122 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 123 static void fwohci_phy_busreset(struct fwohci_softc *); 124 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 125 126 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 127 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 128 129 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 130 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 131 static void fwohci_ir_input(struct fwohci_softc *, struct fwohci_ctx *); 132 133 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 134 struct fwohci_pkt *); 135 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 136 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 137 struct fwohci_pkt *); 138 139 static int fwohci_guidrom_init(struct fwohci_softc *); 140 static void fwohci_configrom_init(struct fwohci_softc *); 141 static int fwohci_configrom_input(struct fwohci_softc *, void *, 142 struct fwohci_pkt *); 143 static void fwohci_selfid_init(struct fwohci_softc *); 144 static int fwohci_selfid_input(struct fwohci_softc *); 145 146 static void fwohci_csr_init(struct fwohci_softc *); 147 static int fwohci_csr_input(struct fwohci_softc *, void *, 148 struct fwohci_pkt *); 149 150 static void fwohci_uid_collect(struct fwohci_softc *); 151 static void fwohci_uid_req(struct fwohci_softc *, int); 152 static int fwohci_uid_input(struct fwohci_softc *, void *, 153 struct fwohci_pkt *); 154 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 155 static void fwohci_check_nodes(struct fwohci_softc *); 156 157 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 158 void (*)(struct device *, struct mbuf *)); 159 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 160 static int fwohci_if_input_iso(struct fwohci_softc *, void *, struct fwohci_pkt *); 161 static int fwohci_if_output(struct device *, struct mbuf *, 162 void (*)(struct device *, struct mbuf *)); 163 static int fwohci_if_setiso(struct device *, u_int32_t, u_int32_t, u_int32_t, 164 void (*)(struct device *, struct mbuf *)); 165 static int fwohci_read(struct ieee1394_abuf *); 166 static int fwohci_write(struct ieee1394_abuf *); 167 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 168 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 169 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 170 struct fwohci_pkt *); 171 static int fwohci_inreg(struct ieee1394_abuf *, int); 172 static int fwohci_unreg(struct ieee1394_abuf *, int); 173 static int fwohci_parse_input(struct fwohci_softc *, void *, 174 struct fwohci_pkt *); 175 static int fwohci_submatch(struct device *, struct cfdata *, void *); 176 177 #ifdef FW_DEBUG 178 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 179 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 180 181 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 182 183 #define DPRINTF(x) if (fwdebug) printf x 184 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 185 int fwdebug = 1; 186 #else 187 #define DPRINTF(x) 188 #define DPRINTFN(n,x) 189 #endif 190 191 int 192 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 193 { 194 int i; 195 u_int32_t val; 196 #if 0 197 int error; 198 #endif 199 200 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 201 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 202 203 evcnt_attach_dynamic(&sc->sc_isocnt, EVCNT_TYPE_MISC, ev, 204 sc->sc_sc1394.sc1394_dev.dv_xname, "iso"); 205 evcnt_attach_dynamic(&sc->sc_isopktcnt, EVCNT_TYPE_MISC, ev, 206 sc->sc_sc1394.sc1394_dev.dv_xname, "isopackets"); 207 208 /* 209 * Wait for reset completion 210 */ 211 for (i = 0; i < OHCI_LOOP; i++) { 212 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 213 if ((val & OHCI_HCControl_SoftReset) == 0) 214 break; 215 DELAY(10); 216 } 217 218 /* What dialect of OHCI is this device? 219 */ 220 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 221 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 222 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 223 224 LIST_INIT(&sc->sc_nodelist); 225 226 if (fwohci_guidrom_init(sc) != 0) { 227 printf("\n%s: fatal: no global UID ROM\n", 228 sc->sc_sc1394.sc1394_dev.dv_xname); 229 return -1; 230 } 231 232 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 233 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 234 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 235 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 236 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 237 238 /* Get the maximum link speed and receive size 239 */ 240 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 241 sc->sc_sc1394.sc1394_link_speed = 242 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 243 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 244 printf(", %s", 245 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 246 } else { 247 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 248 } 249 250 /* MaxRec is encoded as log2(max_rec_octets)-1 251 */ 252 sc->sc_sc1394.sc1394_max_receive = 253 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 254 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 255 256 /* 257 * Count how many isochronous ctx we have. 258 */ 259 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 260 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 261 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 262 for (i = 0; val != 0; val >>= 1) { 263 if (val & 0x1) 264 i++; 265 } 266 sc->sc_isoctx = i; 267 printf(", %d iso_ctx", sc->sc_isoctx); 268 269 printf("\n"); 270 271 #if 0 272 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 273 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 274 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 275 return error; 276 #endif 277 278 sc->sc_dying = 0; 279 sc->sc_nodeid = 0xffff; /* invalid */ 280 281 sc->sc_sc1394.sc1394_callback.sc1394_read = fwohci_read; 282 sc->sc_sc1394.sc1394_callback.sc1394_write = fwohci_write; 283 sc->sc_sc1394.sc1394_callback.sc1394_inreg = fwohci_inreg; 284 sc->sc_sc1394.sc1394_callback.sc1394_unreg = fwohci_unreg; 285 286 kthread_create(fwohci_create_event_thread, sc); 287 return 0; 288 } 289 290 static int 291 fwohci_if_setiso(struct device *self, u_int32_t channel, u_int32_t tag, 292 u_int32_t direction, void (*handler)(struct device *, struct mbuf *)) 293 { 294 struct fwohci_softc *sc = (struct fwohci_softc *)self; 295 int retval; 296 int s; 297 298 if (direction == 1) { 299 return EIO; 300 } 301 302 s = splnet(); 303 retval = fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 304 channel, tag, fwohci_if_input_iso, handler); 305 splx(s); 306 307 if (!retval) { 308 printf("%s: dummy iso handler set\n", 309 sc->sc_sc1394.sc1394_dev.dv_xname); 310 } else { 311 printf("%s: dummy iso handler cannot set\n", 312 sc->sc_sc1394.sc1394_dev.dv_xname); 313 } 314 315 return retval; 316 } 317 318 int 319 fwohci_intr(void *arg) 320 { 321 struct fwohci_softc * const sc = arg; 322 int progress = 0; 323 u_int32_t intmask, iso; 324 325 for (;;) { 326 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 327 328 /* 329 * On a bus reset, everything except bus reset gets 330 * cleared. That can't get cleared until the selfid 331 * phase completes (which happens outside the 332 * interrupt routines). So if just a bus reset is left 333 * in the mask and it's already in the sc_intmask, 334 * just return. 335 */ 336 337 if ((intmask == 0) || 338 (progress && (intmask == OHCI_Int_BusReset) && 339 (sc->sc_intmask & OHCI_Int_BusReset))) { 340 if (progress) 341 wakeup(fwohci_event_thread); 342 return progress; 343 } 344 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 345 intmask & ~OHCI_Int_BusReset); 346 #ifdef FW_DEBUG 347 if (fwdebug > 1) 348 fwohci_show_intr(sc, intmask); 349 #endif 350 351 if (intmask & OHCI_Int_BusReset) { 352 /* 353 * According to OHCI spec 6.1.1 "busReset", 354 * All asynchronous transmit must be stopped before 355 * clearing BusReset. Moreover, the BusReset 356 * interrupt bit should not be cleared during the 357 * SelfID phase. Thus we turned off interrupt mask 358 * bit of BusReset instead until SelfID completion 359 * or SelfID timeout. 360 */ 361 intmask &= OHCI_Int_SelfIDComplete; 362 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 363 OHCI_Int_BusReset); 364 sc->sc_intmask = OHCI_Int_BusReset; 365 } 366 sc->sc_intmask |= intmask; 367 368 if (intmask & OHCI_Int_IsochTx) { 369 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 370 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 371 } 372 if (intmask & OHCI_Int_IsochRx) { 373 #if NO_THREAD 374 int i; 375 int asyncstream = 0; 376 #endif 377 378 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 379 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 380 #if NO_THREAD 381 for (i = 0; i < sc->sc_isoctx; i++) { 382 if ((iso & (1<<i)) && sc->sc_ctx_ir[i] != NULL) { 383 if (sc->sc_ctx_ir[i]->fc_type == FWOHCI_CTX_ISO_SINGLE) { 384 asyncstream |= (1 << i); 385 continue; 386 } 387 bus_dmamap_sync(sc->sc_dmat, 388 sc->sc_ddmamap, 389 0, sizeof(struct fwohci_desc) * sc->sc_descsize, 390 BUS_DMASYNC_PREREAD); 391 sc->sc_isocnt.ev_count++; 392 393 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 394 } 395 } 396 if (asyncstream != 0) { 397 sc->sc_iso |= asyncstream; 398 } else { 399 /* all iso intr is pure isochronous */ 400 sc->sc_intmask &= ~OHCI_Int_IsochRx; 401 } 402 #else 403 sc->sc_iso |= iso; 404 #endif /* NO_THREAD */ 405 } 406 407 if (!progress) { 408 sc->sc_intrcnt.ev_count++; 409 progress = 1; 410 } 411 } 412 } 413 414 static void 415 fwohci_create_event_thread(void *arg) 416 { 417 struct fwohci_softc *sc = arg; 418 419 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 420 sc->sc_sc1394.sc1394_dev.dv_xname)) { 421 printf("%s: unable to create event thread\n", 422 sc->sc_sc1394.sc1394_dev.dv_xname); 423 panic("fwohci_create_event_thread"); 424 } 425 } 426 427 static void 428 fwohci_thread_init(void *arg) 429 { 430 struct fwohci_softc *sc = arg; 431 int i; 432 433 /* 434 * Allocate descriptors 435 */ 436 if (fwohci_desc_alloc(sc)) { 437 printf("%s: not enabling interrupts\n", 438 sc->sc_sc1394.sc1394_dev.dv_xname); 439 kthread_exit(1); 440 } 441 442 /* 443 * Enable Link Power 444 */ 445 446 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 447 448 /* 449 * Allocate DMA Context 450 */ 451 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 452 OHCI_CTX_ASYNC_RX_REQUEST, FWOHCI_CTX_ASYNC); 453 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 454 OHCI_CTX_ASYNC_RX_RESPONSE, FWOHCI_CTX_ASYNC); 455 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST, 456 FWOHCI_CTX_ASYNC); 457 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE, 458 FWOHCI_CTX_ASYNC); 459 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 460 M_DEVBUF, M_WAITOK); 461 for (i = 0; i < sc->sc_isoctx; i++) 462 sc->sc_ctx_ir[i] = NULL; 463 464 /* 465 * Allocate buffer for configuration ROM and SelfID buffer 466 */ 467 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 468 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 469 470 callout_init(&sc->sc_selfid_callout); 471 472 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 473 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 474 sc->sc_sc1394.sc1394_ifsetiso = fwohci_if_setiso; 475 476 /* 477 * establish hooks for shutdown and suspend/resume 478 */ 479 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 480 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 481 482 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 483 fwohci_print); 484 485 /* Main loop. It's not coming back normally. */ 486 487 fwohci_event_thread(sc); 488 489 kthread_exit(0); 490 } 491 492 static void 493 fwohci_event_thread(struct fwohci_softc *sc) 494 { 495 int i, s; 496 u_int32_t intmask, iso; 497 498 s = splbio(); 499 500 /* 501 * Initialize hardware registers. 502 */ 503 504 fwohci_hw_init(sc); 505 506 /* Initial Bus Reset */ 507 fwohci_phy_busreset(sc); 508 splx(s); 509 510 while (!sc->sc_dying) { 511 s = splbio(); 512 intmask = sc->sc_intmask; 513 if (intmask == 0) { 514 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 515 splx(s); 516 continue; 517 } 518 sc->sc_intmask = 0; 519 splx(s); 520 521 if (intmask & OHCI_Int_BusReset) { 522 fwohci_buf_stop_tx(sc); 523 if (sc->sc_uidtbl != NULL) { 524 free(sc->sc_uidtbl, M_DEVBUF); 525 sc->sc_uidtbl = NULL; 526 } 527 528 callout_reset(&sc->sc_selfid_callout, 529 OHCI_SELFID_TIMEOUT, 530 (void (*)(void *))fwohci_phy_busreset, sc); 531 sc->sc_nodeid = 0xffff; /* indicate invalid */ 532 sc->sc_rootid = 0; 533 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 534 } 535 if (intmask & OHCI_Int_SelfIDComplete) { 536 s = splbio(); 537 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 538 OHCI_Int_BusReset); 539 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 540 OHCI_Int_BusReset); 541 splx(s); 542 callout_stop(&sc->sc_selfid_callout); 543 if (fwohci_selfid_input(sc) == 0) { 544 fwohci_buf_start_rx(sc); 545 fwohci_uid_collect(sc); 546 } 547 } 548 if (intmask & OHCI_Int_ReqTxComplete) 549 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 550 if (intmask & OHCI_Int_RespTxComplete) 551 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 552 if (intmask & OHCI_Int_RQPkt) 553 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 554 if (intmask & OHCI_Int_RSPkt) 555 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 556 if (intmask & OHCI_Int_IsochRx) { 557 s = splbio(); 558 iso = sc->sc_iso; 559 sc->sc_iso = 0; 560 splx(s); 561 for (i = 0; i < sc->sc_isoctx; i++) { 562 if ((iso & (1 << i)) && 563 sc->sc_ctx_ir[i] != NULL) { 564 fwohci_ir_input(sc, sc->sc_ctx_ir[i]); 565 sc->sc_isocnt.ev_count++; 566 } 567 } 568 } 569 } 570 } 571 572 #if 0 573 static int 574 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 575 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 576 { 577 bus_dma_segment_t segs[1]; 578 int error, nsegs, steps; 579 580 steps = 0; 581 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 582 segs, 1, &nsegs, flags); 583 if (error) 584 goto cleanup; 585 586 steps = 1; 587 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 588 kvap, flags); 589 if (error) 590 goto cleanup; 591 592 if (error == 0) 593 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 594 size, flags, mapp); 595 if (error) 596 goto cleanup; 597 if (error == 0) 598 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 599 flags); 600 if (error) 601 goto cleanup; 602 603 cleanup: 604 switch (steps) { 605 case 1: 606 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 607 } 608 609 return error; 610 } 611 #endif 612 613 int 614 fwohci_print(void *aux, const char *pnp) 615 { 616 char *name = aux; 617 618 if (pnp) 619 printf("%s at %s", name, pnp); 620 621 return UNCONF; 622 } 623 624 static void 625 fwohci_hw_init(struct fwohci_softc *sc) 626 { 627 int i; 628 u_int32_t val; 629 630 /* 631 * Software Reset. 632 */ 633 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 634 for (i = 0; i < OHCI_LOOP; i++) { 635 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 636 if ((val & OHCI_HCControl_SoftReset) == 0) 637 break; 638 DELAY(10); 639 } 640 641 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 642 643 /* 644 * First, initilize CSRs with undefined value to default settings. 645 */ 646 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 647 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 648 #if 0 649 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 650 #else 651 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 652 #endif 653 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 654 for (i = 0; i < sc->sc_isoctx; i++) { 655 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 656 ~0); 657 } 658 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 659 660 fwohci_configrom_init(sc); 661 fwohci_selfid_init(sc); 662 fwohci_buf_init_rx(sc); 663 fwohci_csr_init(sc); 664 665 /* 666 * Final CSR settings. 667 */ 668 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 669 OHCI_LinkControl_CycleTimerEnable | 670 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 671 672 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 673 674 /* clear receive filter */ 675 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 676 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 677 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 678 679 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 680 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 681 #if BYTE_ORDER == BIG_ENDIAN 682 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 683 OHCI_HCControl_NoByteSwapData); 684 #endif 685 686 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 687 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 688 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 689 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 690 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 691 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 692 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 693 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 694 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 695 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 696 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 697 698 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 699 700 /* 701 * Start the receivers 702 */ 703 fwohci_buf_start_rx(sc); 704 } 705 706 static void 707 fwohci_power(int why, void *arg) 708 { 709 struct fwohci_softc *sc = arg; 710 int s; 711 712 s = splbio(); 713 switch (why) { 714 case PWR_SUSPEND: 715 case PWR_STANDBY: 716 fwohci_shutdown(sc); 717 break; 718 case PWR_RESUME: 719 fwohci_hw_init(sc); 720 fwohci_phy_busreset(sc); 721 break; 722 case PWR_SOFTSUSPEND: 723 case PWR_SOFTSTANDBY: 724 case PWR_SOFTRESUME: 725 break; 726 } 727 splx(s); 728 } 729 730 static void 731 fwohci_shutdown(void *arg) 732 { 733 struct fwohci_softc *sc = arg; 734 u_int32_t val; 735 736 callout_stop(&sc->sc_selfid_callout); 737 /* disable all interrupt */ 738 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 739 fwohci_buf_stop_tx(sc); 740 fwohci_buf_stop_rx(sc); 741 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 742 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 743 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 744 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 745 fwohci_phy_busreset(sc); 746 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 747 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 748 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 749 } 750 751 /* 752 * COMMON FUNCTIONS 753 */ 754 755 /* 756 * read the PHY Register. 757 */ 758 static u_int8_t 759 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 760 { 761 int i; 762 u_int32_t val; 763 764 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 765 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 766 for (i = 0; i < OHCI_LOOP; i++) { 767 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 768 OHCI_PhyControl_RdDone) 769 break; 770 DELAY(10); 771 } 772 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 773 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 774 } 775 776 /* 777 * write the PHY Register. 778 */ 779 static void 780 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 781 { 782 int i; 783 784 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 785 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 786 (val << OHCI_PhyControl_WrData_BITPOS)); 787 for (i = 0; i < OHCI_LOOP; i++) { 788 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 789 OHCI_PhyControl_WrReg)) 790 break; 791 DELAY(10); 792 } 793 } 794 795 /* 796 * Initiate Bus Reset 797 */ 798 static void 799 fwohci_phy_busreset(struct fwohci_softc *sc) 800 { 801 int s; 802 u_int8_t val; 803 804 s = splbio(); 805 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 806 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 807 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 808 callout_stop(&sc->sc_selfid_callout); 809 val = fwohci_phy_read(sc, 1); 810 val = (val & 0x80) | /* preserve RHB (force root) */ 811 0x40 | /* Initiate Bus Reset */ 812 0x3f; /* default GAP count */ 813 fwohci_phy_write(sc, 1, val); 814 splx(s); 815 } 816 817 /* 818 * PHY Packet 819 */ 820 static void 821 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 822 { 823 u_int32_t val; 824 825 val = pkt->fp_hdr[1]; 826 if (val != ~pkt->fp_hdr[2]) { 827 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 828 OHCI_CTXCTL_EVENT_BUS_RESET) { 829 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 830 pkt->fp_hdr[2])); 831 } else { 832 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 833 sc->sc_sc1394.sc1394_dev.dv_xname, val, 834 pkt->fp_hdr[2]); 835 } 836 return; 837 } 838 #ifdef FW_DEBUG 839 if (fwdebug > 1) 840 fwohci_show_phypkt(sc, val); 841 #endif 842 } 843 844 /* 845 * Descriptor for context DMA. 846 */ 847 static int 848 fwohci_desc_alloc(struct fwohci_softc *sc) 849 { 850 int error, mapsize, dsize; 851 852 /* 853 * allocate descriptor buffer 854 */ 855 856 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 857 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 858 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 859 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 860 mapsize = howmany(sc->sc_descsize, NBBY); 861 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK|M_ZERO); 862 863 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 864 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 865 printf("%s: unable to allocate descriptor buffer, error = %d\n", 866 sc->sc_sc1394.sc1394_dev.dv_xname, error); 867 goto fail_0; 868 } 869 870 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 871 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 872 != 0) { 873 printf("%s: unable to map descriptor buffer, error = %d\n", 874 sc->sc_sc1394.sc1394_dev.dv_xname, error); 875 goto fail_1; 876 } 877 878 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 879 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 880 printf("%s: unable to create descriptor buffer DMA map, " 881 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 882 goto fail_2; 883 } 884 885 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 886 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 887 printf("%s: unable to load descriptor buffer DMA map, " 888 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 889 goto fail_3; 890 } 891 892 return 0; 893 894 fail_3: 895 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 896 fail_2: 897 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 898 fail_1: 899 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 900 fail_0: 901 return error; 902 } 903 904 static struct fwohci_desc * 905 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 906 { 907 int i, n; 908 909 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 910 for (i = 0; ; i++) { 911 if (i == ndesc) { 912 for (i = 0; i < ndesc; i++) 913 setbit(sc->sc_descmap, n + i); 914 return sc->sc_desc + n; 915 } 916 if (isset(sc->sc_descmap, n + i)) 917 break; 918 } 919 } 920 return NULL; 921 } 922 923 static void 924 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 925 { 926 int i, n; 927 928 n = fd - sc->sc_desc; 929 for (i = 0; i < ndesc; i++, n++) { 930 #ifdef DIAGNOSTIC 931 if (isclr(sc->sc_descmap, n)) 932 panic("fwohci_desc_put: duplicated free"); 933 #endif 934 clrbit(sc->sc_descmap, n); 935 } 936 } 937 938 /* 939 * Asyncronous/Isochronous Transmit/Receive Context 940 */ 941 static int 942 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 943 int bufcnt, int ctx, int ctxtype) 944 { 945 int i, error; 946 struct fwohci_ctx *fc; 947 struct fwohci_buf *fb; 948 struct fwohci_desc *fd; 949 #if DOUBLEBUF 950 int buf2cnt; 951 #endif 952 953 fc = malloc(sizeof(*fc), M_DEVBUF, M_WAITOK|M_ZERO); 954 LIST_INIT(&fc->fc_handler); 955 TAILQ_INIT(&fc->fc_buf); 956 fc->fc_ctx = ctx; 957 fc->fc_buffers = fb = malloc(sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK|M_ZERO); 958 fc->fc_bufcnt = bufcnt; 959 #if DOUBLEBUF 960 TAILQ_INIT(&fc->fc_buf2); /* for isochronous */ 961 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 962 buf2cnt = bufcnt/2; 963 bufcnt -= buf2cnt; 964 if (buf2cnt == 0) { 965 panic("cannot allocate iso buffer"); 966 } 967 } 968 #endif 969 for (i = 0; i < bufcnt; i++, fb++) { 970 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 971 goto fail; 972 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 973 error = ENOBUFS; 974 goto fail; 975 } 976 fb->fb_desc = fd; 977 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 978 ((caddr_t)fd - (caddr_t)sc->sc_desc); 979 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 980 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 981 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 982 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 983 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 984 } 985 #if DOUBLEBUF 986 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 987 for (i = bufcnt; i < bufcnt + buf2cnt; i++, fb++) { 988 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 989 goto fail; 990 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 991 error = ENOBUFS; 992 goto fail; 993 } 994 fb->fb_desc = fd; 995 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 996 ((caddr_t)fd - (caddr_t)sc->sc_desc); 997 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 998 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 999 BUS_DMASYNC_PREWRITE); 1000 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1001 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1002 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1003 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1004 TAILQ_INSERT_TAIL(&fc->fc_buf2, fb, fb_list); 1005 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1006 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1007 BUS_DMASYNC_POSTWRITE); 1008 } 1009 } 1010 #endif /* DOUBLEBUF */ 1011 fc->fc_type = ctxtype; 1012 *fcp = fc; 1013 return 0; 1014 1015 fail: 1016 while (i-- > 0) { 1017 fb--; 1018 if (fb->fb_desc) 1019 fwohci_desc_put(sc, fb->fb_desc, 1); 1020 fwohci_buf_free(sc, fb); 1021 } 1022 free(fc, M_DEVBUF); 1023 return error; 1024 } 1025 1026 static void 1027 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1028 { 1029 struct fwohci_buf *fb; 1030 struct fwohci_handler *fh; 1031 1032 #if DOUBLEBUF 1033 if ((fc->fc_type == FWOHCI_CTX_ISO_MULTI) && 1034 (TAILQ_FIRST(&fc->fc_buf) > TAILQ_FIRST(&fc->fc_buf2))) { 1035 struct fwohci_buf_s fctmp; 1036 1037 fctmp = fc->fc_buf; 1038 fc->fc_buf = fc->fc_buf2; 1039 fc->fc_buf2 = fctmp; 1040 } 1041 #endif 1042 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1043 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1044 NULL, NULL); 1045 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1046 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1047 if (fb->fb_desc) 1048 fwohci_desc_put(sc, fb->fb_desc, 1); 1049 fwohci_buf_free(sc, fb); 1050 } 1051 #if DOUBLEBUF 1052 while ((fb = TAILQ_FIRST(&fc->fc_buf2)) != NULL) { 1053 TAILQ_REMOVE(&fc->fc_buf2, fb, fb_list); 1054 if (fb->fb_desc) 1055 fwohci_desc_put(sc, fb->fb_desc, 1); 1056 fwohci_buf_free(sc, fb); 1057 } 1058 #endif /* DOUBLEBUF */ 1059 free(fc->fc_buffers, M_DEVBUF); 1060 free(fc, M_DEVBUF); 1061 } 1062 1063 static void 1064 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1065 { 1066 struct fwohci_buf *fb, *nfb; 1067 struct fwohci_desc *fd; 1068 struct fwohci_handler *fh; 1069 int n; 1070 1071 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1072 nfb = TAILQ_NEXT(fb, fb_list); 1073 fb->fb_off = 0; 1074 fd = fb->fb_desc; 1075 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1076 fd->fd_rescount = fd->fd_reqcount; 1077 } 1078 1079 #if DOUBLEBUF 1080 for (fb = TAILQ_FIRST(&fc->fc_buf2); fb != NULL; fb = nfb) { 1081 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1082 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1083 BUS_DMASYNC_PREWRITE); 1084 nfb = TAILQ_NEXT(fb, fb_list); 1085 fb->fb_off = 0; 1086 fd = fb->fb_desc; 1087 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1088 fd->fd_rescount = fd->fd_reqcount; 1089 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1090 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1091 BUS_DMASYNC_POSTWRITE); 1092 } 1093 #endif /* DOUBLEBUF */ 1094 1095 n = fc->fc_ctx; 1096 fb = TAILQ_FIRST(&fc->fc_buf); 1097 if (fc->fc_type != FWOHCI_CTX_ASYNC) { 1098 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1099 fb->fb_daddr | 1); 1100 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1101 OHCI_CTXCTL_RX_BUFFER_FILL | 1102 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1103 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1104 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1105 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1106 OHCI_CTXCTL_RX_ISOCH_HEADER); 1107 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1108 OHCI_SYNC_RX_DMA_WRITE(sc, n, 1109 OHCI_SUBREG_ContextControlSet, 1110 OHCI_CTXCTL_RX_BUFFER_FILL); 1111 } 1112 fh = LIST_FIRST(&fc->fc_handler); 1113 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1114 (OHCI_CTXMATCH_TAG0 << fh->fh_key2) | fh->fh_key1); 1115 } else { 1116 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1117 fb->fb_daddr | 1); 1118 } 1119 } 1120 1121 /* 1122 * DMA data buffer 1123 */ 1124 static int 1125 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1126 { 1127 int error; 1128 1129 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1130 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1131 printf("%s: unable to allocate buffer, error = %d\n", 1132 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1133 goto fail_0; 1134 } 1135 1136 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1137 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1138 printf("%s: unable to map buffer, error = %d\n", 1139 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1140 goto fail_1; 1141 } 1142 1143 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1144 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1145 printf("%s: unable to create buffer DMA map, " 1146 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1147 error); 1148 goto fail_2; 1149 } 1150 1151 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1152 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1153 printf("%s: unable to load buffer DMA map, " 1154 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1155 error); 1156 goto fail_3; 1157 } 1158 1159 return 0; 1160 1161 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1162 fail_3: 1163 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1164 fail_2: 1165 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1166 fail_1: 1167 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1168 fail_0: 1169 return error; 1170 } 1171 1172 static void 1173 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1174 { 1175 1176 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1177 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1178 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1179 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1180 } 1181 1182 static void 1183 fwohci_buf_init_rx(struct fwohci_softc *sc) 1184 { 1185 int i; 1186 1187 /* 1188 * Initialize for Asynchronous Receive Queue. 1189 */ 1190 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1191 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1192 1193 /* 1194 * Initialize for Isochronous Receive Queue. 1195 */ 1196 for (i = 0; i < sc->sc_isoctx; i++) { 1197 if (sc->sc_ctx_ir[i] != NULL) 1198 fwohci_ctx_init(sc, sc->sc_ctx_ir[i]); 1199 } 1200 } 1201 1202 static void 1203 fwohci_buf_start_rx(struct fwohci_softc *sc) 1204 { 1205 int i; 1206 1207 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1208 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1209 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1210 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1211 for (i = 0; i < sc->sc_isoctx; i++) { 1212 if (sc->sc_ctx_ir[i] != NULL) 1213 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1214 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1215 } 1216 } 1217 1218 static void 1219 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1220 { 1221 int i; 1222 1223 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1224 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1225 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1226 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1227 1228 /* 1229 * Make sure the transmitter is stopped. 1230 */ 1231 for (i = 0; i < OHCI_LOOP; i++) { 1232 DELAY(10); 1233 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1234 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1235 continue; 1236 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1237 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1238 continue; 1239 break; 1240 } 1241 1242 /* 1243 * Initialize for Asynchronous Transmit Queue. 1244 */ 1245 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1246 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1247 } 1248 1249 static void 1250 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1251 { 1252 int i; 1253 1254 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1255 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1256 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1257 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1258 for (i = 0; i < sc->sc_isoctx; i++) { 1259 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1260 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1261 } 1262 } 1263 1264 static void 1265 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1266 { 1267 struct fwohci_buf *fb, *tfb; 1268 1269 #if DOUBLEBUF 1270 if (fc->fc_type != FWOHCI_CTX_ISO_MULTI) { 1271 #endif 1272 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1273 if (fc->fc_type) { 1274 if (fb->fb_off == 0) 1275 break; 1276 } else { 1277 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1278 fb->fb_desc->fd_rescount != 0) 1279 break; 1280 } 1281 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1282 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1283 fb->fb_off = 0; 1284 fb->fb_desc->fd_branch = 0; 1285 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1286 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1287 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1288 } 1289 #if DOUBLEBUF 1290 } else { 1291 struct fwohci_buf_s fctmp; 1292 1293 /* cleaning buffer */ 1294 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; 1295 fb = TAILQ_NEXT(fb, fb_list)) { 1296 fb->fb_off = 0; 1297 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1298 } 1299 1300 /* rotating buffer */ 1301 fctmp = fc->fc_buf; 1302 fc->fc_buf = fc->fc_buf2; 1303 fc->fc_buf2 = fctmp; 1304 } 1305 #endif 1306 } 1307 1308 static int 1309 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_buf **fbp, caddr_t *pp, 1310 int len) 1311 { 1312 struct fwohci_buf *fb; 1313 struct fwohci_desc *fd; 1314 int bufend; 1315 1316 fb = *fbp; 1317 again: 1318 fd = fb->fb_desc; 1319 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1320 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1321 fd->fd_reqcount, fd->fd_rescount, len, 1322 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1323 bufend = fd->fd_reqcount - fd->fd_rescount; 1324 if (fb->fb_off >= bufend) { 1325 DPRINTFN(5, ("buf %x finish req %d res %d off %d ", 1326 fb->fb_desc->fd_data, fd->fd_reqcount, fd->fd_rescount, 1327 fb->fb_off)); 1328 if (fd->fd_rescount == 0) { 1329 *fbp = fb = TAILQ_NEXT(fb, fb_list); 1330 if (fb != NULL) 1331 goto again; 1332 } 1333 return 0; 1334 } 1335 if (fb->fb_off + len > bufend) 1336 len = bufend - fb->fb_off; 1337 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1338 BUS_DMASYNC_POSTREAD); 1339 *pp = fb->fb_buf + fb->fb_off; 1340 fb->fb_off += roundup(len, 4); 1341 return len; 1342 } 1343 1344 static int 1345 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1346 struct fwohci_pkt *pkt) 1347 { 1348 caddr_t p; 1349 struct fwohci_buf *fb; 1350 int len, count, i; 1351 #ifdef FW_DEBUG 1352 int tlabel; 1353 #endif 1354 1355 memset(pkt, 0, sizeof(*pkt)); 1356 pkt->fp_uio.uio_iov = pkt->fp_iov; 1357 pkt->fp_uio.uio_rw = UIO_WRITE; 1358 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1359 1360 /* get first quadlet */ 1361 fb = TAILQ_FIRST(&fc->fc_buf); 1362 count = 4; 1363 len = fwohci_buf_pktget(sc, &fb, &p, count); 1364 if (len <= 0) { 1365 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1366 fc->fc_ctx)); 1367 return 0; 1368 } 1369 pkt->fp_hdr[0] = *(u_int32_t *)p; 1370 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1371 switch (pkt->fp_tcode) { 1372 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1373 case IEEE1394_TCODE_READ_RESP_QUAD: 1374 pkt->fp_hlen = 12; 1375 pkt->fp_dlen = 4; 1376 break; 1377 case IEEE1394_TCODE_READ_REQ_BLOCK: 1378 pkt->fp_hlen = 16; 1379 pkt->fp_dlen = 0; 1380 break; 1381 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1382 case IEEE1394_TCODE_READ_RESP_BLOCK: 1383 case IEEE1394_TCODE_LOCK_REQ: 1384 case IEEE1394_TCODE_LOCK_RESP: 1385 pkt->fp_hlen = 16; 1386 break; 1387 case IEEE1394_TCODE_STREAM_DATA: 1388 #ifdef DIAGNOSTIC 1389 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) 1390 #endif 1391 { 1392 pkt->fp_hlen = 4; 1393 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1394 DPRINTFN(5, ("[%d]", pkt->fp_dlen)); 1395 break; 1396 } 1397 #ifdef DIAGNOSTIC 1398 else { 1399 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1400 return 0; 1401 } 1402 #endif 1403 default: 1404 pkt->fp_hlen = 12; 1405 pkt->fp_dlen = 0; 1406 break; 1407 } 1408 1409 /* get header */ 1410 while (count < pkt->fp_hlen) { 1411 len = fwohci_buf_pktget(sc, &fb, &p, pkt->fp_hlen - count); 1412 if (len == 0) { 1413 printf("fwohci_buf_input: malformed input 1: %d\n", 1414 pkt->fp_hlen - count); 1415 return 0; 1416 } 1417 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1418 count += len; 1419 } 1420 if (pkt->fp_hlen == 16 && 1421 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1422 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1423 #ifdef FW_DEBUG 1424 tlabel = (pkt->fp_hdr[0] & 0x0000fc00) >> 10; 1425 #endif 1426 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, tlabel=0x%x, hlen=%d, " 1427 "dlen=%d\n", pkt->fp_tcode, tlabel, pkt->fp_hlen, pkt->fp_dlen)); 1428 1429 /* get data */ 1430 count = 0; 1431 i = 0; 1432 while (count < pkt->fp_dlen) { 1433 len = fwohci_buf_pktget(sc, &fb, 1434 (caddr_t *)&pkt->fp_iov[i].iov_base, 1435 pkt->fp_dlen - count); 1436 if (len == 0) { 1437 printf("fwohci_buf_input: malformed input 2: %d\n", 1438 pkt->fp_dlen - count); 1439 return 0; 1440 } 1441 pkt->fp_iov[i++].iov_len = len; 1442 count += len; 1443 } 1444 pkt->fp_uio.uio_iovcnt = i; 1445 pkt->fp_uio.uio_resid = count; 1446 1447 /* get trailer */ 1448 len = fwohci_buf_pktget(sc, &fb, (caddr_t *)&pkt->fp_trail, 1449 sizeof(*pkt->fp_trail)); 1450 if (len <= 0) { 1451 printf("fwohci_buf_input: malformed input 3: %d\n", 1452 pkt->fp_hlen - count); 1453 return 0; 1454 } 1455 return 1; 1456 } 1457 1458 static int 1459 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1460 struct fwohci_pkt *pkt) 1461 { 1462 caddr_t p; 1463 int len; 1464 struct fwohci_buf *fb; 1465 struct fwohci_desc *fd; 1466 1467 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1468 return fwohci_buf_input(sc, fc, pkt); 1469 } 1470 1471 memset(pkt, 0, sizeof(*pkt)); 1472 pkt->fp_uio.uio_iov = pkt->fp_iov; 1473 pkt->fp_uio.uio_rw = UIO_WRITE; 1474 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1475 1476 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1477 if (fb == NULL) 1478 return 0; 1479 if (fb->fb_off == 0) 1480 break; 1481 } 1482 fd = fb->fb_desc; 1483 len = fd->fd_reqcount - fd->fd_rescount; 1484 if (len == 0) 1485 return 0; 1486 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1487 BUS_DMASYNC_POSTREAD); 1488 1489 p = fb->fb_buf; 1490 fb->fb_off += roundup(len, 4); 1491 if (len < 8) { 1492 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1493 return 0; 1494 } 1495 1496 /* 1497 * get trailer first, may be bogus data unless status update 1498 * in descriptor is set. 1499 */ 1500 pkt->fp_trail = (u_int32_t *)p; 1501 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1502 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1503 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1504 #ifdef DIAGNOSTIC 1505 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1506 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1507 pkt->fp_tcode); 1508 return 0; 1509 } 1510 #endif 1511 pkt->fp_hlen = 4; 1512 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1513 p += 8; 1514 len -= 8; 1515 if (pkt->fp_dlen != len) { 1516 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1517 pkt->fp_dlen, len); 1518 return 0; 1519 } 1520 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1521 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1522 pkt->fp_iov[0].iov_base = p; 1523 pkt->fp_iov[0].iov_len = len; 1524 pkt->fp_uio.uio_iovcnt = 0; 1525 pkt->fp_uio.uio_resid = len; 1526 return 1; 1527 } 1528 1529 static int 1530 fwohci_handler_set(struct fwohci_softc *sc, 1531 int tcode, u_int32_t key1, u_int32_t key2, 1532 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1533 void *arg) 1534 { 1535 struct fwohci_ctx *fc; 1536 struct fwohci_handler *fh; 1537 int i, j; 1538 1539 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1540 int isasync = key1 & OHCI_ASYNC_STREAM; 1541 1542 key1 &= IEEE1394_ISOCH_MASK; 1543 j = sc->sc_isoctx; 1544 fh = NULL; 1545 for (i = 0; i < sc->sc_isoctx; i++) { 1546 if ((fc = sc->sc_ctx_ir[i]) == NULL) { 1547 if (j == sc->sc_isoctx) 1548 j = i; 1549 continue; 1550 } 1551 fh = LIST_FIRST(&fc->fc_handler); 1552 if (fh->fh_tcode == tcode && 1553 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1554 break; 1555 fh = NULL; 1556 } 1557 if (fh == NULL) { 1558 if (handler == NULL) 1559 return 0; 1560 if (j == sc->sc_isoctx) { 1561 DPRINTF(("fwohci_handler_set: no more free " 1562 "context\n")); 1563 return ENOMEM; 1564 } 1565 if ((fc = sc->sc_ctx_ir[j]) == NULL) { 1566 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j, 1567 isasync ? FWOHCI_CTX_ISO_SINGLE : 1568 FWOHCI_CTX_ISO_MULTI); 1569 sc->sc_ctx_ir[j] = fc; 1570 } 1571 } 1572 } else { 1573 switch (tcode) { 1574 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1575 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1576 case IEEE1394_TCODE_READ_REQ_QUAD: 1577 case IEEE1394_TCODE_READ_REQ_BLOCK: 1578 case IEEE1394_TCODE_LOCK_REQ: 1579 fc = sc->sc_ctx_arrq; 1580 break; 1581 case IEEE1394_TCODE_WRITE_RESP: 1582 case IEEE1394_TCODE_READ_RESP_QUAD: 1583 case IEEE1394_TCODE_READ_RESP_BLOCK: 1584 case IEEE1394_TCODE_LOCK_RESP: 1585 fc = sc->sc_ctx_arrs; 1586 break; 1587 default: 1588 return EIO; 1589 } 1590 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1591 fh = LIST_NEXT(fh, fh_list)) { 1592 if (fh->fh_tcode == tcode && 1593 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1594 break; 1595 } 1596 } 1597 if (handler == NULL) { 1598 if (fh != NULL) { 1599 LIST_REMOVE(fh, fh_list); 1600 free(fh, M_DEVBUF); 1601 } 1602 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1603 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1604 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1605 sc->sc_ctx_ir[fc->fc_ctx] = NULL; 1606 fwohci_ctx_free(sc, fc); 1607 } 1608 return 0; 1609 } 1610 if (fh == NULL) { 1611 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1612 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1613 } 1614 fh->fh_tcode = tcode; 1615 fh->fh_key1 = key1; 1616 fh->fh_key2 = key2; 1617 fh->fh_handler = handler; 1618 fh->fh_handarg = arg; 1619 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1620 fc->fc_ctx, tcode, key1, key2)); 1621 1622 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1623 fwohci_ctx_init(sc, fc); 1624 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1625 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1626 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1627 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1628 } 1629 return 0; 1630 } 1631 1632 /* 1633 * Asyncronous Receive Requests input frontend. 1634 */ 1635 static void 1636 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1637 { 1638 int rcode; 1639 u_int32_t key1, key2; 1640 struct fwohci_handler *fh; 1641 struct fwohci_pkt pkt, res; 1642 1643 /* 1644 * Do not return if next packet is in the buffer, or the next 1645 * packet cannot be received until the next receive interrupt. 1646 */ 1647 while (fwohci_buf_input(sc, fc, &pkt)) { 1648 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 1649 fwohci_phy_input(sc, &pkt); 1650 continue; 1651 } 1652 key1 = pkt.fp_hdr[1] & 0xffff; 1653 key2 = pkt.fp_hdr[2]; 1654 memset(&res, 0, sizeof(res)); 1655 res.fp_uio.uio_rw = UIO_WRITE; 1656 res.fp_uio.uio_segflg = UIO_SYSSPACE; 1657 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1658 fh = LIST_NEXT(fh, fh_list)) { 1659 if (pkt.fp_tcode == fh->fh_tcode && 1660 key1 == fh->fh_key1 && 1661 key2 == fh->fh_key2) { 1662 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1663 &pkt); 1664 break; 1665 } 1666 } 1667 if (fh == NULL) { 1668 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 1669 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 1670 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 1671 key2)); 1672 } 1673 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 1674 OHCI_CTXCTL_EVENT_ACK_PENDING) 1675 continue; 1676 if (rcode != -1) 1677 fwohci_atrs_output(sc, rcode, &pkt, &res); 1678 } 1679 fwohci_buf_next(sc, fc); 1680 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1681 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1682 } 1683 1684 1685 /* 1686 * Asynchronous Receive Response input frontend. 1687 */ 1688 static void 1689 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1690 { 1691 struct fwohci_pkt pkt; 1692 struct fwohci_handler *fh; 1693 u_int16_t srcid; 1694 int rcode, tlabel; 1695 1696 while (fwohci_buf_input(sc, fc, &pkt)) { 1697 srcid = pkt.fp_hdr[1] >> 16; 1698 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 1699 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 1700 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 1701 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 1702 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 1703 pkt.fp_dlen)); 1704 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1705 fh = LIST_NEXT(fh, fh_list)) { 1706 if (pkt.fp_tcode == fh->fh_tcode && 1707 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 1708 tlabel == fh->fh_key2) { 1709 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 1710 LIST_REMOVE(fh, fh_list); 1711 free(fh, M_DEVBUF); 1712 break; 1713 } 1714 } 1715 if (fh == NULL) 1716 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 1717 } 1718 fwohci_buf_next(sc, fc); 1719 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1720 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1721 } 1722 1723 /* 1724 * Isochronous Receive input frontend. 1725 */ 1726 static void 1727 fwohci_ir_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1728 { 1729 int rcode, chan, tag; 1730 struct iovec *iov; 1731 struct fwohci_handler *fh; 1732 struct fwohci_pkt pkt; 1733 1734 #if DOUBLEBUF 1735 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1736 struct fwohci_buf *fb; 1737 int i; 1738 u_int32_t reg; 1739 1740 /* stop dma engine before read buffer */ 1741 reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, 1742 OHCI_SUBREG_ContextControlClear); 1743 DPRINTFN(5, ("ir_input %08x =>", reg)); 1744 if (reg & OHCI_CTXCTL_RUN) { 1745 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1746 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1747 } 1748 DPRINTFN(5, (" %08x\n", OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlClear))); 1749 1750 i = 0; 1751 while ((reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet)) & OHCI_CTXCTL_ACTIVE) { 1752 delay(10); 1753 if (++i > 10000) { 1754 printf("cannot stop dma engine 0x%08x\n", reg); 1755 return; 1756 } 1757 } 1758 1759 /* rotate dma buffer */ 1760 fb = TAILQ_FIRST(&fc->fc_buf2); 1761 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_CommandPtr, 1762 fb->fb_daddr | 1); 1763 /* start dma engine */ 1764 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1765 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1766 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, 1767 (1 << fc->fc_ctx)); 1768 } 1769 #endif 1770 1771 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 1772 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 1773 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 1774 DPRINTFN(1, ("fwohci_ir_input: hdr 0x%08x, tcode 0x%0x, hlen %d" 1775 ", dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 1776 pkt.fp_dlen)); 1777 if (tag == IEEE1394_TAG_GASP) { 1778 /* 1779 * The pkt with tag=3 is GASP format. 1780 * Move GASP header to header part. 1781 */ 1782 if (pkt.fp_dlen < 8) 1783 continue; 1784 iov = pkt.fp_iov; 1785 /* assuming pkt per buffer mode */ 1786 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 1787 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 1788 iov->iov_base = (caddr_t)iov->iov_base + 8; 1789 iov->iov_len -= 8; 1790 pkt.fp_hlen += 8; 1791 pkt.fp_dlen -= 8; 1792 } 1793 sc->sc_isopktcnt.ev_count++; 1794 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1795 fh = LIST_NEXT(fh, fh_list)) { 1796 if (pkt.fp_tcode == fh->fh_tcode && 1797 chan == fh->fh_key1 && tag == fh->fh_key2) { 1798 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 1799 &pkt); 1800 break; 1801 } 1802 } 1803 #ifdef FW_DEBUG 1804 if (fh == NULL) { 1805 DPRINTFN(1, ("fwohci_ir_input: no handler\n")); 1806 } else { 1807 DPRINTFN(1, ("fwohci_ir_input: rcode %d\n", rcode)); 1808 } 1809 #endif 1810 } 1811 fwohci_buf_next(sc, fc); 1812 1813 if (fc->fc_type == FWOHCI_CTX_ISO_SINGLE) { 1814 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1815 OHCI_SUBREG_ContextControlSet, 1816 OHCI_CTXCTL_WAKE); 1817 } 1818 } 1819 1820 /* 1821 * Asynchronous Transmit common routine. 1822 */ 1823 static int 1824 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1825 struct fwohci_pkt *pkt) 1826 { 1827 struct fwohci_buf *fb; 1828 struct fwohci_desc *fd; 1829 struct mbuf *m, *m0; 1830 int i, ndesc, error, off, len; 1831 u_int32_t val; 1832 #ifdef FW_DEBUG 1833 struct iovec *iov; 1834 int tlabel = (pkt->fp_hdr[0] & 0x0000fc00) >> 10; 1835 #endif 1836 1837 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 1838 /* We can't send anything during selfid duration */ 1839 return EAGAIN; 1840 1841 #ifdef FW_DEBUG 1842 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, tlabel 0x%x hlen %d, " 1843 "dlen %d", pkt->fp_tcode, tlabel, pkt->fp_hlen, pkt->fp_dlen)); 1844 for (i = 0; i < pkt->fp_hlen/4; i++) 1845 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 1846 DPRINTFN(2, ("$")); 1847 for (ndesc = 0, iov = pkt->fp_iov; 1848 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 1849 for (i = 0; i < iov->iov_len; i++) 1850 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 1851 ((u_int8_t *)iov->iov_base)[i])); 1852 DPRINTFN(2, ("$")); 1853 } 1854 DPRINTFN(1, ("\n")); 1855 #endif 1856 1857 if ((m = pkt->fp_m) != NULL) { 1858 for (ndesc = 2; m != NULL; m = m->m_next) 1859 ndesc++; 1860 if (ndesc > OHCI_DESC_MAX) { 1861 m0 = NULL; 1862 ndesc = 2; 1863 for (off = 0; off < pkt->fp_dlen; off += len) { 1864 if (m0 == NULL) { 1865 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1866 if (m0 != NULL) 1867 M_COPY_PKTHDR(m0, pkt->fp_m); 1868 m = m0; 1869 } else { 1870 MGET(m->m_next, M_DONTWAIT, MT_DATA); 1871 m = m->m_next; 1872 } 1873 if (m != NULL) 1874 MCLGET(m, M_DONTWAIT); 1875 if (m == NULL || (m->m_flags & M_EXT) == 0) { 1876 m_freem(m0); 1877 return ENOMEM; 1878 } 1879 len = pkt->fp_dlen - off; 1880 if (len > m->m_ext.ext_size) 1881 len = m->m_ext.ext_size; 1882 m_copydata(pkt->fp_m, off, len, 1883 mtod(m, caddr_t)); 1884 m->m_len = len; 1885 ndesc++; 1886 } 1887 m_freem(pkt->fp_m); 1888 pkt->fp_m = m0; 1889 } 1890 } else 1891 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 1892 1893 if (ndesc > OHCI_DESC_MAX) 1894 return ENOBUFS; 1895 1896 if (fc->fc_bufcnt > 50) /*XXX*/ 1897 return ENOBUFS; 1898 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 1899 fb->fb_nseg = ndesc; 1900 fb->fb_desc = fwohci_desc_get(sc, ndesc); 1901 if (fb->fb_desc == NULL) { 1902 free(fb, M_DEVBUF); 1903 return ENOBUFS; 1904 } 1905 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1906 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 1907 fb->fb_m = pkt->fp_m; 1908 fb->fb_callback = pkt->fp_callback; 1909 fb->fb_statuscb = pkt->fp_statuscb; 1910 fb->fb_statusarg = pkt->fp_statusarg; 1911 1912 if (ndesc > 2) { 1913 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, ndesc, 1914 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1915 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1916 free(fb, M_DEVBUF); 1917 return error; 1918 } 1919 1920 if (pkt->fp_m != NULL) 1921 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 1922 pkt->fp_m, BUS_DMA_WAITOK); 1923 else 1924 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 1925 &pkt->fp_uio, BUS_DMA_WAITOK); 1926 if (error != 0) { 1927 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1928 fwohci_desc_put(sc, fb->fb_desc, ndesc); 1929 free(fb, M_DEVBUF); 1930 return error; 1931 } 1932 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 1933 BUS_DMASYNC_PREWRITE); 1934 } 1935 1936 fd = fb->fb_desc; 1937 fd->fd_flags = OHCI_DESC_IMMED; 1938 fd->fd_reqcount = pkt->fp_hlen; 1939 fd->fd_data = 0; 1940 fd->fd_branch = 0; 1941 fd->fd_status = 0; 1942 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 1943 i = 3; /* XXX: 3 sec */ 1944 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 1945 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 1946 ((((val >> 25) + i) & 0x7) << 13); 1947 } else 1948 fd->fd_timestamp = 0; 1949 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 1950 for (i = 0; i < ndesc - 2; i++) { 1951 fd = fb->fb_desc + 2 + i; 1952 fd->fd_flags = 0; 1953 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 1954 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 1955 fd->fd_branch = 0; 1956 fd->fd_status = 0; 1957 fd->fd_timestamp = 0; 1958 } 1959 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 1960 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 1961 1962 #ifdef FW_DEBUG 1963 DPRINTFN(1, ("fwohci_at_output: desc %ld", 1964 (long)(fb->fb_desc - sc->sc_desc))); 1965 for (i = 0; i < ndesc * 4; i++) 1966 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 1967 ((u_int32_t *)fb->fb_desc)[i])); 1968 DPRINTFN(1, ("\n")); 1969 #endif 1970 1971 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 1972 OHCI_SUBREG_ContextControlClear); 1973 1974 if (val & OHCI_CTXCTL_RUN) { 1975 if (fc->fc_branch == NULL) { 1976 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1977 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1978 goto run; 1979 } 1980 *fc->fc_branch = fb->fb_daddr | ndesc; 1981 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1982 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 1983 } else { 1984 run: 1985 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1986 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 1987 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 1988 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1989 } 1990 fc->fc_branch = &fd->fd_branch; 1991 1992 fc->fc_bufcnt++; 1993 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1994 pkt->fp_m = NULL; 1995 return 0; 1996 } 1997 1998 static void 1999 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 2000 { 2001 struct fwohci_buf *fb; 2002 struct fwohci_desc *fd; 2003 struct fwohci_pkt pkt; 2004 int i; 2005 2006 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 2007 fd = fb->fb_desc; 2008 #ifdef FW_DEBUG 2009 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 2010 force ? "force " : "", (long)(fd - sc->sc_desc), 2011 fb->fb_nseg)); 2012 for (i = 0; i < fb->fb_nseg * 4; i++) 2013 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 2014 ((u_int32_t *)fd)[i])); 2015 DPRINTFN(1, ("\n")); 2016 #endif 2017 if (fb->fb_nseg > 2) 2018 fd += fb->fb_nseg - 1; 2019 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 2020 break; 2021 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 2022 if (fc->fc_branch == &fd->fd_branch) { 2023 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2024 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2025 fc->fc_branch = NULL; 2026 for (i = 0; i < OHCI_LOOP; i++) { 2027 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 2028 OHCI_SUBREG_ContextControlClear) & 2029 OHCI_CTXCTL_ACTIVE)) 2030 break; 2031 DELAY(10); 2032 } 2033 } 2034 2035 if (fb->fb_statuscb) { 2036 memset(&pkt, 0, sizeof(pkt)); 2037 pkt.fp_status = fd->fd_status; 2038 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 2039 2040 /* Indicate this is just returning the status bits. */ 2041 pkt.fp_tcode = -1; 2042 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 2043 fb->fb_statuscb = NULL; 2044 fb->fb_statusarg = NULL; 2045 } 2046 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 2047 if (fb->fb_nseg > 2) 2048 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 2049 fc->fc_bufcnt--; 2050 if (fb->fb_callback) { 2051 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 2052 fb->fb_callback = NULL; 2053 } else if (fb->fb_m != NULL) 2054 m_freem(fb->fb_m); 2055 free(fb, M_DEVBUF); 2056 } 2057 } 2058 2059 /* 2060 * Asynchronous Transmit Reponse -- in response of request packet. 2061 */ 2062 static void 2063 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 2064 struct fwohci_pkt *res) 2065 { 2066 2067 if (((*req->fp_trail & 0x001f0000) >> 16) != 2068 OHCI_CTXCTL_EVENT_ACK_PENDING) 2069 return; 2070 2071 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 2072 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 2073 switch (req->fp_tcode) { 2074 case IEEE1394_TCODE_WRITE_REQ_QUAD: 2075 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 2076 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 2077 res->fp_hlen = 12; 2078 break; 2079 case IEEE1394_TCODE_READ_REQ_QUAD: 2080 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2081 res->fp_hlen = 16; 2082 res->fp_dlen = 0; 2083 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 2084 res->fp_hdr[3] = 2085 *(u_int32_t *)res->fp_iov[0].iov_base; 2086 res->fp_uio.uio_iovcnt = 0; 2087 break; 2088 case IEEE1394_TCODE_READ_REQ_BLOCK: 2089 case IEEE1394_TCODE_LOCK_REQ: 2090 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 2091 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 2092 else 2093 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2094 res->fp_hlen = 16; 2095 res->fp_dlen = res->fp_uio.uio_resid; 2096 res->fp_hdr[3] = res->fp_dlen << 16; 2097 break; 2098 } 2099 res->fp_hdr[0] |= (res->fp_tcode << 4); 2100 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 2101 } 2102 2103 /* 2104 * APPLICATION LAYER SERVICES 2105 */ 2106 2107 /* 2108 * Retrieve Global UID from GUID ROM 2109 */ 2110 static int 2111 fwohci_guidrom_init(struct fwohci_softc *sc) 2112 { 2113 int i, n, off; 2114 u_int32_t val1, val2; 2115 2116 /* Extract the Global UID 2117 */ 2118 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 2119 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 2120 2121 if (val1 != 0 || val2 != 0) { 2122 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 2123 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 2124 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 2125 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 2126 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 2127 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 2128 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 2129 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 2130 } else { 2131 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 2132 if ((val1 & OHCI_Version_GUID_ROM) == 0) 2133 return -1; 2134 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 2135 for (i = 0; i < OHCI_LOOP; i++) { 2136 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2137 if (!(val1 & OHCI_Guid_AddrReset)) 2138 break; 2139 DELAY(10); 2140 } 2141 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 2142 val2 = 0; 2143 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 2144 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 2145 OHCI_Guid_RdStart); 2146 for (i = 0; i < OHCI_LOOP; i++) { 2147 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2148 if (!(val1 & OHCI_Guid_RdStart)) 2149 break; 2150 DELAY(10); 2151 } 2152 if (n < off) 2153 continue; 2154 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 2155 sc->sc_sc1394.sc1394_guid[n - off] = val1; 2156 val2 |= val1; 2157 } 2158 if (val2 == 0) 2159 return -1; 2160 } 2161 return 0; 2162 } 2163 2164 /* 2165 * Initialization for Configuration ROM (no DMA context) 2166 */ 2167 2168 #define CFR_MAXUNIT 20 2169 2170 struct configromctx { 2171 u_int32_t *ptr; 2172 int curunit; 2173 struct { 2174 u_int32_t *start; 2175 int length; 2176 u_int32_t *refer; 2177 int refunit; 2178 } unit[CFR_MAXUNIT]; 2179 }; 2180 2181 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 2182 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 2183 2184 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 2185 2186 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 2187 2188 #define CFR_PUT_CRC(cfr, n) \ 2189 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 2190 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 2191 2192 #define CFR_START_UNIT(cfr, n) \ 2193 do { \ 2194 if ((cfr)->unit[n].refer != NULL) { \ 2195 *(cfr)->unit[n].refer |= \ 2196 (cfr)->ptr - (cfr)->unit[n].refer; \ 2197 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 2198 } \ 2199 (cfr)->curunit = (n); \ 2200 (cfr)->unit[n].start = (cfr)->ptr++; \ 2201 } while (0 /* CONSTCOND */) 2202 2203 #define CFR_PUT_REFER(cfr, key, n) \ 2204 do { \ 2205 (cfr)->unit[n].refer = (cfr)->ptr; \ 2206 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2207 *(cfr)->ptr++ = (key) << 24; \ 2208 } while (0 /* CONSTCOND */) 2209 2210 #define CFR_END_UNIT(cfr) \ 2211 do { \ 2212 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2213 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2214 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2215 } while (0 /* CONSTCOND */) 2216 2217 static u_int16_t 2218 fwohci_crc16(u_int32_t *ptr, int len) 2219 { 2220 int shift; 2221 u_int32_t crc, sum, data; 2222 2223 crc = 0; 2224 while (len-- > 0) { 2225 data = *ptr++; 2226 for (shift = 28; shift >= 0; shift -= 4) { 2227 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2228 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2229 } 2230 crc &= 0xffff; 2231 } 2232 return crc; 2233 } 2234 2235 static void 2236 fwohci_configrom_init(struct fwohci_softc *sc) 2237 { 2238 int i, val; 2239 struct fwohci_buf *fb; 2240 u_int32_t *hdr; 2241 struct configromctx cfr; 2242 2243 fb = &sc->sc_buf_cnfrom; 2244 memset(&cfr, 0, sizeof(cfr)); 2245 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2246 2247 /* headers */ 2248 CFR_START_UNIT(&cfr, 0); 2249 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2250 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2251 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2252 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2253 CFR_END_UNIT(&cfr); 2254 /* copy info_length from crc_length */ 2255 *hdr |= (*hdr & 0x00ff0000) << 8; 2256 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2257 2258 /* root directory */ 2259 CFR_START_UNIT(&cfr, 1); 2260 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2261 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2262 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2263 /* spt,64,fix,lst,drq */ 2264 #ifdef INET 2265 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2266 #endif /* INET */ 2267 #ifdef INET6 2268 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2269 #endif /* INET6 */ 2270 CFR_END_UNIT(&cfr); 2271 2272 CFR_START_UNIT(&cfr, 2); 2273 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2274 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2275 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2276 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2277 CFR_END_UNIT(&cfr); 2278 2279 #ifdef INET 2280 /* IPv4 unit directory */ 2281 CFR_START_UNIT(&cfr, 3); 2282 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2283 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2284 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2285 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2286 CFR_PUT_REFER(&cfr, 0x95, 8); /* Unit location */ 2287 CFR_END_UNIT(&cfr); 2288 2289 CFR_START_UNIT(&cfr, 6); 2290 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2291 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2292 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2293 CFR_END_UNIT(&cfr); 2294 2295 CFR_START_UNIT(&cfr, 7); 2296 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2297 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2298 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2299 CFR_END_UNIT(&cfr); 2300 2301 CFR_START_UNIT(&cfr, 8); /* Spec's valid addr range. */ 2302 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2303 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2304 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2305 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2306 CFR_END_UNIT(&cfr); 2307 2308 #endif /* INET */ 2309 2310 #ifdef INET6 2311 /* IPv6 unit directory */ 2312 CFR_START_UNIT(&cfr, 4); 2313 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2314 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2315 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2316 /* XXX: TBA by IANA */ 2317 CFR_PUT_REFER(&cfr, 0x81, 10); /* textual descriptor offset */ 2318 CFR_PUT_REFER(&cfr, 0x95, 11); /* Unit location */ 2319 CFR_END_UNIT(&cfr); 2320 2321 CFR_START_UNIT(&cfr, 9); 2322 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2323 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2324 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2325 CFR_END_UNIT(&cfr); 2326 2327 CFR_START_UNIT(&cfr, 10); 2328 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2329 CFR_PUT_DATA1(&cfr, 0); 2330 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2331 CFR_END_UNIT(&cfr); 2332 2333 CFR_START_UNIT(&cfr, 11); /* Spec's valid addr range. */ 2334 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2335 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2336 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2337 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2338 CFR_END_UNIT(&cfr); 2339 2340 #endif /* INET6 */ 2341 2342 fb->fb_off = cfr.ptr - hdr; 2343 #ifdef FW_DEBUG 2344 DPRINTF(("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2345 for (i = 0; i < fb->fb_off; i++) 2346 DPRINTF(("%s%08x", i&7?" ":"\n ", hdr[i])); 2347 DPRINTF(("\n")); 2348 #endif /* FW_DEBUG */ 2349 2350 /* 2351 * Make network byte order for DMA 2352 */ 2353 for (i = 0; i < fb->fb_off; i++) 2354 HTONL(hdr[i]); 2355 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2356 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2357 2358 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2359 fb->fb_dmamap->dm_segs[0].ds_addr); 2360 2361 /* This register is only valid on OHCI 1.1. */ 2362 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2363 if ((OHCI_Version_GET_Version(val) == 1) && 2364 (OHCI_Version_GET_Revision(val) == 1)) 2365 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2366 OHCI_HCControl_BIBImageValid); 2367 2368 /* Just allow quad reads of the rom. */ 2369 for (i = 0; i < fb->fb_off; i++) 2370 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2371 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2372 fwohci_configrom_input, NULL); 2373 } 2374 2375 static int 2376 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2377 struct fwohci_pkt *pkt) 2378 { 2379 struct fwohci_pkt res; 2380 u_int32_t loc, *rom; 2381 2382 /* This will be used as an array index so size accordingly. */ 2383 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2384 if ((loc & 0x03) != 0) { 2385 /* alignment error */ 2386 return IEEE1394_RCODE_ADDRESS_ERROR; 2387 } 2388 else 2389 loc /= 4; 2390 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2391 2392 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2393 ntohl(rom[loc]))); 2394 2395 memset(&res, 0, sizeof(res)); 2396 res.fp_hdr[3] = rom[loc]; 2397 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2398 return -1; 2399 } 2400 2401 /* 2402 * SelfID buffer (no DMA context) 2403 */ 2404 static void 2405 fwohci_selfid_init(struct fwohci_softc *sc) 2406 { 2407 struct fwohci_buf *fb; 2408 2409 fb = &sc->sc_buf_selfid; 2410 #ifdef DIAGNOSTIC 2411 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2412 panic("fwohci_selfid_init: not aligned: %ld (%ld) %p", 2413 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_addr, 2414 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2415 #endif 2416 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2417 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2418 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2419 2420 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2421 fb->fb_dmamap->dm_segs[0].ds_addr); 2422 } 2423 2424 static int 2425 fwohci_selfid_input(struct fwohci_softc *sc) 2426 { 2427 int i; 2428 u_int32_t count, val, gen; 2429 u_int32_t *buf; 2430 2431 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2432 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2433 again: 2434 if (val & OHCI_SelfID_Error) { 2435 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2436 return -1; 2437 } 2438 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2439 2440 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2441 0, count << 2, BUS_DMASYNC_POSTREAD); 2442 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2443 2444 #ifdef FW_DEBUG 2445 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2446 val)); 2447 for (i = 0; i < count; i++) 2448 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2449 DPRINTFN(1, ("\n")); 2450 #endif /* FW_DEBUG */ 2451 2452 for (i = 1; i < count; i += 2) { 2453 if (buf[i] != ~buf[i + 1]) 2454 break; 2455 if (buf[i] & 0x00000001) 2456 continue; /* more pkt */ 2457 if (buf[i] & 0x00800000) 2458 continue; /* external id */ 2459 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2460 if ((buf[i] & 0x00400800) == 0x00400800) 2461 sc->sc_irmid = sc->sc_rootid; 2462 } 2463 2464 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2465 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2466 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2467 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2468 goto again; 2469 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2470 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2471 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2472 return -1; 2473 } 2474 if (i != count) { 2475 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2476 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2477 #if 1 2478 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2479 /* 2480 * XXX: CXD3222 sometimes fails to DMA 2481 * selfid packet?? 2482 */ 2483 sc->sc_rootid = (count - 1) / 2 - 1; 2484 sc->sc_irmid = sc->sc_rootid; 2485 } else 2486 #endif 2487 return -1; 2488 } 2489 2490 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2491 if ((val & OHCI_NodeId_IDValid) == 0) { 2492 sc->sc_nodeid = 0xffff; /* invalid */ 2493 printf("%s: nodeid is invalid\n", 2494 sc->sc_sc1394.sc1394_dev.dv_xname); 2495 return -1; 2496 } 2497 sc->sc_nodeid = val & 0xffff; 2498 2499 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 2500 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 2501 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 2502 sc->sc_irmid)); 2503 2504 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 2505 return -1; 2506 2507 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 2508 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 2509 OHCI_LinkControl_CycleMaster); 2510 else 2511 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 2512 OHCI_LinkControl_CycleMaster); 2513 return 0; 2514 } 2515 2516 /* 2517 * some CSRs are handled by driver. 2518 */ 2519 static void 2520 fwohci_csr_init(struct fwohci_softc *sc) 2521 { 2522 int i; 2523 static u_int32_t csr[] = { 2524 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 2525 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 2526 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 2527 CSR_SB_BROADCAST_CHANNEL 2528 }; 2529 2530 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 2531 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 2532 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2533 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2534 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 2535 } 2536 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 2537 } 2538 2539 static int 2540 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2541 { 2542 struct fwohci_pkt res; 2543 u_int32_t reg; 2544 2545 /* 2546 * XXX need to do special functionality other than just r/w... 2547 */ 2548 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 2549 2550 if ((reg & 0x03) != 0) { 2551 /* alignment error */ 2552 return IEEE1394_RCODE_ADDRESS_ERROR; 2553 } 2554 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 2555 *(u_int32_t *)(&sc->sc_csr[reg]))); 2556 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 2557 DPRINTFN(1, (" -> 0x%08x\n", 2558 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 2559 *(u_int32_t *)&sc->sc_csr[reg] = 2560 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 2561 } else { 2562 DPRINTFN(1, ("\n")); 2563 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 2564 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 2565 res.fp_iov[0].iov_len = 4; 2566 res.fp_uio.uio_resid = 4; 2567 res.fp_uio.uio_iovcnt = 1; 2568 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2569 return -1; 2570 } 2571 return IEEE1394_RCODE_COMPLETE; 2572 } 2573 2574 /* 2575 * Mapping between nodeid and unique ID (EUI-64). 2576 * 2577 * Track old mappings and simply update their devices with the new id's when 2578 * they match an existing EUI. This allows proper renumeration of the bus. 2579 */ 2580 static void 2581 fwohci_uid_collect(struct fwohci_softc *sc) 2582 { 2583 int i; 2584 struct fwohci_uidtbl *fu; 2585 struct ieee1394_softc *iea; 2586 2587 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2588 iea->sc1394_node_id = 0xffff; 2589 2590 if (sc->sc_uidtbl != NULL) 2591 free(sc->sc_uidtbl, M_DEVBUF); 2592 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 2593 M_NOWAIT|M_ZERO); /* XXX M_WAITOK requires locks */ 2594 if (sc->sc_uidtbl == NULL) 2595 return; 2596 2597 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 2598 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 2599 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 2600 fu->fu_valid = 3; 2601 2602 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 2603 if (iea) { 2604 iea->sc1394_node_id = i; 2605 DPRINTF(("%s: Updating nodeid to %d\n", 2606 iea->sc1394_dev.dv_xname, 2607 iea->sc1394_node_id)); 2608 } 2609 } else { 2610 fu->fu_valid = 0; 2611 fwohci_uid_req(sc, i); 2612 } 2613 } 2614 if (sc->sc_rootid == 0) 2615 fwohci_check_nodes(sc); 2616 } 2617 2618 static void 2619 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 2620 { 2621 struct fwohci_pkt pkt; 2622 2623 memset(&pkt, 0, sizeof(pkt)); 2624 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 2625 pkt.fp_hlen = 12; 2626 pkt.fp_dlen = 0; 2627 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2628 (pkt.fp_tcode << 4); 2629 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 2630 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 2631 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2632 sc->sc_tlabel, fwohci_uid_input, (void *)0); 2633 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2634 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2635 2636 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 2637 (pkt.fp_tcode << 4); 2638 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 2639 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 2640 sc->sc_tlabel, fwohci_uid_input, (void *)1); 2641 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 2642 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 2643 } 2644 2645 static int 2646 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 2647 { 2648 struct fwohci_uidtbl *fu; 2649 struct ieee1394_softc *iea; 2650 struct ieee1394_attach_args fwa; 2651 int i, n, done, rcode, found; 2652 2653 found = 0; 2654 2655 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2656 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 2657 if (rcode != IEEE1394_RCODE_COMPLETE || 2658 sc->sc_uidtbl == NULL || 2659 n > sc->sc_rootid) 2660 return 0; 2661 fu = &sc->sc_uidtbl[n]; 2662 if (arg == 0) { 2663 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 2664 fu->fu_valid |= 0x1; 2665 } else { 2666 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 2667 fu->fu_valid |= 0x2; 2668 } 2669 #ifdef FW_DEBUG 2670 if (fu->fu_valid == 0x3) 2671 DPRINTFN(1, ("fwohci_uid_input: " 2672 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 2673 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 2674 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 2675 #endif 2676 if (fu->fu_valid == 0x3) { 2677 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 2678 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 2679 found = 1; 2680 iea->sc1394_node_id = n; 2681 DPRINTF(("%s: Updating nodeid to %d\n", 2682 iea->sc1394_dev.dv_xname, 2683 iea->sc1394_node_id)); 2684 if (iea->sc1394_callback.sc1394_reset) 2685 iea->sc1394_callback.sc1394_reset(iea, 2686 iea->sc1394_callback.sc1394_resetarg); 2687 break; 2688 } 2689 if (!found) { 2690 strcpy(fwa.name, "fwnode"); 2691 memcpy(fwa.uid, fu->fu_uid, 8); 2692 fwa.nodeid = n; 2693 iea = (struct ieee1394_softc *) 2694 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 2695 fwohci_print, fwohci_submatch); 2696 if (iea != NULL) 2697 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 2698 sc1394_node); 2699 } 2700 } 2701 done = 1; 2702 2703 for (i = 0; i < sc->sc_rootid + 1; i++) { 2704 fu = &sc->sc_uidtbl[i]; 2705 if (fu->fu_valid != 0x3) { 2706 done = 0; 2707 break; 2708 } 2709 } 2710 if (done) 2711 fwohci_check_nodes(sc); 2712 2713 return 0; 2714 } 2715 2716 static void 2717 fwohci_check_nodes(struct fwohci_softc *sc) 2718 { 2719 struct device *detach = NULL; 2720 struct ieee1394_softc *iea; 2721 2722 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 2723 2724 /* 2725 * Have to defer detachment until the next 2726 * loop iteration since config_detach 2727 * free's the softc and the loop iterator 2728 * needs data from the softc to move 2729 * forward. 2730 */ 2731 2732 if (detach) { 2733 config_detach(detach, 0); 2734 detach = NULL; 2735 } 2736 if (iea->sc1394_node_id == 0xffff) { 2737 detach = (struct device *)iea; 2738 LIST_REMOVE(iea, sc1394_node); 2739 } 2740 } 2741 if (detach) 2742 config_detach(detach, 0); 2743 } 2744 2745 static int 2746 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 2747 { 2748 struct fwohci_uidtbl *fu; 2749 int n; 2750 static const u_int8_t bcast[] = 2751 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2752 2753 fu = sc->sc_uidtbl; 2754 if (fu == NULL) { 2755 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2756 return IEEE1394_BCAST_PHY_ID; 2757 fwohci_uid_collect(sc); /* try to get */ 2758 return -1; 2759 } 2760 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 2761 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 2762 return n; 2763 } 2764 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 2765 return IEEE1394_BCAST_PHY_ID; 2766 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 2767 if (fu->fu_valid != 0x3) { 2768 /* 2769 * XXX: need timer before retransmission 2770 */ 2771 fwohci_uid_req(sc, n); 2772 } 2773 } 2774 return -1; 2775 } 2776 2777 /* 2778 * functions to support network interface 2779 */ 2780 static int 2781 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 2782 void (*handler)(struct device *, struct mbuf *)) 2783 { 2784 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2785 2786 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 2787 handler ? fwohci_if_input : NULL, handler); 2788 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 2789 (sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & IEEE1394_ISOCH_MASK) | 2790 OHCI_ASYNC_STREAM, 2791 IEEE1394_TAG_GASP, handler ? fwohci_if_input : NULL, handler); 2792 return 0; 2793 } 2794 2795 static int 2796 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2797 { 2798 int n, len; 2799 struct mbuf *m; 2800 struct iovec *iov; 2801 void (*handler)(struct device *, struct mbuf *) = arg; 2802 2803 #ifdef FW_DEBUG 2804 int i; 2805 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 2806 pkt->fp_dlen)); 2807 for (i = 0; i < pkt->fp_hlen/4; i++) 2808 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2809 DPRINTFN(2, ("$")); 2810 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2811 iov = &pkt->fp_iov[n]; 2812 for (i = 0; i < iov->iov_len; i++) 2813 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2814 ((u_int8_t *)iov->iov_base)[i])); 2815 DPRINTFN(2, ("$")); 2816 } 2817 DPRINTFN(1, ("\n")); 2818 #endif /* FW_DEBUG */ 2819 len = pkt->fp_dlen; 2820 MGETHDR(m, M_DONTWAIT, MT_DATA); 2821 if (m == NULL) 2822 return IEEE1394_RCODE_COMPLETE; 2823 m->m_len = 16; 2824 if (len + m->m_len > MHLEN) { 2825 MCLGET(m, M_DONTWAIT); 2826 if ((m->m_flags & M_EXT) == 0) { 2827 m_freem(m); 2828 return IEEE1394_RCODE_COMPLETE; 2829 } 2830 } 2831 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2832 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2833 sc->sc_uidtbl[n].fu_valid != 0x3) { 2834 printf("%s: packet from unknown node: phy id %d\n", 2835 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2836 m_freem(m); 2837 fwohci_uid_req(sc, n); 2838 return IEEE1394_RCODE_COMPLETE; 2839 } 2840 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2841 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 2842 m->m_flags |= M_BCAST; 2843 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 2844 } else { 2845 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2846 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2847 } 2848 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2849 mtod(m, u_int8_t *)[9] = 2850 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2851 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2852 2853 m->m_pkthdr.rcvif = NULL; /* set in child */ 2854 m->m_pkthdr.len = len + m->m_len; 2855 /* 2856 * We may use receive buffer by external mbuf instead of copy here. 2857 * But asynchronous receive buffer must be operate in buffer fill 2858 * mode, so that each receive buffer will shared by multiple mbufs. 2859 * If upper layer doesn't free mbuf soon, e.g. application program 2860 * is suspended, buffer must be reallocated. 2861 * Isochronous buffer must be operate in packet buffer mode, and 2862 * it is easy to map receive buffer to external mbuf. But it is 2863 * used for broadcast/multicast only, and is expected not so 2864 * performance sensitive for now. 2865 * XXX: The performance may be important for multicast case, 2866 * so we should revisit here later. 2867 * -- onoe 2868 */ 2869 n = 0; 2870 iov = pkt->fp_uio.uio_iov; 2871 while (len > 0) { 2872 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2873 iov->iov_len); 2874 m->m_len += iov->iov_len; 2875 len -= iov->iov_len; 2876 iov++; 2877 } 2878 (*handler)(sc->sc_sc1394.sc1394_if, m); 2879 return IEEE1394_RCODE_COMPLETE; 2880 } 2881 2882 static int 2883 fwohci_if_input_iso(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 2884 { 2885 int n, len; 2886 int chan, tag; 2887 struct mbuf *m; 2888 struct iovec *iov; 2889 void (*handler)(struct device *, struct mbuf *) = arg; 2890 #ifdef FW_DEBUG 2891 int i; 2892 #endif 2893 2894 chan = (pkt->fp_hdr[0] & 0x00003f00) >> 8; 2895 tag = (pkt->fp_hdr[0] & 0x0000c000) >> 14; 2896 #ifdef FW_DEBUG 2897 DPRINTFN(1, ("fwohci_if_input_iso: " 2898 "tcode=0x%x, chan=%d, tag=%x, dlen=%d", 2899 pkt->fp_tcode, chan, tag, pkt->fp_dlen)); 2900 for (i = 0; i < pkt->fp_hlen/4; i++) 2901 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 2902 DPRINTFN(2, ("$")); 2903 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 2904 iov = &pkt->fp_iov[n]; 2905 for (i = 0; i < iov->iov_len; i++) 2906 DPRINTFN(2, ("%s%02x", 2907 (i%32)?((i%4)?"":" "):"\n\t", 2908 ((u_int8_t *)iov->iov_base)[i])); 2909 DPRINTFN(2, ("$")); 2910 } 2911 DPRINTFN(2, ("\n")); 2912 #endif /* FW_DEBUG */ 2913 len = pkt->fp_dlen; 2914 MGETHDR(m, M_DONTWAIT, MT_DATA); 2915 if (m == NULL) 2916 return IEEE1394_RCODE_COMPLETE; 2917 m->m_len = 16; 2918 if (m->m_len + len > MHLEN) { 2919 MCLGET(m, M_DONTWAIT); 2920 if ((m->m_flags & M_EXT) == 0) { 2921 m_freem(m); 2922 return IEEE1394_RCODE_COMPLETE; 2923 } 2924 } 2925 2926 m->m_flags |= M_BCAST; 2927 2928 if (tag == IEEE1394_TAG_GASP) { 2929 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 2930 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 2931 sc->sc_uidtbl[n].fu_valid != 0x3) { 2932 printf("%s: packet from unknown node: phy id %d\n", 2933 sc->sc_sc1394.sc1394_dev.dv_xname, n); 2934 m_freem(m); 2935 return IEEE1394_RCODE_COMPLETE; 2936 } 2937 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 2938 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 2939 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 2940 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 2941 mtod(m, u_int8_t *)[9] = 2942 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 2943 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 2944 } 2945 mtod(m, u_int8_t *)[14] = chan; 2946 mtod(m, u_int8_t *)[15] = tag; 2947 2948 2949 m->m_pkthdr.rcvif = NULL; /* set in child */ 2950 m->m_pkthdr.len = len + m->m_len; 2951 /* 2952 * We may use receive buffer by external mbuf instead of copy here. 2953 * But asynchronous receive buffer must be operate in buffer fill 2954 * mode, so that each receive buffer will shared by multiple mbufs. 2955 * If upper layer doesn't free mbuf soon, e.g. application program 2956 * is suspended, buffer must be reallocated. 2957 * Isochronous buffer must be operate in packet buffer mode, and 2958 * it is easy to map receive buffer to external mbuf. But it is 2959 * used for broadcast/multicast only, and is expected not so 2960 * performance sensitive for now. 2961 * XXX: The performance may be important for multicast case, 2962 * so we should revisit here later. 2963 * -- onoe 2964 */ 2965 n = 0; 2966 iov = pkt->fp_uio.uio_iov; 2967 while (len > 0) { 2968 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 2969 iov->iov_len); 2970 m->m_len += iov->iov_len; 2971 len -= iov->iov_len; 2972 iov++; 2973 } 2974 (*handler)(sc->sc_sc1394.sc1394_if, m); 2975 return IEEE1394_RCODE_COMPLETE; 2976 } 2977 2978 2979 2980 static int 2981 fwohci_if_output(struct device *self, struct mbuf *m0, 2982 void (*callback)(struct device *, struct mbuf *)) 2983 { 2984 struct fwohci_softc *sc = (struct fwohci_softc *)self; 2985 struct fwohci_pkt pkt; 2986 u_int8_t *p; 2987 int n, error, spd, hdrlen, maxrec; 2988 #ifdef FW_DEBUG 2989 struct mbuf *m; 2990 #endif 2991 2992 p = mtod(m0, u_int8_t *); 2993 if (m0->m_flags & (M_BCAST | M_MCAST)) { 2994 spd = IEEE1394_SPD_S100; /*XXX*/ 2995 maxrec = 512; /*XXX*/ 2996 hdrlen = 8; 2997 } else { 2998 n = fwohci_uid_lookup(sc, p); 2999 if (n < 0) { 3000 printf("%s: nodeid unknown:" 3001 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 3002 sc->sc_sc1394.sc1394_dev.dv_xname, 3003 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 3004 error = EHOSTUNREACH; 3005 goto end; 3006 } 3007 if (n == IEEE1394_BCAST_PHY_ID) { 3008 printf("%s: broadcast with !M_MCAST\n", 3009 sc->sc_sc1394.sc1394_dev.dv_xname); 3010 #ifdef FW_DEBUG 3011 DPRINTFN(2, ("packet:")); 3012 for (m = m0; m != NULL; m = m->m_next) { 3013 for (n = 0; n < m->m_len; n++) 3014 DPRINTFN(2, ("%s%02x", (n%32)? 3015 ((n%4)?"":" "):"\n ", 3016 mtod(m, u_int8_t *)[n])); 3017 DPRINTFN(2, ("$")); 3018 } 3019 DPRINTFN(2, ("\n")); 3020 #endif 3021 error = EHOSTUNREACH; 3022 goto end; 3023 } 3024 maxrec = 2 << p[8]; 3025 spd = p[9]; 3026 hdrlen = 0; 3027 } 3028 if (spd > sc->sc_sc1394.sc1394_link_speed) { 3029 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 3030 spd, sc->sc_sc1394.sc1394_link_speed)); 3031 spd = sc->sc_sc1394.sc1394_link_speed; 3032 } 3033 if (maxrec > (512 << spd)) { 3034 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 3035 "\n", maxrec, spd)); 3036 maxrec = 512 << spd; 3037 } 3038 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 3039 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 3040 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 3041 maxrec >>= 1; 3042 } 3043 if (maxrec < 512) { 3044 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 3045 "minimum\n", maxrec)); 3046 maxrec = 512; 3047 } 3048 3049 m_adj(m0, 16 - hdrlen); 3050 if (m0->m_pkthdr.len > maxrec) { 3051 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 3052 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 3053 error = E2BIG; /*XXX*/ 3054 goto end; 3055 } 3056 3057 memset(&pkt, 0, sizeof(pkt)); 3058 pkt.fp_uio.uio_iov = pkt.fp_iov; 3059 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3060 pkt.fp_uio.uio_rw = UIO_WRITE; 3061 if (m0->m_flags & (M_BCAST | M_MCAST)) { 3062 /* construct GASP header */ 3063 p = mtod(m0, u_int8_t *); 3064 p[0] = sc->sc_nodeid >> 8; 3065 p[1] = sc->sc_nodeid & 0xff; 3066 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 3067 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 3068 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 3069 pkt.fp_hlen = 8; 3070 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 3071 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 3072 OHCI_NodeId_NodeNumber) << 8); 3073 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 3074 } else { 3075 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 3076 pkt.fp_hlen = 16; 3077 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 3078 (spd << 16); 3079 pkt.fp_hdr[1] = 3080 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 3081 (p[10] << 8) | p[11]; 3082 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 3083 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 3084 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3085 } 3086 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 3087 pkt.fp_dlen = m0->m_pkthdr.len; 3088 pkt.fp_m = m0; 3089 pkt.fp_callback = callback; 3090 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3091 m0 = pkt.fp_m; 3092 end: 3093 if (m0 != NULL) { 3094 if (callback) 3095 (*callback)(sc->sc_sc1394.sc1394_if, m0); 3096 else 3097 m_freem(m0); 3098 } 3099 return error; 3100 } 3101 3102 /* 3103 * High level routines to provide abstraction to attaching layers to 3104 * send/receive data. 3105 */ 3106 3107 /* 3108 * These break down into 4 routines as follows: 3109 * 3110 * int fwohci_read(struct ieee1394_abuf *) 3111 * 3112 * This routine will attempt to read a region from the requested node. 3113 * A callback must be provided which will be called when either the completed 3114 * read is done or an unrecoverable error occurs. This is mainly a convenience 3115 * routine since it will encapsulate retrying a region as quadlet vs. block 3116 * reads and recombining all the returned data. This could also be done with a 3117 * series of write/inreg's for each packet sent. 3118 * 3119 * int fwohci_write(struct ieee1394_abuf *) 3120 * 3121 * The work horse main entry point for putting packets on the bus. This is the 3122 * generalized interface for fwnode/etc code to put packets out onto the bus. 3123 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and 3124 * optionally will callback via a func pointer to the calling code with the 3125 * resulting ACK code from the packet. If the ACK code is to be ignored (i.e. 3126 * no cb) then the write routine will take care of free'ing the abuf since the 3127 * fwnode/etc code won't have any knowledge of when to do this. This allows for 3128 * simple one-off packets to be sent from the upper-level code without worrying 3129 * about a callback for cleanup. 3130 * 3131 * int fwohci_inreg(struct ieee1394_abuf *, int) 3132 * 3133 * This is very simple. It evals the abuf passed in and registers an internal 3134 * handler as the callback for packets received for that operation. 3135 * The integer argument specifies whether on a block read/write operation to 3136 * allow sub-regions to be read/written (in block form) as well. 3137 * 3138 * XXX: This whole structure needs to be redone as a list of regions and 3139 * operations allowed on those regions. 3140 * 3141 * int fwohci_unreg(struct ieee1394_abuf *, int) 3142 * 3143 * This simply unregisters the respective callback done via inreg for items 3144 * which only need to register an area for a one-time operation (like a status 3145 * buffer a remote node will write to when the current operation is done). The 3146 * int argument specifies the same behavior as inreg, except in reverse (i.e. 3147 * it unregisters). 3148 */ 3149 3150 static int 3151 fwohci_read(struct ieee1394_abuf *ab) 3152 { 3153 struct fwohci_pkt pkt; 3154 struct ieee1394_softc *sc = ab->ab_req; 3155 struct fwohci_softc *psc = 3156 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3157 struct fwohci_cb *fcb; 3158 u_int32_t high, lo; 3159 int rv, tcode; 3160 3161 /* Have to have a callback when reading. */ 3162 if (ab->ab_cb == NULL) 3163 return -1; 3164 3165 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 3166 fcb->ab = ab; 3167 fcb->count = 0; 3168 fcb->abuf_valid = 1; 3169 3170 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3171 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3172 3173 memset(&pkt, 0, sizeof(pkt)); 3174 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3175 pkt.fp_hdr[2] = lo; 3176 pkt.fp_dlen = 0; 3177 3178 if (ab->ab_length == 4) { 3179 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3180 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 3181 pkt.fp_hlen = 12; 3182 } else { 3183 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 3184 pkt.fp_hlen = 16; 3185 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 3186 pkt.fp_hdr[3] = (ab->ab_length << 16); 3187 } 3188 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3189 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3190 3191 pkt.fp_statusarg = fcb; 3192 pkt.fp_statuscb = fwohci_read_resp; 3193 3194 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3195 psc->sc_tlabel, fwohci_read_resp, fcb); 3196 if (rv) 3197 return rv; 3198 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3199 if (rv) 3200 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3201 psc->sc_tlabel, NULL, NULL); 3202 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3203 fcb->count = 1; 3204 return rv; 3205 } 3206 3207 static int 3208 fwohci_write(struct ieee1394_abuf *ab) 3209 { 3210 struct fwohci_pkt pkt; 3211 struct ieee1394_softc *sc = ab->ab_req; 3212 struct fwohci_softc *psc = 3213 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3214 u_int32_t high, lo; 3215 int rv; 3216 3217 if (ab->ab_length > IEEE1394_MAX_REC(sc->sc1394_max_receive)) { 3218 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 3219 return E2BIG; 3220 } 3221 3222 if (ab->ab_data && ab->ab_uio) 3223 panic("Can't call with uio and data set"); 3224 if ((ab->ab_data == NULL) && (ab->ab_uio == NULL)) 3225 panic("One of either ab_data or ab_uio must be set"); 3226 3227 memset(&pkt, 0, sizeof(pkt)); 3228 3229 pkt.fp_tcode = ab->ab_tcode; 3230 if (ab->ab_data) { 3231 pkt.fp_uio.uio_iov = pkt.fp_iov; 3232 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3233 pkt.fp_uio.uio_rw = UIO_WRITE; 3234 } else 3235 memcpy(&pkt.fp_uio, ab->ab_uio, sizeof(struct uio)); 3236 3237 pkt.fp_statusarg = ab; 3238 pkt.fp_statuscb = fwohci_write_ack; 3239 3240 switch (ab->ab_tcode) { 3241 case IEEE1394_TCODE_WRITE_RESP: 3242 pkt.fp_hlen = 12; 3243 case IEEE1394_TCODE_READ_RESP_QUAD: 3244 case IEEE1394_TCODE_READ_RESP_BLOCK: 3245 if (!pkt.fp_hlen) 3246 pkt.fp_hlen = 16; 3247 high = ab->ab_retlen; 3248 ab->ab_retlen = 0; 3249 lo = 0; 3250 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3251 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 3252 break; 3253 default: 3254 pkt.fp_hlen = 16; 3255 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3256 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3257 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3258 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3259 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3260 break; 3261 } 3262 3263 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3264 pkt.fp_hdr[2] = lo; 3265 if (pkt.fp_hlen == 16) { 3266 if (ab->ab_length == 4) { 3267 pkt.fp_hdr[3] = ab->ab_data[0]; 3268 pkt.fp_dlen = 0; 3269 } else { 3270 pkt.fp_hdr[3] = (ab->ab_length << 16); 3271 pkt.fp_dlen = ab->ab_length; 3272 if (ab->ab_data) { 3273 pkt.fp_uio.uio_iovcnt = 1; 3274 pkt.fp_uio.uio_resid = ab->ab_length; 3275 pkt.fp_iov[0].iov_base = ab->ab_data; 3276 pkt.fp_iov[0].iov_len = ab->ab_length; 3277 } 3278 } 3279 } 3280 switch (ab->ab_tcode) { 3281 case IEEE1394_TCODE_WRITE_RESP: 3282 case IEEE1394_TCODE_READ_RESP_QUAD: 3283 case IEEE1394_TCODE_READ_RESP_BLOCK: 3284 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 3285 break; 3286 default: 3287 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3288 break; 3289 } 3290 return rv; 3291 } 3292 3293 static int 3294 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3295 { 3296 struct fwohci_cb *fcb = arg; 3297 struct ieee1394_abuf *ab = fcb->ab; 3298 struct fwohci_pkt newpkt; 3299 u_int32_t *cur, high, lo; 3300 int i, tcode, rcode, status, rv; 3301 3302 /* 3303 * Both the ACK handling and normal response callbacks are handled here. 3304 * The main reason for this is the various error conditions that can 3305 * occur trying to block read some areas and the ways that gets reported 3306 * back to calling station. This is a variety of ACK codes, responses, 3307 * etc which makes it much more difficult to process if both aren't 3308 * handled here. 3309 */ 3310 3311 /* Check for status packet. */ 3312 3313 if (pkt->fp_tcode == -1) { 3314 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3315 rcode = -1; 3316 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3317 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3318 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3319 DPRINTFN(2, ("Got status packet: 0x%02x\n", 3320 (unsigned int)status)); 3321 fcb->count--; 3322 3323 /* 3324 * Got all the ack's back and the buffer is invalid (i.e. the 3325 * callback has been called. Clean up. 3326 */ 3327 3328 if (fcb->abuf_valid == 0) { 3329 if (fcb->count == 0) 3330 free(fcb, M_DEVBUF); 3331 return IEEE1394_RCODE_COMPLETE; 3332 } 3333 } else { 3334 status = -1; 3335 tcode = pkt->fp_tcode; 3336 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3337 } 3338 3339 /* 3340 * Some area's (like the config rom want to be read as quadlets only. 3341 * 3342 * The current ideas to try are: 3343 * 3344 * Got an ACK_TYPE_ERROR on a block read. 3345 * 3346 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 3347 * response. 3348 * 3349 * In all cases construct a new packet for a quadlet read and let 3350 * mutli_resp handle the iteration over the space. 3351 */ 3352 3353 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 3354 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 3355 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 3356 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 3357 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 3358 3359 /* Read the area in quadlet chunks (internally track this). */ 3360 3361 memset(&newpkt, 0, sizeof(newpkt)); 3362 3363 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3364 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3365 3366 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3367 newpkt.fp_hlen = 12; 3368 newpkt.fp_dlen = 0; 3369 newpkt.fp_hdr[1] = 3370 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3371 newpkt.fp_hdr[2] = lo; 3372 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3373 (newpkt.fp_tcode << 4); 3374 3375 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3376 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3377 fwohci_read_multi_resp, fcb); 3378 if (rv) { 3379 (*ab->ab_cb)(ab, -1); 3380 goto cleanup; 3381 } 3382 newpkt.fp_statusarg = fcb; 3383 newpkt.fp_statuscb = fwohci_read_resp; 3384 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3385 if (rv) { 3386 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3387 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 3388 NULL); 3389 (*ab->ab_cb)(ab, -1); 3390 goto cleanup; 3391 } 3392 fcb->count++; 3393 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3394 return IEEE1394_RCODE_COMPLETE; 3395 } else if ((rcode != -1) || ((status != -1) && 3396 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3397 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3398 3399 /* 3400 * Recombine all the iov data into 1 chunk for higher 3401 * level code. 3402 */ 3403 3404 if (rcode != -1) { 3405 cur = ab->ab_data; 3406 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3407 /* 3408 * Make sure and don't exceed the buffer 3409 * allocated for return. 3410 */ 3411 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3412 ab->ab_length) { 3413 memcpy(cur, pkt->fp_iov[i].iov_base, 3414 (ab->ab_length - ab->ab_retlen)); 3415 ab->ab_retlen = ab->ab_length; 3416 break; 3417 } 3418 memcpy(cur, pkt->fp_iov[i].iov_base, 3419 pkt->fp_iov[i].iov_len); 3420 cur += pkt->fp_iov[i].iov_len; 3421 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3422 } 3423 } 3424 if (status != -1) 3425 /* XXX: Need a complete tlabel interface. */ 3426 for (i = 0; i < 64; i++) 3427 fwohci_handler_set(sc, 3428 IEEE1394_TCODE_READ_RESP_QUAD, 3429 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3430 (*ab->ab_cb)(ab, rcode); 3431 goto cleanup; 3432 } else 3433 /* Good ack packet. */ 3434 return IEEE1394_RCODE_COMPLETE; 3435 3436 /* Can't get here unless ab->ab_cb has been called. */ 3437 3438 cleanup: 3439 fcb->abuf_valid = 0; 3440 if (fcb->count == 0) 3441 free(fcb, M_DEVBUF); 3442 return IEEE1394_RCODE_COMPLETE; 3443 } 3444 3445 static int 3446 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3447 struct fwohci_pkt *pkt) 3448 { 3449 struct fwohci_cb *fcb = arg; 3450 struct ieee1394_abuf *ab = fcb->ab; 3451 struct fwohci_pkt newpkt; 3452 u_int32_t high, lo; 3453 int rcode, rv; 3454 3455 /* 3456 * Bad return codes from the wire, just return what's already in the 3457 * buf. 3458 */ 3459 3460 /* Make sure a response packet didn't arrive after a bad ACK. */ 3461 if (fcb->abuf_valid == 0) 3462 return IEEE1394_RCODE_COMPLETE; 3463 3464 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3465 3466 if (rcode) { 3467 (*ab->ab_cb)(ab, rcode); 3468 goto cleanup; 3469 } 3470 3471 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3472 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3473 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3474 ab->ab_retlen = ab->ab_length; 3475 } else { 3476 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3477 pkt->fp_iov[0].iov_base, 4); 3478 ab->ab_retlen += 4; 3479 } 3480 /* Still more, loop and read 4 more bytes. */ 3481 if (ab->ab_retlen < ab->ab_length) { 3482 memset(&newpkt, 0, sizeof(newpkt)); 3483 3484 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3485 lo = (ab->ab_addr & 0x00000000ffffffffULL) + ab->ab_retlen; 3486 3487 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3488 newpkt.fp_hlen = 12; 3489 newpkt.fp_dlen = 0; 3490 newpkt.fp_hdr[1] = 3491 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3492 newpkt.fp_hdr[2] = lo; 3493 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3494 (newpkt.fp_tcode << 4); 3495 3496 newpkt.fp_statusarg = fcb; 3497 newpkt.fp_statuscb = fwohci_read_resp; 3498 3499 /* 3500 * Bad return code. Just give up and return what's 3501 * come in now. 3502 */ 3503 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3504 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3505 fwohci_read_multi_resp, fcb); 3506 if (rv) 3507 (*ab->ab_cb)(ab, -1); 3508 else { 3509 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3510 if (rv) { 3511 fwohci_handler_set(sc, 3512 IEEE1394_TCODE_READ_RESP_QUAD, 3513 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3514 NULL, NULL); 3515 (*ab->ab_cb)(ab, -1); 3516 } else { 3517 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3518 fcb->count++; 3519 return IEEE1394_RCODE_COMPLETE; 3520 } 3521 } 3522 } else 3523 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 3524 3525 cleanup: 3526 /* Can't get here unless ab_cb has been called. */ 3527 fcb->abuf_valid = 0; 3528 if (fcb->count == 0) 3529 free(fcb, M_DEVBUF); 3530 return IEEE1394_RCODE_COMPLETE; 3531 } 3532 3533 static int 3534 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3535 { 3536 struct ieee1394_abuf *ab = arg; 3537 u_int16_t status; 3538 3539 3540 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3541 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3542 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3543 DPRINTF(("Got status packet: 0x%02x\n", 3544 (unsigned int)status)); 3545 3546 /* No callback means this level should free the buffers. */ 3547 if (ab->ab_cb) 3548 (*ab->ab_cb)(ab, status); 3549 else { 3550 if (ab->ab_data) 3551 free(ab->ab_data, M_1394DATA); 3552 free(ab, M_1394DATA); 3553 } 3554 return IEEE1394_RCODE_COMPLETE; 3555 } 3556 3557 static int 3558 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 3559 { 3560 struct ieee1394_softc *sc = ab->ab_req; 3561 struct fwohci_softc *psc = 3562 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3563 u_int32_t high, lo; 3564 int i, j, rv; 3565 3566 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3567 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3568 3569 rv = 0; 3570 switch (ab->ab_tcode) { 3571 case IEEE1394_TCODE_READ_REQ_QUAD: 3572 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3573 if (ab->ab_cb) 3574 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3575 fwohci_parse_input, ab); 3576 else 3577 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 3578 NULL); 3579 break; 3580 case IEEE1394_TCODE_READ_REQ_BLOCK: 3581 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3582 if (allow) { 3583 for (i = 0; i < (ab->ab_length / 4); i++) { 3584 if (ab->ab_cb) { 3585 rv = fwohci_handler_set(psc, 3586 ab->ab_tcode, high, lo + (i * 4), 3587 fwohci_parse_input, ab); 3588 if (rv) 3589 break; 3590 } else 3591 fwohci_handler_set(psc, ab->ab_tcode, 3592 high, lo + (i * 4), NULL, NULL); 3593 } 3594 if (i != (ab->ab_length / 4)) { 3595 j = i + 1; 3596 for (i = 0; i < j; i++) 3597 fwohci_handler_set(psc, ab->ab_tcode, 3598 high, lo + (i * 4), NULL, NULL); 3599 } 3600 3601 /* 3602 * XXX: Need something to indicate writing a smaller 3603 * amount is ok. 3604 */ 3605 if (ab->ab_cb) 3606 ab->ab_subok = 1; 3607 } else { 3608 if (ab->ab_cb) 3609 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 3610 lo, fwohci_parse_input, ab); 3611 else 3612 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 3613 NULL, NULL); 3614 } 3615 break; 3616 default: 3617 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 3618 return -1; 3619 break; 3620 } 3621 return rv; 3622 } 3623 3624 static int 3625 fwohci_unreg(struct ieee1394_abuf *ab, int allow) 3626 { 3627 void *save; 3628 int rv; 3629 3630 save = ab->ab_cb; 3631 ab->ab_cb = NULL; 3632 rv = fwohci_inreg(ab, allow); 3633 ab->ab_cb = save; 3634 return rv; 3635 } 3636 3637 static int 3638 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3639 { 3640 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 3641 u_int64_t addr; 3642 u_int32_t *cur; 3643 int i, count, ret; 3644 3645 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3646 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 3647 addr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 3648 3649 /* Make sure it's always 0 in case this gets reused multiple times. */ 3650 ab->ab_retlen = 0; 3651 3652 switch (ab->ab_tcode) { 3653 case IEEE1394_TCODE_READ_REQ_QUAD: 3654 ab->ab_retlen = 4; 3655 /* Response's (if required) will come from callback code */ 3656 ret = -1; 3657 break; 3658 case IEEE1394_TCODE_READ_REQ_BLOCK: 3659 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3660 if (ab->ab_subok) { 3661 if ((addr + ab->ab_retlen) > 3662 (ab->ab_addr + ab->ab_length)) 3663 return IEEE1394_RCODE_ADDRESS_ERROR; 3664 } else 3665 if (ab->ab_retlen != ab->ab_length) 3666 return IEEE1394_RCODE_ADDRESS_ERROR; 3667 /* Response's (if required) will come from callback code */ 3668 ret = -1; 3669 break; 3670 case IEEE1394_TCODE_WRITE_REQ_QUAD: 3671 ab->ab_retlen = 4; 3672 /* Fall through. */ 3673 3674 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 3675 if (!ab->ab_retlen) 3676 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 3677 if (ab->ab_subok) { 3678 if ((addr + ab->ab_retlen) > 3679 (ab->ab_addr + ab->ab_length)) 3680 return IEEE1394_RCODE_ADDRESS_ERROR; 3681 } else 3682 if (ab->ab_retlen != ab->ab_length) 3683 return IEEE1394_RCODE_ADDRESS_ERROR; 3684 3685 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 3686 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 3687 ab->ab_data[0] = pkt->fp_hdr[3]; 3688 else { 3689 count = 0; 3690 cur = ab->ab_data; 3691 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3692 memcpy(cur, pkt->fp_iov[i].iov_base, 3693 pkt->fp_iov[i].iov_len); 3694 cur += pkt->fp_iov[i].iov_len; 3695 count += pkt->fp_iov[i].iov_len; 3696 } 3697 if (ab->ab_retlen != count) 3698 panic("Packet claims %d length " 3699 "but only %d bytes returned\n", 3700 ab->ab_retlen, count); 3701 } 3702 ret = IEEE1394_RCODE_COMPLETE; 3703 break; 3704 default: 3705 panic("Got a callback for a tcode that wasn't requested: %d", 3706 ab->ab_tcode); 3707 break; 3708 } 3709 ab->ab_addr = addr; 3710 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 3711 return ret; 3712 } 3713 3714 static int 3715 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 3716 { 3717 struct ieee1394_attach_args *fwa = aux; 3718 3719 /* Both halves must be filled in for a match. */ 3720 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 3721 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 3722 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 3723 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 3724 return (config_match(parent, cf, aux)); 3725 return 0; 3726 } 3727 3728 int 3729 fwohci_detach(struct fwohci_softc *sc, int flags) 3730 { 3731 int rv = 0; 3732 3733 if (sc->sc_sc1394.sc1394_if != NULL) 3734 rv = config_detach(sc->sc_sc1394.sc1394_if, flags); 3735 if (rv != 0) 3736 return (rv); 3737 3738 callout_stop(&sc->sc_selfid_callout); 3739 3740 if (sc->sc_powerhook != NULL) 3741 powerhook_disestablish(sc->sc_powerhook); 3742 if (sc->sc_shutdownhook != NULL) 3743 shutdownhook_disestablish(sc->sc_shutdownhook); 3744 3745 return (rv); 3746 } 3747 3748 int 3749 fwohci_activate(struct device *self, enum devact act) 3750 { 3751 struct fwohci_softc *sc = (struct fwohci_softc *)self; 3752 int s, rv = 0; 3753 3754 s = splhigh(); 3755 switch (act) { 3756 case DVACT_ACTIVATE: 3757 rv = EOPNOTSUPP; 3758 break; 3759 3760 case DVACT_DEACTIVATE: 3761 if (sc->sc_sc1394.sc1394_if != NULL) 3762 rv = config_deactivate(sc->sc_sc1394.sc1394_if); 3763 break; 3764 } 3765 splx(s); 3766 3767 return (rv); 3768 } 3769 3770 #ifdef FW_DEBUG 3771 static void 3772 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 3773 { 3774 3775 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 3776 intmask); 3777 if (intmask & OHCI_Int_CycleTooLong) 3778 printf(" CycleTooLong"); 3779 if (intmask & OHCI_Int_UnrecoverableError) 3780 printf(" UnrecoverableError"); 3781 if (intmask & OHCI_Int_CycleInconsistent) 3782 printf(" CycleInconsistent"); 3783 if (intmask & OHCI_Int_BusReset) 3784 printf(" BusReset"); 3785 if (intmask & OHCI_Int_SelfIDComplete) 3786 printf(" SelfIDComplete"); 3787 if (intmask & OHCI_Int_LockRespErr) 3788 printf(" LockRespErr"); 3789 if (intmask & OHCI_Int_PostedWriteErr) 3790 printf(" PostedWriteErr"); 3791 if (intmask & OHCI_Int_ReqTxComplete) 3792 printf(" ReqTxComplete(0x%04x)", 3793 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 3794 OHCI_SUBREG_ContextControlClear)); 3795 if (intmask & OHCI_Int_RespTxComplete) 3796 printf(" RespTxComplete(0x%04x)", 3797 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 3798 OHCI_SUBREG_ContextControlClear)); 3799 if (intmask & OHCI_Int_ARRS) 3800 printf(" ARRS(0x%04x)", 3801 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3802 OHCI_SUBREG_ContextControlClear)); 3803 if (intmask & OHCI_Int_ARRQ) 3804 printf(" ARRQ(0x%04x)", 3805 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3806 OHCI_SUBREG_ContextControlClear)); 3807 if (intmask & OHCI_Int_IsochRx) 3808 printf(" IsochRx(0x%08x)", 3809 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 3810 if (intmask & OHCI_Int_IsochTx) 3811 printf(" IsochTx(0x%08x)", 3812 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 3813 if (intmask & OHCI_Int_RQPkt) 3814 printf(" RQPkt(0x%04x)", 3815 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 3816 OHCI_SUBREG_ContextControlClear)); 3817 if (intmask & OHCI_Int_RSPkt) 3818 printf(" RSPkt(0x%04x)", 3819 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 3820 OHCI_SUBREG_ContextControlClear)); 3821 printf("\n"); 3822 } 3823 3824 static void 3825 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 3826 { 3827 u_int8_t key, phyid; 3828 3829 key = (val & 0xc0000000) >> 30; 3830 phyid = (val & 0x3f000000) >> 24; 3831 printf("%s: PHY packet from %d: ", 3832 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 3833 switch (key) { 3834 case 0: 3835 printf("PHY Config:"); 3836 if (val & 0x00800000) 3837 printf(" ForceRoot"); 3838 if (val & 0x00400000) 3839 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3840 printf("\n"); 3841 break; 3842 case 1: 3843 printf("Link-on\n"); 3844 break; 3845 case 2: 3846 printf("SelfID:"); 3847 if (val & 0x00800000) { 3848 printf(" #%d", (val & 0x00700000) >> 20); 3849 } else { 3850 if (val & 0x00400000) 3851 printf(" LinkActive"); 3852 printf(" Gap=%x", (val & 0x003f0000) >> 16); 3853 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 3854 if (val & 0x00000800) 3855 printf(" Cont"); 3856 if (val & 0x00000002) 3857 printf(" InitiateBusReset"); 3858 } 3859 if (val & 0x00000001) 3860 printf(" +"); 3861 printf("\n"); 3862 break; 3863 default: 3864 printf("unknown: 0x%08x\n", val); 3865 break; 3866 } 3867 } 3868 #endif /* FW_DEBUG */ 3869
Indexes created Thu Sep 25 16:09:42 GMT 2025