fwohci.c revision 1.66
1 /* $NetBSD: fwohci.c,v 1.66 2002/12/09 09:09:54 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 /* 47 * The first version to support isochronous acquisition part is wrtten 48 * by HAYAKAWA Koichi <haya (at) netbsd.org>. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.66 2002/12/09 09:09:54 jmc Exp $"); 53 54 #define FWOHCI_WAIT_DEBUG 1 55 56 #define FWOHCI_IT_BUFNUM 4 57 58 #include "opt_inet.h" 59 #include "fwiso.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kthread.h> 64 #include <sys/socket.h> 65 #include <sys/callout.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/malloc.h> 69 #include <sys/mbuf.h> 70 #include <sys/poll.h> 71 #include <sys/select.h> 72 73 #if __NetBSD_Version__ >= 105010000 74 #include <uvm/uvm_extern.h> 75 #else 76 #include <vm/vm.h> 77 #endif 78 79 #include <machine/bus.h> 80 #include <machine/intr.h> 81 82 #include <dev/ieee1394/ieee1394reg.h> 83 #include <dev/ieee1394/fwohcireg.h> 84 85 #include <dev/ieee1394/ieee1394var.h> 86 #include <dev/ieee1394/fwohcivar.h> 87 #include <dev/ieee1394/fwisovar.h> 88 89 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 90 91 #if 0 92 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 93 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 94 #endif 95 static void fwohci_create_event_thread(void *); 96 static void fwohci_thread_init(void *); 97 98 static void fwohci_event_thread(struct fwohci_softc *); 99 static void fwohci_hw_init(struct fwohci_softc *); 100 static void fwohci_power(int, void *); 101 static void fwohci_shutdown(void *); 102 103 static int fwohci_desc_alloc(struct fwohci_softc *); 104 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 105 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 106 107 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 108 int, int, int); 109 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 110 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 111 112 static int fwohci_misc_dmabuf_alloc(bus_dma_tag_t, int, int, 113 bus_dma_segment_t *, bus_dmamap_t *, void **, const char *); 114 static void fwohci_misc_dmabuf_free(bus_dma_tag_t, int, int, 115 bus_dma_segment_t *, bus_dmamap_t *, caddr_t); 116 117 static struct fwohci_ir_ctx *fwohci_ir_ctx_construct(struct fwohci_softc *, 118 int, int, int, int, int, int); 119 static void fwohci_ir_ctx_destruct(struct fwohci_ir_ctx *); 120 121 static int fwohci_ir_buf_setup(struct fwohci_ir_ctx *); 122 static int fwohci_ir_init(struct fwohci_ir_ctx *); 123 static int fwohci_ir_start(struct fwohci_ir_ctx *); 124 static void fwohci_ir_intr(struct fwohci_softc *, struct fwohci_ir_ctx *); 125 static int fwohci_ir_stop(struct fwohci_ir_ctx *); 126 static int fwohci_ir_ctx_packetnum(struct fwohci_ir_ctx *); 127 #ifdef USEDRAIN 128 static int fwohci_ir_ctx_drain(struct fwohci_ir_ctx *); 129 #endif /* USEDRAIN */ 130 131 static int fwohci_it_desc_alloc(struct fwohci_it_ctx *); 132 static void fwohci_it_desc_free(struct fwohci_it_ctx *itc); 133 struct fwohci_it_ctx *fwohci_it_ctx_construct(struct fwohci_softc *, 134 int, int, int, int); 135 void fwohci_it_ctx_destruct(struct fwohci_it_ctx *); 136 int fwohci_it_ctx_writedata(ieee1394_it_tag_t, int, 137 struct ieee1394_it_datalist *, int); 138 static void fwohci_it_ctx_run(struct fwohci_it_ctx *); 139 int fwohci_it_ctx_flush(ieee1394_it_tag_t); 140 static void fwohci_it_intr(struct fwohci_softc *, struct fwohci_it_ctx *); 141 142 int fwohci_itd_construct(struct fwohci_it_ctx *, struct fwohci_it_dmabuf *, 143 int, struct fwohci_desc *, bus_addr_t, int, int, paddr_t); 144 void fwohci_itd_destruct(struct fwohci_it_dmabuf *); 145 static int fwohci_itd_dmabuf_alloc(struct fwohci_it_dmabuf *); 146 static void fwohci_itd_dmabuf_free(struct fwohci_it_dmabuf *); 147 int fwohci_itd_link(struct fwohci_it_dmabuf *, struct fwohci_it_dmabuf *); 148 int fwohci_itd_unlink(struct fwohci_it_dmabuf *); 149 int fwohci_itd_writedata(struct fwohci_it_dmabuf *, int, 150 struct ieee1394_it_datalist *); 151 int fwohci_itd_isfilled(struct fwohci_it_dmabuf *); 152 153 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 154 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 155 static void fwohci_buf_init_rx(struct fwohci_softc *); 156 static void fwohci_buf_start_rx(struct fwohci_softc *); 157 static void fwohci_buf_stop_tx(struct fwohci_softc *); 158 static void fwohci_buf_stop_rx(struct fwohci_softc *); 159 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 160 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_buf **, 161 caddr_t *, int); 162 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 163 struct fwohci_pkt *); 164 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 165 struct fwohci_pkt *); 166 167 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 168 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 169 static void fwohci_phy_busreset(struct fwohci_softc *); 170 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 171 172 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 173 int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), void *); 174 175 ieee1394_ir_tag_t fwohci_ir_ctx_set(struct device *, int, int, int, int, int); 176 int fwohci_ir_ctx_clear(struct device *, ieee1394_ir_tag_t); 177 int fwohci_ir_read(struct device *, ieee1394_ir_tag_t, struct uio *, 178 int, int); 179 int fwohci_ir_wait(struct device *, ieee1394_ir_tag_t, void *, char *name); 180 int fwohci_ir_select(struct device *, ieee1394_ir_tag_t, struct proc *); 181 182 183 184 ieee1394_it_tag_t fwohci_it_set(struct ieee1394_softc *, int, int); 185 static ieee1394_it_tag_t fwohci_it_ctx_set(struct fwohci_softc *, int, int, int); 186 int fwohci_it_ctx_clear(ieee1394_it_tag_t *); 187 188 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 189 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 190 static void fwohci_as_input(struct fwohci_softc *, struct fwohci_ctx *); 191 192 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 193 struct fwohci_pkt *); 194 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 195 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 196 struct fwohci_pkt *); 197 198 static int fwohci_guidrom_init(struct fwohci_softc *); 199 static void fwohci_configrom_init(struct fwohci_softc *); 200 static int fwohci_configrom_input(struct fwohci_softc *, void *, 201 struct fwohci_pkt *); 202 static void fwohci_selfid_init(struct fwohci_softc *); 203 static int fwohci_selfid_input(struct fwohci_softc *); 204 205 static void fwohci_csr_init(struct fwohci_softc *); 206 static int fwohci_csr_input(struct fwohci_softc *, void *, 207 struct fwohci_pkt *); 208 209 static void fwohci_uid_collect(struct fwohci_softc *); 210 static void fwohci_uid_req(struct fwohci_softc *, int); 211 static int fwohci_uid_input(struct fwohci_softc *, void *, 212 struct fwohci_pkt *); 213 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 214 static void fwohci_check_nodes(struct fwohci_softc *); 215 216 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 217 void (*)(struct device *, struct mbuf *)); 218 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 219 static int fwohci_if_input_iso(struct fwohci_softc *, void *, struct fwohci_pkt *); 220 221 static int fwohci_if_output(struct device *, struct mbuf *, 222 void (*)(struct device *, struct mbuf *)); 223 static int fwohci_if_setiso(struct device *, u_int32_t, u_int32_t, u_int32_t, 224 void (*)(struct device *, struct mbuf *)); 225 static int fwohci_read(struct ieee1394_abuf *); 226 static int fwohci_write(struct ieee1394_abuf *); 227 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 228 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 229 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 230 struct fwohci_pkt *); 231 static int fwohci_inreg(struct ieee1394_abuf *, int); 232 static int fwohci_unreg(struct ieee1394_abuf *, int); 233 static int fwohci_parse_input(struct fwohci_softc *, void *, 234 struct fwohci_pkt *); 235 static int fwohci_submatch(struct device *, struct cfdata *, void *); 236 237 /* XXX */ 238 u_int16_t fwohci_cycletimer(struct fwohci_softc *); 239 u_int16_t fwohci_it_cycletimer(ieee1394_it_tag_t); 240 241 #ifdef FW_DEBUG 242 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 243 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 244 245 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 246 247 #define DPRINTF(x) if (fwdebug) printf x 248 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 249 int fwdebug = 1; 250 #else 251 #define DPRINTF(x) 252 #define DPRINTFN(n,x) 253 #endif 254 255 #define OHCI_ITHEADER_SPD_MASK 0x00070000 256 #define OHCI_ITHEADER_SPD_BITPOS 16 257 #define OHCI_ITHEADER_TAG_MASK 0x0000c000 258 #define OHCI_ITHEADER_TAG_BITPOS 14 259 #define OHCI_ITHEADER_CHAN_MASK 0x00003f00 260 #define OHCI_ITHEADER_CHAN_BITPOS 8 261 #define OHCI_ITHEADER_TCODE_MASK 0x000000f0 262 #define OHCI_ITHEADER_TCODE_BITPOS 4 263 #define OHCI_ITHEADER_SY_MASK 0x0000000f 264 #define OHCI_ITHEADER_SY_BITPOS 0 265 266 #define OHCI_ITHEADER_VAL(fld, val) \ 267 (OHCI_ITHEADER_##fld##_MASK & ((val) << OHCI_ITHEADER_##fld##_BITPOS)) 268 269 int 270 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 271 { 272 int i; 273 u_int32_t val; 274 #if 0 275 int error; 276 #endif 277 278 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 279 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 280 281 evcnt_attach_dynamic(&sc->sc_isocnt, EVCNT_TYPE_MISC, ev, 282 sc->sc_sc1394.sc1394_dev.dv_xname, "isorcvs"); 283 evcnt_attach_dynamic(&sc->sc_ascnt, EVCNT_TYPE_MISC, ev, 284 sc->sc_sc1394.sc1394_dev.dv_xname, "asrcvs"); 285 evcnt_attach_dynamic(&sc->sc_itintrcnt, EVCNT_TYPE_INTR, ev, 286 sc->sc_sc1394.sc1394_dev.dv_xname, "itintr"); 287 288 /* 289 * Wait for reset completion 290 */ 291 for (i = 0; i < OHCI_LOOP; i++) { 292 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 293 if ((val & OHCI_HCControl_SoftReset) == 0) 294 break; 295 DELAY(10); 296 } 297 298 /* What dialect of OHCI is this device? 299 */ 300 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 301 printf("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 302 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 303 304 LIST_INIT(&sc->sc_nodelist); 305 306 if (fwohci_guidrom_init(sc) != 0) { 307 printf("\n%s: fatal: no global UID ROM\n", 308 sc->sc_sc1394.sc1394_dev.dv_xname); 309 return -1; 310 } 311 312 printf(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 313 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 314 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 315 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 316 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 317 318 /* Get the maximum link speed and receive size 319 */ 320 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 321 sc->sc_sc1394.sc1394_link_speed = 322 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 323 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 324 printf(", %s", 325 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 326 } else { 327 printf(", unknown speed %u", sc->sc_sc1394.sc1394_link_speed); 328 } 329 330 /* MaxRec is encoded as log2(max_rec_octets)-1 331 */ 332 sc->sc_sc1394.sc1394_max_receive = 333 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 334 printf(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 335 336 /* 337 * Count how many isochronous receive ctx we have. 338 */ 339 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 340 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 341 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 342 for (i = 0; val != 0; val >>= 1) { 343 if (val & 0x1) 344 i++; 345 } 346 sc->sc_isoctx = i; 347 printf(", %d ir_ctx", sc->sc_isoctx); 348 349 /* 350 * Count how many isochronous transmit ctx we have. 351 */ 352 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 353 val = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntMaskClear); 354 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskClear, ~0); 355 for (i = 0; val != 0; val >>= 1) { 356 if (val & 0x1) { 357 i++; 358 OHCI_SYNC_TX_DMA_WRITE(sc, i,OHCI_SUBREG_CommandPtr,0); 359 } 360 } 361 sc->sc_itctx = i; 362 363 printf(", %d it_ctx", sc->sc_itctx); 364 365 printf("\n"); 366 367 #if 0 368 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 369 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 370 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 371 return error; 372 #endif 373 374 sc->sc_dying = 0; 375 sc->sc_nodeid = 0xffff; /* invalid */ 376 377 sc->sc_sc1394.sc1394_callback.sc1394_read = fwohci_read; 378 sc->sc_sc1394.sc1394_callback.sc1394_write = fwohci_write; 379 sc->sc_sc1394.sc1394_callback.sc1394_inreg = fwohci_inreg; 380 sc->sc_sc1394.sc1394_callback.sc1394_unreg = fwohci_unreg; 381 382 kthread_create(fwohci_create_event_thread, sc); 383 return 0; 384 } 385 386 static int 387 fwohci_if_setiso(struct device *self, u_int32_t channel, u_int32_t tag, 388 u_int32_t direction, void (*handler)(struct device *, struct mbuf *)) 389 { 390 struct fwohci_softc *sc = (struct fwohci_softc *)self; 391 int retval; 392 int s; 393 394 if (direction == 1) { 395 return EIO; 396 } 397 398 s = splnet(); 399 retval = fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 400 channel, 1 << tag, fwohci_if_input_iso, handler); 401 splx(s); 402 403 if (!retval) { 404 printf("%s: dummy iso handler set\n", 405 sc->sc_sc1394.sc1394_dev.dv_xname); 406 } else { 407 printf("%s: dummy iso handler cannot set\n", 408 sc->sc_sc1394.sc1394_dev.dv_xname); 409 } 410 411 return retval; 412 } 413 414 int 415 fwohci_intr(void *arg) 416 { 417 struct fwohci_softc * const sc = arg; 418 int progress = 0; 419 u_int32_t intmask, iso; 420 421 for (;;) { 422 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 423 424 /* 425 * On a bus reset, everything except bus reset gets 426 * cleared. That can't get cleared until the selfid 427 * phase completes (which happens outside the 428 * interrupt routines). So if just a bus reset is left 429 * in the mask and it's already in the sc_intmask, 430 * just return. 431 */ 432 433 if ((intmask == 0) || 434 (progress && (intmask == OHCI_Int_BusReset) && 435 (sc->sc_intmask & OHCI_Int_BusReset))) { 436 if (progress) 437 wakeup(fwohci_event_thread); 438 return progress; 439 } 440 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 441 intmask & ~OHCI_Int_BusReset); 442 #ifdef FW_DEBUG 443 if (fwdebug > 1) 444 fwohci_show_intr(sc, intmask); 445 #endif 446 447 if (intmask & OHCI_Int_BusReset) { 448 /* 449 * According to OHCI spec 6.1.1 "busReset", 450 * All asynchronous transmit must be stopped before 451 * clearing BusReset. Moreover, the BusReset 452 * interrupt bit should not be cleared during the 453 * SelfID phase. Thus we turned off interrupt mask 454 * bit of BusReset instead until SelfID completion 455 * or SelfID timeout. 456 */ 457 intmask &= OHCI_Int_SelfIDComplete; 458 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 459 OHCI_Int_BusReset); 460 sc->sc_intmask = OHCI_Int_BusReset; 461 } 462 sc->sc_intmask |= intmask; 463 464 if (intmask & OHCI_Int_IsochTx) { 465 int i; 466 467 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 468 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 469 470 sc->sc_itintrcnt.ev_count++; 471 for (i = 0; i < sc->sc_itctx; ++i) { 472 if ((iso & (1<<i)) == 0 || 473 sc->sc_ctx_it[i] == NULL) { 474 continue; 475 } 476 477 fwohci_it_intr(sc, sc->sc_ctx_it[i]); 478 } 479 } 480 if (intmask & OHCI_Int_IsochRx) { 481 int i; 482 483 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 484 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 485 486 for (i = 0; i < sc->sc_isoctx; i++) { 487 if ((iso & (1 << i)) 488 && sc->sc_ctx_ir[i] != NULL) { 489 iso &= ~(1 << i); 490 fwohci_ir_intr(sc, sc->sc_ctx_ir[i]); 491 } 492 } 493 494 if (iso == 0) { 495 sc->sc_intmask &= ~OHCI_Int_IsochRx; 496 } 497 sc->sc_iso |= iso; 498 } 499 500 if (!progress) { 501 sc->sc_intrcnt.ev_count++; 502 progress = 1; 503 } 504 } 505 } 506 507 static void 508 fwohci_create_event_thread(void *arg) 509 { 510 struct fwohci_softc *sc = arg; 511 512 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 513 sc->sc_sc1394.sc1394_dev.dv_xname)) { 514 printf("%s: unable to create event thread\n", 515 sc->sc_sc1394.sc1394_dev.dv_xname); 516 panic("fwohci_create_event_thread"); 517 } 518 } 519 520 static void 521 fwohci_thread_init(void *arg) 522 { 523 struct fwohci_softc *sc = arg; 524 int i; 525 526 /* 527 * Allocate descriptors 528 */ 529 if (fwohci_desc_alloc(sc)) { 530 printf("%s: not enabling interrupts\n", 531 sc->sc_sc1394.sc1394_dev.dv_xname); 532 kthread_exit(1); 533 } 534 535 /* 536 * Enable Link Power 537 */ 538 539 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 540 541 /* 542 * Allocate DMA Context 543 */ 544 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 545 OHCI_CTX_ASYNC_RX_REQUEST, FWOHCI_CTX_ASYNC); 546 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 547 OHCI_CTX_ASYNC_RX_RESPONSE, FWOHCI_CTX_ASYNC); 548 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST, 549 FWOHCI_CTX_ASYNC); 550 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE, 551 FWOHCI_CTX_ASYNC); 552 sc->sc_ctx_as = malloc(sizeof(sc->sc_ctx_as[0]) * sc->sc_isoctx, 553 M_DEVBUF, M_WAITOK); 554 if (sc->sc_ctx_as == NULL) { 555 printf("no asynchronous stream\n"); 556 } else { 557 for (i = 0; i < sc->sc_isoctx; i++) 558 sc->sc_ctx_as[i] = NULL; 559 } 560 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 561 M_DEVBUF, M_WAITOK|M_ZERO); 562 sc->sc_ctx_it = malloc(sizeof(sc->sc_ctx_it[0]) * sc->sc_itctx, 563 M_DEVBUF, M_WAITOK|M_ZERO); 564 565 /* 566 * Allocate buffer for configuration ROM and SelfID buffer 567 */ 568 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 569 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 570 571 callout_init(&sc->sc_selfid_callout); 572 573 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 574 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 575 sc->sc_sc1394.sc1394_ifsetiso = fwohci_if_setiso; 576 577 sc->sc_sc1394.sc1394_ir_open = fwohci_ir_ctx_set; 578 sc->sc_sc1394.sc1394_ir_close = fwohci_ir_ctx_clear; 579 sc->sc_sc1394.sc1394_ir_read = fwohci_ir_read; 580 sc->sc_sc1394.sc1394_ir_wait = fwohci_ir_wait; 581 sc->sc_sc1394.sc1394_ir_select = fwohci_ir_select; 582 583 #if 0 584 sc->sc_sc1394.sc1394_it_open = fwohci_it_open; 585 sc->sc_sc1394.sc1394_it_write = fwohci_it_write; 586 sc->sc_sc1394.sc1394_it_close = fwohci_it_close; 587 /* XXX: need fwohci_it_flush? */ 588 #endif 589 590 /* 591 * establish hooks for shutdown and suspend/resume 592 */ 593 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 594 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 595 596 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 597 fwohci_print); 598 599 #if NFWISO > 0 600 fwiso_register_if(&sc->sc_sc1394); 601 #endif 602 603 /* Main loop. It's not coming back normally. */ 604 605 fwohci_event_thread(sc); 606 607 kthread_exit(0); 608 } 609 610 static void 611 fwohci_event_thread(struct fwohci_softc *sc) 612 { 613 int i, s; 614 u_int32_t intmask, iso; 615 616 s = splbio(); 617 618 /* 619 * Initialize hardware registers. 620 */ 621 622 fwohci_hw_init(sc); 623 624 /* Initial Bus Reset */ 625 fwohci_phy_busreset(sc); 626 splx(s); 627 628 while (!sc->sc_dying) { 629 s = splbio(); 630 intmask = sc->sc_intmask; 631 if (intmask == 0) { 632 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 633 splx(s); 634 continue; 635 } 636 sc->sc_intmask = 0; 637 splx(s); 638 639 if (intmask & OHCI_Int_BusReset) { 640 fwohci_buf_stop_tx(sc); 641 if (sc->sc_uidtbl != NULL) { 642 free(sc->sc_uidtbl, M_DEVBUF); 643 sc->sc_uidtbl = NULL; 644 } 645 646 callout_reset(&sc->sc_selfid_callout, 647 OHCI_SELFID_TIMEOUT, 648 (void (*)(void *))fwohci_phy_busreset, sc); 649 sc->sc_nodeid = 0xffff; /* indicate invalid */ 650 sc->sc_rootid = 0; 651 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 652 } 653 if (intmask & OHCI_Int_SelfIDComplete) { 654 s = splbio(); 655 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 656 OHCI_Int_BusReset); 657 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 658 OHCI_Int_BusReset); 659 splx(s); 660 callout_stop(&sc->sc_selfid_callout); 661 if (fwohci_selfid_input(sc) == 0) { 662 fwohci_buf_start_rx(sc); 663 fwohci_uid_collect(sc); 664 } 665 } 666 if (intmask & OHCI_Int_ReqTxComplete) 667 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 668 if (intmask & OHCI_Int_RespTxComplete) 669 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 670 if (intmask & OHCI_Int_RQPkt) 671 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 672 if (intmask & OHCI_Int_RSPkt) 673 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 674 if (intmask & OHCI_Int_IsochRx) { 675 if (sc->sc_ctx_as == NULL) { 676 continue; 677 } 678 s = splbio(); 679 iso = sc->sc_iso; 680 sc->sc_iso = 0; 681 splx(s); 682 for (i = 0; i < sc->sc_isoctx; i++) { 683 if ((iso & (1 << i)) && 684 sc->sc_ctx_as[i] != NULL) { 685 fwohci_as_input(sc, sc->sc_ctx_as[i]); 686 sc->sc_ascnt.ev_count++; 687 } 688 } 689 } 690 } 691 } 692 693 #if 0 694 static int 695 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 696 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 697 { 698 bus_dma_segment_t segs[1]; 699 int error, nsegs, steps; 700 701 steps = 0; 702 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 703 segs, 1, &nsegs, flags); 704 if (error) 705 goto cleanup; 706 707 steps = 1; 708 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 709 kvap, flags); 710 if (error) 711 goto cleanup; 712 713 if (error == 0) 714 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 715 size, flags, mapp); 716 if (error) 717 goto cleanup; 718 if (error == 0) 719 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 720 flags); 721 if (error) 722 goto cleanup; 723 724 cleanup: 725 switch (steps) { 726 case 1: 727 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 728 } 729 730 return error; 731 } 732 #endif 733 734 int 735 fwohci_print(void *aux, const char *pnp) 736 { 737 char *name = aux; 738 739 if (pnp) 740 printf("%s at %s", name, pnp); 741 742 return UNCONF; 743 } 744 745 static void 746 fwohci_hw_init(struct fwohci_softc *sc) 747 { 748 int i; 749 u_int32_t val; 750 751 /* 752 * Software Reset. 753 */ 754 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 755 for (i = 0; i < OHCI_LOOP; i++) { 756 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 757 if ((val & OHCI_HCControl_SoftReset) == 0) 758 break; 759 DELAY(10); 760 } 761 762 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 763 764 /* 765 * First, initilize CSRs with undefined value to default settings. 766 */ 767 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 768 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 769 #if 0 770 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 771 #else 772 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 773 #endif 774 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 775 for (i = 0; i < sc->sc_isoctx; i++) { 776 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 777 ~0); 778 } 779 for (i = 0; i < sc->sc_itctx; i++) { 780 OHCI_SYNC_TX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 781 ~0); 782 } 783 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 784 785 fwohci_configrom_init(sc); 786 fwohci_selfid_init(sc); 787 fwohci_buf_init_rx(sc); 788 fwohci_csr_init(sc); 789 790 /* 791 * Final CSR settings. 792 */ 793 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 794 OHCI_LinkControl_CycleTimerEnable | 795 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 796 797 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 798 799 /* clear receive filter */ 800 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 801 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 802 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 803 804 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 805 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 806 #if BYTE_ORDER == BIG_ENDIAN 807 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 808 OHCI_HCControl_NoByteSwapData); 809 #endif 810 811 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 812 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 813 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 814 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 815 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 816 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 817 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 818 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 819 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 820 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 821 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 822 823 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 824 825 /* 826 * Start the receivers 827 */ 828 fwohci_buf_start_rx(sc); 829 } 830 831 static void 832 fwohci_power(int why, void *arg) 833 { 834 struct fwohci_softc *sc = arg; 835 int s; 836 837 s = splbio(); 838 switch (why) { 839 case PWR_SUSPEND: 840 case PWR_STANDBY: 841 fwohci_shutdown(sc); 842 break; 843 case PWR_RESUME: 844 fwohci_hw_init(sc); 845 fwohci_phy_busreset(sc); 846 break; 847 case PWR_SOFTSUSPEND: 848 case PWR_SOFTSTANDBY: 849 case PWR_SOFTRESUME: 850 break; 851 } 852 splx(s); 853 } 854 855 static void 856 fwohci_shutdown(void *arg) 857 { 858 struct fwohci_softc *sc = arg; 859 u_int32_t val; 860 861 callout_stop(&sc->sc_selfid_callout); 862 /* disable all interrupt */ 863 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 864 fwohci_buf_stop_tx(sc); 865 fwohci_buf_stop_rx(sc); 866 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 867 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 868 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 869 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 870 fwohci_phy_busreset(sc); 871 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 872 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 873 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 874 } 875 876 /* 877 * COMMON FUNCTIONS 878 */ 879 880 /* 881 * read the PHY Register. 882 */ 883 static u_int8_t 884 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 885 { 886 int i; 887 u_int32_t val; 888 889 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 890 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 891 for (i = 0; i < OHCI_LOOP; i++) { 892 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 893 OHCI_PhyControl_RdDone) 894 break; 895 DELAY(10); 896 } 897 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 898 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 899 } 900 901 /* 902 * write the PHY Register. 903 */ 904 static void 905 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 906 { 907 int i; 908 909 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 910 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 911 (val << OHCI_PhyControl_WrData_BITPOS)); 912 for (i = 0; i < OHCI_LOOP; i++) { 913 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 914 OHCI_PhyControl_WrReg)) 915 break; 916 DELAY(10); 917 } 918 } 919 920 /* 921 * Initiate Bus Reset 922 */ 923 static void 924 fwohci_phy_busreset(struct fwohci_softc *sc) 925 { 926 int s; 927 u_int8_t val; 928 929 s = splbio(); 930 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 931 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 932 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 933 callout_stop(&sc->sc_selfid_callout); 934 val = fwohci_phy_read(sc, 1); 935 val = (val & 0x80) | /* preserve RHB (force root) */ 936 0x40 | /* Initiate Bus Reset */ 937 0x3f; /* default GAP count */ 938 fwohci_phy_write(sc, 1, val); 939 splx(s); 940 } 941 942 /* 943 * PHY Packet 944 */ 945 static void 946 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 947 { 948 u_int32_t val; 949 950 val = pkt->fp_hdr[1]; 951 if (val != ~pkt->fp_hdr[2]) { 952 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 953 OHCI_CTXCTL_EVENT_BUS_RESET) { 954 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 955 pkt->fp_hdr[2])); 956 } else { 957 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 958 sc->sc_sc1394.sc1394_dev.dv_xname, val, 959 pkt->fp_hdr[2]); 960 } 961 return; 962 } 963 #ifdef FW_DEBUG 964 if (fwdebug > 1) 965 fwohci_show_phypkt(sc, val); 966 #endif 967 } 968 969 /* 970 * Descriptor for context DMA. 971 */ 972 static int 973 fwohci_desc_alloc(struct fwohci_softc *sc) 974 { 975 int error, mapsize, dsize; 976 977 /* 978 * allocate descriptor buffer 979 */ 980 981 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 982 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 983 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 984 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 985 mapsize = howmany(sc->sc_descsize, NBBY); 986 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK|M_ZERO); 987 988 if (sc->sc_descmap == NULL) { 989 printf("fwohci_desc_alloc: cannot get memory\n"); 990 return -1; 991 } 992 993 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 994 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 995 printf("%s: unable to allocate descriptor buffer, error = %d\n", 996 sc->sc_sc1394.sc1394_dev.dv_xname, error); 997 goto fail_0; 998 } 999 1000 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 1001 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 1002 != 0) { 1003 printf("%s: unable to map descriptor buffer, error = %d\n", 1004 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1005 goto fail_1; 1006 } 1007 1008 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 1009 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 1010 printf("%s: unable to create descriptor buffer DMA map, " 1011 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 1012 goto fail_2; 1013 } 1014 1015 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 1016 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 1017 printf("%s: unable to load descriptor buffer DMA map, " 1018 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 1019 goto fail_3; 1020 } 1021 1022 return 0; 1023 1024 fail_3: 1025 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1026 fail_2: 1027 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 1028 fail_1: 1029 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 1030 fail_0: 1031 return error; 1032 } 1033 1034 static struct fwohci_desc * 1035 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 1036 { 1037 int i, n; 1038 1039 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 1040 for (i = 0; ; i++) { 1041 if (i == ndesc) { 1042 for (i = 0; i < ndesc; i++) 1043 setbit(sc->sc_descmap, n + i); 1044 return sc->sc_desc + n; 1045 } 1046 if (isset(sc->sc_descmap, n + i)) 1047 break; 1048 } 1049 } 1050 return NULL; 1051 } 1052 1053 static void 1054 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 1055 { 1056 int i, n; 1057 1058 n = fd - sc->sc_desc; 1059 for (i = 0; i < ndesc; i++, n++) { 1060 #ifdef DIAGNOSTIC 1061 if (isclr(sc->sc_descmap, n)) 1062 panic("fwohci_desc_put: duplicated free"); 1063 #endif 1064 clrbit(sc->sc_descmap, n); 1065 } 1066 } 1067 1068 /* 1069 * Asyncronous/Isochronous Transmit/Receive Context 1070 */ 1071 static int 1072 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 1073 int bufcnt, int ctx, int ctxtype) 1074 { 1075 int i, error; 1076 struct fwohci_ctx *fc; 1077 struct fwohci_buf *fb; 1078 struct fwohci_desc *fd; 1079 #if DOUBLEBUF 1080 int buf2cnt; 1081 #endif 1082 1083 fc = malloc(sizeof(*fc), M_DEVBUF, M_WAITOK|M_ZERO); 1084 LIST_INIT(&fc->fc_handler); 1085 TAILQ_INIT(&fc->fc_buf); 1086 fc->fc_ctx = ctx; 1087 fc->fc_buffers = fb = malloc(sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK|M_ZERO); 1088 fc->fc_bufcnt = bufcnt; 1089 #if DOUBLEBUF 1090 TAILQ_INIT(&fc->fc_buf2); /* for isochronous */ 1091 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 1092 buf2cnt = bufcnt/2; 1093 bufcnt -= buf2cnt; 1094 if (buf2cnt == 0) { 1095 panic("cannot allocate iso buffer"); 1096 } 1097 } 1098 #endif 1099 for (i = 0; i < bufcnt; i++, fb++) { 1100 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 1101 goto fail; 1102 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 1103 error = ENOBUFS; 1104 goto fail; 1105 } 1106 fb->fb_desc = fd; 1107 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1108 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1109 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1110 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1111 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1112 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1113 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1114 } 1115 #if DOUBLEBUF 1116 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 1117 for (i = bufcnt; i < bufcnt + buf2cnt; i++, fb++) { 1118 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 1119 goto fail; 1120 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 1121 error = ENOBUFS; 1122 goto fail; 1123 } 1124 fb->fb_desc = fd; 1125 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1126 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1127 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1128 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1129 BUS_DMASYNC_PREWRITE); 1130 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1131 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1132 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1133 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1134 TAILQ_INSERT_TAIL(&fc->fc_buf2, fb, fb_list); 1135 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1136 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1137 BUS_DMASYNC_POSTWRITE); 1138 } 1139 } 1140 #endif /* DOUBLEBUF */ 1141 fc->fc_type = ctxtype; 1142 *fcp = fc; 1143 return 0; 1144 1145 fail: 1146 while (i-- > 0) { 1147 fb--; 1148 if (fb->fb_desc) 1149 fwohci_desc_put(sc, fb->fb_desc, 1); 1150 fwohci_buf_free(sc, fb); 1151 } 1152 free(fc, M_DEVBUF); 1153 return error; 1154 } 1155 1156 static void 1157 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1158 { 1159 struct fwohci_buf *fb; 1160 struct fwohci_handler *fh; 1161 1162 #if DOUBLEBUF 1163 if ((fc->fc_type == FWOHCI_CTX_ISO_MULTI) && 1164 (TAILQ_FIRST(&fc->fc_buf) > TAILQ_FIRST(&fc->fc_buf2))) { 1165 struct fwohci_buf_s fctmp; 1166 1167 fctmp = fc->fc_buf; 1168 fc->fc_buf = fc->fc_buf2; 1169 fc->fc_buf2 = fctmp; 1170 } 1171 #endif 1172 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1173 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1174 NULL, NULL); 1175 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1176 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1177 if (fb->fb_desc) 1178 fwohci_desc_put(sc, fb->fb_desc, 1); 1179 fwohci_buf_free(sc, fb); 1180 } 1181 #if DOUBLEBUF 1182 while ((fb = TAILQ_FIRST(&fc->fc_buf2)) != NULL) { 1183 TAILQ_REMOVE(&fc->fc_buf2, fb, fb_list); 1184 if (fb->fb_desc) 1185 fwohci_desc_put(sc, fb->fb_desc, 1); 1186 fwohci_buf_free(sc, fb); 1187 } 1188 #endif /* DOUBLEBUF */ 1189 free(fc->fc_buffers, M_DEVBUF); 1190 free(fc, M_DEVBUF); 1191 } 1192 1193 static void 1194 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1195 { 1196 struct fwohci_buf *fb, *nfb; 1197 struct fwohci_desc *fd; 1198 struct fwohci_handler *fh; 1199 int n; 1200 1201 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1202 nfb = TAILQ_NEXT(fb, fb_list); 1203 fb->fb_off = 0; 1204 fd = fb->fb_desc; 1205 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1206 fd->fd_rescount = fd->fd_reqcount; 1207 } 1208 1209 #if DOUBLEBUF 1210 for (fb = TAILQ_FIRST(&fc->fc_buf2); fb != NULL; fb = nfb) { 1211 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1212 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1213 BUS_DMASYNC_PREWRITE); 1214 nfb = TAILQ_NEXT(fb, fb_list); 1215 fb->fb_off = 0; 1216 fd = fb->fb_desc; 1217 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1218 fd->fd_rescount = fd->fd_reqcount; 1219 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1220 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1221 BUS_DMASYNC_POSTWRITE); 1222 } 1223 #endif /* DOUBLEBUF */ 1224 1225 n = fc->fc_ctx; 1226 fb = TAILQ_FIRST(&fc->fc_buf); 1227 if (fc->fc_type != FWOHCI_CTX_ASYNC) { 1228 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1229 fb->fb_daddr | 1); 1230 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1231 OHCI_CTXCTL_RX_BUFFER_FILL | 1232 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1233 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1234 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1235 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1236 OHCI_CTXCTL_RX_ISOCH_HEADER); 1237 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1238 OHCI_SYNC_RX_DMA_WRITE(sc, n, 1239 OHCI_SUBREG_ContextControlSet, 1240 OHCI_CTXCTL_RX_BUFFER_FILL); 1241 } 1242 fh = LIST_FIRST(&fc->fc_handler); 1243 1244 if (fh->fh_key1 == IEEE1394_ISO_CHANNEL_ANY) { 1245 OHCI_SYNC_RX_DMA_WRITE(sc, n, 1246 OHCI_SUBREG_ContextControlSet, 1247 OHCI_CTXCTL_RX_MULTI_CHAN_MODE); 1248 1249 /* Receive all the isochronous channels */ 1250 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiSet, 1251 0xffffffff); 1252 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoSet, 1253 0xffffffff); 1254 DPRINTF(("%s: CTXCTL 0x%08x\n", 1255 sc->sc_sc1394.sc1394_dev.dv_xname, 1256 OHCI_SYNC_RX_DMA_READ(sc, n, 1257 OHCI_SUBREG_ContextControlSet))); 1258 } 1259 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1260 (fh->fh_key2 << OHCI_CTXMATCH_TAG_BITPOS) | 1261 (fh->fh_key1 & IEEE1394_ISO_CHANNEL_MASK)); 1262 } else { 1263 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1264 fb->fb_daddr | 1); 1265 } 1266 } 1267 1268 /* 1269 * DMA data buffer 1270 */ 1271 static int 1272 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1273 { 1274 int error; 1275 1276 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1277 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1278 printf("%s: unable to allocate buffer, error = %d\n", 1279 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1280 goto fail_0; 1281 } 1282 1283 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1284 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1285 printf("%s: unable to map buffer, error = %d\n", 1286 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1287 goto fail_1; 1288 } 1289 1290 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1291 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1292 printf("%s: unable to create buffer DMA map, " 1293 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1294 error); 1295 goto fail_2; 1296 } 1297 1298 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1299 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1300 printf("%s: unable to load buffer DMA map, " 1301 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1302 error); 1303 goto fail_3; 1304 } 1305 1306 return 0; 1307 1308 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1309 fail_3: 1310 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1311 fail_2: 1312 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1313 fail_1: 1314 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1315 fail_0: 1316 return error; 1317 } 1318 1319 static void 1320 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1321 { 1322 1323 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1324 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1325 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1326 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1327 } 1328 1329 static void 1330 fwohci_buf_init_rx(struct fwohci_softc *sc) 1331 { 1332 int i; 1333 1334 /* 1335 * Initialize for Asynchronous Receive Queue. 1336 */ 1337 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1338 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1339 1340 /* 1341 * Initialize for Isochronous Receive Queue. 1342 */ 1343 if (sc->sc_ctx_as != NULL) { 1344 for (i = 0; i < sc->sc_isoctx; i++) { 1345 if (sc->sc_ctx_as[i] != NULL) 1346 fwohci_ctx_init(sc, sc->sc_ctx_as[i]); 1347 } 1348 } 1349 } 1350 1351 static void 1352 fwohci_buf_start_rx(struct fwohci_softc *sc) 1353 { 1354 int i; 1355 1356 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1357 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1358 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1359 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1360 if (sc->sc_ctx_as != NULL) { 1361 for (i = 0; i < sc->sc_isoctx; i++) { 1362 if (sc->sc_ctx_as[i] != NULL) 1363 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1364 OHCI_SUBREG_ContextControlSet, 1365 OHCI_CTXCTL_RUN); 1366 } 1367 } 1368 } 1369 1370 static void 1371 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1372 { 1373 int i; 1374 1375 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1376 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1377 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1378 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1379 1380 /* 1381 * Make sure the transmitter is stopped. 1382 */ 1383 for (i = 0; i < OHCI_LOOP; i++) { 1384 DELAY(10); 1385 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1386 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1387 continue; 1388 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1389 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1390 continue; 1391 break; 1392 } 1393 1394 /* 1395 * Initialize for Asynchronous Transmit Queue. 1396 */ 1397 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1398 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1399 } 1400 1401 static void 1402 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1403 { 1404 int i; 1405 1406 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1407 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1408 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1409 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1410 for (i = 0; i < sc->sc_isoctx; i++) { 1411 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1412 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1413 } 1414 } 1415 1416 static void 1417 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1418 { 1419 struct fwohci_buf *fb, *tfb; 1420 1421 #if DOUBLEBUF 1422 if (fc->fc_type != FWOHCI_CTX_ISO_MULTI) { 1423 #endif 1424 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1425 if (fc->fc_type) { 1426 if (fb->fb_off == 0) 1427 break; 1428 } else { 1429 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1430 fb->fb_desc->fd_rescount != 0) 1431 break; 1432 } 1433 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1434 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1435 fb->fb_off = 0; 1436 fb->fb_desc->fd_branch = 0; 1437 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1438 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1439 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1440 } 1441 #if DOUBLEBUF 1442 } else { 1443 struct fwohci_buf_s fctmp; 1444 1445 /* cleaning buffer */ 1446 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; 1447 fb = TAILQ_NEXT(fb, fb_list)) { 1448 fb->fb_off = 0; 1449 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1450 } 1451 1452 /* rotating buffer */ 1453 fctmp = fc->fc_buf; 1454 fc->fc_buf = fc->fc_buf2; 1455 fc->fc_buf2 = fctmp; 1456 } 1457 #endif 1458 } 1459 1460 static int 1461 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_buf **fbp, caddr_t *pp, 1462 int len) 1463 { 1464 struct fwohci_buf *fb; 1465 struct fwohci_desc *fd; 1466 int bufend; 1467 1468 fb = *fbp; 1469 again: 1470 fd = fb->fb_desc; 1471 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1472 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1473 fd->fd_reqcount, fd->fd_rescount, len, 1474 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1475 bufend = fd->fd_reqcount - fd->fd_rescount; 1476 if (fb->fb_off >= bufend) { 1477 DPRINTFN(5, ("buf %x finish req %d res %d off %d ", 1478 fb->fb_desc->fd_data, fd->fd_reqcount, fd->fd_rescount, 1479 fb->fb_off)); 1480 if (fd->fd_rescount == 0) { 1481 *fbp = fb = TAILQ_NEXT(fb, fb_list); 1482 if (fb != NULL) 1483 goto again; 1484 } 1485 return 0; 1486 } 1487 if (fb->fb_off + len > bufend) 1488 len = bufend - fb->fb_off; 1489 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1490 BUS_DMASYNC_POSTREAD); 1491 *pp = fb->fb_buf + fb->fb_off; 1492 fb->fb_off += roundup(len, 4); 1493 return len; 1494 } 1495 1496 static int 1497 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1498 struct fwohci_pkt *pkt) 1499 { 1500 caddr_t p; 1501 struct fwohci_buf *fb; 1502 int len, count, i; 1503 #ifdef FW_DEBUG 1504 int tlabel; 1505 #endif 1506 1507 memset(pkt, 0, sizeof(*pkt)); 1508 pkt->fp_uio.uio_iov = pkt->fp_iov; 1509 pkt->fp_uio.uio_rw = UIO_WRITE; 1510 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1511 1512 /* get first quadlet */ 1513 fb = TAILQ_FIRST(&fc->fc_buf); 1514 count = 4; 1515 len = fwohci_buf_pktget(sc, &fb, &p, count); 1516 if (len <= 0) { 1517 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1518 fc->fc_ctx)); 1519 return 0; 1520 } 1521 pkt->fp_hdr[0] = *(u_int32_t *)p; 1522 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1523 switch (pkt->fp_tcode) { 1524 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1525 case IEEE1394_TCODE_READ_RESP_QUAD: 1526 pkt->fp_hlen = 12; 1527 pkt->fp_dlen = 4; 1528 break; 1529 case IEEE1394_TCODE_READ_REQ_BLOCK: 1530 pkt->fp_hlen = 16; 1531 pkt->fp_dlen = 0; 1532 break; 1533 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1534 case IEEE1394_TCODE_READ_RESP_BLOCK: 1535 case IEEE1394_TCODE_LOCK_REQ: 1536 case IEEE1394_TCODE_LOCK_RESP: 1537 pkt->fp_hlen = 16; 1538 break; 1539 case IEEE1394_TCODE_STREAM_DATA: 1540 #ifdef DIAGNOSTIC 1541 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) 1542 #endif 1543 { 1544 pkt->fp_hlen = 4; 1545 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1546 DPRINTFN(5, ("[%d]", pkt->fp_dlen)); 1547 break; 1548 } 1549 #ifdef DIAGNOSTIC 1550 else { 1551 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1552 return 0; 1553 } 1554 #endif 1555 default: 1556 pkt->fp_hlen = 12; 1557 pkt->fp_dlen = 0; 1558 break; 1559 } 1560 1561 /* get header */ 1562 while (count < pkt->fp_hlen) { 1563 len = fwohci_buf_pktget(sc, &fb, &p, pkt->fp_hlen - count); 1564 if (len == 0) { 1565 printf("fwohci_buf_input: malformed input 1: %d\n", 1566 pkt->fp_hlen - count); 1567 return 0; 1568 } 1569 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1570 count += len; 1571 } 1572 if (pkt->fp_hlen == 16 && 1573 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1574 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1575 #ifdef FW_DEBUG 1576 tlabel = (pkt->fp_hdr[0] & 0x0000fc00) >> 10; 1577 #endif 1578 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, tlabel=0x%x, hlen=%d, " 1579 "dlen=%d\n", pkt->fp_tcode, tlabel, pkt->fp_hlen, pkt->fp_dlen)); 1580 1581 /* get data */ 1582 count = 0; 1583 i = 0; 1584 while (count < pkt->fp_dlen) { 1585 len = fwohci_buf_pktget(sc, &fb, 1586 (caddr_t *)&pkt->fp_iov[i].iov_base, 1587 pkt->fp_dlen - count); 1588 if (len == 0) { 1589 printf("fwohci_buf_input: malformed input 2: %d\n", 1590 pkt->fp_dlen - count); 1591 return 0; 1592 } 1593 pkt->fp_iov[i++].iov_len = len; 1594 count += len; 1595 } 1596 pkt->fp_uio.uio_iovcnt = i; 1597 pkt->fp_uio.uio_resid = count; 1598 1599 /* get trailer */ 1600 len = fwohci_buf_pktget(sc, &fb, (caddr_t *)&pkt->fp_trail, 1601 sizeof(*pkt->fp_trail)); 1602 if (len <= 0) { 1603 printf("fwohci_buf_input: malformed input 3: %d\n", 1604 pkt->fp_hlen - count); 1605 return 0; 1606 } 1607 return 1; 1608 } 1609 1610 static int 1611 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1612 struct fwohci_pkt *pkt) 1613 { 1614 caddr_t p; 1615 int len; 1616 struct fwohci_buf *fb; 1617 struct fwohci_desc *fd; 1618 1619 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1620 return fwohci_buf_input(sc, fc, pkt); 1621 } 1622 1623 memset(pkt, 0, sizeof(*pkt)); 1624 pkt->fp_uio.uio_iov = pkt->fp_iov; 1625 pkt->fp_uio.uio_rw = UIO_WRITE; 1626 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1627 1628 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1629 if (fb == NULL) 1630 return 0; 1631 if (fb->fb_off == 0) 1632 break; 1633 } 1634 fd = fb->fb_desc; 1635 len = fd->fd_reqcount - fd->fd_rescount; 1636 if (len == 0) 1637 return 0; 1638 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1639 BUS_DMASYNC_POSTREAD); 1640 1641 p = fb->fb_buf; 1642 fb->fb_off += roundup(len, 4); 1643 if (len < 8) { 1644 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1645 return 0; 1646 } 1647 1648 /* 1649 * get trailer first, may be bogus data unless status update 1650 * in descriptor is set. 1651 */ 1652 pkt->fp_trail = (u_int32_t *)p; 1653 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1654 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1655 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1656 #ifdef DIAGNOSTIC 1657 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1658 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1659 pkt->fp_tcode); 1660 return 0; 1661 } 1662 #endif 1663 pkt->fp_hlen = 4; 1664 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1665 p += 8; 1666 len -= 8; 1667 if (pkt->fp_dlen != len) { 1668 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1669 pkt->fp_dlen, len); 1670 return 0; 1671 } 1672 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1673 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1674 pkt->fp_iov[0].iov_base = p; 1675 pkt->fp_iov[0].iov_len = len; 1676 pkt->fp_uio.uio_iovcnt = 0; 1677 pkt->fp_uio.uio_resid = len; 1678 return 1; 1679 } 1680 1681 static int 1682 fwohci_handler_set(struct fwohci_softc *sc, 1683 int tcode, u_int32_t key1, u_int32_t key2, 1684 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1685 void *arg) 1686 { 1687 struct fwohci_ctx *fc; 1688 struct fwohci_handler *fh; 1689 int i, j; 1690 1691 if (tcode == IEEE1394_TCODE_STREAM_DATA && 1692 (((key1 & OHCI_ASYNC_STREAM) && sc->sc_ctx_as != NULL) 1693 || (key1 & OHCI_ASYNC_STREAM) == 0)) { 1694 int isasync = key1 & OHCI_ASYNC_STREAM; 1695 1696 key1 = key1 & IEEE1394_ISO_CHANNEL_ANY ? 1697 IEEE1394_ISO_CHANNEL_ANY : (key1 & IEEE1394_ISOCH_MASK); 1698 if (key1 & IEEE1394_ISO_CHANNEL_ANY) { 1699 printf("%s: key changed to %x\n", 1700 sc->sc_sc1394.sc1394_dev.dv_xname, key1); 1701 } 1702 j = sc->sc_isoctx; 1703 fh = NULL; 1704 1705 for (i = 0; i < sc->sc_isoctx; i++) { 1706 if ((fc = sc->sc_ctx_as[i]) == NULL) { 1707 if (j == sc->sc_isoctx) 1708 j = i; 1709 continue; 1710 } 1711 fh = LIST_FIRST(&fc->fc_handler); 1712 if (fh->fh_tcode == tcode && 1713 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1714 break; 1715 fh = NULL; 1716 } 1717 if (fh == NULL) { 1718 if (handler == NULL) 1719 return 0; 1720 if (j == sc->sc_isoctx) { 1721 DPRINTF(("fwohci_handler_set: no more free " 1722 "context\n")); 1723 return ENOMEM; 1724 } 1725 if ((fc = sc->sc_ctx_as[j]) == NULL) { 1726 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j, 1727 isasync ? FWOHCI_CTX_ISO_SINGLE : 1728 FWOHCI_CTX_ISO_MULTI); 1729 sc->sc_ctx_as[j] = fc; 1730 } 1731 } 1732 #ifdef FW_DEBUG 1733 if (fh == NULL && handler != NULL) { 1734 printf("use ir context %d\n", j); 1735 } else if (fh != NULL && handler == NULL) { 1736 printf("remove ir context %d\n", i); 1737 } 1738 #endif 1739 } else { 1740 switch (tcode) { 1741 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1742 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1743 case IEEE1394_TCODE_READ_REQ_QUAD: 1744 case IEEE1394_TCODE_READ_REQ_BLOCK: 1745 case IEEE1394_TCODE_LOCK_REQ: 1746 fc = sc->sc_ctx_arrq; 1747 break; 1748 case IEEE1394_TCODE_WRITE_RESP: 1749 case IEEE1394_TCODE_READ_RESP_QUAD: 1750 case IEEE1394_TCODE_READ_RESP_BLOCK: 1751 case IEEE1394_TCODE_LOCK_RESP: 1752 fc = sc->sc_ctx_arrs; 1753 break; 1754 default: 1755 return EIO; 1756 } 1757 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1758 fh = LIST_NEXT(fh, fh_list)) { 1759 if (fh->fh_tcode == tcode && 1760 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1761 break; 1762 } 1763 } 1764 if (handler == NULL) { 1765 if (fh != NULL) { 1766 LIST_REMOVE(fh, fh_list); 1767 free(fh, M_DEVBUF); 1768 } 1769 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1770 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1771 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1772 sc->sc_ctx_as[fc->fc_ctx] = NULL; 1773 fwohci_ctx_free(sc, fc); 1774 } 1775 return 0; 1776 } 1777 if (fh == NULL) { 1778 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1779 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1780 } 1781 fh->fh_tcode = tcode; 1782 fh->fh_key1 = key1; 1783 fh->fh_key2 = key2; 1784 fh->fh_handler = handler; 1785 fh->fh_handarg = arg; 1786 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x\n", 1787 fc->fc_ctx, tcode, key1, key2)); 1788 1789 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1790 fwohci_ctx_init(sc, fc); 1791 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1792 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1793 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1794 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1795 } 1796 return 0; 1797 } 1798 1799 1800 1801 1802 1803 /* 1804 * static ieee1394_ir_tag_t 1805 * fwohci_ir_ctx_set(struct device *dev, int channel, int tagbm, 1806 * int bufnum, int maxsize, int flags) 1807 * 1808 * This function will return non-negative value if it succeeds. 1809 * This return value is pointer to the context of isochronous 1810 * transmission. This function will return NULL value if it 1811 * fails. 1812 */ 1813 ieee1394_ir_tag_t 1814 fwohci_ir_ctx_set(struct device *dev, int channel, int tagbm, 1815 int bufnum, int maxsize, int flags) 1816 { 1817 int i, openctx; 1818 struct fwohci_ir_ctx *irc; 1819 struct fwohci_softc *sc = (struct fwohci_softc *)dev; 1820 const char *xname = sc->sc_sc1394.sc1394_dev.dv_xname; 1821 1822 printf("%s: ir_ctx_set channel %d tagbm 0x%x maxsize %d bufnum %d\n", 1823 xname, channel, tagbm, maxsize, bufnum); 1824 /* 1825 * This loop will find the smallest vacant context and check 1826 * whether other channel uses the same channel. 1827 */ 1828 openctx = sc->sc_isoctx; 1829 for (i = 0; i < sc->sc_isoctx; ++i) { 1830 if (sc->sc_ctx_ir[i] == NULL) { 1831 /* 1832 * Find a vacant contet. If this has the 1833 * smallest context number, register it. 1834 */ 1835 if (openctx == sc->sc_isoctx) { 1836 openctx = i; 1837 } 1838 } else { 1839 /* 1840 * This context is used. Check whether this 1841 * context uses the same channel as ours. 1842 */ 1843 if (sc->sc_ctx_ir[i]->irc_channel == channel) { 1844 /* Using same channel. */ 1845 printf("%s: channel %d occupied by ctx%d\n", 1846 xname, channel, i); 1847 return NULL; 1848 } 1849 } 1850 } 1851 1852 /* 1853 * If there is a vacant context, allocate isochronous transmit 1854 * context for it. 1855 */ 1856 if (openctx != sc->sc_isoctx) { 1857 printf("%s using ctx %d for iso receive\n", xname, openctx); 1858 if ((irc = fwohci_ir_ctx_construct(sc, openctx, channel, 1859 tagbm, bufnum, maxsize, flags)) == NULL) { 1860 return NULL; 1861 } 1862 #ifndef IR_CTX_OPENTEST 1863 sc->sc_ctx_ir[openctx] = irc; 1864 #else 1865 fwohci_ir_ctx_destruct(irc); 1866 irc = NULL; 1867 #endif 1868 } else { 1869 printf("%s: cannot find any vacant contexts\n", xname); 1870 irc = NULL; 1871 } 1872 1873 return (ieee1394_ir_tag_t)irc; 1874 } 1875 1876 1877 /* 1878 * int fwohci_ir_ctx_clear(struct device *dev, ieee1394_ir_tag_t *ir) 1879 * 1880 * This function will return 0 if it succeed. Otherwise return 1881 * negative value. 1882 */ 1883 int 1884 fwohci_ir_ctx_clear(struct device *dev, ieee1394_ir_tag_t ir) 1885 { 1886 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)ir; 1887 struct fwohci_softc *sc = irc->irc_sc; 1888 int i; 1889 1890 if (sc->sc_ctx_ir[irc->irc_num] != irc) { 1891 printf("fwohci_ir_ctx_clear: irc differs %p %p\n", 1892 sc->sc_ctx_ir[irc->irc_num], irc); 1893 return -1; 1894 } 1895 1896 i = 0; 1897 while (irc->irc_status & IRC_STATUS_RUN) { 1898 tsleep((void *)irc, PWAIT|PCATCH, "IEEE1394 iso receive", 100); 1899 if (irc->irc_status & IRC_STATUS_RUN) { 1900 if (fwohci_ir_stop(irc) == 0) { 1901 irc->irc_status &= ~IRC_STATUS_RUN; 1902 } 1903 1904 } 1905 if (++i > 20) { 1906 u_int32_t reg 1907 = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 1908 OHCI_SUBREG_ContextControlSet); 1909 1910 printf("fwochi_ir_ctx_clear: " 1911 "Cannot stop iso receive engine\n"); 1912 printf("%s: intr IR_CommandPtr 0x%08x " 1913 "ContextCtrl 0x%08x%s%s%s%s\n", 1914 sc->sc_sc1394.sc1394_dev.dv_xname, 1915 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 1916 OHCI_SUBREG_CommandPtr), 1917 reg, 1918 reg & OHCI_CTXCTL_RUN ? " run" : "", 1919 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 1920 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 1921 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 1922 1923 return EBUSY; 1924 } 1925 } 1926 1927 printf("fwohci_ir_ctx_clear: DMA engine is stopped. get %d frames max queuelen %d pos %d\n", 1928 irc->irc_pktcount, irc->irc_maxqueuelen, irc->irc_maxqueuepos); 1929 1930 fwohci_ir_ctx_destruct(irc); 1931 1932 sc->sc_ctx_ir[irc->irc_num] = NULL; 1933 1934 return 0; 1935 } 1936 1937 1938 1939 1940 1941 1942 1943 1944 ieee1394_it_tag_t 1945 fwohci_it_set(struct ieee1394_softc *isc, int channel, int tagbm) 1946 { 1947 ieee1394_it_tag_t rv; 1948 int tag; 1949 1950 for (tag = 0; tagbm != 0 && (tagbm & 0x01) == 0; tagbm >>= 1, ++tag); 1951 1952 rv = fwohci_it_ctx_set((struct fwohci_softc *)isc, channel, tag, 488); 1953 1954 return rv; 1955 } 1956 1957 /* 1958 * static ieee1394_it_tag_t 1959 * fwohci_it_ctx_set(struct fwohci_softc *sc, 1960 * u_int32_t key1 (channel), u_int32_t key2 (tag), int maxsize) 1961 * 1962 * This function will return non-negative value if it succeeds. 1963 * This return value is pointer to the context of isochronous 1964 * transmission. This function will return NULL value if it 1965 * fails. 1966 */ 1967 static ieee1394_it_tag_t 1968 fwohci_it_ctx_set(struct fwohci_softc *sc, int channel, int tag, int maxsize) 1969 { 1970 int i, openctx; 1971 struct fwohci_it_ctx *itc; 1972 const char *xname = sc->sc_sc1394.sc1394_dev.dv_xname; 1973 #ifdef TEST_CHAIN 1974 extern int fwohci_test_chain(struct fwohci_it_ctx *); 1975 #endif /* TEST_CHAIN */ 1976 #ifdef TEST_WRITE 1977 extern void fwohci_test_write(struct fwohci_it_ctx *itc); 1978 #endif /* TEST_WRITE */ 1979 1980 printf("%s: it_ctx_set channel %d tag %d maxsize %d\n", 1981 xname, channel, tag, maxsize); 1982 1983 /* 1984 * This loop will find the smallest vacant context and check 1985 * whether other channel uses the same channel. 1986 */ 1987 openctx = sc->sc_itctx; 1988 for (i = 0; i < sc->sc_itctx; ++i) { 1989 if (sc->sc_ctx_it[i] == NULL) { 1990 /* 1991 * Find a vacant contet. If this has the 1992 * smallest context number, register it. 1993 */ 1994 if (openctx == sc->sc_itctx) { 1995 openctx = i; 1996 } 1997 } else { 1998 /* 1999 * This context is used. Check whether this 2000 * context uses the same channel as ours. 2001 */ 2002 if (sc->sc_ctx_it[i]->itc_channel == channel) { 2003 /* Using same channel. */ 2004 printf("%s: channel %d occupied by ctx%d\n", 2005 xname, channel, i); 2006 return NULL; 2007 } 2008 } 2009 } 2010 2011 /* 2012 * If there is a vacant context, allocate isochronous transmit 2013 * context for it. 2014 */ 2015 if (openctx != sc->sc_itctx) { 2016 printf("%s using ctx %d for iso trasmit\n", xname, openctx); 2017 if ((itc = fwohci_it_ctx_construct(sc, openctx, channel, 2018 tag, maxsize)) == NULL) { 2019 return NULL; 2020 } 2021 sc->sc_ctx_it[openctx] = itc; 2022 2023 #ifdef TEST_CHAIN 2024 fwohci_test_chain(itc); 2025 #endif /* TEST_CHAIN */ 2026 #ifdef TEST_WRITE 2027 fwohci_test_write(itc); 2028 itc = NULL; 2029 #endif /* TEST_WRITE */ 2030 2031 } else { 2032 printf("%s: cannot find any vacant contexts\n", xname); 2033 itc = NULL; 2034 } 2035 2036 return (ieee1394_it_tag_t)itc; 2037 } 2038 2039 2040 /* 2041 * int fwohci_it_ctx_clear(ieee1394_it_tag_t *it) 2042 * 2043 * This function will return 0 if it succeed. Otherwise return 2044 * negative value. 2045 */ 2046 int 2047 fwohci_it_ctx_clear(ieee1394_it_tag_t *it) 2048 { 2049 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 2050 struct fwohci_softc *sc = itc->itc_sc; 2051 int i; 2052 2053 if (sc->sc_ctx_it[itc->itc_num] != itc) { 2054 printf("fwohci_it_ctx_clear: itc differs %p %p\n", 2055 sc->sc_ctx_it[itc->itc_num], itc); 2056 return -1; 2057 } 2058 2059 fwohci_it_ctx_flush(it); 2060 2061 i = 0; 2062 while (itc->itc_flags & ITC_FLAGS_RUN) { 2063 tsleep((void *)itc, PWAIT|PCATCH, "IEEE1394 iso transmit", 100); 2064 if (itc->itc_flags & ITC_FLAGS_RUN) { 2065 u_int32_t reg; 2066 2067 reg = OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2068 OHCI_SUBREG_ContextControlSet); 2069 2070 if ((reg & OHCI_CTXCTL_WAKE) == 0) { 2071 itc->itc_flags &= ~ITC_FLAGS_RUN; 2072 printf("fwochi_it_ctx_clear: " 2073 "DMA engine stopped without intr\n"); 2074 } 2075 printf("%s: %d intr IT_CommandPtr 0x%08x " 2076 "ContextCtrl 0x%08x%s%s%s%s\n", 2077 sc->sc_sc1394.sc1394_dev.dv_xname, i, 2078 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2079 OHCI_SUBREG_CommandPtr), 2080 reg, 2081 reg & OHCI_CTXCTL_RUN ? " run" : "", 2082 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 2083 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 2084 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 2085 2086 2087 } 2088 if (++i > 20) { 2089 u_int32_t reg 2090 = OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2091 OHCI_SUBREG_ContextControlSet); 2092 2093 printf("fwochi_it_ctx_clear: " 2094 "Cannot stop iso transmit engine\n"); 2095 printf("%s: intr IT_CommandPtr 0x%08x " 2096 "ContextCtrl 0x%08x%s%s%s%s\n", 2097 sc->sc_sc1394.sc1394_dev.dv_xname, 2098 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2099 OHCI_SUBREG_CommandPtr), 2100 reg, 2101 reg & OHCI_CTXCTL_RUN ? " run" : "", 2102 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 2103 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 2104 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 2105 2106 return EBUSY; 2107 } 2108 } 2109 2110 printf("fwohci_it_ctx_clear: DMA engine is stopped.\n"); 2111 2112 fwohci_it_ctx_destruct(itc); 2113 2114 sc->sc_ctx_it[itc->itc_num] = NULL; 2115 2116 2117 return 0; 2118 } 2119 2120 2121 2122 2123 2124 2125 /* 2126 * Asyncronous Receive Requests input frontend. 2127 */ 2128 static void 2129 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 2130 { 2131 int rcode; 2132 u_int32_t key1, key2; 2133 struct fwohci_handler *fh; 2134 struct fwohci_pkt pkt, res; 2135 2136 /* 2137 * Do not return if next packet is in the buffer, or the next 2138 * packet cannot be received until the next receive interrupt. 2139 */ 2140 while (fwohci_buf_input(sc, fc, &pkt)) { 2141 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 2142 fwohci_phy_input(sc, &pkt); 2143 continue; 2144 } 2145 key1 = pkt.fp_hdr[1] & 0xffff; 2146 key2 = pkt.fp_hdr[2]; 2147 memset(&res, 0, sizeof(res)); 2148 res.fp_uio.uio_rw = UIO_WRITE; 2149 res.fp_uio.uio_segflg = UIO_SYSSPACE; 2150 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 2151 fh = LIST_NEXT(fh, fh_list)) { 2152 if (pkt.fp_tcode == fh->fh_tcode && 2153 key1 == fh->fh_key1 && 2154 key2 == fh->fh_key2) { 2155 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 2156 &pkt); 2157 break; 2158 } 2159 } 2160 if (fh == NULL) { 2161 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 2162 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 2163 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 2164 key2)); 2165 } 2166 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 2167 OHCI_CTXCTL_EVENT_ACK_PENDING) 2168 continue; 2169 if (rcode != -1) 2170 fwohci_atrs_output(sc, rcode, &pkt, &res); 2171 } 2172 fwohci_buf_next(sc, fc); 2173 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2174 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 2175 } 2176 2177 2178 /* 2179 * Asynchronous Receive Response input frontend. 2180 */ 2181 static void 2182 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 2183 { 2184 struct fwohci_pkt pkt; 2185 struct fwohci_handler *fh; 2186 u_int16_t srcid; 2187 int rcode, tlabel; 2188 2189 while (fwohci_buf_input(sc, fc, &pkt)) { 2190 srcid = pkt.fp_hdr[1] >> 16; 2191 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 2192 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 2193 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 2194 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 2195 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 2196 pkt.fp_dlen)); 2197 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 2198 fh = LIST_NEXT(fh, fh_list)) { 2199 if (pkt.fp_tcode == fh->fh_tcode && 2200 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 2201 tlabel == fh->fh_key2) { 2202 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 2203 LIST_REMOVE(fh, fh_list); 2204 free(fh, M_DEVBUF); 2205 break; 2206 } 2207 } 2208 if (fh == NULL) 2209 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 2210 } 2211 fwohci_buf_next(sc, fc); 2212 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2213 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 2214 } 2215 2216 /* 2217 * Isochronous Receive input frontend. 2218 */ 2219 static void 2220 fwohci_as_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 2221 { 2222 int rcode, chan, tag; 2223 struct iovec *iov; 2224 struct fwohci_handler *fh; 2225 struct fwohci_pkt pkt; 2226 2227 #if DOUBLEBUF 2228 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 2229 struct fwohci_buf *fb; 2230 int i; 2231 u_int32_t reg; 2232 2233 /* stop dma engine before read buffer */ 2234 reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, 2235 OHCI_SUBREG_ContextControlClear); 2236 DPRINTFN(5, ("ir_input %08x =>", reg)); 2237 if (reg & OHCI_CTXCTL_RUN) { 2238 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 2239 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2240 } 2241 DPRINTFN(5, (" %08x\n", OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlClear))); 2242 2243 i = 0; 2244 while ((reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet)) & OHCI_CTXCTL_ACTIVE) { 2245 delay(10); 2246 if (++i > 10000) { 2247 printf("cannot stop dma engine 0x%08x\n", reg); 2248 return; 2249 } 2250 } 2251 2252 /* rotate dma buffer */ 2253 fb = TAILQ_FIRST(&fc->fc_buf2); 2254 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_CommandPtr, 2255 fb->fb_daddr | 1); 2256 /* start dma engine */ 2257 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 2258 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 2259 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, 2260 (1 << fc->fc_ctx)); 2261 } 2262 #endif 2263 2264 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 2265 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 2266 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 2267 DPRINTFN(1, ("fwohci_as_input: hdr 0x%08x, tcode 0x%0x, hlen %d" 2268 ", dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 2269 pkt.fp_dlen)); 2270 if (tag == IEEE1394_TAG_GASP && 2271 fc->fc_type == FWOHCI_CTX_ISO_SINGLE) { 2272 /* 2273 * The pkt with tag=3 is GASP format. 2274 * Move GASP header to header part. 2275 */ 2276 if (pkt.fp_dlen < 8) 2277 continue; 2278 iov = pkt.fp_iov; 2279 /* assuming pkt per buffer mode */ 2280 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 2281 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 2282 iov->iov_base = (caddr_t)iov->iov_base + 8; 2283 iov->iov_len -= 8; 2284 pkt.fp_hlen += 8; 2285 pkt.fp_dlen -= 8; 2286 } 2287 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 2288 fh = LIST_NEXT(fh, fh_list)) { 2289 if (pkt.fp_tcode == fh->fh_tcode && 2290 (chan == fh->fh_key1 || 2291 fh->fh_key1 == IEEE1394_ISO_CHANNEL_ANY) && 2292 ((1 << tag) & fh->fh_key2) != 0) { 2293 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 2294 &pkt); 2295 break; 2296 } 2297 } 2298 #ifdef FW_DEBUG 2299 if (fh == NULL) { 2300 DPRINTFN(1, ("fwohci_as_input: no handler\n")); 2301 } else { 2302 DPRINTFN(1, ("fwohci_as_input: rcode %d\n", rcode)); 2303 } 2304 #endif 2305 } 2306 fwohci_buf_next(sc, fc); 2307 2308 if (fc->fc_type == FWOHCI_CTX_ISO_SINGLE) { 2309 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 2310 OHCI_SUBREG_ContextControlSet, 2311 OHCI_CTXCTL_WAKE); 2312 } 2313 } 2314 2315 /* 2316 * Asynchronous Transmit common routine. 2317 */ 2318 static int 2319 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 2320 struct fwohci_pkt *pkt) 2321 { 2322 struct fwohci_buf *fb; 2323 struct fwohci_desc *fd; 2324 struct mbuf *m, *m0; 2325 int i, ndesc, error, off, len; 2326 u_int32_t val; 2327 #ifdef FW_DEBUG 2328 struct iovec *iov; 2329 int tlabel = (pkt->fp_hdr[0] & 0x0000fc00) >> 10; 2330 #endif 2331 2332 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 2333 /* We can't send anything during selfid duration */ 2334 return EAGAIN; 2335 2336 #ifdef FW_DEBUG 2337 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, tlabel 0x%x hlen %d, " 2338 "dlen %d", pkt->fp_tcode, tlabel, pkt->fp_hlen, pkt->fp_dlen)); 2339 for (i = 0; i < pkt->fp_hlen/4; i++) 2340 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2341 DPRINTFN(2, ("$")); 2342 for (ndesc = 0, iov = pkt->fp_iov; 2343 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 2344 for (i = 0; i < iov->iov_len; i++) 2345 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2346 ((u_int8_t *)iov->iov_base)[i])); 2347 DPRINTFN(2, ("$")); 2348 } 2349 DPRINTFN(1, ("\n")); 2350 #endif 2351 2352 if ((m = pkt->fp_m) != NULL) { 2353 for (ndesc = 2; m != NULL; m = m->m_next) 2354 ndesc++; 2355 if (ndesc > OHCI_DESC_MAX) { 2356 m0 = NULL; 2357 ndesc = 2; 2358 for (off = 0; off < pkt->fp_dlen; off += len) { 2359 if (m0 == NULL) { 2360 MGETHDR(m0, M_DONTWAIT, MT_DATA); 2361 if (m0 != NULL) 2362 M_COPY_PKTHDR(m0, pkt->fp_m); 2363 m = m0; 2364 } else { 2365 MGET(m->m_next, M_DONTWAIT, MT_DATA); 2366 m = m->m_next; 2367 } 2368 if (m != NULL) 2369 MCLGET(m, M_DONTWAIT); 2370 if (m == NULL || (m->m_flags & M_EXT) == 0) { 2371 m_freem(m0); 2372 return ENOMEM; 2373 } 2374 len = pkt->fp_dlen - off; 2375 if (len > m->m_ext.ext_size) 2376 len = m->m_ext.ext_size; 2377 m_copydata(pkt->fp_m, off, len, 2378 mtod(m, caddr_t)); 2379 m->m_len = len; 2380 ndesc++; 2381 } 2382 m_freem(pkt->fp_m); 2383 pkt->fp_m = m0; 2384 } 2385 } else 2386 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 2387 2388 if (ndesc > OHCI_DESC_MAX) 2389 return ENOBUFS; 2390 2391 if (fc->fc_bufcnt > 50) /*XXX*/ 2392 return ENOBUFS; 2393 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 2394 if (ndesc > 2) { 2395 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, 2396 OHCI_DESC_MAX - 2, pkt->fp_dlen, 0, BUS_DMA_WAITOK, 2397 &fb->fb_dmamap)) != 0) { 2398 fwohci_desc_put(sc, fb->fb_desc, ndesc); 2399 free(fb, M_DEVBUF); 2400 return error; 2401 } 2402 2403 if (pkt->fp_m != NULL) 2404 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 2405 pkt->fp_m, BUS_DMA_WAITOK); 2406 else 2407 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 2408 &pkt->fp_uio, BUS_DMA_WAITOK); 2409 if (error != 0) { 2410 DPRINTFN(1, ("Can't load DMA map: %d\n", error)); 2411 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 2412 fwohci_desc_put(sc, fb->fb_desc, ndesc); 2413 free(fb, M_DEVBUF); 2414 return error; 2415 } 2416 ndesc = fb->fb_dmamap->dm_nsegs + 2; 2417 2418 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 2419 BUS_DMASYNC_PREWRITE); 2420 } 2421 2422 fb->fb_nseg = ndesc; 2423 fb->fb_desc = fwohci_desc_get(sc, ndesc); 2424 if (fb->fb_desc == NULL) { 2425 free(fb, M_DEVBUF); 2426 return ENOBUFS; 2427 } 2428 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 2429 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 2430 fb->fb_m = pkt->fp_m; 2431 fb->fb_callback = pkt->fp_callback; 2432 fb->fb_statuscb = pkt->fp_statuscb; 2433 fb->fb_statusarg = pkt->fp_statusarg; 2434 2435 fd = fb->fb_desc; 2436 fd->fd_flags = OHCI_DESC_IMMED; 2437 fd->fd_reqcount = pkt->fp_hlen; 2438 fd->fd_data = 0; 2439 fd->fd_branch = 0; 2440 fd->fd_status = 0; 2441 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 2442 i = 3; /* XXX: 3 sec */ 2443 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 2444 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 2445 ((((val >> 25) + i) & 0x7) << 13); 2446 } else 2447 fd->fd_timestamp = 0; 2448 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 2449 for (i = 0; i < ndesc - 2; i++) { 2450 fd = fb->fb_desc + 2 + i; 2451 fd->fd_flags = 0; 2452 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 2453 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 2454 fd->fd_branch = 0; 2455 fd->fd_status = 0; 2456 fd->fd_timestamp = 0; 2457 } 2458 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 2459 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 2460 2461 #ifdef FW_DEBUG 2462 DPRINTFN(1, ("fwohci_at_output: desc %ld", 2463 (long)(fb->fb_desc - sc->sc_desc))); 2464 for (i = 0; i < ndesc * 4; i++) 2465 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 2466 ((u_int32_t *)fb->fb_desc)[i])); 2467 DPRINTFN(1, ("\n")); 2468 #endif 2469 2470 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 2471 OHCI_SUBREG_ContextControlClear); 2472 2473 if (val & OHCI_CTXCTL_RUN) { 2474 if (fc->fc_branch == NULL) { 2475 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2476 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2477 goto run; 2478 } 2479 *fc->fc_branch = fb->fb_daddr | ndesc; 2480 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2481 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 2482 } else { 2483 run: 2484 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2485 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 2486 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2487 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 2488 } 2489 fc->fc_branch = &fd->fd_branch; 2490 2491 fc->fc_bufcnt++; 2492 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 2493 pkt->fp_m = NULL; 2494 return 0; 2495 } 2496 2497 static void 2498 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 2499 { 2500 struct fwohci_buf *fb; 2501 struct fwohci_desc *fd; 2502 struct fwohci_pkt pkt; 2503 int i; 2504 2505 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 2506 fd = fb->fb_desc; 2507 #ifdef FW_DEBUG 2508 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 2509 force ? "force " : "", (long)(fd - sc->sc_desc), 2510 fb->fb_nseg)); 2511 for (i = 0; i < fb->fb_nseg * 4; i++) 2512 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 2513 ((u_int32_t *)fd)[i])); 2514 DPRINTFN(1, ("\n")); 2515 #endif 2516 if (fb->fb_nseg > 2) 2517 fd += fb->fb_nseg - 1; 2518 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 2519 break; 2520 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 2521 if (fc->fc_branch == &fd->fd_branch) { 2522 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2523 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2524 fc->fc_branch = NULL; 2525 for (i = 0; i < OHCI_LOOP; i++) { 2526 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 2527 OHCI_SUBREG_ContextControlClear) & 2528 OHCI_CTXCTL_ACTIVE)) 2529 break; 2530 DELAY(10); 2531 } 2532 } 2533 2534 if (fb->fb_statuscb) { 2535 memset(&pkt, 0, sizeof(pkt)); 2536 pkt.fp_status = fd->fd_status; 2537 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 2538 2539 /* Indicate this is just returning the status bits. */ 2540 pkt.fp_tcode = -1; 2541 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 2542 fb->fb_statuscb = NULL; 2543 fb->fb_statusarg = NULL; 2544 } 2545 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 2546 if (fb->fb_nseg > 2) 2547 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 2548 fc->fc_bufcnt--; 2549 if (fb->fb_callback) { 2550 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 2551 fb->fb_callback = NULL; 2552 } else if (fb->fb_m != NULL) 2553 m_freem(fb->fb_m); 2554 free(fb, M_DEVBUF); 2555 } 2556 } 2557 2558 /* 2559 * Asynchronous Transmit Reponse -- in response of request packet. 2560 */ 2561 static void 2562 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 2563 struct fwohci_pkt *res) 2564 { 2565 2566 if (((*req->fp_trail & 0x001f0000) >> 16) != 2567 OHCI_CTXCTL_EVENT_ACK_PENDING) 2568 return; 2569 2570 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 2571 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 2572 switch (req->fp_tcode) { 2573 case IEEE1394_TCODE_WRITE_REQ_QUAD: 2574 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 2575 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 2576 res->fp_hlen = 12; 2577 break; 2578 case IEEE1394_TCODE_READ_REQ_QUAD: 2579 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2580 res->fp_hlen = 16; 2581 res->fp_dlen = 0; 2582 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 2583 res->fp_hdr[3] = 2584 *(u_int32_t *)res->fp_iov[0].iov_base; 2585 res->fp_uio.uio_iovcnt = 0; 2586 break; 2587 case IEEE1394_TCODE_READ_REQ_BLOCK: 2588 case IEEE1394_TCODE_LOCK_REQ: 2589 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 2590 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 2591 else 2592 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2593 res->fp_hlen = 16; 2594 res->fp_dlen = res->fp_uio.uio_resid; 2595 res->fp_hdr[3] = res->fp_dlen << 16; 2596 break; 2597 } 2598 res->fp_hdr[0] |= (res->fp_tcode << 4); 2599 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 2600 } 2601 2602 /* 2603 * APPLICATION LAYER SERVICES 2604 */ 2605 2606 /* 2607 * Retrieve Global UID from GUID ROM 2608 */ 2609 static int 2610 fwohci_guidrom_init(struct fwohci_softc *sc) 2611 { 2612 int i, n, off; 2613 u_int32_t val1, val2; 2614 2615 /* Extract the Global UID 2616 */ 2617 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 2618 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 2619 2620 if (val1 != 0 || val2 != 0) { 2621 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 2622 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 2623 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 2624 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 2625 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 2626 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 2627 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 2628 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 2629 } else { 2630 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 2631 if ((val1 & OHCI_Version_GUID_ROM) == 0) 2632 return -1; 2633 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 2634 for (i = 0; i < OHCI_LOOP; i++) { 2635 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2636 if (!(val1 & OHCI_Guid_AddrReset)) 2637 break; 2638 DELAY(10); 2639 } 2640 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 2641 val2 = 0; 2642 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 2643 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 2644 OHCI_Guid_RdStart); 2645 for (i = 0; i < OHCI_LOOP; i++) { 2646 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2647 if (!(val1 & OHCI_Guid_RdStart)) 2648 break; 2649 DELAY(10); 2650 } 2651 if (n < off) 2652 continue; 2653 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 2654 sc->sc_sc1394.sc1394_guid[n - off] = val1; 2655 val2 |= val1; 2656 } 2657 if (val2 == 0) 2658 return -1; 2659 } 2660 return 0; 2661 } 2662 2663 /* 2664 * Initialization for Configuration ROM (no DMA context) 2665 */ 2666 2667 #define CFR_MAXUNIT 20 2668 2669 struct configromctx { 2670 u_int32_t *ptr; 2671 int curunit; 2672 struct { 2673 u_int32_t *start; 2674 int length; 2675 u_int32_t *refer; 2676 int refunit; 2677 } unit[CFR_MAXUNIT]; 2678 }; 2679 2680 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 2681 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 2682 2683 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 2684 2685 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 2686 2687 #define CFR_PUT_CRC(cfr, n) \ 2688 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 2689 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 2690 2691 #define CFR_START_UNIT(cfr, n) \ 2692 do { \ 2693 if ((cfr)->unit[n].refer != NULL) { \ 2694 *(cfr)->unit[n].refer |= \ 2695 (cfr)->ptr - (cfr)->unit[n].refer; \ 2696 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 2697 } \ 2698 (cfr)->curunit = (n); \ 2699 (cfr)->unit[n].start = (cfr)->ptr++; \ 2700 } while (0 /* CONSTCOND */) 2701 2702 #define CFR_PUT_REFER(cfr, key, n) \ 2703 do { \ 2704 (cfr)->unit[n].refer = (cfr)->ptr; \ 2705 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2706 *(cfr)->ptr++ = (key) << 24; \ 2707 } while (0 /* CONSTCOND */) 2708 2709 #define CFR_END_UNIT(cfr) \ 2710 do { \ 2711 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2712 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2713 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2714 } while (0 /* CONSTCOND */) 2715 2716 static u_int16_t 2717 fwohci_crc16(u_int32_t *ptr, int len) 2718 { 2719 int shift; 2720 u_int32_t crc, sum, data; 2721 2722 crc = 0; 2723 while (len-- > 0) { 2724 data = *ptr++; 2725 for (shift = 28; shift >= 0; shift -= 4) { 2726 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2727 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2728 } 2729 crc &= 0xffff; 2730 } 2731 return crc; 2732 } 2733 2734 static void 2735 fwohci_configrom_init(struct fwohci_softc *sc) 2736 { 2737 int i, val; 2738 struct fwohci_buf *fb; 2739 u_int32_t *hdr; 2740 struct configromctx cfr; 2741 2742 fb = &sc->sc_buf_cnfrom; 2743 memset(&cfr, 0, sizeof(cfr)); 2744 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2745 2746 /* headers */ 2747 CFR_START_UNIT(&cfr, 0); 2748 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2749 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2750 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2751 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2752 CFR_END_UNIT(&cfr); 2753 /* copy info_length from crc_length */ 2754 *hdr |= (*hdr & 0x00ff0000) << 8; 2755 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2756 2757 /* root directory */ 2758 CFR_START_UNIT(&cfr, 1); 2759 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2760 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2761 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2762 /* spt,64,fix,lst,drq */ 2763 #ifdef INET 2764 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2765 #endif /* INET */ 2766 #ifdef INET6 2767 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2768 #endif /* INET6 */ 2769 CFR_END_UNIT(&cfr); 2770 2771 CFR_START_UNIT(&cfr, 2); 2772 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2773 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2774 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2775 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2776 CFR_END_UNIT(&cfr); 2777 2778 #ifdef INET 2779 /* IPv4 unit directory */ 2780 CFR_START_UNIT(&cfr, 3); 2781 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2782 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2783 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2784 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2785 CFR_PUT_REFER(&cfr, 0x95, 8); /* Unit location */ 2786 CFR_END_UNIT(&cfr); 2787 2788 CFR_START_UNIT(&cfr, 6); 2789 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2790 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2791 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2792 CFR_END_UNIT(&cfr); 2793 2794 CFR_START_UNIT(&cfr, 7); 2795 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2796 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2797 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2798 CFR_END_UNIT(&cfr); 2799 2800 CFR_START_UNIT(&cfr, 8); /* Spec's valid addr range. */ 2801 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2802 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2803 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2804 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2805 CFR_END_UNIT(&cfr); 2806 2807 #endif /* INET */ 2808 2809 #ifdef INET6 2810 /* IPv6 unit directory */ 2811 CFR_START_UNIT(&cfr, 4); 2812 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2813 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2814 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2815 /* XXX: TBA by IANA */ 2816 CFR_PUT_REFER(&cfr, 0x81, 10); /* textual descriptor offset */ 2817 CFR_PUT_REFER(&cfr, 0x95, 11); /* Unit location */ 2818 CFR_END_UNIT(&cfr); 2819 2820 CFR_START_UNIT(&cfr, 9); 2821 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2822 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2823 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2824 CFR_END_UNIT(&cfr); 2825 2826 CFR_START_UNIT(&cfr, 10); 2827 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2828 CFR_PUT_DATA1(&cfr, 0); 2829 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2830 CFR_END_UNIT(&cfr); 2831 2832 CFR_START_UNIT(&cfr, 11); /* Spec's valid addr range. */ 2833 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2834 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2835 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2836 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2837 CFR_END_UNIT(&cfr); 2838 2839 #endif /* INET6 */ 2840 2841 fb->fb_off = cfr.ptr - hdr; 2842 #ifdef FW_DEBUG 2843 DPRINTF(("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2844 for (i = 0; i < fb->fb_off; i++) 2845 DPRINTF(("%s%08x", i&7?" ":"\n ", hdr[i])); 2846 DPRINTF(("\n")); 2847 #endif /* FW_DEBUG */ 2848 2849 /* 2850 * Make network byte order for DMA 2851 */ 2852 for (i = 0; i < fb->fb_off; i++) 2853 HTONL(hdr[i]); 2854 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2855 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2856 2857 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2858 fb->fb_dmamap->dm_segs[0].ds_addr); 2859 2860 /* This register is only valid on OHCI 1.1. */ 2861 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2862 if ((OHCI_Version_GET_Version(val) == 1) && 2863 (OHCI_Version_GET_Revision(val) == 1)) 2864 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2865 OHCI_HCControl_BIBImageValid); 2866 2867 /* Just allow quad reads of the rom. */ 2868 for (i = 0; i < fb->fb_off; i++) 2869 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2870 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 2871 fwohci_configrom_input, NULL); 2872 } 2873 2874 static int 2875 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2876 struct fwohci_pkt *pkt) 2877 { 2878 struct fwohci_pkt res; 2879 u_int32_t loc, *rom; 2880 2881 /* This will be used as an array index so size accordingly. */ 2882 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2883 if ((loc & 0x03) != 0) { 2884 /* alignment error */ 2885 return IEEE1394_RCODE_ADDRESS_ERROR; 2886 } 2887 else 2888 loc /= 4; 2889 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2890 2891 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2892 ntohl(rom[loc]))); 2893 2894 memset(&res, 0, sizeof(res)); 2895 res.fp_hdr[3] = rom[loc]; 2896 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2897 return -1; 2898 } 2899 2900 /* 2901 * SelfID buffer (no DMA context) 2902 */ 2903 static void 2904 fwohci_selfid_init(struct fwohci_softc *sc) 2905 { 2906 struct fwohci_buf *fb; 2907 2908 fb = &sc->sc_buf_selfid; 2909 #ifdef DIAGNOSTIC 2910 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2911 panic("fwohci_selfid_init: not aligned: %ld (%ld) %p", 2912 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_addr, 2913 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2914 #endif 2915 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2916 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2917 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2918 2919 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2920 fb->fb_dmamap->dm_segs[0].ds_addr); 2921 } 2922 2923 static int 2924 fwohci_selfid_input(struct fwohci_softc *sc) 2925 { 2926 int i; 2927 u_int32_t count, val, gen; 2928 u_int32_t *buf; 2929 2930 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2931 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2932 again: 2933 if (val & OHCI_SelfID_Error) { 2934 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2935 return -1; 2936 } 2937 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2938 2939 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2940 0, count << 2, BUS_DMASYNC_POSTREAD); 2941 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2942 2943 #ifdef FW_DEBUG 2944 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2945 val)); 2946 for (i = 0; i < count; i++) 2947 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2948 DPRINTFN(1, ("\n")); 2949 #endif /* FW_DEBUG */ 2950 2951 for (i = 1; i < count; i += 2) { 2952 if (buf[i] != ~buf[i + 1]) 2953 break; 2954 if (buf[i] & 0x00000001) 2955 continue; /* more pkt */ 2956 if (buf[i] & 0x00800000) 2957 continue; /* external id */ 2958 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 2959 if ((buf[i] & 0x00400800) == 0x00400800) 2960 sc->sc_irmid = sc->sc_rootid; 2961 } 2962 2963 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2964 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 2965 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 2966 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 2967 goto again; 2968 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 2969 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 2970 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 2971 return -1; 2972 } 2973 if (i != count) { 2974 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 2975 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 2976 #if 1 2977 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 2978 /* 2979 * XXX: CXD3222 sometimes fails to DMA 2980 * selfid packet?? 2981 */ 2982 sc->sc_rootid = (count - 1) / 2 - 1; 2983 sc->sc_irmid = sc->sc_rootid; 2984 } else 2985 #endif 2986 return -1; 2987 } 2988 2989 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 2990 if ((val & OHCI_NodeId_IDValid) == 0) { 2991 sc->sc_nodeid = 0xffff; /* invalid */ 2992 printf("%s: nodeid is invalid\n", 2993 sc->sc_sc1394.sc1394_dev.dv_xname); 2994 return -1; 2995 } 2996 sc->sc_nodeid = val & 0xffff; 2997 sc->sc_sc1394.sc1394_node_id = sc->sc_nodeid & OHCI_NodeId_NodeNumber; 2998 2999 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 3000 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 3001 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 3002 sc->sc_irmid)); 3003 3004 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 3005 return -1; 3006 3007 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 3008 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 3009 OHCI_LinkControl_CycleMaster); 3010 else 3011 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 3012 OHCI_LinkControl_CycleMaster); 3013 return 0; 3014 } 3015 3016 /* 3017 * some CSRs are handled by driver. 3018 */ 3019 static void 3020 fwohci_csr_init(struct fwohci_softc *sc) 3021 { 3022 int i; 3023 static u_int32_t csr[] = { 3024 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 3025 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 3026 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 3027 CSR_SB_BROADCAST_CHANNEL 3028 }; 3029 3030 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 3031 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 3032 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 3033 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 3034 CSR_BASE_HI, CSR_BASE_LO + csr[i], fwohci_csr_input, NULL); 3035 } 3036 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 3037 } 3038 3039 static int 3040 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3041 { 3042 struct fwohci_pkt res; 3043 u_int32_t reg; 3044 3045 /* 3046 * XXX need to do special functionality other than just r/w... 3047 */ 3048 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 3049 3050 if ((reg & 0x03) != 0) { 3051 /* alignment error */ 3052 return IEEE1394_RCODE_ADDRESS_ERROR; 3053 } 3054 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 3055 *(u_int32_t *)(&sc->sc_csr[reg]))); 3056 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 3057 DPRINTFN(1, (" -> 0x%08x\n", 3058 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 3059 *(u_int32_t *)&sc->sc_csr[reg] = 3060 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 3061 } else { 3062 DPRINTFN(1, ("\n")); 3063 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 3064 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 3065 res.fp_iov[0].iov_len = 4; 3066 res.fp_uio.uio_resid = 4; 3067 res.fp_uio.uio_iovcnt = 1; 3068 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 3069 return -1; 3070 } 3071 return IEEE1394_RCODE_COMPLETE; 3072 } 3073 3074 /* 3075 * Mapping between nodeid and unique ID (EUI-64). 3076 * 3077 * Track old mappings and simply update their devices with the new id's when 3078 * they match an existing EUI. This allows proper renumeration of the bus. 3079 */ 3080 static void 3081 fwohci_uid_collect(struct fwohci_softc *sc) 3082 { 3083 int i; 3084 struct fwohci_uidtbl *fu; 3085 struct ieee1394_softc *iea; 3086 3087 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 3088 iea->sc1394_node_id = 0xffff; 3089 3090 if (sc->sc_uidtbl != NULL) 3091 free(sc->sc_uidtbl, M_DEVBUF); 3092 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 3093 M_NOWAIT|M_ZERO); /* XXX M_WAITOK requires locks */ 3094 if (sc->sc_uidtbl == NULL) 3095 return; 3096 3097 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 3098 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 3099 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 3100 fu->fu_valid = 3; 3101 3102 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 3103 if (iea) { 3104 iea->sc1394_node_id = i; 3105 DPRINTF(("%s: Updating nodeid to %d\n", 3106 iea->sc1394_dev.dv_xname, 3107 iea->sc1394_node_id)); 3108 } 3109 } else { 3110 fu->fu_valid = 0; 3111 fwohci_uid_req(sc, i); 3112 } 3113 } 3114 if (sc->sc_rootid == 0) 3115 fwohci_check_nodes(sc); 3116 } 3117 3118 static void 3119 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 3120 { 3121 struct fwohci_pkt pkt; 3122 3123 memset(&pkt, 0, sizeof(pkt)); 3124 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3125 pkt.fp_hlen = 12; 3126 pkt.fp_dlen = 0; 3127 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3128 (pkt.fp_tcode << 4); 3129 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 3130 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 3131 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 3132 sc->sc_tlabel, fwohci_uid_input, (void *)0); 3133 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3134 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3135 3136 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3137 (pkt.fp_tcode << 4); 3138 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 3139 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 3140 sc->sc_tlabel, fwohci_uid_input, (void *)1); 3141 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3142 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3143 } 3144 3145 static int 3146 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 3147 { 3148 struct fwohci_uidtbl *fu; 3149 struct ieee1394_softc *iea; 3150 struct ieee1394_attach_args fwa; 3151 int i, n, done, rcode, found; 3152 3153 found = 0; 3154 3155 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 3156 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 3157 if (rcode != IEEE1394_RCODE_COMPLETE || 3158 sc->sc_uidtbl == NULL || 3159 n > sc->sc_rootid) 3160 return 0; 3161 fu = &sc->sc_uidtbl[n]; 3162 if (arg == 0) { 3163 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 3164 fu->fu_valid |= 0x1; 3165 } else { 3166 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 3167 fu->fu_valid |= 0x2; 3168 } 3169 #ifdef FW_DEBUG 3170 if (fu->fu_valid == 0x3) 3171 DPRINTFN(1, ("fwohci_uid_input: " 3172 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 3173 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 3174 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 3175 #endif 3176 if (fu->fu_valid == 0x3) { 3177 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 3178 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 3179 found = 1; 3180 iea->sc1394_node_id = n; 3181 DPRINTF(("%s: Updating nodeid to %d\n", 3182 iea->sc1394_dev.dv_xname, 3183 iea->sc1394_node_id)); 3184 if (iea->sc1394_callback.sc1394_reset) 3185 iea->sc1394_callback.sc1394_reset(iea, 3186 iea->sc1394_callback.sc1394_resetarg); 3187 break; 3188 } 3189 if (!found) { 3190 strcpy(fwa.name, "fwnode"); 3191 memcpy(fwa.uid, fu->fu_uid, 8); 3192 fwa.nodeid = n; 3193 iea = (struct ieee1394_softc *) 3194 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 3195 fwohci_print, fwohci_submatch); 3196 if (iea != NULL) 3197 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 3198 sc1394_node); 3199 } 3200 } 3201 done = 1; 3202 3203 for (i = 0; i < sc->sc_rootid + 1; i++) { 3204 fu = &sc->sc_uidtbl[i]; 3205 if (fu->fu_valid != 0x3) { 3206 done = 0; 3207 break; 3208 } 3209 } 3210 if (done) 3211 fwohci_check_nodes(sc); 3212 3213 return 0; 3214 } 3215 3216 static void 3217 fwohci_check_nodes(struct fwohci_softc *sc) 3218 { 3219 struct device *detach = NULL; 3220 struct ieee1394_softc *iea; 3221 3222 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 3223 3224 /* 3225 * Have to defer detachment until the next 3226 * loop iteration since config_detach 3227 * free's the softc and the loop iterator 3228 * needs data from the softc to move 3229 * forward. 3230 */ 3231 3232 if (detach) { 3233 config_detach(detach, 0); 3234 detach = NULL; 3235 } 3236 if (iea->sc1394_node_id == 0xffff) { 3237 detach = (struct device *)iea; 3238 LIST_REMOVE(iea, sc1394_node); 3239 } 3240 } 3241 if (detach) 3242 config_detach(detach, 0); 3243 } 3244 3245 static int 3246 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 3247 { 3248 struct fwohci_uidtbl *fu; 3249 int n; 3250 static const u_int8_t bcast[] = 3251 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3252 3253 fu = sc->sc_uidtbl; 3254 if (fu == NULL) { 3255 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 3256 return IEEE1394_BCAST_PHY_ID; 3257 fwohci_uid_collect(sc); /* try to get */ 3258 return -1; 3259 } 3260 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 3261 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 3262 return n; 3263 } 3264 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 3265 return IEEE1394_BCAST_PHY_ID; 3266 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 3267 if (fu->fu_valid != 0x3) { 3268 /* 3269 * XXX: need timer before retransmission 3270 */ 3271 fwohci_uid_req(sc, n); 3272 } 3273 } 3274 return -1; 3275 } 3276 3277 /* 3278 * functions to support network interface 3279 */ 3280 static int 3281 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 3282 void (*handler)(struct device *, struct mbuf *)) 3283 { 3284 struct fwohci_softc *sc = (struct fwohci_softc *)self; 3285 3286 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 3287 handler ? fwohci_if_input : NULL, handler); 3288 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 3289 (sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & IEEE1394_ISOCH_MASK) | 3290 OHCI_ASYNC_STREAM, 3291 1 << IEEE1394_TAG_GASP, 3292 handler ? fwohci_if_input : NULL, handler); 3293 return 0; 3294 } 3295 3296 static int 3297 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3298 { 3299 int n, len; 3300 struct mbuf *m; 3301 struct iovec *iov; 3302 void (*handler)(struct device *, struct mbuf *) = arg; 3303 3304 #ifdef FW_DEBUG 3305 int i; 3306 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 3307 pkt->fp_dlen)); 3308 for (i = 0; i < pkt->fp_hlen/4; i++) 3309 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 3310 DPRINTFN(2, ("$")); 3311 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 3312 iov = &pkt->fp_iov[n]; 3313 for (i = 0; i < iov->iov_len; i++) 3314 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 3315 ((u_int8_t *)iov->iov_base)[i])); 3316 DPRINTFN(2, ("$")); 3317 } 3318 DPRINTFN(1, ("\n")); 3319 #endif /* FW_DEBUG */ 3320 len = pkt->fp_dlen; 3321 MGETHDR(m, M_DONTWAIT, MT_DATA); 3322 if (m == NULL) 3323 return IEEE1394_RCODE_COMPLETE; 3324 m->m_len = 16; 3325 if (len + m->m_len > MHLEN) { 3326 MCLGET(m, M_DONTWAIT); 3327 if ((m->m_flags & M_EXT) == 0) { 3328 m_freem(m); 3329 return IEEE1394_RCODE_COMPLETE; 3330 } 3331 } 3332 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 3333 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 3334 sc->sc_uidtbl[n].fu_valid != 0x3) { 3335 printf("%s: packet from unknown node: phy id %d\n", 3336 sc->sc_sc1394.sc1394_dev.dv_xname, n); 3337 m_freem(m); 3338 fwohci_uid_req(sc, n); 3339 return IEEE1394_RCODE_COMPLETE; 3340 } 3341 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 3342 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 3343 m->m_flags |= M_BCAST; 3344 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 3345 } else { 3346 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 3347 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 3348 } 3349 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 3350 mtod(m, u_int8_t *)[9] = 3351 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 3352 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 3353 3354 m->m_pkthdr.rcvif = NULL; /* set in child */ 3355 m->m_pkthdr.len = len + m->m_len; 3356 /* 3357 * We may use receive buffer by external mbuf instead of copy here. 3358 * But asynchronous receive buffer must be operate in buffer fill 3359 * mode, so that each receive buffer will shared by multiple mbufs. 3360 * If upper layer doesn't free mbuf soon, e.g. application program 3361 * is suspended, buffer must be reallocated. 3362 * Isochronous buffer must be operate in packet buffer mode, and 3363 * it is easy to map receive buffer to external mbuf. But it is 3364 * used for broadcast/multicast only, and is expected not so 3365 * performance sensitive for now. 3366 * XXX: The performance may be important for multicast case, 3367 * so we should revisit here later. 3368 * -- onoe 3369 */ 3370 n = 0; 3371 iov = pkt->fp_uio.uio_iov; 3372 while (len > 0) { 3373 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 3374 iov->iov_len); 3375 m->m_len += iov->iov_len; 3376 len -= iov->iov_len; 3377 iov++; 3378 } 3379 (*handler)(sc->sc_sc1394.sc1394_if, m); 3380 return IEEE1394_RCODE_COMPLETE; 3381 } 3382 3383 static int 3384 fwohci_if_input_iso(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3385 { 3386 int n, len; 3387 int chan, tag; 3388 struct mbuf *m; 3389 struct iovec *iov; 3390 void (*handler)(struct device *, struct mbuf *) = arg; 3391 #ifdef FW_DEBUG 3392 int i; 3393 #endif 3394 3395 chan = (pkt->fp_hdr[0] & 0x00003f00) >> 8; 3396 tag = (pkt->fp_hdr[0] & 0x0000c000) >> 14; 3397 #ifdef FW_DEBUG 3398 DPRINTFN(1, ("fwohci_if_input_iso: " 3399 "tcode=0x%x, chan=%d, tag=%x, dlen=%d", 3400 pkt->fp_tcode, chan, tag, pkt->fp_dlen)); 3401 for (i = 0; i < pkt->fp_hlen/4; i++) 3402 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 3403 DPRINTFN(2, ("$")); 3404 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 3405 iov = &pkt->fp_iov[n]; 3406 for (i = 0; i < iov->iov_len; i++) 3407 DPRINTFN(2, ("%s%02x", 3408 (i%32)?((i%4)?"":" "):"\n\t", 3409 ((u_int8_t *)iov->iov_base)[i])); 3410 DPRINTFN(2, ("$")); 3411 } 3412 DPRINTFN(2, ("\n")); 3413 #endif /* FW_DEBUG */ 3414 len = pkt->fp_dlen; 3415 MGETHDR(m, M_DONTWAIT, MT_DATA); 3416 if (m == NULL) 3417 return IEEE1394_RCODE_COMPLETE; 3418 m->m_len = 16; 3419 if (m->m_len + len > MHLEN) { 3420 MCLGET(m, M_DONTWAIT); 3421 if ((m->m_flags & M_EXT) == 0) { 3422 m_freem(m); 3423 return IEEE1394_RCODE_COMPLETE; 3424 } 3425 } 3426 3427 m->m_flags |= M_BCAST; 3428 3429 if (tag == IEEE1394_TAG_GASP) { 3430 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 3431 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 3432 sc->sc_uidtbl[n].fu_valid != 0x3) { 3433 printf("%s: packet from unknown node: phy id %d\n", 3434 sc->sc_sc1394.sc1394_dev.dv_xname, n); 3435 m_freem(m); 3436 return IEEE1394_RCODE_COMPLETE; 3437 } 3438 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 3439 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 3440 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 3441 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 3442 mtod(m, u_int8_t *)[9] = 3443 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 3444 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 3445 } 3446 mtod(m, u_int8_t *)[14] = chan; 3447 mtod(m, u_int8_t *)[15] = tag; 3448 3449 3450 m->m_pkthdr.rcvif = NULL; /* set in child */ 3451 m->m_pkthdr.len = len + m->m_len; 3452 /* 3453 * We may use receive buffer by external mbuf instead of copy here. 3454 * But asynchronous receive buffer must be operate in buffer fill 3455 * mode, so that each receive buffer will shared by multiple mbufs. 3456 * If upper layer doesn't free mbuf soon, e.g. application program 3457 * is suspended, buffer must be reallocated. 3458 * Isochronous buffer must be operate in packet buffer mode, and 3459 * it is easy to map receive buffer to external mbuf. But it is 3460 * used for broadcast/multicast only, and is expected not so 3461 * performance sensitive for now. 3462 * XXX: The performance may be important for multicast case, 3463 * so we should revisit here later. 3464 * -- onoe 3465 */ 3466 n = 0; 3467 iov = pkt->fp_uio.uio_iov; 3468 while (len > 0) { 3469 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 3470 iov->iov_len); 3471 m->m_len += iov->iov_len; 3472 len -= iov->iov_len; 3473 iov++; 3474 } 3475 (*handler)(sc->sc_sc1394.sc1394_if, m); 3476 return IEEE1394_RCODE_COMPLETE; 3477 } 3478 3479 3480 3481 static int 3482 fwohci_if_output(struct device *self, struct mbuf *m0, 3483 void (*callback)(struct device *, struct mbuf *)) 3484 { 3485 struct fwohci_softc *sc = (struct fwohci_softc *)self; 3486 struct fwohci_pkt pkt; 3487 u_int8_t *p; 3488 int n, error, spd, hdrlen, maxrec; 3489 #ifdef FW_DEBUG 3490 struct mbuf *m; 3491 #endif 3492 3493 p = mtod(m0, u_int8_t *); 3494 if (m0->m_flags & (M_BCAST | M_MCAST)) { 3495 spd = IEEE1394_SPD_S100; /*XXX*/ 3496 maxrec = 512; /*XXX*/ 3497 hdrlen = 8; 3498 } else { 3499 n = fwohci_uid_lookup(sc, p); 3500 if (n < 0) { 3501 printf("%s: nodeid unknown:" 3502 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 3503 sc->sc_sc1394.sc1394_dev.dv_xname, 3504 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 3505 error = EHOSTUNREACH; 3506 goto end; 3507 } 3508 if (n == IEEE1394_BCAST_PHY_ID) { 3509 printf("%s: broadcast with !M_MCAST\n", 3510 sc->sc_sc1394.sc1394_dev.dv_xname); 3511 #ifdef FW_DEBUG 3512 DPRINTFN(2, ("packet:")); 3513 for (m = m0; m != NULL; m = m->m_next) { 3514 for (n = 0; n < m->m_len; n++) 3515 DPRINTFN(2, ("%s%02x", (n%32)? 3516 ((n%4)?"":" "):"\n ", 3517 mtod(m, u_int8_t *)[n])); 3518 DPRINTFN(2, ("$")); 3519 } 3520 DPRINTFN(2, ("\n")); 3521 #endif 3522 error = EHOSTUNREACH; 3523 goto end; 3524 } 3525 maxrec = 2 << p[8]; 3526 spd = p[9]; 3527 hdrlen = 0; 3528 } 3529 if (spd > sc->sc_sc1394.sc1394_link_speed) { 3530 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 3531 spd, sc->sc_sc1394.sc1394_link_speed)); 3532 spd = sc->sc_sc1394.sc1394_link_speed; 3533 } 3534 if (maxrec > (512 << spd)) { 3535 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 3536 "\n", maxrec, spd)); 3537 maxrec = 512 << spd; 3538 } 3539 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 3540 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 3541 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 3542 maxrec >>= 1; 3543 } 3544 if (maxrec < 512) { 3545 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 3546 "minimum\n", maxrec)); 3547 maxrec = 512; 3548 } 3549 3550 m_adj(m0, 16 - hdrlen); 3551 if (m0->m_pkthdr.len > maxrec) { 3552 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 3553 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 3554 error = E2BIG; /*XXX*/ 3555 goto end; 3556 } 3557 3558 memset(&pkt, 0, sizeof(pkt)); 3559 pkt.fp_uio.uio_iov = pkt.fp_iov; 3560 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3561 pkt.fp_uio.uio_rw = UIO_WRITE; 3562 if (m0->m_flags & (M_BCAST | M_MCAST)) { 3563 /* construct GASP header */ 3564 p = mtod(m0, u_int8_t *); 3565 p[0] = sc->sc_nodeid >> 8; 3566 p[1] = sc->sc_nodeid & 0xff; 3567 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 3568 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 3569 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 3570 pkt.fp_hlen = 8; 3571 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 3572 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 3573 OHCI_NodeId_NodeNumber) << 8); 3574 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 3575 } else { 3576 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 3577 pkt.fp_hlen = 16; 3578 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 3579 (spd << 16); 3580 pkt.fp_hdr[1] = 3581 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 3582 (p[10] << 8) | p[11]; 3583 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 3584 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 3585 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3586 } 3587 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 3588 pkt.fp_dlen = m0->m_pkthdr.len; 3589 pkt.fp_m = m0; 3590 pkt.fp_callback = callback; 3591 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3592 m0 = pkt.fp_m; 3593 end: 3594 if (m0 != NULL) { 3595 if (callback) 3596 (*callback)(sc->sc_sc1394.sc1394_if, m0); 3597 else 3598 m_freem(m0); 3599 } 3600 return error; 3601 } 3602 3603 /* 3604 * High level routines to provide abstraction to attaching layers to 3605 * send/receive data. 3606 */ 3607 3608 /* 3609 * These break down into 4 routines as follows: 3610 * 3611 * int fwohci_read(struct ieee1394_abuf *) 3612 * 3613 * This routine will attempt to read a region from the requested node. 3614 * A callback must be provided which will be called when either the completed 3615 * read is done or an unrecoverable error occurs. This is mainly a convenience 3616 * routine since it will encapsulate retrying a region as quadlet vs. block 3617 * reads and recombining all the returned data. This could also be done with a 3618 * series of write/inreg's for each packet sent. 3619 * 3620 * int fwohci_write(struct ieee1394_abuf *) 3621 * 3622 * The work horse main entry point for putting packets on the bus. This is the 3623 * generalized interface for fwnode/etc code to put packets out onto the bus. 3624 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and 3625 * optionally will callback via a func pointer to the calling code with the 3626 * resulting ACK code from the packet. If the ACK code is to be ignored (i.e. 3627 * no cb) then the write routine will take care of free'ing the abuf since the 3628 * fwnode/etc code won't have any knowledge of when to do this. This allows for 3629 * simple one-off packets to be sent from the upper-level code without worrying 3630 * about a callback for cleanup. 3631 * 3632 * int fwohci_inreg(struct ieee1394_abuf *, int) 3633 * 3634 * This is very simple. It evals the abuf passed in and registers an internal 3635 * handler as the callback for packets received for that operation. 3636 * The integer argument specifies whether on a block read/write operation to 3637 * allow sub-regions to be read/written (in block form) as well. 3638 * 3639 * XXX: This whole structure needs to be redone as a list of regions and 3640 * operations allowed on those regions. 3641 * 3642 * int fwohci_unreg(struct ieee1394_abuf *, int) 3643 * 3644 * This simply unregisters the respective callback done via inreg for items 3645 * which only need to register an area for a one-time operation (like a status 3646 * buffer a remote node will write to when the current operation is done). The 3647 * int argument specifies the same behavior as inreg, except in reverse (i.e. 3648 * it unregisters). 3649 */ 3650 3651 static int 3652 fwohci_read(struct ieee1394_abuf *ab) 3653 { 3654 struct fwohci_pkt pkt; 3655 struct ieee1394_softc *sc = ab->ab_req; 3656 struct fwohci_softc *psc = 3657 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3658 struct fwohci_cb *fcb; 3659 u_int32_t high, lo; 3660 int rv, tcode; 3661 3662 /* Have to have a callback when reading. */ 3663 if (ab->ab_cb == NULL) 3664 return -1; 3665 3666 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 3667 fcb->ab = ab; 3668 fcb->count = 0; 3669 fcb->abuf_valid = 1; 3670 3671 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3672 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3673 3674 memset(&pkt, 0, sizeof(pkt)); 3675 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3676 pkt.fp_hdr[2] = lo; 3677 pkt.fp_dlen = 0; 3678 3679 if (ab->ab_length == 4) { 3680 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3681 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 3682 pkt.fp_hlen = 12; 3683 } else { 3684 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 3685 pkt.fp_hlen = 16; 3686 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 3687 pkt.fp_hdr[3] = (ab->ab_length << 16); 3688 } 3689 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3690 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3691 3692 pkt.fp_statusarg = fcb; 3693 pkt.fp_statuscb = fwohci_read_resp; 3694 3695 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3696 psc->sc_tlabel, fwohci_read_resp, fcb); 3697 if (rv) 3698 return rv; 3699 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3700 if (rv) 3701 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3702 psc->sc_tlabel, NULL, NULL); 3703 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3704 fcb->count = 1; 3705 return rv; 3706 } 3707 3708 static int 3709 fwohci_write(struct ieee1394_abuf *ab) 3710 { 3711 struct fwohci_pkt pkt; 3712 struct ieee1394_softc *sc = ab->ab_req; 3713 struct fwohci_softc *psc = 3714 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3715 u_int32_t high, lo; 3716 int rv; 3717 3718 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_BLOCK) { 3719 if (ab->ab_length > IEEE1394_MAX_REC(sc->sc1394_max_receive)) { 3720 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 3721 return E2BIG; 3722 } 3723 } 3724 3725 if (ab->ab_length > 3726 IEEE1394_MAX_ASYNCH_FOR_SPEED(sc->sc1394_link_speed)) { 3727 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 3728 return E2BIG; 3729 } 3730 3731 if (ab->ab_data && ab->ab_uio) 3732 panic("Can't call with uio and data set"); 3733 if ((ab->ab_data == NULL) && (ab->ab_uio == NULL)) 3734 panic("One of either ab_data or ab_uio must be set"); 3735 3736 memset(&pkt, 0, sizeof(pkt)); 3737 3738 pkt.fp_tcode = ab->ab_tcode; 3739 if (ab->ab_data) { 3740 pkt.fp_uio.uio_iov = pkt.fp_iov; 3741 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3742 pkt.fp_uio.uio_rw = UIO_WRITE; 3743 } else 3744 memcpy(&pkt.fp_uio, ab->ab_uio, sizeof(struct uio)); 3745 3746 pkt.fp_statusarg = ab; 3747 pkt.fp_statuscb = fwohci_write_ack; 3748 3749 switch (ab->ab_tcode) { 3750 case IEEE1394_TCODE_WRITE_RESP: 3751 pkt.fp_hlen = 12; 3752 case IEEE1394_TCODE_READ_RESP_QUAD: 3753 case IEEE1394_TCODE_READ_RESP_BLOCK: 3754 if (!pkt.fp_hlen) 3755 pkt.fp_hlen = 16; 3756 high = ab->ab_retlen; 3757 ab->ab_retlen = 0; 3758 lo = 0; 3759 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3760 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 3761 break; 3762 default: 3763 pkt.fp_hlen = 16; 3764 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3765 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3766 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3767 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3768 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3769 break; 3770 } 3771 3772 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3773 pkt.fp_hdr[2] = lo; 3774 if (pkt.fp_hlen == 16) { 3775 if (ab->ab_length == 4) { 3776 pkt.fp_hdr[3] = ab->ab_data[0]; 3777 pkt.fp_dlen = 0; 3778 } else { 3779 pkt.fp_hdr[3] = (ab->ab_length << 16); 3780 pkt.fp_dlen = ab->ab_length; 3781 if (ab->ab_data) { 3782 pkt.fp_uio.uio_iovcnt = 1; 3783 pkt.fp_uio.uio_resid = ab->ab_length; 3784 pkt.fp_iov[0].iov_base = ab->ab_data; 3785 pkt.fp_iov[0].iov_len = ab->ab_length; 3786 } 3787 } 3788 } 3789 switch (ab->ab_tcode) { 3790 case IEEE1394_TCODE_WRITE_RESP: 3791 case IEEE1394_TCODE_READ_RESP_QUAD: 3792 case IEEE1394_TCODE_READ_RESP_BLOCK: 3793 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 3794 break; 3795 default: 3796 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3797 break; 3798 } 3799 return rv; 3800 } 3801 3802 static int 3803 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3804 { 3805 struct fwohci_cb *fcb = arg; 3806 struct ieee1394_abuf *ab = fcb->ab; 3807 struct fwohci_pkt newpkt; 3808 u_int32_t *cur, high, lo; 3809 int i, tcode, rcode, status, rv; 3810 3811 /* 3812 * Both the ACK handling and normal response callbacks are handled here. 3813 * The main reason for this is the various error conditions that can 3814 * occur trying to block read some areas and the ways that gets reported 3815 * back to calling station. This is a variety of ACK codes, responses, 3816 * etc which makes it much more difficult to process if both aren't 3817 * handled here. 3818 */ 3819 3820 /* Check for status packet. */ 3821 3822 if (pkt->fp_tcode == -1) { 3823 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3824 rcode = -1; 3825 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3826 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3827 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3828 DPRINTFN(2, ("Got status packet: 0x%02x\n", 3829 (unsigned int)status)); 3830 fcb->count--; 3831 3832 /* 3833 * Got all the ack's back and the buffer is invalid (i.e. the 3834 * callback has been called. Clean up. 3835 */ 3836 3837 if (fcb->abuf_valid == 0) { 3838 if (fcb->count == 0) 3839 free(fcb, M_DEVBUF); 3840 return IEEE1394_RCODE_COMPLETE; 3841 } 3842 } else { 3843 status = -1; 3844 tcode = pkt->fp_tcode; 3845 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3846 } 3847 3848 /* 3849 * Some area's (like the config rom want to be read as quadlets only. 3850 * 3851 * The current ideas to try are: 3852 * 3853 * Got an ACK_TYPE_ERROR on a block read. 3854 * 3855 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 3856 * response. 3857 * 3858 * In all cases construct a new packet for a quadlet read and let 3859 * mutli_resp handle the iteration over the space. 3860 */ 3861 3862 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 3863 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 3864 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 3865 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 3866 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 3867 3868 /* Read the area in quadlet chunks (internally track this). */ 3869 3870 memset(&newpkt, 0, sizeof(newpkt)); 3871 3872 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3873 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3874 3875 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3876 newpkt.fp_hlen = 12; 3877 newpkt.fp_dlen = 0; 3878 newpkt.fp_hdr[1] = 3879 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3880 newpkt.fp_hdr[2] = lo; 3881 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3882 (newpkt.fp_tcode << 4); 3883 3884 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3885 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 3886 fwohci_read_multi_resp, fcb); 3887 if (rv) { 3888 (*ab->ab_cb)(ab, -1); 3889 goto cleanup; 3890 } 3891 newpkt.fp_statusarg = fcb; 3892 newpkt.fp_statuscb = fwohci_read_resp; 3893 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3894 if (rv) { 3895 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3896 ab->ab_req->sc1394_node_id, sc->sc_tlabel, NULL, 3897 NULL); 3898 (*ab->ab_cb)(ab, -1); 3899 goto cleanup; 3900 } 3901 fcb->count++; 3902 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3903 return IEEE1394_RCODE_COMPLETE; 3904 } else if ((rcode != -1) || ((status != -1) && 3905 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3906 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3907 3908 /* 3909 * Recombine all the iov data into 1 chunk for higher 3910 * level code. 3911 */ 3912 3913 if (rcode != -1) { 3914 cur = ab->ab_data; 3915 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3916 /* 3917 * Make sure and don't exceed the buffer 3918 * allocated for return. 3919 */ 3920 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3921 ab->ab_length) { 3922 memcpy(cur, pkt->fp_iov[i].iov_base, 3923 (ab->ab_length - ab->ab_retlen)); 3924 ab->ab_retlen = ab->ab_length; 3925 break; 3926 } 3927 memcpy(cur, pkt->fp_iov[i].iov_base, 3928 pkt->fp_iov[i].iov_len); 3929 cur += pkt->fp_iov[i].iov_len; 3930 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3931 } 3932 } 3933 if (status != -1) 3934 /* XXX: Need a complete tlabel interface. */ 3935 for (i = 0; i < 64; i++) 3936 fwohci_handler_set(sc, 3937 IEEE1394_TCODE_READ_RESP_QUAD, 3938 ab->ab_req->sc1394_node_id, i, NULL, NULL); 3939 (*ab->ab_cb)(ab, rcode); 3940 goto cleanup; 3941 } else 3942 /* Good ack packet. */ 3943 return IEEE1394_RCODE_COMPLETE; 3944 3945 /* Can't get here unless ab->ab_cb has been called. */ 3946 3947 cleanup: 3948 fcb->abuf_valid = 0; 3949 if (fcb->count == 0) 3950 free(fcb, M_DEVBUF); 3951 return IEEE1394_RCODE_COMPLETE; 3952 } 3953 3954 static int 3955 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 3956 struct fwohci_pkt *pkt) 3957 { 3958 struct fwohci_cb *fcb = arg; 3959 struct ieee1394_abuf *ab = fcb->ab; 3960 struct fwohci_pkt newpkt; 3961 u_int32_t high, lo; 3962 int rcode, rv; 3963 3964 /* 3965 * Bad return codes from the wire, just return what's already in the 3966 * buf. 3967 */ 3968 3969 /* Make sure a response packet didn't arrive after a bad ACK. */ 3970 if (fcb->abuf_valid == 0) 3971 return IEEE1394_RCODE_COMPLETE; 3972 3973 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3974 3975 if (rcode) { 3976 (*ab->ab_cb)(ab, rcode); 3977 goto cleanup; 3978 } 3979 3980 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 3981 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3982 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 3983 ab->ab_retlen = ab->ab_length; 3984 } else { 3985 memcpy(((char *)ab->ab_data + ab->ab_retlen), 3986 pkt->fp_iov[0].iov_base, 4); 3987 ab->ab_retlen += 4; 3988 } 3989 /* Still more, loop and read 4 more bytes. */ 3990 if (ab->ab_retlen < ab->ab_length) { 3991 memset(&newpkt, 0, sizeof(newpkt)); 3992 3993 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3994 lo = (ab->ab_addr & 0x00000000ffffffffULL) + ab->ab_retlen; 3995 3996 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3997 newpkt.fp_hlen = 12; 3998 newpkt.fp_dlen = 0; 3999 newpkt.fp_hdr[1] = 4000 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 4001 newpkt.fp_hdr[2] = lo; 4002 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 4003 (newpkt.fp_tcode << 4); 4004 4005 newpkt.fp_statusarg = fcb; 4006 newpkt.fp_statuscb = fwohci_read_resp; 4007 4008 /* 4009 * Bad return code. Just give up and return what's 4010 * come in now. 4011 */ 4012 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 4013 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 4014 fwohci_read_multi_resp, fcb); 4015 if (rv) 4016 (*ab->ab_cb)(ab, -1); 4017 else { 4018 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 4019 if (rv) { 4020 fwohci_handler_set(sc, 4021 IEEE1394_TCODE_READ_RESP_QUAD, 4022 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 4023 NULL, NULL); 4024 (*ab->ab_cb)(ab, -1); 4025 } else { 4026 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 4027 fcb->count++; 4028 return IEEE1394_RCODE_COMPLETE; 4029 } 4030 } 4031 } else 4032 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 4033 4034 cleanup: 4035 /* Can't get here unless ab_cb has been called. */ 4036 fcb->abuf_valid = 0; 4037 if (fcb->count == 0) 4038 free(fcb, M_DEVBUF); 4039 return IEEE1394_RCODE_COMPLETE; 4040 } 4041 4042 static int 4043 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 4044 { 4045 struct ieee1394_abuf *ab = arg; 4046 u_int16_t status; 4047 4048 4049 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 4050 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 4051 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 4052 DPRINTF(("Got status packet: 0x%02x\n", 4053 (unsigned int)status)); 4054 4055 /* No callback means this level should free the buffers. */ 4056 if (ab->ab_cb) 4057 (*ab->ab_cb)(ab, status); 4058 else { 4059 if (ab->ab_data) 4060 free(ab->ab_data, M_1394DATA); 4061 free(ab, M_1394DATA); 4062 } 4063 return IEEE1394_RCODE_COMPLETE; 4064 } 4065 4066 static int 4067 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 4068 { 4069 struct ieee1394_softc *sc = ab->ab_req; 4070 struct fwohci_softc *psc = 4071 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 4072 u_int32_t high, lo; 4073 int i, j, rv; 4074 4075 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 4076 lo = (ab->ab_addr & 0x00000000ffffffffULL); 4077 4078 rv = 0; 4079 switch (ab->ab_tcode) { 4080 case IEEE1394_TCODE_READ_REQ_QUAD: 4081 case IEEE1394_TCODE_WRITE_REQ_QUAD: 4082 if (ab->ab_cb) 4083 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 4084 fwohci_parse_input, ab); 4085 else 4086 fwohci_handler_set(psc, ab->ab_tcode, high, lo, NULL, 4087 NULL); 4088 break; 4089 case IEEE1394_TCODE_READ_REQ_BLOCK: 4090 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 4091 if (allow) { 4092 for (i = 0; i < (ab->ab_length / 4); i++) { 4093 if (ab->ab_cb) { 4094 rv = fwohci_handler_set(psc, 4095 ab->ab_tcode, high, lo + (i * 4), 4096 fwohci_parse_input, ab); 4097 if (rv) 4098 break; 4099 } else 4100 fwohci_handler_set(psc, ab->ab_tcode, 4101 high, lo + (i * 4), NULL, NULL); 4102 } 4103 if (i != (ab->ab_length / 4)) { 4104 j = i + 1; 4105 for (i = 0; i < j; i++) 4106 fwohci_handler_set(psc, ab->ab_tcode, 4107 high, lo + (i * 4), NULL, NULL); 4108 } 4109 4110 /* 4111 * XXX: Need something to indicate writing a smaller 4112 * amount is ok. 4113 */ 4114 if (ab->ab_cb) 4115 ab->ab_subok = 1; 4116 } else { 4117 if (ab->ab_cb) 4118 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 4119 lo, fwohci_parse_input, ab); 4120 else 4121 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 4122 NULL, NULL); 4123 } 4124 break; 4125 default: 4126 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 4127 return -1; 4128 break; 4129 } 4130 return rv; 4131 } 4132 4133 static int 4134 fwohci_unreg(struct ieee1394_abuf *ab, int allow) 4135 { 4136 void *save; 4137 int rv; 4138 4139 save = ab->ab_cb; 4140 ab->ab_cb = NULL; 4141 rv = fwohci_inreg(ab, allow); 4142 ab->ab_cb = save; 4143 return rv; 4144 } 4145 4146 static int 4147 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 4148 { 4149 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 4150 u_int64_t addr; 4151 u_int8_t *cur; 4152 int i, count, ret; 4153 4154 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 4155 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 4156 addr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 4157 4158 /* Make sure it's always 0 in case this gets reused multiple times. */ 4159 ab->ab_retlen = 0; 4160 4161 switch (ab->ab_tcode) { 4162 case IEEE1394_TCODE_READ_REQ_QUAD: 4163 ab->ab_retlen = 4; 4164 /* Response's (if required) will come from callback code */ 4165 ret = -1; 4166 break; 4167 case IEEE1394_TCODE_READ_REQ_BLOCK: 4168 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 4169 if (ab->ab_subok) { 4170 if ((addr + ab->ab_retlen) > 4171 (ab->ab_addr + ab->ab_length)) 4172 return IEEE1394_RCODE_ADDRESS_ERROR; 4173 } else 4174 if (ab->ab_retlen != ab->ab_length) 4175 return IEEE1394_RCODE_ADDRESS_ERROR; 4176 /* Response's (if required) will come from callback code */ 4177 ret = -1; 4178 break; 4179 case IEEE1394_TCODE_WRITE_REQ_QUAD: 4180 ab->ab_retlen = 4; 4181 /* Fall through. */ 4182 4183 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 4184 if (!ab->ab_retlen) 4185 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 4186 if (ab->ab_subok) { 4187 if ((addr + ab->ab_retlen) > 4188 (ab->ab_addr + ab->ab_length)) 4189 return IEEE1394_RCODE_ADDRESS_ERROR; 4190 } else 4191 if (ab->ab_retlen != ab->ab_length) 4192 return IEEE1394_RCODE_ADDRESS_ERROR; 4193 4194 ab->ab_data = malloc(ab->ab_retlen, M_1394DATA, M_WAITOK); 4195 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 4196 ab->ab_data[0] = pkt->fp_hdr[3]; 4197 else { 4198 count = 0; 4199 cur = (u_int8_t *)ab->ab_data; 4200 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 4201 memcpy(cur, pkt->fp_iov[i].iov_base, 4202 pkt->fp_iov[i].iov_len); 4203 cur += pkt->fp_iov[i].iov_len; 4204 count += pkt->fp_iov[i].iov_len; 4205 } 4206 if (ab->ab_retlen != count) 4207 panic("Packet claims %d length " 4208 "but only %d bytes returned\n", 4209 ab->ab_retlen, count); 4210 } 4211 ret = IEEE1394_RCODE_COMPLETE; 4212 break; 4213 default: 4214 panic("Got a callback for a tcode that wasn't requested: %d", 4215 ab->ab_tcode); 4216 break; 4217 } 4218 ab->ab_addr = addr; 4219 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 4220 return ret; 4221 } 4222 4223 static int 4224 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 4225 { 4226 struct ieee1394_attach_args *fwa = aux; 4227 4228 /* Both halves must be filled in for a match. */ 4229 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 4230 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 4231 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 4232 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 4233 return (config_match(parent, cf, aux)); 4234 return 0; 4235 } 4236 4237 int 4238 fwohci_detach(struct fwohci_softc *sc, int flags) 4239 { 4240 int rv = 0; 4241 4242 if (sc->sc_sc1394.sc1394_if != NULL) 4243 rv = config_detach(sc->sc_sc1394.sc1394_if, flags); 4244 if (rv != 0) 4245 return (rv); 4246 4247 callout_stop(&sc->sc_selfid_callout); 4248 4249 if (sc->sc_powerhook != NULL) 4250 powerhook_disestablish(sc->sc_powerhook); 4251 if (sc->sc_shutdownhook != NULL) 4252 shutdownhook_disestablish(sc->sc_shutdownhook); 4253 4254 return (rv); 4255 } 4256 4257 int 4258 fwohci_activate(struct device *self, enum devact act) 4259 { 4260 struct fwohci_softc *sc = (struct fwohci_softc *)self; 4261 int s, rv = 0; 4262 4263 s = splhigh(); 4264 switch (act) { 4265 case DVACT_ACTIVATE: 4266 rv = EOPNOTSUPP; 4267 break; 4268 4269 case DVACT_DEACTIVATE: 4270 if (sc->sc_sc1394.sc1394_if != NULL) 4271 rv = config_deactivate(sc->sc_sc1394.sc1394_if); 4272 break; 4273 } 4274 splx(s); 4275 4276 return (rv); 4277 } 4278 4279 #ifdef FW_DEBUG 4280 static void 4281 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 4282 { 4283 4284 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 4285 intmask); 4286 if (intmask & OHCI_Int_CycleTooLong) 4287 printf(" CycleTooLong"); 4288 if (intmask & OHCI_Int_UnrecoverableError) 4289 printf(" UnrecoverableError"); 4290 if (intmask & OHCI_Int_CycleInconsistent) 4291 printf(" CycleInconsistent"); 4292 if (intmask & OHCI_Int_BusReset) 4293 printf(" BusReset"); 4294 if (intmask & OHCI_Int_SelfIDComplete) 4295 printf(" SelfIDComplete"); 4296 if (intmask & OHCI_Int_LockRespErr) 4297 printf(" LockRespErr"); 4298 if (intmask & OHCI_Int_PostedWriteErr) 4299 printf(" PostedWriteErr"); 4300 if (intmask & OHCI_Int_ReqTxComplete) 4301 printf(" ReqTxComplete(0x%04x)", 4302 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 4303 OHCI_SUBREG_ContextControlClear)); 4304 if (intmask & OHCI_Int_RespTxComplete) 4305 printf(" RespTxComplete(0x%04x)", 4306 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 4307 OHCI_SUBREG_ContextControlClear)); 4308 if (intmask & OHCI_Int_ARRS) 4309 printf(" ARRS(0x%04x)", 4310 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 4311 OHCI_SUBREG_ContextControlClear)); 4312 if (intmask & OHCI_Int_ARRQ) 4313 printf(" ARRQ(0x%04x)", 4314 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 4315 OHCI_SUBREG_ContextControlClear)); 4316 if (intmask & OHCI_Int_IsochRx) 4317 printf(" IsochRx(0x%08x)", 4318 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 4319 if (intmask & OHCI_Int_IsochTx) 4320 printf(" IsochTx(0x%08x)", 4321 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 4322 if (intmask & OHCI_Int_RQPkt) 4323 printf(" RQPkt(0x%04x)", 4324 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 4325 OHCI_SUBREG_ContextControlClear)); 4326 if (intmask & OHCI_Int_RSPkt) 4327 printf(" RSPkt(0x%04x)", 4328 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 4329 OHCI_SUBREG_ContextControlClear)); 4330 printf("\n"); 4331 } 4332 4333 static void 4334 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 4335 { 4336 u_int8_t key, phyid; 4337 4338 key = (val & 0xc0000000) >> 30; 4339 phyid = (val & 0x3f000000) >> 24; 4340 printf("%s: PHY packet from %d: ", 4341 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 4342 switch (key) { 4343 case 0: 4344 printf("PHY Config:"); 4345 if (val & 0x00800000) 4346 printf(" ForceRoot"); 4347 if (val & 0x00400000) 4348 printf(" Gap=%x", (val & 0x003f0000) >> 16); 4349 printf("\n"); 4350 break; 4351 case 1: 4352 printf("Link-on\n"); 4353 break; 4354 case 2: 4355 printf("SelfID:"); 4356 if (val & 0x00800000) { 4357 printf(" #%d", (val & 0x00700000) >> 20); 4358 } else { 4359 if (val & 0x00400000) 4360 printf(" LinkActive"); 4361 printf(" Gap=%x", (val & 0x003f0000) >> 16); 4362 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 4363 if (val & 0x00000800) 4364 printf(" Cont"); 4365 if (val & 0x00000002) 4366 printf(" InitiateBusReset"); 4367 } 4368 if (val & 0x00000001) 4369 printf(" +"); 4370 printf("\n"); 4371 break; 4372 default: 4373 printf("unknown: 0x%08x\n", val); 4374 break; 4375 } 4376 } 4377 #endif /* FW_DEBUG */ 4378 4379 #if 0 4380 void fwohci_dumpreg(struct ieee1394_softc *, struct fwiso_regdump *); 4381 4382 void 4383 fwohci_dumpreg(struct ieee1394_softc *isc, struct fwiso_regdump *fr) 4384 { 4385 struct fwohci_softc *sc = (struct fwohci_softc *)isc; 4386 #if 0 4387 u_int32_t val; 4388 4389 printf("%s: dump reg\n", isc->sc1394_dev.dv_xname); 4390 printf("\tNodeID reg 0x%08x\n", 4391 OHCI_CSR_READ(sc, OHCI_REG_NodeId)); 4392 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 4393 printf("\tIsoCounter 0x%08x, %d %d %d", val, 4394 (val >> 25) & 0xfe, (val >> 12) & 0x1fff, val & 0xfff); 4395 val = OHCI_CSR_READ(sc, OHCI_REG_IntMaskSet); 4396 printf(" IntMask 0x%08x, %s\n", val, 4397 val & OHCI_Int_IsochTx ? "isoTx" : ""); 4398 4399 val = OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_ContextControlSet); 4400 printf("\tIT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 4401 OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_CommandPtr), 4402 val, 4403 val & OHCI_CTXCTL_RUN ? " run" : "", 4404 val & OHCI_CTXCTL_WAKE ? " wake" : "", 4405 val & OHCI_CTXCTL_DEAD ? " dead" : "", 4406 val & OHCI_CTXCTL_ACTIVE ? " active" : ""); 4407 #endif 4408 4409 fr->fr_nodeid = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 4410 fr->fr_isocounter = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 4411 fr->fr_intmask = OHCI_CSR_READ(sc, OHCI_REG_IntMaskSet); 4412 fr->fr_it0_commandptr = OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_CommandPtr); 4413 fr->fr_it0_contextctrl = OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_ContextControlSet); 4414 4415 4416 } 4417 #endif 4418 4419 4420 u_int16_t 4421 fwohci_cycletimer(struct fwohci_softc *sc) 4422 { 4423 u_int32_t reg; 4424 4425 reg = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 4426 4427 return (reg >> 12)&0xffff; 4428 } 4429 4430 4431 u_int16_t 4432 fwohci_it_cycletimer(ieee1394_it_tag_t it) 4433 { 4434 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 4435 4436 return fwohci_cycletimer(itc->itc_sc); 4437 } 4438 4439 4440 4441 4442 4443 /* 4444 * return value: if positive value, number of DMA buffer segments. If 4445 * negative value, error happens. Never zero. 4446 */ 4447 static int 4448 fwohci_misc_dmabuf_alloc(bus_dma_tag_t dmat, int dsize, int segno, 4449 bus_dma_segment_t *segp, bus_dmamap_t *dmapp, void **mapp, 4450 const char *xname) 4451 { 4452 int nsegs; 4453 int error; 4454 4455 printf("fwohci_misc_desc_alloc: dsize %d segno %d\n", dsize, segno); 4456 4457 if ((error = bus_dmamem_alloc(dmat, dsize, PAGE_SIZE, 0, 4458 segp, segno, &nsegs, 0)) != 0) { 4459 printf("%s: unable to allocate descriptor buffer, error = %d\n", 4460 xname, error); 4461 goto fail_0; 4462 } 4463 4464 DPRINTF(("fwohci_misc_desc_alloc: %d segment[s]\n", nsegs)); 4465 4466 if ((error = bus_dmamem_map(dmat, segp, nsegs, dsize, (caddr_t *)mapp, 4467 BUS_DMA_COHERENT | BUS_DMA_WAITOK)) != 0) { 4468 printf("%s: unable to map descriptor buffer, error = %d\n", 4469 xname, error); 4470 goto fail_1; 4471 } 4472 4473 DPRINTF(("fwohci_misc_desc_alloc: %s map ok\n", xname)); 4474 4475 #ifdef FWOHCI_DEBUG 4476 { 4477 int loop; 4478 4479 for (loop = 0; loop < nsegs; ++loop) { 4480 printf("\t%.2d: 0x%lx - 0x%lx\n", loop, 4481 (long)segp[loop].ds_addr, 4482 (long)segp[loop].ds_addr + segp[loop].ds_len - 1); 4483 } 4484 } 4485 #endif /* FWOHCI_DEBUG */ 4486 4487 if ((error = bus_dmamap_create(dmat, dsize, nsegs, dsize, 4488 0, BUS_DMA_WAITOK, dmapp)) != 0) { 4489 printf("%s: unable to create descriptor buffer DMA map, " 4490 "error = %d\n", xname, error); 4491 goto fail_2; 4492 } 4493 4494 DPRINTF(("fwohci_misc_dmabuf_alloc: bus_dmamem_create success\n")); 4495 4496 if ((error = bus_dmamap_load(dmat, *dmapp, *mapp, dsize, NULL, 4497 BUS_DMA_WAITOK)) != 0) { 4498 printf("%s: unable to load descriptor buffer DMA map, " 4499 "error = %d\n", xname, error); 4500 goto fail_3; 4501 } 4502 4503 DPRINTF(("fwohci_it_desc_alloc: bus_dmamem_load success\n")); 4504 4505 return nsegs; 4506 4507 fail_3: 4508 bus_dmamap_destroy(dmat, *dmapp); 4509 fail_2: 4510 bus_dmamem_unmap(dmat, *mapp, dsize); 4511 fail_1: 4512 bus_dmamem_free(dmat, segp, nsegs); 4513 fail_0: 4514 return error; 4515 } 4516 4517 4518 static void 4519 fwohci_misc_dmabuf_free(bus_dma_tag_t dmat, int dsize, int nsegs, 4520 bus_dma_segment_t *segp, bus_dmamap_t *dmapp, caddr_t map) 4521 { 4522 bus_dmamap_destroy(dmat, *dmapp); 4523 bus_dmamem_unmap(dmat, map, dsize); 4524 bus_dmamem_free(dmat, segp, nsegs); 4525 } 4526 4527 4528 4529 4530 /* 4531 * Isochronous receive service 4532 */ 4533 4534 /* 4535 * static struct fwohci_ir_ctx * 4536 * fwohci_ir_ctx_construct(struct fwohci_softc *sc, int no, int ch, int tagbm, 4537 * int bufnum, int maxsize, int flags) 4538 */ 4539 static struct fwohci_ir_ctx * 4540 fwohci_ir_ctx_construct(struct fwohci_softc *sc, int no, int ch, int tagbm, 4541 int bufnum, int maxsize, int flags) 4542 { 4543 struct fwohci_ir_ctx *irc; 4544 int i; 4545 4546 printf("fwohci_ir_construct(%s, %d, %d, %x, %d, %d\n", 4547 sc->sc_sc1394.sc1394_dev.dv_xname, no, ch, tagbm, bufnum, maxsize); 4548 4549 if ((irc = malloc(sizeof(*irc), M_DEVBUF, M_WAITOK|M_ZERO)) == NULL) { 4550 return NULL; 4551 } 4552 4553 irc->irc_sc = sc; 4554 4555 irc->irc_num = no; 4556 irc->irc_status = 0; 4557 4558 irc->irc_channel = ch; 4559 irc->irc_tagbm = tagbm; 4560 4561 irc->irc_desc_num = bufnum; 4562 4563 irc->irc_flags = flags; 4564 4565 /* add header */ 4566 maxsize += 8; 4567 /* rounding up */ 4568 for (i = 32; i < maxsize; i <<= 1); 4569 printf("fwohci_ir_ctx_construct: maxsize %d => %d\n", 4570 maxsize, i); 4571 4572 maxsize = i; 4573 4574 irc->irc_maxsize = maxsize; 4575 irc->irc_buf_totalsize = bufnum * maxsize; 4576 4577 if (fwohci_ir_buf_setup(irc)) { 4578 /* cannot alloc descriptor */ 4579 return NULL; 4580 } 4581 4582 irc->irc_readtop = irc->irc_desc_map; 4583 irc->irc_writeend = irc->irc_desc_map + irc->irc_desc_num - 1; 4584 irc->irc_savedbranch = irc->irc_writeend->fd_branch; 4585 irc->irc_writeend->fd_branch = 0; 4586 /* sync */ 4587 4588 if (fwohci_ir_stop(irc) || fwohci_ir_init(irc)) { 4589 return NULL; 4590 } 4591 4592 irc->irc_status |= IRC_STATUS_READY; 4593 4594 return irc; 4595 } 4596 4597 4598 4599 /* 4600 * static void fwohci_ir_ctx_destruct(struct fwohci_ir_ctx *irc) 4601 * 4602 * This function release all DMA buffers and itself. 4603 */ 4604 static void 4605 fwohci_ir_ctx_destruct(struct fwohci_ir_ctx *irc) 4606 { 4607 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, irc->irc_buf_totalsize, 4608 irc->irc_buf_nsegs, irc->irc_buf_segs, 4609 &irc->irc_buf_dmamap, (caddr_t)irc->irc_buf); 4610 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4611 irc->irc_desc_size, 4612 irc->irc_desc_nsegs, &irc->irc_desc_seg, 4613 &irc->irc_desc_dmamap, (caddr_t)irc->irc_desc_map); 4614 4615 free(irc, M_DEVBUF); 4616 } 4617 4618 4619 4620 4621 /* 4622 * static int fwohci_ir_buf_setup(struct fwohci_ir_ctx *irc) 4623 * 4624 * Allocates descriptors for context DMA dedicated for 4625 * isochronous receive. 4626 * 4627 * This function returns 0 (zero) if it succeeds. Otherwise, 4628 * return negative value. 4629 */ 4630 static int 4631 fwohci_ir_buf_setup(struct fwohci_ir_ctx *irc) 4632 { 4633 int nsegs; 4634 struct fwohci_desc *fd; 4635 u_int32_t branch; 4636 int bufno = 0; /* DMA segment */ 4637 bus_size_t bufused = 0; /* offset in a DMA segment */ 4638 4639 irc->irc_desc_size = irc->irc_desc_num * sizeof(struct fwohci_desc); 4640 4641 nsegs = fwohci_misc_dmabuf_alloc(irc->irc_sc->sc_dmat, 4642 irc->irc_desc_size, 1, &irc->irc_desc_seg, &irc->irc_desc_dmamap, 4643 (void **)&irc->irc_desc_map, 4644 irc->irc_sc->sc_sc1394.sc1394_dev.dv_xname); 4645 4646 if (nsegs < 0) { 4647 printf("fwohci_ir_buf_alloc: cannot get descriptor\n"); 4648 return -1; 4649 } 4650 irc->irc_desc_nsegs = nsegs; 4651 4652 nsegs = fwohci_misc_dmabuf_alloc(irc->irc_sc->sc_dmat, 4653 irc->irc_buf_totalsize, 16, irc->irc_buf_segs, 4654 &irc->irc_buf_dmamap, (void **)&irc->irc_buf, 4655 irc->irc_sc->sc_sc1394.sc1394_dev.dv_xname); 4656 4657 if (nsegs < 0) { 4658 printf("fwohci_ir_buf_alloc: cannot get DMA buffer\n"); 4659 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4660 irc->irc_desc_size, 4661 irc->irc_desc_nsegs, &irc->irc_desc_seg, 4662 &irc->irc_desc_dmamap, (caddr_t)irc->irc_desc_map); 4663 return -1; 4664 } 4665 irc->irc_buf_nsegs = nsegs; 4666 4667 branch = irc->irc_desc_dmamap->dm_segs[0].ds_addr 4668 + sizeof(struct fwohci_desc); 4669 bufno = 0; 4670 bufused = 0; 4671 4672 for (fd = irc->irc_desc_map; 4673 fd < irc->irc_desc_map + irc->irc_desc_num; ++fd) { 4674 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_LAST 4675 | OHCI_DESC_STATUS | OHCI_DESC_BRANCH; 4676 if (irc->irc_flags & IEEE1394_IR_SHORTDELAY) { 4677 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 4678 } 4679 #if 0 4680 if ((fd - irc->irc_desc_map) % 64 == 0) { 4681 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 4682 } 4683 #endif 4684 fd->fd_reqcount = irc->irc_maxsize; 4685 fd->fd_status = fd->fd_rescount = 0; 4686 4687 fd->fd_branch = branch | 0x01; 4688 branch += sizeof(struct fwohci_desc); 4689 4690 /* physical addr to data? */ 4691 fd->fd_data = 4692 (u_int32_t)((irc->irc_buf_segs[bufno].ds_addr + bufused)); 4693 bufused += irc->irc_maxsize; 4694 if (bufused > irc->irc_buf_segs[bufno].ds_len) { 4695 bufused = 0; 4696 if (++bufno == irc->irc_buf_nsegs) { 4697 /* fail */ 4698 printf("fwohci_ir_buf_setup fail\n"); 4699 4700 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4701 irc->irc_desc_size, 4702 irc->irc_desc_nsegs, &irc->irc_desc_seg, 4703 &irc->irc_desc_dmamap, 4704 (caddr_t)irc->irc_desc_map); 4705 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4706 irc->irc_buf_totalsize, 4707 irc->irc_buf_nsegs, irc->irc_buf_segs, 4708 &irc->irc_buf_dmamap, 4709 (caddr_t)irc->irc_buf); 4710 return -1; 4711 } 4712 } 4713 4714 #ifdef FWOHCI_DEBUG 4715 if (fd < irc->irc_desc_map + 4 4716 || (fd > irc->irc_desc_map + irc->irc_desc_num - 4)) { 4717 printf("fwohci_ir_buf_setup: desc %d %p buf %08x" 4718 " size %d branch %08x\n", 4719 fd - irc->irc_desc_map, fd, fd->fd_data, 4720 fd->fd_reqcount, fd->fd_branch); 4721 } 4722 #endif /* FWOHCI_DEBUG */ 4723 } 4724 4725 --fd; 4726 fd->fd_branch = irc->irc_desc_dmamap->dm_segs[0].ds_addr | 1; 4727 DPRINTF(("fwohci_ir_buf_setup: desc %d %p buf %08x size %d branch %08x\n", 4728 fd - irc->irc_desc_map, fd, fd->fd_data, fd->fd_reqcount, 4729 fd->fd_branch)); 4730 4731 return 0; 4732 } 4733 4734 4735 4736 /* 4737 * static void fwohci_ir_init(struct fwohci_ir_ctx *irc) 4738 * 4739 * This function initialise DMA engine. 4740 */ 4741 static int 4742 fwohci_ir_init(struct fwohci_ir_ctx *irc) 4743 { 4744 struct fwohci_softc *sc = irc->irc_sc; 4745 int n = irc->irc_num; 4746 u_int32_t ctxmatch; 4747 4748 ctxmatch = irc->irc_channel & IEEE1394_ISO_CHANNEL_MASK; 4749 4750 if (irc->irc_channel & IEEE1394_ISO_CHANNEL_ANY) { 4751 OHCI_SYNC_RX_DMA_WRITE(sc, n, 4752 OHCI_SUBREG_ContextControlSet, 4753 OHCI_CTXCTL_RX_MULTI_CHAN_MODE); 4754 4755 /* Receive all the isochronous channels */ 4756 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiSet, 0xffffffff); 4757 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoSet, 0xffffffff); 4758 ctxmatch = 0; 4759 } 4760 4761 ctxmatch |= ((irc->irc_tagbm & 0x0f) << OHCI_CTXMATCH_TAG_BITPOS); 4762 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, ctxmatch); 4763 4764 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 4765 OHCI_CTXCTL_RX_BUFFER_FILL | OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE); 4766 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 4767 OHCI_CTXCTL_RX_ISOCH_HEADER); 4768 4769 printf("fwohci_ir_init\n"); 4770 4771 return 0; 4772 } 4773 4774 4775 /* 4776 * static int fwohci_ir_start(struct fwohci_ir_ctx *irc) 4777 * 4778 * This function starts DMA engine. This function must call 4779 * after fwohci_ir_init() and active bit of context control 4780 * register negated. This function will not check it. 4781 */ 4782 static int 4783 fwohci_ir_start(struct fwohci_ir_ctx *irc) 4784 { 4785 struct fwohci_softc *sc = irc->irc_sc; 4786 int startidx = irc->irc_readtop - irc->irc_desc_map; 4787 u_int32_t startaddr; 4788 4789 startaddr = irc->irc_desc_dmamap->dm_segs[0].ds_addr 4790 + sizeof(struct fwohci_desc)*startidx; 4791 4792 OHCI_SYNC_RX_DMA_WRITE(sc, irc->irc_num, OHCI_SUBREG_CommandPtr, 4793 startaddr | 1); 4794 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, 4795 (1 << irc->irc_num)); 4796 OHCI_SYNC_RX_DMA_WRITE(sc, irc->irc_num, 4797 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 4798 4799 printf("fwohci_ir_start: CmdPtr %08x Ctx %08x startidx %d\n", 4800 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, OHCI_SUBREG_CommandPtr), 4801 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, OHCI_SUBREG_ContextControlSet), 4802 startidx); 4803 4804 irc->irc_status &= ~IRC_STATUS_READY; 4805 irc->irc_status |= IRC_STATUS_RUN; 4806 4807 if ((irc->irc_flags & IEEE1394_IR_TRIGGER_CIP_SYNC) == 0) { 4808 irc->irc_status |= IRC_STATUS_RECEIVE; 4809 } 4810 4811 return 0; 4812 } 4813 4814 4815 4816 /* 4817 * static int fwohci_ir_stop(struct fwohci_ir_ctx *irc) 4818 * 4819 * This function stops DMA engine. 4820 */ 4821 static int 4822 fwohci_ir_stop(struct fwohci_ir_ctx *irc) 4823 { 4824 struct fwohci_softc *sc = irc->irc_sc; 4825 int i; 4826 4827 printf("fwohci_ir_stop\n"); 4828 4829 OHCI_SYNC_RX_DMA_WRITE(sc, irc->irc_num, 4830 OHCI_SUBREG_ContextControlClear, 4831 OHCI_CTXCTL_RUN | OHCI_CTXCTL_DEAD); 4832 4833 i = 0; 4834 while (OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4835 OHCI_SUBREG_ContextControlSet) & OHCI_CTXCTL_ACTIVE) { 4836 #if 0 4837 u_int32_t reg = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4838 OHCI_SUBREG_ContextControlClear); 4839 4840 printf("%s: %d intr IR_CommandPtr 0x%08x " 4841 "ContextCtrl 0x%08x%s%s%s%s\n", 4842 sc->sc_sc1394.sc1394_dev.dv_xname, i, 4843 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4844 OHCI_SUBREG_CommandPtr), 4845 reg, 4846 reg & OHCI_CTXCTL_RUN ? " run" : "", 4847 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 4848 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 4849 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 4850 #endif 4851 if (i > 20) { 4852 printf("fwohci_ir_stop: %s does not stop\n", 4853 sc->sc_sc1394.sc1394_dev.dv_xname); 4854 return 1; 4855 } 4856 DELAY(10); 4857 } 4858 4859 irc->irc_status &= ~IRC_STATUS_RUN; 4860 4861 return 0; 4862 } 4863 4864 4865 4866 4867 4868 4869 static void 4870 fwohci_ir_intr(struct fwohci_softc *sc, struct fwohci_ir_ctx *irc) 4871 { 4872 const char *xname = sc->sc_sc1394.sc1394_dev.dv_xname; 4873 u_int32_t cmd, ctx; 4874 int idx; 4875 struct fwohci_desc *fd; 4876 4877 sc->sc_isocnt.ev_count++; 4878 4879 if (!(irc->irc_status & IRC_STATUS_RUN)) { 4880 printf("fwohci_ir_intr: not running\n"); 4881 return; 4882 } 4883 4884 bus_dmamap_sync(sc->sc_dmat, irc->irc_desc_dmamap, 4885 0, irc->irc_desc_size, BUS_DMASYNC_PREREAD); 4886 4887 ctx = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4888 OHCI_SUBREG_ContextControlSet); 4889 4890 cmd = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4891 OHCI_SUBREG_CommandPtr); 4892 4893 #define OHCI_CTXCTL_RUNNING (OHCI_CTXCTL_RUN|OHCI_CTXCTL_ACTIVE) 4894 #define OHCI_CTXCTL_RUNNING_MASK (OHCI_CTXCTL_RUNNING|OHCI_CTXCTL_DEAD) 4895 4896 idx = (cmd & 0xfffffff8) - (u_int32_t)irc->irc_desc_dmamap->dm_segs[0].ds_addr; 4897 idx /= sizeof(struct fwohci_desc); 4898 4899 if ((ctx & OHCI_CTXCTL_RUNNING_MASK) == OHCI_CTXCTL_RUNNING) { 4900 if (irc->irc_waitchan != NULL) { 4901 DPRINTF(("fwohci_ir_intr: wakeup " 4902 "ctx %d CmdPtr %08x Ctxctl %08x idx %d\n", 4903 irc->irc_num, cmd, ctx, idx)); 4904 #ifdef FWOHCI_WAIT_DEBUG 4905 irc->irc_cycle[1] = fwohci_cycletimer(irc->irc_sc); 4906 #endif 4907 wakeup((void *)irc->irc_waitchan); 4908 } 4909 selwakeup(&irc->irc_sel); 4910 return; 4911 } 4912 4913 fd = irc->irc_desc_map + idx; 4914 4915 printf("fwohci_ir_intr: %s error " 4916 "ctx %d CmdPtr %08x Ctxctl %08x idx %d\n", xname, 4917 irc->irc_num, cmd, ctx, idx); 4918 printf("\tfd flag %x branch %x stat %x rescnt %x total pkt %d\n", 4919 fd->fd_flags, fd->fd_branch, fd->fd_status,fd->fd_rescount, 4920 irc->irc_pktcount); 4921 } 4922 4923 4924 4925 4926 /* 4927 * static int fwohci_ir_ctx_packetnum(struct fwohci_ir_ctx *irc) 4928 * 4929 * This function obtains the lenth of descriptors with data. 4930 */ 4931 static int 4932 fwohci_ir_ctx_packetnum(struct fwohci_ir_ctx *irc) 4933 { 4934 struct fwohci_desc *fd = irc->irc_readtop; 4935 int i = 0; 4936 4937 /* XXX SYNC */ 4938 while (fd->fd_status != 0) { 4939 if (fd == irc->irc_readtop && i > 0) { 4940 printf("descriptor filled %d at %d\n", i, 4941 irc->irc_pktcount); 4942 #ifdef FWOHCI_WAIT_DEBUG 4943 irc->irc_cycle[2] = fwohci_cycletimer(irc->irc_sc); 4944 printf("cycletimer %d:%d %d:%d %d:%d\n", 4945 irc->irc_cycle[0]>>13, irc->irc_cycle[0]&0x1fff, 4946 irc->irc_cycle[1]>>13, irc->irc_cycle[1]&0x1fff, 4947 irc->irc_cycle[2]>>13, irc->irc_cycle[2]&0x1fff); 4948 #endif 4949 4950 break; 4951 } 4952 4953 ++i; 4954 ++fd; 4955 if (fd == irc->irc_desc_map + irc->irc_desc_num) { 4956 fd = irc->irc_desc_map; 4957 } 4958 4959 } 4960 4961 return i; 4962 } 4963 4964 4965 4966 4967 /* 4968 * int fwohci_ir_read(struct device *dev, ieee1394_ir_tag_t tag, 4969 * struct uio *uio, int headoffs, int flags) 4970 * 4971 * This function reads data from fwohci's isochronous receive 4972 * buffer. 4973 */ 4974 int 4975 fwohci_ir_read(struct device *dev, ieee1394_ir_tag_t tag, struct uio *uio, 4976 int headoffs, int flags) 4977 { 4978 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)tag; 4979 int packetnum; 4980 int copylen, hdrshim, fwisohdrsiz; 4981 struct fwohci_desc *fd, *fdprev; 4982 u_int8_t *data; 4983 int status = 0; 4984 u_int32_t tmpbranch; 4985 int pktcount_prev = irc->irc_pktcount; 4986 #ifdef FW_DEBUG 4987 int totalread = 0; 4988 #endif 4989 4990 if (irc->irc_status & IRC_STATUS_READY) { 4991 printf("fwohci_ir_read: starting iso read engine\n"); 4992 fwohci_ir_start(irc); 4993 } 4994 4995 packetnum = fwohci_ir_ctx_packetnum(irc); 4996 4997 DPRINTF(("fwohci_ir_read resid %d DMA buf %d\n", 4998 uio->uio_resid, packetnum)); 4999 5000 if (packetnum == 0) { 5001 return EAGAIN; 5002 } 5003 5004 #ifdef USEDRAIN 5005 if (packetnum > irc->irc_desc_num - irc->irc_desc_num/4) { 5006 packetnum -= fwohci_ir_ctx_drain(irc); 5007 if (irc->irc_pktcount != 0) { 5008 printf("fwohci_ir_read overrun %d\n", 5009 irc->irc_pktcount); 5010 } 5011 } 5012 #endif /* USEDRAIN */ 5013 5014 fd = irc->irc_readtop; 5015 5016 #if 0 5017 if ((irc->irc_status & IRC_STATUS_RECEIVE) == 0 5018 && irc->irc_flags & IEEE1394_IR_TRIGGER_CIP_SYNC) { 5019 unsigned int s; 5020 int i = 0; 5021 5022 fdprev = fd; 5023 while (fd->fd_status != 0) { 5024 s = data[14] << 8; 5025 s |= data[15]; 5026 5027 if (s != 0x0000ffffu) { 5028 DPRINTF(("find header %x at %d\n", 5029 s, irc->irc_pktcount)); 5030 irc->irc_status |= IRC_STATUS_RECEIVE; 5031 break; 5032 } 5033 5034 fd->fd_rescount = 0; 5035 fd->fd_status = 0; 5036 5037 fdprev = fd; 5038 if (++fd == irc->irc_desc_map + irc->irc_desc_num) { 5039 fd = irc->irc_desc_map; 5040 data = irc->irc_buf; 5041 } 5042 ++i; 5043 } 5044 5045 /* XXX SYNC */ 5046 if (i > 0) { 5047 tmpbranch = fdprev->fd_branch; 5048 fdprev->fd_branch = 0; 5049 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5050 irc->irc_writeend = fdprev; 5051 irc->irc_savedbranch = tmpbranch; 5052 } 5053 /* XXX SYNC */ 5054 5055 if (fd->fd_status == 0) { 5056 return EAGAIN; 5057 } 5058 } 5059 #endif 5060 5061 hdrshim = 8; 5062 fwisohdrsiz = 0; 5063 data = irc->irc_buf + (fd - irc->irc_desc_map) * irc->irc_maxsize; 5064 if (irc->irc_flags & IEEE1394_IR_NEEDHEADER) { 5065 fwisohdrsiz = sizeof(struct fwiso_header); 5066 } 5067 5068 while (fd->fd_status != 0 && 5069 (copylen = fd->fd_reqcount - fd->fd_rescount - hdrshim - headoffs) 5070 + fwisohdrsiz < uio->uio_resid) { 5071 5072 DPRINTF(("pkt %04x:%04x uiomove %p, %d\n", 5073 fd->fd_status, fd->fd_rescount, 5074 (void *)(data + 8 + headoffs), copylen)); 5075 if ((irc->irc_status & IRC_STATUS_RECEIVE) == 0) { 5076 DPRINTF(("[%d]", copylen)); 5077 if (irc->irc_pktcount > 1000) { 5078 printf("no header found\n"); 5079 status = EIO; 5080 break; /* XXX */ 5081 } 5082 } else { 5083 DPRINTF(("<%d>", copylen)); 5084 } 5085 5086 if ((irc->irc_status & IRC_STATUS_RECEIVE) == 0 5087 && irc->irc_flags & IEEE1394_IR_TRIGGER_CIP_SYNC 5088 && copylen > 0) { 5089 unsigned int s; 5090 5091 s = data[14] << 8; 5092 s |= data[15]; 5093 5094 if (s != 0x0000ffffu) { 5095 DPRINTF(("find header %x at %d\n", 5096 s, irc->irc_pktcount)); 5097 irc->irc_status |= IRC_STATUS_RECEIVE; 5098 } 5099 } 5100 5101 if (irc->irc_status & IRC_STATUS_RECEIVE) { 5102 if (copylen > 0) { 5103 if (irc->irc_flags & IEEE1394_IR_NEEDHEADER) { 5104 struct fwiso_header fh; 5105 5106 fh.fh_timestamp = htonl((*(u_int32_t *)data) & 0xffff); 5107 fh.fh_speed = htonl((fd->fd_status >> 5)& 0x00000007); 5108 fh.fh_capture_size = htonl(copylen + 4); 5109 fh.fh_iso_header = htonl(*(u_int32_t *)(data + 4)); 5110 status = uiomove((void *)&fh, 5111 sizeof(fh), uio); 5112 if (status != 0) { 5113 /* An error happens */ 5114 printf("uio error in hdr\n"); 5115 break; 5116 } 5117 } 5118 status = uiomove((void *)(data + 8 + headoffs), 5119 copylen, uio); 5120 if (status != 0) { 5121 /* An error happens */ 5122 printf("uio error\n"); 5123 break; 5124 } 5125 #ifdef FW_DEBUG 5126 totalread += copylen; 5127 #endif 5128 } 5129 } 5130 5131 fd->fd_rescount = 0; 5132 fd->fd_status = 0; 5133 5134 #if 0 5135 /* advance writeend pointer and fill branch */ 5136 5137 tmpbranch = fd->fd_branch; 5138 fd->fd_branch = 0; 5139 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5140 irc->irc_writeend = fd; 5141 irc->irc_savedbranch = tmpbranch; 5142 #endif 5143 fdprev = fd; 5144 5145 data += irc->irc_maxsize; 5146 if (++fd == irc->irc_desc_map + irc->irc_desc_num) { 5147 fd = irc->irc_desc_map; 5148 data = irc->irc_buf; 5149 } 5150 ++irc->irc_pktcount; 5151 } 5152 5153 #if 1 5154 if (irc->irc_pktcount != pktcount_prev) { 5155 /* XXX SYNC */ 5156 tmpbranch = fdprev->fd_branch; 5157 fdprev->fd_branch = 0; 5158 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5159 irc->irc_writeend = fdprev; 5160 irc->irc_savedbranch = tmpbranch; 5161 /* XXX SYNC */ 5162 } 5163 #endif 5164 5165 if (!(OHCI_SYNC_RX_DMA_READ(irc->irc_sc, irc->irc_num, 5166 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE)) { 5167 /* do wake */ 5168 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5169 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 5170 } 5171 5172 if (packetnum > irc->irc_maxqueuelen) { 5173 irc->irc_maxqueuelen = packetnum; 5174 irc->irc_maxqueuepos = irc->irc_pktcount; 5175 } 5176 5177 if (irc->irc_pktcount == pktcount_prev) { 5178 #if 0 5179 printf("fwohci_ir_read: process 0 packet, total %d\n", 5180 irc->irc_pktcount); 5181 if (++pktfail > 30) { 5182 return 0; 5183 } 5184 #endif 5185 return EAGAIN; 5186 } 5187 5188 irc->irc_readtop = fd; 5189 5190 DPRINTF(("fwochi_ir_read: process %d packet, total %d\n", 5191 totalread, irc->irc_pktcount)); 5192 5193 return status; 5194 } 5195 5196 5197 5198 5199 /* 5200 * int fwohci_ir_wait(struct device *dev, ieee1394_ir_tag_t tag, 5201 * void *wchan, char *name) 5202 * 5203 * This function waits till new data comes. 5204 */ 5205 int 5206 fwohci_ir_wait(struct device *dev, ieee1394_ir_tag_t tag, void *wchan, char *name) 5207 { 5208 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)tag; 5209 struct fwohci_desc *fd; 5210 int pktnum; 5211 int stat; 5212 5213 if ((pktnum = fwohci_ir_ctx_packetnum(irc)) > 4) { 5214 DPRINTF(("fwohci_ir_wait enough data %d\n", pktnum)); 5215 return 0; 5216 } 5217 5218 fd = irc->irc_readtop + 32; 5219 if (fd >= irc->irc_desc_map + irc->irc_desc_num) { 5220 fd -= irc->irc_desc_num; 5221 } 5222 5223 irc->irc_waitchan = wchan; 5224 if ((irc->irc_flags & IEEE1394_IR_SHORTDELAY) == 0) { 5225 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 5226 DPRINTF(("fwohci_ir_wait stops %d set intr %d\n", 5227 irc->irc_readtop - irc->irc_desc_map, 5228 fd - irc->irc_desc_map)); 5229 /* XXX SYNC */ 5230 } 5231 5232 #ifdef FWOHCI_WAIT_DEBUG 5233 irc->irc_cycle[0] = fwohci_cycletimer(irc->irc_sc); 5234 #endif 5235 5236 irc->irc_status |= IRC_STATUS_SLEEPING; 5237 if ((stat = tsleep(wchan, PCATCH|PRIBIO, name, hz*10)) != 0) { 5238 irc->irc_waitchan = NULL; 5239 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 5240 if (stat == EWOULDBLOCK) { 5241 printf("fwohci_ir_wait: timeout\n"); 5242 return EIO; 5243 } else { 5244 return EINTR; 5245 } 5246 } 5247 5248 irc->irc_waitchan = NULL; 5249 if ((irc->irc_flags & IEEE1394_IR_SHORTDELAY) == 0) { 5250 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 5251 /* XXX SYNC */ 5252 } 5253 5254 DPRINTF(("fwohci_ir_wait: wakeup\n")); 5255 5256 return 0; 5257 } 5258 5259 5260 5261 5262 /* 5263 * int fwohci_ir_select(struct device *dev, ieee1394_ir_tag_t tag, 5264 * struct proc *p) 5265 * 5266 * This function returns the number of packets in queue. 5267 */ 5268 int 5269 fwohci_ir_select(struct device *dev, ieee1394_ir_tag_t tag, struct proc *p) 5270 { 5271 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)tag; 5272 int pktnum; 5273 5274 if (irc->irc_status & IRC_STATUS_READY) { 5275 printf("fwohci_ir_select: starting iso read engine\n"); 5276 fwohci_ir_start(irc); 5277 } 5278 5279 if ((pktnum = fwohci_ir_ctx_packetnum(irc)) == 0) { 5280 selrecord(p, &irc->irc_sel); 5281 } 5282 5283 return pktnum; 5284 } 5285 5286 5287 5288 #ifdef USEDRAIN 5289 /* 5290 * int fwohci_ir_ctx_drain(struct fwohci_ir_ctx *irc) 5291 * 5292 * This function will drain all the packets in receive DMA 5293 * buffer. 5294 */ 5295 static int 5296 fwohci_ir_ctx_drain(struct fwohci_ir_ctx *irc) 5297 { 5298 struct fwohci_desc *fd = irc->irc_readtop; 5299 u_int32_t reg; 5300 int count = 0; 5301 5302 reg = OHCI_SYNC_RX_DMA_READ(irc->irc_sc, irc->irc_num, 5303 OHCI_SUBREG_ContextControlClear); 5304 5305 printf("fwohci_ir_ctx_drain ctx%s%s%s%s\n", 5306 reg & OHCI_CTXCTL_RUN ? " run" : "", 5307 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5308 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5309 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5310 5311 if ((reg & OHCI_CTXCTL_RUNNING_MASK) == OHCI_CTXCTL_RUN) { 5312 /* DMA engine is stopped */ 5313 u_int32_t startadr; 5314 5315 for (fd = irc->irc_desc_map; 5316 fd < irc->irc_desc_map + irc->irc_desc_num; 5317 ++fd) { 5318 fd->fd_status = 0; 5319 } 5320 5321 /* Restore branch addr of the last descriptor */ 5322 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5323 5324 irc->irc_readtop = irc->irc_desc_map; 5325 irc->irc_writeend = irc->irc_desc_map + irc->irc_desc_num - 1; 5326 irc->irc_savedbranch = irc->irc_writeend->fd_branch; 5327 irc->irc_writeend->fd_branch = 0; 5328 5329 count = irc->irc_desc_num; 5330 5331 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5332 OHCI_SUBREG_ContextControlClear, 5333 OHCI_CTXCTL_RUN | OHCI_CTXCTL_DEAD); 5334 5335 startadr = (u_int32_t)irc->irc_desc_dmamap->dm_segs[0].ds_addr; 5336 5337 printf("fwohci_ir_ctx_drain: remove %d pkts\n", count); 5338 5339 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5340 OHCI_SUBREG_CommandPtr, startadr | 1); 5341 5342 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5343 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 5344 } else { 5345 const int removecount = irc->irc_desc_num/2; 5346 u_int32_t tmpbranch; 5347 5348 for (count = 0; count < removecount; ++count) { 5349 if (fd->fd_status == 0) { 5350 break; 5351 } 5352 5353 fd->fd_status = 0; 5354 5355 tmpbranch = fd->fd_branch; 5356 fd->fd_branch = 0; 5357 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5358 irc->irc_writeend = fd; 5359 irc->irc_savedbranch = tmpbranch; 5360 5361 if (++fd == irc->irc_desc_map + irc->irc_desc_num) { 5362 fd = irc->irc_desc_map; 5363 } 5364 ++count; 5365 } 5366 5367 printf("fwohci_ir_ctx_drain: remove %d pkts\n", count); 5368 } 5369 5370 return count; 5371 } 5372 #endif /* USEDRAIN */ 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 /* 5383 * service routines for isochronous transmit 5384 */ 5385 5386 5387 struct fwohci_it_ctx * 5388 fwohci_it_ctx_construct(struct fwohci_softc *sc, int no, int ch, int tag, int maxsize) 5389 { 5390 struct fwohci_it_ctx *itc; 5391 size_t dmastrsize; 5392 struct fwohci_it_dmabuf *dmastr; 5393 struct fwohci_desc *desc; 5394 bus_addr_t descphys; 5395 int nodesc; 5396 int i, j; 5397 5398 if ((itc = malloc(sizeof(*itc), M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) { 5399 return itc; 5400 } 5401 5402 itc->itc_num = no; 5403 itc->itc_flags = 0; 5404 itc->itc_sc = sc; 5405 itc->itc_bufnum = FWOHCI_IT_BUFNUM; 5406 5407 itc->itc_channel = ch; 5408 itc->itc_tag = tag; 5409 itc->itc_speed = OHCI_CTXCTL_SPD_100; /* XXX */ 5410 5411 itc->itc_outpkt = 0; 5412 5413 itc->itc_maxsize = maxsize; 5414 5415 dmastrsize = sizeof(struct fwohci_it_dmabuf)*itc->itc_bufnum; 5416 5417 if ((dmastr = malloc(dmastrsize, M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) { 5418 goto error_1; 5419 } 5420 itc->itc_buf = dmastr; 5421 5422 /* 5423 * Get memory for descriptors. One buffer will have 256 5424 * packet entry and 1 trailing descriptor for writing scratch. 5425 * 4-byte space for scratch. 5426 */ 5427 itc->itc_descsize = (256*3 + 1)*itc->itc_bufnum; 5428 5429 if (fwohci_it_desc_alloc(itc)) { 5430 printf("%s: cannot get enough memory for descriptor\n", 5431 sc->sc_sc1394.sc1394_dev.dv_xname); 5432 goto error_2; 5433 } 5434 5435 /* prepare DMA buffer */ 5436 nodesc = itc->itc_descsize/itc->itc_bufnum; 5437 desc = (struct fwohci_desc *)itc->itc_descmap; 5438 descphys = itc->itc_dseg.ds_addr; 5439 5440 for (i = 0; i < itc->itc_bufnum; ++i) { 5441 5442 if (fwohci_itd_construct(itc, &dmastr[i], i, desc, 5443 descphys, nodesc, 5444 itc->itc_maxsize, itc->itc_scratch_paddr)) { 5445 goto error_3; 5446 } 5447 desc += nodesc; 5448 descphys += sizeof(struct fwohci_desc)*nodesc; 5449 } 5450 5451 #if 1 5452 itc->itc_buf_start = itc->itc_buf; 5453 itc->itc_buf_end = itc->itc_buf; 5454 itc->itc_buf_linkend = itc->itc_buf; 5455 #else 5456 itc->itc_bufidx_start = 0; 5457 itc->itc_bufidx_end = 0; 5458 itc->itc_bufidx_linkend = 0; 5459 #endif 5460 itc->itc_buf_cnt = 0; 5461 itc->itc_waitchan = NULL; 5462 *itc->itc_scratch = 0xffffffff; 5463 5464 return itc; 5465 5466 error_3: 5467 for (j = 0; j < i; ++j) { 5468 fwohci_itd_destruct(&dmastr[j]); 5469 } 5470 fwohci_it_desc_free(itc); 5471 error_2: 5472 free(itc->itc_buf, M_DEVBUF); 5473 error_1: 5474 free(itc, M_DEVBUF); 5475 5476 return NULL; 5477 } 5478 5479 5480 5481 void 5482 fwohci_it_ctx_destruct(struct fwohci_it_ctx *itc) 5483 { 5484 int i; 5485 5486 for (i = 0; i < itc->itc_bufnum; ++i) { 5487 fwohci_itd_destruct(&itc->itc_buf[i]); 5488 } 5489 5490 fwohci_it_desc_free(itc); 5491 free(itc, M_DEVBUF); 5492 } 5493 5494 5495 /* 5496 * static int fwohci_it_desc_alloc(struct fwohci_it_ctx *itc) 5497 * 5498 * Allocates descriptors for context DMA dedicated for 5499 * isochronous transmit. 5500 * 5501 * This function returns 0 (zero) if it succeeds. Otherwise, 5502 * return negative value. 5503 */ 5504 static int 5505 fwohci_it_desc_alloc(struct fwohci_it_ctx *itc) 5506 { 5507 bus_dma_tag_t dmat = itc->itc_sc->sc_dmat; 5508 const char *xname = itc->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 5509 int error, dsize; 5510 5511 /* add for scratch */ 5512 itc->itc_descsize++; 5513 5514 /* rounding up to 256 */ 5515 if ((itc->itc_descsize & 0x0ff) != 0) { 5516 itc->itc_descsize = 5517 (itc->itc_descsize & ~0x0ff) + 0x100; 5518 } 5519 /* remove for scratch */ 5520 5521 itc->itc_descsize--; 5522 printf("%s: fwohci_it_desc_alloc will allocate %d descs\n", 5523 xname, itc->itc_descsize); 5524 5525 /* 5526 * allocate descriptor buffer 5527 */ 5528 dsize = sizeof(struct fwohci_desc) * itc->itc_descsize; 5529 5530 printf("%s: fwohci_it_desc_alloc: descriptor %d, dsize %d\n", 5531 xname, itc->itc_descsize, dsize); 5532 5533 if ((error = bus_dmamem_alloc(dmat, dsize, PAGE_SIZE, 0, 5534 &itc->itc_dseg, 1, &itc->itc_dnsegs, 0)) != 0) { 5535 printf("%s: unable to allocate descriptor buffer, error = %d\n", 5536 xname, error); 5537 goto fail_0; 5538 } 5539 5540 printf("fwohci_it_desc_alloc: %d segment[s]\n", itc->itc_dnsegs); 5541 5542 if ((error = bus_dmamem_map(dmat, &itc->itc_dseg, 5543 itc->itc_dnsegs, dsize, (caddr_t *)&itc->itc_descmap, 5544 BUS_DMA_COHERENT | BUS_DMA_WAITOK)) != 0) { 5545 printf("%s: unable to map descriptor buffer, error = %d\n", 5546 xname, error); 5547 goto fail_1; 5548 } 5549 5550 printf("fwohci_it_desc_alloc: bus_dmamem_map success dseg %lx:%lx\n", 5551 (long)itc->itc_dseg.ds_addr, (long)itc->itc_dseg.ds_len); 5552 5553 if ((error = bus_dmamap_create(dmat, dsize, itc->itc_dnsegs, 5554 dsize, 0, BUS_DMA_WAITOK, &itc->itc_ddmamap)) != 0) { 5555 printf("%s: unable to create descriptor buffer DMA map, " 5556 "error = %d\n", xname, error); 5557 goto fail_2; 5558 } 5559 5560 printf("fwohci_it_desc_alloc: bus_dmamem_create success\n"); 5561 5562 { 5563 int loop; 5564 5565 for (loop = 0; loop < itc->itc_ddmamap->dm_nsegs; ++loop) { 5566 printf("\t%.2d: 0x%lx - 0x%lx\n", loop, 5567 (long)itc->itc_ddmamap->dm_segs[loop].ds_addr, 5568 (long)itc->itc_ddmamap->dm_segs[loop].ds_addr + 5569 (long)itc->itc_ddmamap->dm_segs[loop].ds_len - 1); 5570 } 5571 } 5572 5573 if ((error = bus_dmamap_load(dmat, itc->itc_ddmamap, 5574 itc->itc_descmap, dsize, NULL, BUS_DMA_WAITOK)) != 0) { 5575 printf("%s: unable to load descriptor buffer DMA map, " 5576 "error = %d\n", xname, error); 5577 goto fail_3; 5578 } 5579 5580 printf("%s: fwohci_it_desc_alloc: get DMA memory phys:0x%08x vm:%p\n", 5581 xname, (int)itc->itc_ddmamap->dm_segs[0].ds_addr, itc->itc_descmap); 5582 5583 itc->itc_scratch = (u_int32_t *)(itc->itc_descmap 5584 + (sizeof(struct fwohci_desc))*itc->itc_descsize); 5585 itc->itc_scratch_paddr = 5586 itc->itc_ddmamap->dm_segs[0].ds_addr 5587 + (sizeof(struct fwohci_desc))*itc->itc_descsize; 5588 5589 printf("%s: scratch %p, 0x%x\n", xname, itc->itc_scratch, 5590 (int)itc->itc_scratch_paddr); 5591 5592 /* itc->itc_scratch_paddr = vtophys(itc->itc_scratch); */ 5593 5594 return 0; 5595 5596 fail_3: 5597 bus_dmamap_destroy(dmat, itc->itc_ddmamap); 5598 fail_2: 5599 bus_dmamem_unmap(dmat, (caddr_t)itc->itc_descmap, dsize); 5600 fail_1: 5601 bus_dmamem_free(dmat, &itc->itc_dseg, itc->itc_dnsegs); 5602 fail_0: 5603 itc->itc_dnsegs = 0; 5604 itc->itc_descmap = NULL; 5605 return error; 5606 } 5607 5608 5609 static void 5610 fwohci_it_desc_free(struct fwohci_it_ctx *itc) 5611 { 5612 bus_dma_tag_t dmat = itc->itc_sc->sc_dmat; 5613 int dsize = sizeof(struct fwohci_desc) * itc->itc_descsize + 4; 5614 5615 bus_dmamap_destroy(dmat, itc->itc_ddmamap); 5616 bus_dmamem_unmap(dmat, (caddr_t)itc->itc_descmap, dsize); 5617 bus_dmamem_free(dmat, &itc->itc_dseg, itc->itc_dnsegs); 5618 5619 itc->itc_dnsegs = 0; 5620 itc->itc_descmap = NULL; 5621 } 5622 5623 5624 5625 /* 5626 * int fwohci_it_ctx_writedata(ieee1394_it_tag_t it, int ndata, 5627 * struct ieee1394_it_datalist *itdata, int flags) 5628 * 5629 * This function will write packet data to DMA buffer in the 5630 * context. This function will parse ieee1394_it_datalist 5631 * command and fill DMA buffer. This function will return the 5632 * number of written packets, or error code if the return value 5633 * is negative. 5634 * 5635 * When this funtion returns positive value but smaller than 5636 * ndata, it reaches at the ent of DMA buffer. 5637 */ 5638 int 5639 fwohci_it_ctx_writedata(ieee1394_it_tag_t it, int ndata, 5640 struct ieee1394_it_datalist *itdata, int flags) 5641 { 5642 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 5643 int rv; 5644 int writepkt = 0; 5645 struct fwohci_it_dmabuf *itd; 5646 int i = 0; 5647 5648 itd = itc->itc_buf_end; 5649 5650 while (ndata > 0) { 5651 int s; 5652 5653 if (fwohci_itd_isfull(itd) || fwohci_itd_islocked(itd)) { 5654 if (itc->itc_buf_cnt == itc->itc_bufnum) { 5655 /* no space to write */ 5656 printf("sleeping: start linkend end %d %d %d " 5657 "bufcnt %d\n", 5658 itc->itc_buf_start->itd_num, 5659 itc->itc_buf_linkend->itd_num, 5660 itc->itc_buf_end->itd_num, 5661 itc->itc_buf_cnt); 5662 5663 itc->itc_waitchan = itc; 5664 if (tsleep((void *)itc->itc_waitchan, 5665 PCATCH, "fwohci it", 0) == EWOULDBLOCK) { 5666 itc->itc_waitchan = NULL; 5667 printf("fwohci0 signal\n"); 5668 break; 5669 } 5670 printf("waking: start linkend end %d %d %d\n", 5671 itc->itc_buf_start->itd_num, 5672 itc->itc_buf_linkend->itd_num, 5673 itc->itc_buf_end->itd_num); 5674 5675 itc->itc_waitchan = itc; 5676 i = 0; 5677 } else { 5678 /* 5679 * Use next buffer. This DMA buffer is full 5680 * or locked. 5681 */ 5682 INC_BUF(itc, itd); 5683 } 5684 } 5685 5686 if (++i > 10) { 5687 panic("why loop so much %d", itc->itc_buf_cnt); 5688 break; 5689 } 5690 5691 s = splbio(); 5692 5693 if (fwohci_itd_hasdata(itd) == 0) { 5694 ++itc->itc_buf_cnt; 5695 DPRINTF(("<buf cnt %d>\n", itc->itc_buf_cnt)); 5696 } 5697 5698 rv = fwohci_itd_writedata(itd, ndata, itdata); 5699 DPRINTF(("fwohci_it_ctx_writedata: buf %d ndata %d rv %d\n", 5700 itd->itd_num, ndata, rv)); 5701 5702 if (itc->itc_buf_start == itc->itc_buf_linkend 5703 && (itc->itc_flags & ITC_FLAGS_RUN) != 0) { 5704 5705 #ifdef DEBUG_USERADD 5706 printf("fwohci_it_ctx_writedata: emergency!\n"); 5707 #endif 5708 if (itc->itc_buf_linkend != itc->itc_buf_end 5709 && fwohci_itd_hasdata(itc->itc_buf_end)) { 5710 struct fwohci_it_dmabuf *itdn = itc->itc_buf_linkend; 5711 5712 INC_BUF(itc, itdn); 5713 printf("connecting %d after %d\n", 5714 itdn->itd_num, 5715 itc->itc_buf_linkend->itd_num); 5716 if (fwohci_itd_link(itc->itc_buf_linkend, itdn)) { 5717 printf("fwohci_it_ctx_writedata:" 5718 " cannot link correctly\n"); 5719 return -1; 5720 } 5721 itc->itc_buf_linkend = itdn; 5722 } 5723 } 5724 5725 splx(s); 5726 5727 if (rv < 0) { 5728 /* some errors happend */ 5729 break; 5730 } 5731 5732 writepkt += rv; 5733 ndata -= rv; 5734 itdata += rv; 5735 itc->itc_buf_end = itd; 5736 } 5737 5738 /* Start DMA engine if stopped */ 5739 if ((itc->itc_flags & ITC_FLAGS_RUN) == 0) { 5740 if (itc->itc_buf_cnt > itc->itc_bufnum - 1 || flags) { 5741 /* run */ 5742 printf("fwohci_itc_ctl_writedata: DMA engine start\n"); 5743 fwohci_it_ctx_run(itc); 5744 } 5745 } 5746 5747 return writepkt; 5748 } 5749 5750 5751 5752 static void 5753 fwohci_it_ctx_run(struct fwohci_it_ctx *itc) 5754 { 5755 struct fwohci_softc *sc = itc->itc_sc; 5756 int ctx = itc->itc_num; 5757 struct fwohci_it_dmabuf *itd 5758 = (struct fwohci_it_dmabuf *)itc->itc_buf_start; 5759 u_int32_t reg; 5760 int i; 5761 5762 if (itc->itc_flags & ITC_FLAGS_RUN) { 5763 return; 5764 } 5765 itc->itc_flags |= ITC_FLAGS_RUN; 5766 5767 /* 5768 * dirty, but I can't imagine better place to save branch addr 5769 * of top DMA buffer and substitute 0 to it. 5770 */ 5771 itd->itd_savedbranch = itd->itd_lastdesc->fd_branch; 5772 itd->itd_lastdesc->fd_branch = 0; 5773 5774 if (itc->itc_buf_cnt > 1) { 5775 struct fwohci_it_dmabuf *itdn = itd; 5776 5777 #if 0 5778 INC_BUF(itc, itdn); 5779 5780 if (fwohci_itd_link(itd, itdn)) { 5781 printf("fwohci_it_ctx_run: cannot link correctly\n"); 5782 return; 5783 } 5784 itc->itc_buf_linkend = itdn; 5785 #else 5786 for (;;) { 5787 INC_BUF(itc, itdn); 5788 5789 if (itdn == itc->itc_buf_end) { 5790 break; 5791 } 5792 if (fwohci_itd_link(itd, itdn)) { 5793 printf("fwohci_it_ctx_run: cannot link\n"); 5794 return; 5795 } 5796 itd = itdn; 5797 } 5798 itc->itc_buf_linkend = itd; 5799 #endif 5800 } else { 5801 itd->itd_lastdesc->fd_flags |= OHCI_DESC_INTR_ALWAYS; 5802 itc->itc_buf_linkend = itc->itc_buf_end; 5803 itc->itc_buf_end->itd_flags |= ITD_FLAGS_LOCK; 5804 5805 /* sanity check */ 5806 if (itc->itc_buf_end != itc->itc_buf_start) { 5807 printf("buf start & end differs %p %p\n", 5808 itc->itc_buf_end, itc->itc_buf_start); 5809 } 5810 #if 0 5811 { 5812 u_int32_t *fdp; 5813 u_int32_t adr; 5814 int i; 5815 5816 printf("fwohci_it_ctx_run: itc_buf_cnt 1, DMA buf %d\n", 5817 itd->itd_num); 5818 printf(" last desc %p npacket %d, %d 0x%04x%04x", 5819 itd->itd_lastdesc, itd->itd_npacket, 5820 (itd->itd_lastdesc - itd->itd_desc)/3, 5821 itd->itd_lastdesc->fd_flags, 5822 itd->itd_lastdesc->fd_reqcount); 5823 fdp = (u_int32_t *)itd->itd_desc; 5824 adr = (u_int32_t)itd->itd_desc_phys; /* XXX */ 5825 5826 for (i = 0; i < 7*4; ++i) { 5827 if (i % 4 == 0) { 5828 printf("\n%x:", adr + 4*i); 5829 } 5830 printf(" %08x", fdp[i]); 5831 } 5832 5833 if (itd->itd_npacket > 4) { 5834 printf("\n..."); 5835 i = (itd->itd_npacket - 2)*12 + 4; 5836 } else { 5837 i = 2*12 + 4; 5838 } 5839 for (;i < itd->itd_npacket*12 + 4; ++i) { 5840 if (i % 4 == 0) { 5841 printf("\n%x:", adr + 4*i); 5842 } 5843 printf(" %08x", fdp[i]); 5844 } 5845 printf("\n"); 5846 } 5847 #endif 5848 } 5849 { 5850 struct fwohci_desc *fd; 5851 5852 printf("fwohci_it_ctx_run: link start linkend end %d %d %d\n", 5853 itc->itc_buf_start->itd_num, 5854 itc->itc_buf_linkend->itd_num, 5855 itc->itc_buf_end->itd_num); 5856 5857 fd = itc->itc_buf_start->itd_desc; 5858 if ((fd->fd_flags & 0xff00) != OHCI_DESC_STORE_VALUE) { 5859 printf("fwohci_it_ctx_run: start buf not with STORE\n"); 5860 } 5861 fd += 3; 5862 if ((fd->fd_flags & OHCI_DESC_INTR_ALWAYS) == 0) { 5863 printf("fwohci_it_ctx_run: start buf does not have intr\n"); 5864 } 5865 5866 fd = itc->itc_buf_linkend->itd_desc; 5867 if ((fd->fd_flags & 0xff00) != OHCI_DESC_STORE_VALUE) { 5868 printf("fwohci_it_ctx_run: linkend buf not with STORE\n"); 5869 } 5870 fd += 3; 5871 if ((fd->fd_flags & OHCI_DESC_INTR_ALWAYS) == 0) { 5872 printf("fwohci_it_ctx_run: linkend buf does not have intr\n"); 5873 } 5874 } 5875 5876 *itc->itc_scratch = 0xffffffff; 5877 5878 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_ContextControlClear, 5879 0xffff0000); 5880 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_ContextControlSet); 5881 5882 printf("fwohci_it_ctx_run start for ctx %d\n", ctx); 5883 printf("%s: bfr IT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 5884 sc->sc_sc1394.sc1394_dev.dv_xname, 5885 OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_CommandPtr), 5886 reg, 5887 reg & OHCI_CTXCTL_RUN ? " run" : "", 5888 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5889 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5890 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5891 5892 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_ContextControlClear, 5893 OHCI_CTXCTL_RUN); 5894 5895 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_ContextControlSet); 5896 i = 0; 5897 while (reg & (OHCI_CTXCTL_ACTIVE | OHCI_CTXCTL_RUN)) { 5898 delay(100); 5899 if (++i > 1000) { 5900 printf("%s: cannot stop iso transmit engine\n", 5901 sc->sc_sc1394.sc1394_dev.dv_xname); 5902 break; 5903 } 5904 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, 5905 OHCI_SUBREG_ContextControlSet); 5906 } 5907 5908 printf("%s: itm IT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 5909 sc->sc_sc1394.sc1394_dev.dv_xname, 5910 OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_CommandPtr), 5911 reg, 5912 reg & OHCI_CTXCTL_RUN ? " run" : "", 5913 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5914 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5915 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5916 5917 printf("%s: writing CommandPtr to 0x%08x\n", 5918 sc->sc_sc1394.sc1394_dev.dv_xname, 5919 (int)itc->itc_buf_start->itd_desc_phys); 5920 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_CommandPtr, 5921 fwohci_itd_list_head(itc->itc_buf_start) | 4); 5922 5923 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_ContextControlSet, 5924 OHCI_CTXCTL_RUN | OHCI_CTXCTL_WAKE); 5925 5926 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_ContextControlSet); 5927 5928 printf("%s: aft IT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 5929 sc->sc_sc1394.sc1394_dev.dv_xname, 5930 OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_CommandPtr), 5931 reg, 5932 reg & OHCI_CTXCTL_RUN ? " run" : "", 5933 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5934 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5935 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5936 } 5937 5938 5939 5940 int 5941 fwohci_it_ctx_flush(ieee1394_it_tag_t it) 5942 { 5943 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 5944 int rv = 0; 5945 5946 if ((itc->itc_flags & ITC_FLAGS_RUN) == 0 5947 && itc->itc_buf_cnt > 0) { 5948 printf("fwohci_it_ctx_flush: %s flushing\n", 5949 itc->itc_sc->sc_sc1394.sc1394_dev.dv_xname); 5950 5951 fwohci_it_ctx_run(itc); 5952 rv = 1; 5953 } 5954 5955 return rv; 5956 } 5957 5958 5959 /* 5960 * static void fwohci_it_intr(struct fwohci_softc *sc, 5961 * struct fwochi_it_ctx *itc) 5962 * 5963 * This function is the interrupt handler for isochronous 5964 * transmit interrupt. This function will 1) unlink used 5965 * (already transmitted) buffers, 2) link new filled buffers, if 5966 * necessary and 3) say some free dma buffers exist to 5967 * fwiso_write() 5968 */ 5969 static void 5970 fwohci_it_intr(struct fwohci_softc *sc, struct fwohci_it_ctx *itc) 5971 { 5972 struct fwohci_it_dmabuf *itd, *newstartbuf; 5973 u_int16_t scratchval; 5974 u_int32_t reg; 5975 5976 reg = OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 5977 OHCI_SUBREG_ContextControlSet); 5978 5979 /* print out debug info */ 5980 #ifdef FW_DEBUG 5981 printf("fwohci_it_intr: CTX %d\n", itc->itc_num); 5982 5983 printf("fwohci_it_intr: %s: IT_CommandPtr 0x%08x " 5984 "ContextCtrl 0x%08x%s%s%s%s\n", 5985 sc->sc_sc1394.sc1394_dev.dv_xname, 5986 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, OHCI_SUBREG_CommandPtr), 5987 reg, 5988 reg & OHCI_CTXCTL_RUN ? " run" : "", 5989 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5990 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5991 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5992 printf("fwohci_it_intr: %s: scratch %x start %d end %d valid %d\n", 5993 sc->sc_sc1394.sc1394_dev.dv_xname, *itc->itc_scratch, 5994 itc->itc_buf_start->itd_num, itc->itc_buf_end->itd_num, 5995 itc->itc_buf_cnt); 5996 { 5997 u_int32_t reg 5998 = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 5999 printf("\t\tIsoCounter 0x%08x, %d %d %d\n", reg, 6000 (reg >> 25) & 0xfe, (reg >> 12) & 0x1fff, reg & 0xfff); 6001 } 6002 #endif /* FW_DEBUG */ 6003 /* end print out debug info */ 6004 6005 scratchval = (*itc->itc_scratch) & 0x0000ffff; 6006 *itc->itc_scratch = 0xffffffff; 6007 6008 if ((reg & OHCI_CTXCTL_ACTIVE) == 0 && scratchval != 0xffff) { 6009 /* DMA engine has been stopped */ 6010 printf("DMA engine stopped\n"); 6011 printf("fwohci_it_intr: %s: IT_CommandPtr 0x%08x " 6012 "ContextCtrl 0x%08x%s%s%s%s\n", 6013 sc->sc_sc1394.sc1394_dev.dv_xname, 6014 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, OHCI_SUBREG_CommandPtr), 6015 reg, 6016 reg & OHCI_CTXCTL_RUN ? " run" : "", 6017 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 6018 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 6019 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 6020 printf("fwohci_it_intr: %s: scratch %x start %d end %d valid %d\n", 6021 sc->sc_sc1394.sc1394_dev.dv_xname, *itc->itc_scratch, 6022 itc->itc_buf_start->itd_num, itc->itc_buf_end->itd_num, 6023 itc->itc_buf_cnt); 6024 { 6025 u_int32_t reg 6026 = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 6027 printf("\t\tIsoCounter 0x%08x, %d %d %d\n", reg, 6028 (reg >> 25) & 0xfe, (reg >> 12) & 0x1fff, reg & 0xfff); 6029 } 6030 printf("\t\tbranch of lastdesc 0x%08x\n", 6031 itc->itc_buf_start->itd_lastdesc->fd_branch); 6032 6033 scratchval = 0xffff; 6034 itc->itc_flags &= ~ITC_FLAGS_RUN; 6035 } 6036 6037 /* unlink old buffers */ 6038 if (scratchval != 0xffff) { 6039 /* normal path */ 6040 newstartbuf = &itc->itc_buf[scratchval]; 6041 } else { 6042 /* DMA engine stopped */ 6043 newstartbuf = itc->itc_buf_linkend; 6044 INC_BUF(itc, newstartbuf); 6045 } 6046 6047 itd = (struct fwohci_it_dmabuf *)itc->itc_buf_start; 6048 itc->itc_buf_start = newstartbuf; 6049 while (itd != newstartbuf) { 6050 itc->itc_outpkt += itd->itd_npacket; 6051 fwohci_itd_unlink(itd); 6052 INC_BUF(itc, itd); 6053 --itc->itc_buf_cnt; 6054 DPRINTF(("<buf cnt %d>\n", itc->itc_buf_cnt)); 6055 } 6056 6057 #ifdef DEBUG_USERADD 6058 if (scratchval != 0xffff) { 6059 printf("fwohci0: intr start %d dataend %d %d\n", scratchval, 6060 itc->itc_buf_end->itd_num, itc->itc_outpkt); 6061 } 6062 #endif 6063 6064 if (scratchval == 0xffff) { 6065 /* no data supplied */ 6066 printf("fwohci_it_intr: no it data. output total %d\n", 6067 itc->itc_outpkt); 6068 6069 if (itc->itc_buf_cnt > 0) { 6070 printf("fwohci_it_intr: it DMA stops " 6071 "w/ valid databuf %d buf %d data %d" 6072 " intr reg 0x%08x\n", 6073 itc->itc_buf_cnt, 6074 itc->itc_buf_end->itd_num, 6075 fwohci_itd_hasdata(itc->itc_buf_end), 6076 OHCI_CSR_READ(sc, OHCI_REG_IntEventSet)); 6077 } else { 6078 /* All the data gone */ 6079 itc->itc_buf_start 6080 = itc->itc_buf_end 6081 = itc->itc_buf_linkend 6082 = &itc->itc_buf[0]; 6083 printf("fwohci_it_intr: all packets gone\n"); 6084 } 6085 6086 itc->itc_flags &= ~ITC_FLAGS_RUN; 6087 6088 OHCI_SYNC_TX_DMA_WRITE(sc, itc->itc_num, 6089 OHCI_SUBREG_ContextControlClear, 0xffffffff); 6090 OHCI_SYNC_TX_DMA_WRITE(sc, itc->itc_num, 6091 OHCI_SUBREG_CommandPtr, 0); 6092 OHCI_SYNC_TX_DMA_WRITE(sc, itc->itc_num, 6093 OHCI_SUBREG_ContextControlClear, 0x1f); 6094 6095 /* send message */ 6096 if (itc->itc_waitchan != NULL) { 6097 wakeup((void *)itc->itc_waitchan); 6098 } 6099 6100 return; 6101 } 6102 6103 #if 0 6104 /* unlink old buffers */ 6105 newstartbuf = &itc->itc_buf[scratchval]; 6106 6107 itd = (struct fwohci_it_dmabuf *)itc->itc_buf_start; 6108 itc->itc_buf_start = newstartbuf; 6109 while (itd != newstartbuf) { 6110 itc->itc_outpkt += itd->itd_npacket; 6111 fwohci_itd_unlink(itd); 6112 INC_BUF(itc, itd); 6113 --itc->itc_buf_cnt; 6114 DPRINTF(("<buf cnt %d>\n", itc->itc_buf_cnt)); 6115 } 6116 #endif 6117 6118 /* sanity check */ 6119 { 6120 int startidx, endidx, linkendidx; 6121 6122 startidx = itc->itc_buf_start->itd_num; 6123 endidx = itc->itc_buf_end->itd_num; 6124 linkendidx = itc->itc_buf_linkend->itd_num; 6125 6126 if (startidx < endidx) { 6127 if (linkendidx < startidx 6128 || endidx < linkendidx) { 6129 printf("funny, linkend is not between start " 6130 "and end [%d, %d]: %d\n", 6131 startidx, endidx, linkendidx); 6132 } 6133 } else if (startidx > endidx) { 6134 if (linkendidx < startidx 6135 && endidx < linkendidx) { 6136 printf("funny, linkend is not between start " 6137 "and end [%d, %d]: %d\n", 6138 startidx, endidx, linkendidx); 6139 } 6140 } else { 6141 if (linkendidx != startidx) { 6142 printf("funny, linkend is not between start " 6143 "and end [%d, %d]: %d\n", 6144 startidx, endidx, linkendidx); 6145 } 6146 6147 } 6148 } 6149 6150 /* link if some valid DMA buffers exist */ 6151 if (itc->itc_buf_cnt > 1 6152 && itc->itc_buf_linkend != itc->itc_buf_end) { 6153 struct fwohci_it_dmabuf *itdprev; 6154 int i; 6155 6156 DPRINTF(("CTX %d: start linkend dataend bufs %d, %d, %d, %d\n", 6157 itc->itc_num, 6158 itc->itc_buf_start->itd_num, 6159 itc->itc_buf_linkend->itd_num, 6160 itc->itc_buf_end->itd_num, 6161 itc->itc_buf_cnt)); 6162 6163 itd = itdprev = itc->itc_buf_linkend; 6164 INC_BUF(itc, itd); 6165 6166 #if 0 6167 if (fwohci_itd_isfilled(itd) || itc->itc_buf_cnt == 2) { 6168 while (itdprev != itc->itc_buf_end) { 6169 6170 if (fwohci_itd_link(itdprev, itd)) { 6171 break; 6172 } 6173 6174 itdprev = itd; 6175 INC_BUF(itc, itd); 6176 } 6177 itc->itc_buf_linkend = itdprev; 6178 } 6179 #endif 6180 i = 0; 6181 while (itdprev != itc->itc_buf_end) { 6182 if (!fwohci_itd_isfilled(itd) && itc->itc_buf_cnt > 2) { 6183 break; 6184 } 6185 6186 if (fwohci_itd_link(itdprev, itd)) { 6187 break; 6188 } 6189 6190 itdprev = itd; 6191 INC_BUF(itc, itd); 6192 6193 itc->itc_buf_linkend = itdprev; 6194 ++i; 6195 } 6196 6197 if (i > 0) { 6198 DPRINTF(("CTX %d: start linkend dataend bufs %d, %d, %d, %d\n", 6199 itc->itc_num, 6200 itc->itc_buf_start->itd_num, 6201 itc->itc_buf_linkend->itd_num, 6202 itc->itc_buf_end->itd_num, 6203 itc->itc_buf_cnt)); 6204 } 6205 } else { 6206 struct fwohci_it_dmabuf *le; 6207 6208 le = itc->itc_buf_linkend; 6209 6210 printf("CTX %d: start linkend dataend bufs %d, %d, %d, %d no buffer added\n", 6211 itc->itc_num, 6212 itc->itc_buf_start->itd_num, 6213 itc->itc_buf_linkend->itd_num, 6214 itc->itc_buf_end->itd_num, 6215 itc->itc_buf_cnt); 6216 printf("\tlast descriptor %s %04x %08x\n", 6217 le->itd_lastdesc->fd_flags & OHCI_DESC_INTR_ALWAYS ? "intr" : "", 6218 le->itd_lastdesc->fd_flags, 6219 le->itd_lastdesc->fd_branch); 6220 } 6221 6222 /* send message */ 6223 if (itc->itc_waitchan != NULL) { 6224 /* */ 6225 wakeup((void *)itc->itc_waitchan); 6226 } 6227 } 6228 6229 6230 6231 /* 6232 * int fwohci_itd_construct(struct fwohci_it_ctx *itc, 6233 * struct fwohci_it_dmabuf *itd, int num, 6234 * struct fwohci_desc *desc, bus_addr_t phys, 6235 * int descsize, int maxsize, paddr_t scratch) 6236 * 6237 * 6238 * 6239 */ 6240 int 6241 fwohci_itd_construct(struct fwohci_it_ctx *itc, struct fwohci_it_dmabuf *itd, 6242 int num, struct fwohci_desc *desc, bus_addr_t phys, int descsize, 6243 int maxsize, paddr_t scratch) 6244 { 6245 const char *xname = itc->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 6246 struct fwohci_desc *fd; 6247 struct fwohci_desc *descend; 6248 int npkt; 6249 int bufno = 0; /* DMA segment */ 6250 bus_size_t bufused = 0; /* offset in a DMA segment */ 6251 int roundsize; 6252 int tag = itc->itc_tag; 6253 int ch = itc->itc_channel; 6254 6255 itd->itd_ctx = itc; 6256 itd->itd_num = num; 6257 6258 if (descsize > 1024*3) { 6259 printf("%s: fwohci_itd_construct[%d] descsize %d too big\n", 6260 xname, num, descsize); 6261 return -1; 6262 } 6263 6264 itd->itd_desc = desc; 6265 itd->itd_descsize = descsize; 6266 itd->itd_desc_phys = phys; 6267 6268 itd->itd_lastdesc = desc; 6269 itd->itd_npacket = 0; 6270 6271 printf("%s: fwohci_itd_construct[%d] desc %p descsize %d, maxsize %d\n", 6272 xname, itd->itd_num, itd->itd_desc, itd->itd_descsize, maxsize); 6273 6274 if (descsize < 4) { 6275 /* too small descriptor array. at least 4 */ 6276 return -1; 6277 } 6278 6279 /* count up how many packet can handle */ 6280 itd->itd_maxpacket = (descsize - 1)/3; 6281 6282 /* rounding up to power of 2. minimum 16 */ 6283 roundsize = 16; 6284 for (roundsize = 16; roundsize < maxsize; roundsize <<= 1); 6285 itd->itd_maxsize = roundsize; 6286 6287 printf("\t\tdesc%d [%x, %lx]\n", itd->itd_num, 6288 (u_int32_t)phys, 6289 (unsigned long)((u_int32_t)phys 6290 + (itd->itd_maxpacket*3 + 1)*sizeof(struct fwohci_desc))); 6291 printf("%s: fwohci_itd_construct[%d] npkt %d maxsize round up to %d\n", 6292 xname, itd->itd_num, itd->itd_maxpacket, itd->itd_maxsize); 6293 6294 /* obtain DMA buffer */ 6295 if (fwohci_itd_dmabuf_alloc(itd)) { 6296 /* cannot allocate memory for DMA buffer */ 6297 return -1; 6298 } 6299 6300 /* 6301 * make descriptor chain 6302 * 6303 * First descriptor group has a STORE_VALUE, OUTPUT_IMMEDIATE 6304 * and OUTPUT_LAST descriptors Second and after that, a 6305 * descriptor group has an OUTPUT_IMMEDIATE and an OUTPUT_LAST 6306 * descriptor. 6307 */ 6308 descend = desc + descsize; 6309 6310 /* set store value descriptor for 1st descriptor group */ 6311 desc->fd_flags = OHCI_DESC_STORE_VALUE; 6312 desc->fd_reqcount = num; /* write number of DMA buffer class */ 6313 desc->fd_data = scratch; /* at physical memory 'scratch' */ 6314 desc->fd_branch = 0; 6315 desc->fd_status = desc->fd_rescount = 0; 6316 6317 itd->itd_store = desc; 6318 itd->itd_store_phys = phys; 6319 6320 ++desc; 6321 phys += 16; 6322 6323 npkt = 0; 6324 /* make OUTPUT_DESC chain for packets */ 6325 for (fd = desc; fd + 2 < descend; fd += 3, ++npkt) { 6326 struct fwohci_desc *fi = fd; 6327 struct fwohci_desc *fl = fd + 2; 6328 u_int32_t *fi_data = (u_int32_t *)(fd + 1); 6329 6330 #if 0 6331 if (npkt > itd->itd_maxpacket - 3) { 6332 printf("%s: %3d fi fl %p %p\n", xname, npkt, fi,fl); 6333 } 6334 #endif 6335 6336 fi->fd_reqcount = 8; /* data size for OHCI command */ 6337 fi->fd_flags = OHCI_DESC_IMMED; 6338 fi->fd_data = 0; 6339 fi->fd_branch = 0; /* branch for error */ 6340 fi->fd_status = fi->fd_rescount = 0; 6341 6342 /* channel and tag is unchanged */ 6343 *fi_data = OHCI_ITHEADER_VAL(TAG, tag) | 6344 OHCI_ITHEADER_VAL(CHAN, ch) | 6345 OHCI_ITHEADER_VAL(TCODE, IEEE1394_TCODE_STREAM_DATA); 6346 *++fi_data = 0; 6347 *++fi_data = 0; 6348 *++fi_data = 0; 6349 6350 fl->fd_flags = OHCI_DESC_OUTPUT | OHCI_DESC_LAST | 6351 OHCI_DESC_BRANCH; 6352 fl->fd_branch = 6353 (phys + sizeof(struct fwohci_desc)*(npkt + 1)*3) | 0x03; 6354 fl->fd_status = fl->fd_rescount = 0; 6355 6356 #ifdef FW_DEBUG 6357 if (npkt > itd->itd_maxpacket - 3) { 6358 DPRINTF(("%s: %3d fi fl fl branch %p %p 0x%x\n", 6359 xname, npkt, fi, fl, (int)fl->fd_branch)); 6360 } 6361 #endif 6362 6363 /* physical addr to data? */ 6364 fl->fd_data = 6365 (u_int32_t)((itd->itd_seg[bufno].ds_addr + bufused)); 6366 bufused += itd->itd_maxsize; 6367 if (bufused > itd->itd_seg[bufno].ds_len) { 6368 bufused = 0; 6369 if (++bufno == itd->itd_nsegs) { 6370 /* fail */ 6371 break; 6372 } 6373 } 6374 } 6375 6376 #if 0 6377 if (itd->itd_num == 0) { 6378 u_int32_t *fdp; 6379 u_int32_t adr; 6380 int i = 0; 6381 6382 fdp = (u_int32_t *)itd->itd_desc; 6383 adr = (u_int32_t)itd->itd_desc_phys; /* XXX */ 6384 6385 printf("fwohci_itd_construct: audit DMA desc chain. %d\n", 6386 itd->itd_maxpacket); 6387 for (i = 0; i < itd->itd_maxpacket*12 + 4; ++i) { 6388 if (i % 4 == 0) { 6389 printf("\n%x:", adr + 4*i); 6390 } 6391 printf(" %08x", fdp[i]); 6392 } 6393 printf("\n"); 6394 6395 } 6396 #endif 6397 /* last branch should be 0 */ 6398 --fd; 6399 fd->fd_branch = 0; 6400 6401 printf("%s: pkt %d %d maxdesc %p\n", 6402 xname, npkt, itd->itd_maxpacket, descend); 6403 6404 return 0; 6405 } 6406 6407 void 6408 fwohci_itd_destruct(struct fwohci_it_dmabuf *itd) 6409 { 6410 const char *xname = itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 6411 6412 printf("%s: fwohci_itd_destruct %d\n", xname, itd->itd_num); 6413 6414 fwohci_itd_dmabuf_free(itd); 6415 } 6416 6417 6418 /* 6419 * static int fwohci_itd_dmabuf_alloc(struct fwohci_it_dmabuf *itd) 6420 * 6421 * This function allocates DMA memory for fwohci_it_dmabuf. This 6422 * function will return 0 when it succeeds and return non-zero 6423 * value when it fails. 6424 */ 6425 static int 6426 fwohci_itd_dmabuf_alloc(struct fwohci_it_dmabuf *itd) 6427 { 6428 const char *xname = itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 6429 bus_dma_tag_t dmat = itd->itd_ctx->itc_sc->sc_dmat; 6430 6431 int dmasize = itd->itd_maxsize * itd->itd_maxpacket; 6432 int error; 6433 6434 DPRINTF(("%s: fwohci_itd_dmabuf_alloc[%d] dmasize %d maxpkt %d\n", 6435 xname, itd->itd_num, dmasize, itd->itd_maxpacket)); 6436 6437 if ((error = bus_dmamem_alloc(dmat, dmasize, PAGE_SIZE, 0, 6438 itd->itd_seg, FWOHCI_MAX_ITDATASEG, &itd->itd_nsegs, 0)) != 0) { 6439 printf("%s: unable to allocate data buffer, error = %d\n", 6440 xname, error); 6441 goto fail_0; 6442 } 6443 6444 /* checking memory range */ 6445 #ifdef FW_DEBUG 6446 { 6447 int loop; 6448 6449 for (loop = 0; loop < itd->itd_nsegs; ++loop) { 6450 DPRINTF(("\t%.2d: 0x%lx - 0x%lx\n", loop, 6451 (long)itd->itd_seg[loop].ds_addr, 6452 (long)itd->itd_seg[loop].ds_addr 6453 + (long)itd->itd_seg[loop].ds_len - 1)); 6454 } 6455 } 6456 #endif 6457 6458 if ((error = bus_dmamem_map(dmat, itd->itd_seg, itd->itd_nsegs, 6459 dmasize, (caddr_t *)&itd->itd_buf, 6460 BUS_DMA_COHERENT | BUS_DMA_WAITOK)) != 0) { 6461 printf("%s: unable to map data buffer, error = %d\n", 6462 xname, error); 6463 goto fail_1; 6464 } 6465 6466 DPRINTF(("fwohci_it_data_alloc[%d]: bus_dmamem_map addr %p\n", 6467 itd->itd_num, itd->itd_buf)); 6468 6469 if ((error = bus_dmamap_create(dmat, /*chunklen*/dmasize, 6470 itd->itd_nsegs, dmasize, 0, BUS_DMA_WAITOK, 6471 &itd->itd_dmamap)) != 0) { 6472 printf("%s: unable to create data buffer DMA map, " 6473 "error = %d\n", xname, error); 6474 goto fail_2; 6475 } 6476 6477 DPRINTF(("fwohci_it_data_alloc: bus_dmamem_create\n")); 6478 6479 if ((error = bus_dmamap_load(dmat, itd->itd_dmamap, 6480 itd->itd_buf, dmasize, NULL, BUS_DMA_WAITOK)) != 0) { 6481 printf("%s: unable to load data buffer DMA map, error = %d\n", 6482 xname, error); 6483 goto fail_3; 6484 } 6485 6486 DPRINTF(("fwohci_itd_dmabuf_alloc: load DMA memory vm %p\n", 6487 itd->itd_buf)); 6488 DPRINTF(("\tmapsize %ld nsegs %d\n", 6489 (long)itd->itd_dmamap->dm_mapsize, itd->itd_dmamap->dm_nsegs)); 6490 6491 #ifdef FW_DEBUG 6492 { 6493 int loop; 6494 6495 for (loop = 0; loop < itd->itd_dmamap->dm_nsegs; ++loop) { 6496 DPRINTF(("\t%.2d: 0x%lx - 0x%lx\n", loop, 6497 (long)itd->itd_dmamap->dm_segs[loop].ds_addr, 6498 (long)itd->itd_dmamap->dm_segs[loop].ds_addr + 6499 (long)itd->itd_dmamap->dm_segs[loop].ds_len - 1)); 6500 } 6501 } 6502 #endif 6503 6504 return 0; 6505 6506 fail_3: 6507 bus_dmamap_destroy(dmat, itd->itd_dmamap); 6508 fail_2: 6509 bus_dmamem_unmap(dmat, (caddr_t)itd->itd_buf, dmasize); 6510 fail_1: 6511 bus_dmamem_free(dmat, itd->itd_seg, itd->itd_nsegs); 6512 fail_0: 6513 itd->itd_nsegs = 0; 6514 itd->itd_maxpacket = 0; 6515 return error; 6516 } 6517 6518 /* 6519 * static void fwohci_itd_dmabuf_free(struct fwohci_it_dmabuf *itd) 6520 * 6521 * This function will release memory resource allocated by 6522 * fwohci_itd_dmabuf_alloc(). 6523 */ 6524 static void 6525 fwohci_itd_dmabuf_free(struct fwohci_it_dmabuf *itd) 6526 { 6527 bus_dma_tag_t dmat = itd->itd_ctx->itc_sc->sc_dmat; 6528 int dmasize = itd->itd_maxsize * itd->itd_maxpacket; 6529 6530 bus_dmamap_destroy(dmat, itd->itd_dmamap); 6531 bus_dmamem_unmap(dmat, (caddr_t)itd->itd_buf, dmasize); 6532 bus_dmamem_free(dmat, itd->itd_seg, itd->itd_nsegs); 6533 6534 itd->itd_nsegs = 0; 6535 itd->itd_maxpacket = 0; 6536 } 6537 6538 6539 6540 /* 6541 * int fwohci_itd_link(struct fwohci_it_dmabuf *itd, 6542 * struct fwohci_it_dmabuf *itdc) 6543 * 6544 * This function will concatinate two descriptor chains in dmabuf 6545 * itd and itdc. The descriptor link in itdc follows one in itd. 6546 * This function will move interrrupt packet from the end of itd 6547 * to the top of itdc. 6548 * 6549 * This function will return 0 whel this funcion suceeds. If an 6550 * error happens, return a negative value. 6551 */ 6552 int 6553 fwohci_itd_link(struct fwohci_it_dmabuf *itd, struct fwohci_it_dmabuf *itdc) 6554 { 6555 struct fwohci_desc *fd1, *fdc; 6556 6557 if (itdc->itd_lastdesc == itdc->itd_desc) { 6558 /* no valid data */ 6559 printf("fwohci_itd_link: no data\n"); 6560 return -1; 6561 } 6562 6563 if (itdc->itd_flags & ITD_FLAGS_LOCK) { 6564 /* used already */ 6565 printf("fwohci_itd_link: link locked\n"); 6566 return -1; 6567 } 6568 itdc->itd_flags |= ITD_FLAGS_LOCK; 6569 /* for the first one */ 6570 itd->itd_flags |= ITD_FLAGS_LOCK; 6571 6572 DPRINTF(("linking %d after %d: add %d pkts\n", 6573 itdc->itd_num, itd->itd_num, itdc->itd_npacket)); 6574 6575 /* XXX: should sync cache */ 6576 6577 fd1 = itd->itd_lastdesc; 6578 fdc = itdc->itd_desc + 3; /* OUTPUT_LAST in the first descriptor */ 6579 6580 /* sanity check */ 6581 #define OUTPUT_LAST_DESC (OHCI_DESC_OUTPUT | OHCI_DESC_LAST | OHCI_DESC_BRANCH) 6582 if ((fd1->fd_flags & OUTPUT_LAST_DESC) != OUTPUT_LAST_DESC) { 6583 printf("funny! not OUTPUT_LAST descriptor %p\n", fd1); 6584 } 6585 if (itd->itd_lastdesc - itd->itd_desc != 3 * itd->itd_npacket) { 6586 printf("funny! packet number inconsistency %ld <=> %ld\n", 6587 (long)(itd->itd_lastdesc - itd->itd_desc), 6588 (long)(3*itd->itd_npacket)); 6589 } 6590 6591 fd1->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6592 fdc->fd_flags |= OHCI_DESC_INTR_ALWAYS; 6593 fd1->fd_branch = itdc->itd_desc_phys | 4; 6594 6595 itdc->itd_lastdesc->fd_flags |= OHCI_DESC_INTR_ALWAYS; 6596 /* save branch addr of lastdesc and substitute 0 to it */ 6597 itdc->itd_savedbranch = itdc->itd_lastdesc->fd_branch; 6598 itdc->itd_lastdesc->fd_branch = 0; 6599 6600 DPRINTF(("%s: link (%d %d), add pkt %d/%d branch 0x%x next saved 0x%x\n", 6601 itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname, 6602 itd->itd_num, itdc->itd_num, 6603 itdc->itd_npacket, itdc->itd_maxpacket, 6604 (int)fd1->fd_branch, (int)itdc->itd_savedbranch)); 6605 6606 /* XXX: should sync cache */ 6607 6608 return 0; 6609 } 6610 6611 6612 /* 6613 * int fwohci_itd_unlink(struct fwohci_it_dmabuf *itd) 6614 * 6615 * This function will unlink the descriptor chain from valid link 6616 * of descriptors. The target descriptor is specified by the 6617 * arguent. 6618 */ 6619 int 6620 fwohci_itd_unlink(struct fwohci_it_dmabuf *itd) 6621 { 6622 struct fwohci_desc *fd; 6623 6624 /* XXX: should sync cache */ 6625 6626 fd = itd->itd_lastdesc; 6627 6628 fd->fd_branch = itd->itd_savedbranch; 6629 DPRINTF(("%s: unlink buf %d branch restored 0x%x\n", 6630 itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname, 6631 itd->itd_num, (int)fd->fd_branch)); 6632 6633 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6634 itd->itd_lastdesc = itd->itd_desc; 6635 6636 fd = itd->itd_desc + 3; /* 1st OUTPUT_LAST */ 6637 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6638 6639 /* XXX: should sync cache */ 6640 6641 itd->itd_npacket = 0; 6642 itd->itd_lastdesc = itd->itd_desc; 6643 itd->itd_flags &= ~ITD_FLAGS_LOCK; 6644 6645 return 0; 6646 } 6647 6648 6649 /* 6650 * static int fwohci_itd_writedata(struct fwohci_it_dmabuf *, int ndata, 6651 * struct ieee1394_it_datalist *); 6652 * 6653 * This function will return the number of written data, or 6654 * negative value if an error happens 6655 */ 6656 int 6657 fwohci_itd_writedata(struct fwohci_it_dmabuf *itd, int ndata, 6658 struct ieee1394_it_datalist *itdata) 6659 { 6660 int writepkt; 6661 int i; 6662 u_int8_t *p; 6663 struct fwohci_desc *fd; 6664 u_int32_t *fd_idata; 6665 const int dspace = 6666 itd->itd_maxpacket - itd->itd_npacket < ndata ? 6667 itd->itd_maxpacket - itd->itd_npacket : ndata; 6668 6669 if (itd->itd_flags & ITD_FLAGS_LOCK || dspace == 0) { 6670 /* it is locked: cannot write anything */ 6671 if (itd->itd_flags & ITD_FLAGS_LOCK) { 6672 DPRINTF(("fwohci_itd_writedata: buf %d lock flag %s," 6673 " dspace %d\n", 6674 itd->itd_num, 6675 itd->itd_flags & ITD_FLAGS_LOCK ? "ON" : "OFF", 6676 dspace)); 6677 return 0; /* not an error */ 6678 } 6679 } 6680 6681 /* sanity check */ 6682 if (itd->itd_maxpacket < itd->itd_npacket) { 6683 printf("fwohci_itd_writedata: funny! # pkt > maxpkt" 6684 "%d %d\n", itd->itd_npacket, itd->itd_maxpacket); 6685 } 6686 6687 p = itd->itd_buf + itd->itd_maxsize * itd->itd_npacket; 6688 fd = itd->itd_lastdesc; 6689 6690 DPRINTF(("fwohci_itd_writedata(%d[%p], %d, 0x%p) invoked:\n", 6691 itd->itd_num, itd, ndata, itdata)); 6692 6693 for (writepkt = 0; writepkt < dspace; ++writepkt) { 6694 u_int8_t *p1 = p; 6695 int cpysize; 6696 int totalsize = 0; 6697 6698 DPRINTF(("writing %d ", writepkt)); 6699 6700 for (i = 0; i < 4; ++i) { 6701 switch (itdata->it_cmd[i]&IEEE1394_IT_CMD_MASK) { 6702 case IEEE1394_IT_CMD_IMMED: 6703 memcpy(p1, &itdata->it_u[i].id_data, 8); 6704 p1 += 8; 6705 totalsize += 8; 6706 break; 6707 case IEEE1394_IT_CMD_PTR: 6708 cpysize = itdata->it_cmd[i]&IEEE1394_IT_CMD_SIZE; 6709 DPRINTF(("fwohci_itd_writedata: cpy %d %p\n", 6710 cpysize, itdata->it_u[i].id_addr)); 6711 if (totalsize + cpysize > itd->itd_maxsize) { 6712 /* error: too big size */ 6713 break; 6714 } 6715 memcpy(p1, itdata->it_u[i].id_addr, cpysize); 6716 totalsize += cpysize; 6717 break; 6718 case IEEE1394_IT_CMD_NOP: 6719 break; 6720 default: 6721 /* unknown command */ 6722 break; 6723 } 6724 } 6725 6726 /* only for DV test */ 6727 if (totalsize != 488) { 6728 printf("error: totalsize %d at %d\n", 6729 totalsize, writepkt); 6730 } 6731 6732 DPRINTF(("totalsize %d ", totalsize)); 6733 6734 /* fill iso command in OUTPUT_IMMED descriptor */ 6735 6736 /* XXX: sync cache */ 6737 fd += 2; /* next to first descriptor */ 6738 fd_idata = (u_int32_t *)fd; 6739 6740 /* 6741 * Umm, should tag, channel and tcode be written 6742 * previously in itd_construct? 6743 */ 6744 #if 0 6745 *fd_idata = OHCI_ITHEADER_VAL(TAG, tag) | 6746 OHCI_ITHEADER_VAL(CHAN, ch) | 6747 OHCI_ITHEADER_VAL(TCODE, IEEE1394_TCODE_STREAM_DATA); 6748 #endif 6749 *++fd_idata = totalsize << 16; 6750 6751 /* fill data in OUTPUT_LAST descriptor */ 6752 ++fd; 6753 /* intr check... */ 6754 if (fd->fd_flags & OHCI_DESC_INTR_ALWAYS) { 6755 printf("uncleared INTR flag in desc %ld\n", 6756 (long)(fd - itd->itd_desc - 1)/3); 6757 } 6758 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6759 6760 if ((fd - itd->itd_desc - 1)/3 != itd->itd_maxpacket - 1) { 6761 u_int32_t bcal; 6762 6763 bcal = (fd - itd->itd_desc + 1)*sizeof(struct fwohci_desc) + (u_int32_t)itd->itd_desc_phys; 6764 if (bcal != (fd->fd_branch & 0xfffffff0)) { 6765 6766 printf("uum, branch differ at %d, %x %x %ld/%d\n", 6767 itd->itd_num, 6768 bcal, 6769 fd->fd_branch, 6770 (long)((fd - itd->itd_desc - 1)/3), 6771 itd->itd_maxpacket); 6772 } 6773 } else { 6774 /* the last pcaket */ 6775 if (fd->fd_branch != 0) { 6776 printf("uum, branch differ at %d, %x %x %ld/%d\n", 6777 itd->itd_num, 6778 0, 6779 fd->fd_branch, 6780 (long)((fd - itd->itd_desc - 1)/3), 6781 itd->itd_maxpacket); 6782 } 6783 } 6784 6785 /* sanity check */ 6786 if (fd->fd_flags != OUTPUT_LAST_DESC) { 6787 printf("fwohci_itd_writedata: dmabuf %d desc inconsistent %d\n", 6788 itd->itd_num, writepkt + itd->itd_npacket); 6789 break; 6790 } 6791 fd->fd_reqcount = totalsize; 6792 /* XXX: sync cache */ 6793 6794 ++itdata; 6795 p += itd->itd_maxsize; 6796 } 6797 6798 DPRINTF(("loop start %d, %d times %d\n", 6799 itd->itd_npacket, dspace, writepkt)); 6800 6801 itd->itd_npacket += writepkt; 6802 itd->itd_lastdesc = fd; 6803 6804 return writepkt; 6805 } 6806 6807 6808 6809 6810 6811 int 6812 fwohci_itd_isfilled(struct fwohci_it_dmabuf *itd) 6813 { 6814 6815 return itd->itd_npacket*2 > itd->itd_maxpacket ? 1 : 0; 6816 } 6817
Indexes created Sat Sep 27 22:09:54 GMT 2025