fwohci.c revision 1.73
1 /* $NetBSD: fwohci.c,v 1.73 2003/01/31 02:17:13 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * IEEE1394 Open Host Controller Interface 41 * based on OHCI Specification 1.1 (January 6, 2000) 42 * The first version to support network interface part is wrtten by 43 * Atsushi Onoe <onoe (at) netbsd.org>. 44 */ 45 46 /* 47 * The first version to support isochronous acquisition part is wrtten 48 * by HAYAKAWA Koichi <haya (at) netbsd.org>. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.73 2003/01/31 02:17:13 thorpej Exp $"); 53 54 #define FWOHCI_WAIT_DEBUG 1 55 56 #define FWOHCI_IT_BUFNUM 4 57 58 #include "opt_inet.h" 59 #include "fwiso.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kthread.h> 64 #include <sys/socket.h> 65 #include <sys/callout.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/malloc.h> 69 #include <sys/mbuf.h> 70 #include <sys/poll.h> 71 #include <sys/select.h> 72 73 #if __NetBSD_Version__ >= 105010000 74 #include <uvm/uvm_extern.h> 75 #else 76 #include <vm/vm.h> 77 #endif 78 79 #include <machine/bus.h> 80 #include <machine/intr.h> 81 82 #include <dev/ieee1394/ieee1394reg.h> 83 #include <dev/ieee1394/fwohcireg.h> 84 85 #include <dev/ieee1394/ieee1394var.h> 86 #include <dev/ieee1394/fwohcivar.h> 87 #include <dev/ieee1394/fwisovar.h> 88 89 static const char * const ieee1394_speeds[] = { IEEE1394_SPD_STRINGS }; 90 91 #if 0 92 static int fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, 93 int alignment, bus_dmamap_t *mapp, caddr_t *kvap, int flags); 94 #endif 95 static void fwohci_create_event_thread(void *); 96 static void fwohci_thread_init(void *); 97 98 static void fwohci_event_thread(struct fwohci_softc *); 99 static void fwohci_hw_init(struct fwohci_softc *); 100 static void fwohci_power(int, void *); 101 static void fwohci_shutdown(void *); 102 103 static int fwohci_desc_alloc(struct fwohci_softc *); 104 static struct fwohci_desc *fwohci_desc_get(struct fwohci_softc *, int); 105 static void fwohci_desc_put(struct fwohci_softc *, struct fwohci_desc *, int); 106 107 static int fwohci_ctx_alloc(struct fwohci_softc *, struct fwohci_ctx **, 108 int, int, int); 109 static void fwohci_ctx_free(struct fwohci_softc *, struct fwohci_ctx *); 110 static void fwohci_ctx_init(struct fwohci_softc *, struct fwohci_ctx *); 111 112 static int fwohci_misc_dmabuf_alloc(bus_dma_tag_t, int, int, 113 bus_dma_segment_t *, bus_dmamap_t *, void **, const char *); 114 static void fwohci_misc_dmabuf_free(bus_dma_tag_t, int, int, 115 bus_dma_segment_t *, bus_dmamap_t *, caddr_t); 116 117 static struct fwohci_ir_ctx *fwohci_ir_ctx_construct(struct fwohci_softc *, 118 int, int, int, int, int, int); 119 static void fwohci_ir_ctx_destruct(struct fwohci_ir_ctx *); 120 121 static int fwohci_ir_buf_setup(struct fwohci_ir_ctx *); 122 static int fwohci_ir_init(struct fwohci_ir_ctx *); 123 static int fwohci_ir_start(struct fwohci_ir_ctx *); 124 static void fwohci_ir_intr(struct fwohci_softc *, struct fwohci_ir_ctx *); 125 static int fwohci_ir_stop(struct fwohci_ir_ctx *); 126 static int fwohci_ir_ctx_packetnum(struct fwohci_ir_ctx *); 127 #ifdef USEDRAIN 128 static int fwohci_ir_ctx_drain(struct fwohci_ir_ctx *); 129 #endif /* USEDRAIN */ 130 131 static int fwohci_it_desc_alloc(struct fwohci_it_ctx *); 132 static void fwohci_it_desc_free(struct fwohci_it_ctx *itc); 133 struct fwohci_it_ctx *fwohci_it_ctx_construct(struct fwohci_softc *, 134 int, int, int, int); 135 void fwohci_it_ctx_destruct(struct fwohci_it_ctx *); 136 int fwohci_it_ctx_writedata(ieee1394_it_tag_t, int, 137 struct ieee1394_it_datalist *, int); 138 static void fwohci_it_ctx_run(struct fwohci_it_ctx *); 139 int fwohci_it_ctx_flush(ieee1394_it_tag_t); 140 static void fwohci_it_intr(struct fwohci_softc *, struct fwohci_it_ctx *); 141 142 int fwohci_itd_construct(struct fwohci_it_ctx *, struct fwohci_it_dmabuf *, 143 int, struct fwohci_desc *, bus_addr_t, int, int, paddr_t); 144 void fwohci_itd_destruct(struct fwohci_it_dmabuf *); 145 static int fwohci_itd_dmabuf_alloc(struct fwohci_it_dmabuf *); 146 static void fwohci_itd_dmabuf_free(struct fwohci_it_dmabuf *); 147 int fwohci_itd_link(struct fwohci_it_dmabuf *, struct fwohci_it_dmabuf *); 148 int fwohci_itd_unlink(struct fwohci_it_dmabuf *); 149 int fwohci_itd_writedata(struct fwohci_it_dmabuf *, int, 150 struct ieee1394_it_datalist *); 151 int fwohci_itd_isfilled(struct fwohci_it_dmabuf *); 152 153 static int fwohci_buf_alloc(struct fwohci_softc *, struct fwohci_buf *); 154 static void fwohci_buf_free(struct fwohci_softc *, struct fwohci_buf *); 155 static void fwohci_buf_init_rx(struct fwohci_softc *); 156 static void fwohci_buf_start_rx(struct fwohci_softc *); 157 static void fwohci_buf_stop_tx(struct fwohci_softc *); 158 static void fwohci_buf_stop_rx(struct fwohci_softc *); 159 static void fwohci_buf_next(struct fwohci_softc *, struct fwohci_ctx *); 160 static int fwohci_buf_pktget(struct fwohci_softc *, struct fwohci_buf **, 161 caddr_t *, int); 162 static int fwohci_buf_input(struct fwohci_softc *, struct fwohci_ctx *, 163 struct fwohci_pkt *); 164 static int fwohci_buf_input_ppb(struct fwohci_softc *, struct fwohci_ctx *, 165 struct fwohci_pkt *); 166 167 static u_int8_t fwohci_phy_read(struct fwohci_softc *, u_int8_t); 168 static void fwohci_phy_write(struct fwohci_softc *, u_int8_t, u_int8_t); 169 static void fwohci_phy_busreset(struct fwohci_softc *); 170 static void fwohci_phy_input(struct fwohci_softc *, struct fwohci_pkt *); 171 172 static int fwohci_handler_set(struct fwohci_softc *, int, u_int32_t, u_int32_t, 173 u_int32_t, int (*)(struct fwohci_softc *, void *, struct fwohci_pkt *), 174 void *); 175 176 ieee1394_ir_tag_t fwohci_ir_ctx_set(struct device *, int, int, int, int, int); 177 int fwohci_ir_ctx_clear(struct device *, ieee1394_ir_tag_t); 178 int fwohci_ir_read(struct device *, ieee1394_ir_tag_t, struct uio *, 179 int, int); 180 int fwohci_ir_wait(struct device *, ieee1394_ir_tag_t, void *, char *name); 181 int fwohci_ir_select(struct device *, ieee1394_ir_tag_t, struct proc *); 182 183 184 185 ieee1394_it_tag_t fwohci_it_set(struct ieee1394_softc *, int, int); 186 static ieee1394_it_tag_t fwohci_it_ctx_set(struct fwohci_softc *, int, int, int); 187 int fwohci_it_ctx_clear(ieee1394_it_tag_t *); 188 189 static void fwohci_arrq_input(struct fwohci_softc *, struct fwohci_ctx *); 190 static void fwohci_arrs_input(struct fwohci_softc *, struct fwohci_ctx *); 191 static void fwohci_as_input(struct fwohci_softc *, struct fwohci_ctx *); 192 193 static int fwohci_at_output(struct fwohci_softc *, struct fwohci_ctx *, 194 struct fwohci_pkt *); 195 static void fwohci_at_done(struct fwohci_softc *, struct fwohci_ctx *, int); 196 static void fwohci_atrs_output(struct fwohci_softc *, int, struct fwohci_pkt *, 197 struct fwohci_pkt *); 198 199 static int fwohci_guidrom_init(struct fwohci_softc *); 200 static void fwohci_configrom_init(struct fwohci_softc *); 201 static int fwohci_configrom_input(struct fwohci_softc *, void *, 202 struct fwohci_pkt *); 203 static void fwohci_selfid_init(struct fwohci_softc *); 204 static int fwohci_selfid_input(struct fwohci_softc *); 205 206 static void fwohci_csr_init(struct fwohci_softc *); 207 static int fwohci_csr_input(struct fwohci_softc *, void *, 208 struct fwohci_pkt *); 209 210 static void fwohci_uid_collect(struct fwohci_softc *); 211 static void fwohci_uid_req(struct fwohci_softc *, int); 212 static int fwohci_uid_input(struct fwohci_softc *, void *, 213 struct fwohci_pkt *); 214 static int fwohci_uid_lookup(struct fwohci_softc *, const u_int8_t *); 215 static void fwohci_check_nodes(struct fwohci_softc *); 216 217 static int fwohci_if_inreg(struct device *, u_int32_t, u_int32_t, 218 void (*)(struct device *, struct mbuf *)); 219 static int fwohci_if_input(struct fwohci_softc *, void *, struct fwohci_pkt *); 220 static int fwohci_if_input_iso(struct fwohci_softc *, void *, struct fwohci_pkt *); 221 222 static int fwohci_if_output(struct device *, struct mbuf *, 223 void (*)(struct device *, struct mbuf *)); 224 static int fwohci_if_setiso(struct device *, u_int32_t, u_int32_t, u_int32_t, 225 void (*)(struct device *, struct mbuf *)); 226 static int fwohci_read(struct ieee1394_abuf *); 227 static int fwohci_write(struct ieee1394_abuf *); 228 static int fwohci_read_resp(struct fwohci_softc *, void *, struct fwohci_pkt *); 229 static int fwohci_write_ack(struct fwohci_softc *, void *, struct fwohci_pkt *); 230 static int fwohci_read_multi_resp(struct fwohci_softc *, void *, 231 struct fwohci_pkt *); 232 static int fwohci_inreg(struct ieee1394_abuf *, int); 233 static int fwohci_unreg(struct ieee1394_abuf *, int); 234 static int fwohci_parse_input(struct fwohci_softc *, void *, 235 struct fwohci_pkt *); 236 static int fwohci_submatch(struct device *, struct cfdata *, void *); 237 238 /* XXX */ 239 u_int16_t fwohci_cycletimer(struct fwohci_softc *); 240 u_int16_t fwohci_it_cycletimer(ieee1394_it_tag_t); 241 242 #ifdef FW_DEBUG 243 static void fwohci_show_intr(struct fwohci_softc *, u_int32_t); 244 static void fwohci_show_phypkt(struct fwohci_softc *, u_int32_t); 245 246 /* 1 is normal debug, 2 is verbose debug, 3 is complete (packet dumps). */ 247 248 #define DPRINTF(x) if (fwdebug) printf x 249 #define DPRINTFN(n,x) if (fwdebug>(n)) printf x 250 int fwdebug = 1; 251 #else 252 #define DPRINTF(x) 253 #define DPRINTFN(n,x) 254 #endif 255 256 #define OHCI_ITHEADER_SPD_MASK 0x00070000 257 #define OHCI_ITHEADER_SPD_BITPOS 16 258 #define OHCI_ITHEADER_TAG_MASK 0x0000c000 259 #define OHCI_ITHEADER_TAG_BITPOS 14 260 #define OHCI_ITHEADER_CHAN_MASK 0x00003f00 261 #define OHCI_ITHEADER_CHAN_BITPOS 8 262 #define OHCI_ITHEADER_TCODE_MASK 0x000000f0 263 #define OHCI_ITHEADER_TCODE_BITPOS 4 264 #define OHCI_ITHEADER_SY_MASK 0x0000000f 265 #define OHCI_ITHEADER_SY_BITPOS 0 266 267 #define OHCI_ITHEADER_VAL(fld, val) \ 268 (OHCI_ITHEADER_##fld##_MASK & ((val) << OHCI_ITHEADER_##fld##_BITPOS)) 269 270 int 271 fwohci_init(struct fwohci_softc *sc, const struct evcnt *ev) 272 { 273 int i; 274 u_int32_t val; 275 #if 0 276 int error; 277 #endif 278 279 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ev, 280 sc->sc_sc1394.sc1394_dev.dv_xname, "intr"); 281 282 evcnt_attach_dynamic(&sc->sc_isocnt, EVCNT_TYPE_MISC, ev, 283 sc->sc_sc1394.sc1394_dev.dv_xname, "isorcvs"); 284 evcnt_attach_dynamic(&sc->sc_ascnt, EVCNT_TYPE_MISC, ev, 285 sc->sc_sc1394.sc1394_dev.dv_xname, "asrcvs"); 286 evcnt_attach_dynamic(&sc->sc_itintrcnt, EVCNT_TYPE_INTR, ev, 287 sc->sc_sc1394.sc1394_dev.dv_xname, "itintr"); 288 289 /* 290 * Wait for reset completion 291 */ 292 for (i = 0; i < OHCI_LOOP; i++) { 293 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 294 if ((val & OHCI_HCControl_SoftReset) == 0) 295 break; 296 DELAY(10); 297 } 298 299 /* What dialect of OHCI is this device? 300 */ 301 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 302 aprint_normal("%s: OHCI %u.%u", sc->sc_sc1394.sc1394_dev.dv_xname, 303 OHCI_Version_GET_Version(val), OHCI_Version_GET_Revision(val)); 304 305 LIST_INIT(&sc->sc_nodelist); 306 307 if (fwohci_guidrom_init(sc) != 0) { 308 aprint_error("\n%s: fatal: no global UID ROM\n", 309 sc->sc_sc1394.sc1394_dev.dv_xname); 310 return -1; 311 } 312 313 aprint_normal(", %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 314 sc->sc_sc1394.sc1394_guid[0], sc->sc_sc1394.sc1394_guid[1], 315 sc->sc_sc1394.sc1394_guid[2], sc->sc_sc1394.sc1394_guid[3], 316 sc->sc_sc1394.sc1394_guid[4], sc->sc_sc1394.sc1394_guid[5], 317 sc->sc_sc1394.sc1394_guid[6], sc->sc_sc1394.sc1394_guid[7]); 318 319 /* Get the maximum link speed and receive size 320 */ 321 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 322 sc->sc_sc1394.sc1394_link_speed = 323 OHCI_BITVAL(val, OHCI_BusOptions_LinkSpd); 324 if (sc->sc_sc1394.sc1394_link_speed < IEEE1394_SPD_MAX) { 325 aprint_normal(", %s", 326 ieee1394_speeds[sc->sc_sc1394.sc1394_link_speed]); 327 } else { 328 aprint_normal(", unknown speed %u", 329 sc->sc_sc1394.sc1394_link_speed); 330 } 331 332 /* MaxRec is encoded as log2(max_rec_octets)-1 333 */ 334 sc->sc_sc1394.sc1394_max_receive = 335 1 << (OHCI_BITVAL(val, OHCI_BusOptions_MaxRec) + 1); 336 aprint_normal(", %u max_rec", sc->sc_sc1394.sc1394_max_receive); 337 338 /* 339 * Count how many isochronous receive ctx we have. 340 */ 341 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 342 val = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntMaskClear); 343 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskClear, ~0); 344 for (i = 0; val != 0; val >>= 1) { 345 if (val & 0x1) 346 i++; 347 } 348 sc->sc_isoctx = i; 349 aprint_normal(", %d ir_ctx", sc->sc_isoctx); 350 351 /* 352 * Count how many isochronous transmit ctx we have. 353 */ 354 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 355 val = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntMaskClear); 356 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskClear, ~0); 357 for (i = 0; val != 0; val >>= 1) { 358 if (val & 0x1) { 359 i++; 360 OHCI_SYNC_TX_DMA_WRITE(sc, i,OHCI_SUBREG_CommandPtr,0); 361 } 362 } 363 sc->sc_itctx = i; 364 365 aprint_normal(", %d it_ctx", sc->sc_itctx); 366 367 aprint_normal("\n"); 368 369 #if 0 370 error = fwohci_dnamem_alloc(sc, OHCI_CONFIG_SIZE, 371 OHCI_CONFIG_ALIGNMENT, &sc->sc_configrom_map, 372 (caddr_t *) &sc->sc_configrom, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 373 return error; 374 #endif 375 376 sc->sc_dying = 0; 377 sc->sc_nodeid = 0xffff; /* invalid */ 378 379 sc->sc_sc1394.sc1394_callback.sc1394_read = fwohci_read; 380 sc->sc_sc1394.sc1394_callback.sc1394_write = fwohci_write; 381 sc->sc_sc1394.sc1394_callback.sc1394_inreg = fwohci_inreg; 382 sc->sc_sc1394.sc1394_callback.sc1394_unreg = fwohci_unreg; 383 384 kthread_create(fwohci_create_event_thread, sc); 385 return 0; 386 } 387 388 static int 389 fwohci_if_setiso(struct device *self, u_int32_t channel, u_int32_t tag, 390 u_int32_t direction, void (*handler)(struct device *, struct mbuf *)) 391 { 392 struct fwohci_softc *sc = (struct fwohci_softc *)self; 393 int retval; 394 int s; 395 396 if (direction == 1) { 397 return EIO; 398 } 399 400 s = splnet(); 401 retval = fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 402 channel, 1 << tag, 0, fwohci_if_input_iso, handler); 403 splx(s); 404 405 if (!retval) { 406 printf("%s: dummy iso handler set\n", 407 sc->sc_sc1394.sc1394_dev.dv_xname); 408 } else { 409 printf("%s: dummy iso handler cannot set\n", 410 sc->sc_sc1394.sc1394_dev.dv_xname); 411 } 412 413 return retval; 414 } 415 416 int 417 fwohci_intr(void *arg) 418 { 419 struct fwohci_softc * const sc = arg; 420 int progress = 0; 421 u_int32_t intmask, iso; 422 423 for (;;) { 424 intmask = OHCI_CSR_READ(sc, OHCI_REG_IntEventClear); 425 426 /* 427 * On a bus reset, everything except bus reset gets 428 * cleared. That can't get cleared until the selfid 429 * phase completes (which happens outside the 430 * interrupt routines). So if just a bus reset is left 431 * in the mask and it's already in the sc_intmask, 432 * just return. 433 */ 434 435 if ((intmask == 0) || 436 (progress && (intmask == OHCI_Int_BusReset) && 437 (sc->sc_intmask & OHCI_Int_BusReset))) { 438 if (progress) 439 wakeup(fwohci_event_thread); 440 return progress; 441 } 442 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 443 intmask & ~OHCI_Int_BusReset); 444 #ifdef FW_DEBUG 445 if (fwdebug > 1) 446 fwohci_show_intr(sc, intmask); 447 #endif 448 449 if (intmask & OHCI_Int_BusReset) { 450 /* 451 * According to OHCI spec 6.1.1 "busReset", 452 * All asynchronous transmit must be stopped before 453 * clearing BusReset. Moreover, the BusReset 454 * interrupt bit should not be cleared during the 455 * SelfID phase. Thus we turned off interrupt mask 456 * bit of BusReset instead until SelfID completion 457 * or SelfID timeout. 458 */ 459 intmask &= OHCI_Int_SelfIDComplete; 460 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, 461 OHCI_Int_BusReset); 462 sc->sc_intmask = OHCI_Int_BusReset; 463 } 464 sc->sc_intmask |= intmask; 465 466 if (intmask & OHCI_Int_IsochTx) { 467 int i; 468 469 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear); 470 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntEventClear, iso); 471 472 sc->sc_itintrcnt.ev_count++; 473 for (i = 0; i < sc->sc_itctx; ++i) { 474 if ((iso & (1<<i)) == 0 || 475 sc->sc_ctx_it[i] == NULL) { 476 continue; 477 } 478 479 fwohci_it_intr(sc, sc->sc_ctx_it[i]); 480 } 481 } 482 if (intmask & OHCI_Int_IsochRx) { 483 int i; 484 485 iso = OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear); 486 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, iso); 487 488 for (i = 0; i < sc->sc_isoctx; i++) { 489 if ((iso & (1 << i)) 490 && sc->sc_ctx_ir[i] != NULL) { 491 iso &= ~(1 << i); 492 fwohci_ir_intr(sc, sc->sc_ctx_ir[i]); 493 } 494 } 495 496 if (iso == 0) { 497 sc->sc_intmask &= ~OHCI_Int_IsochRx; 498 } 499 sc->sc_iso |= iso; 500 } 501 502 if (!progress) { 503 sc->sc_intrcnt.ev_count++; 504 progress = 1; 505 } 506 } 507 } 508 509 static void 510 fwohci_create_event_thread(void *arg) 511 { 512 struct fwohci_softc *sc = arg; 513 514 if (kthread_create1(fwohci_thread_init, sc, &sc->sc_event_thread, "%s", 515 sc->sc_sc1394.sc1394_dev.dv_xname)) { 516 printf("%s: unable to create event thread\n", 517 sc->sc_sc1394.sc1394_dev.dv_xname); 518 panic("fwohci_create_event_thread"); 519 } 520 } 521 522 static void 523 fwohci_thread_init(void *arg) 524 { 525 struct fwohci_softc *sc = arg; 526 int i; 527 528 /* 529 * Allocate descriptors 530 */ 531 if (fwohci_desc_alloc(sc)) { 532 printf("%s: not enabling interrupts\n", 533 sc->sc_sc1394.sc1394_dev.dv_xname); 534 kthread_exit(1); 535 } 536 537 /* 538 * Enable Link Power 539 */ 540 541 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 542 543 /* 544 * Allocate DMA Context 545 */ 546 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrq, OHCI_BUF_ARRQ_CNT, 547 OHCI_CTX_ASYNC_RX_REQUEST, FWOHCI_CTX_ASYNC); 548 fwohci_ctx_alloc(sc, &sc->sc_ctx_arrs, OHCI_BUF_ARRS_CNT, 549 OHCI_CTX_ASYNC_RX_RESPONSE, FWOHCI_CTX_ASYNC); 550 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrq, 0, OHCI_CTX_ASYNC_TX_REQUEST, 551 FWOHCI_CTX_ASYNC); 552 fwohci_ctx_alloc(sc, &sc->sc_ctx_atrs, 0, OHCI_CTX_ASYNC_TX_RESPONSE, 553 FWOHCI_CTX_ASYNC); 554 sc->sc_ctx_as = malloc(sizeof(sc->sc_ctx_as[0]) * sc->sc_isoctx, 555 M_DEVBUF, M_WAITOK); 556 if (sc->sc_ctx_as == NULL) { 557 printf("no asynchronous stream\n"); 558 } else { 559 for (i = 0; i < sc->sc_isoctx; i++) 560 sc->sc_ctx_as[i] = NULL; 561 } 562 sc->sc_ctx_ir = malloc(sizeof(sc->sc_ctx_ir[0]) * sc->sc_isoctx, 563 M_DEVBUF, M_WAITOK|M_ZERO); 564 sc->sc_ctx_it = malloc(sizeof(sc->sc_ctx_it[0]) * sc->sc_itctx, 565 M_DEVBUF, M_WAITOK|M_ZERO); 566 567 /* 568 * Allocate buffer for configuration ROM and SelfID buffer 569 */ 570 fwohci_buf_alloc(sc, &sc->sc_buf_cnfrom); 571 fwohci_buf_alloc(sc, &sc->sc_buf_selfid); 572 573 callout_init(&sc->sc_selfid_callout); 574 575 sc->sc_sc1394.sc1394_ifinreg = fwohci_if_inreg; 576 sc->sc_sc1394.sc1394_ifoutput = fwohci_if_output; 577 sc->sc_sc1394.sc1394_ifsetiso = fwohci_if_setiso; 578 579 sc->sc_sc1394.sc1394_ir_open = fwohci_ir_ctx_set; 580 sc->sc_sc1394.sc1394_ir_close = fwohci_ir_ctx_clear; 581 sc->sc_sc1394.sc1394_ir_read = fwohci_ir_read; 582 sc->sc_sc1394.sc1394_ir_wait = fwohci_ir_wait; 583 sc->sc_sc1394.sc1394_ir_select = fwohci_ir_select; 584 585 #if 0 586 sc->sc_sc1394.sc1394_it_open = fwohci_it_open; 587 sc->sc_sc1394.sc1394_it_write = fwohci_it_write; 588 sc->sc_sc1394.sc1394_it_close = fwohci_it_close; 589 /* XXX: need fwohci_it_flush? */ 590 #endif 591 592 /* 593 * establish hooks for shutdown and suspend/resume 594 */ 595 sc->sc_shutdownhook = shutdownhook_establish(fwohci_shutdown, sc); 596 sc->sc_powerhook = powerhook_establish(fwohci_power, sc); 597 598 sc->sc_sc1394.sc1394_if = config_found(&sc->sc_sc1394.sc1394_dev, "fw", 599 fwohci_print); 600 601 #if NFWISO > 0 602 fwiso_register_if(&sc->sc_sc1394); 603 #endif 604 605 /* Main loop. It's not coming back normally. */ 606 607 fwohci_event_thread(sc); 608 609 kthread_exit(0); 610 } 611 612 static void 613 fwohci_event_thread(struct fwohci_softc *sc) 614 { 615 int i, s; 616 u_int32_t intmask, iso; 617 618 s = splbio(); 619 620 /* 621 * Initialize hardware registers. 622 */ 623 624 fwohci_hw_init(sc); 625 626 /* Initial Bus Reset */ 627 fwohci_phy_busreset(sc); 628 splx(s); 629 630 while (!sc->sc_dying) { 631 s = splbio(); 632 intmask = sc->sc_intmask; 633 if (intmask == 0) { 634 tsleep(fwohci_event_thread, PZERO, "fwohciev", 0); 635 splx(s); 636 continue; 637 } 638 sc->sc_intmask = 0; 639 splx(s); 640 641 if (intmask & OHCI_Int_BusReset) { 642 fwohci_buf_stop_tx(sc); 643 if (sc->sc_uidtbl != NULL) { 644 free(sc->sc_uidtbl, M_DEVBUF); 645 sc->sc_uidtbl = NULL; 646 } 647 648 callout_reset(&sc->sc_selfid_callout, 649 OHCI_SELFID_TIMEOUT, 650 (void (*)(void *))fwohci_phy_busreset, sc); 651 sc->sc_nodeid = 0xffff; /* indicate invalid */ 652 sc->sc_rootid = 0; 653 sc->sc_irmid = IEEE1394_BCAST_PHY_ID; 654 } 655 if (intmask & OHCI_Int_SelfIDComplete) { 656 s = splbio(); 657 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 658 OHCI_Int_BusReset); 659 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, 660 OHCI_Int_BusReset); 661 splx(s); 662 callout_stop(&sc->sc_selfid_callout); 663 if (fwohci_selfid_input(sc) == 0) { 664 fwohci_buf_start_rx(sc); 665 fwohci_uid_collect(sc); 666 } 667 } 668 if (intmask & OHCI_Int_ReqTxComplete) 669 fwohci_at_done(sc, sc->sc_ctx_atrq, 0); 670 if (intmask & OHCI_Int_RespTxComplete) 671 fwohci_at_done(sc, sc->sc_ctx_atrs, 0); 672 if (intmask & OHCI_Int_RQPkt) 673 fwohci_arrq_input(sc, sc->sc_ctx_arrq); 674 if (intmask & OHCI_Int_RSPkt) 675 fwohci_arrs_input(sc, sc->sc_ctx_arrs); 676 if (intmask & OHCI_Int_IsochRx) { 677 if (sc->sc_ctx_as == NULL) { 678 continue; 679 } 680 s = splbio(); 681 iso = sc->sc_iso; 682 sc->sc_iso = 0; 683 splx(s); 684 for (i = 0; i < sc->sc_isoctx; i++) { 685 if ((iso & (1 << i)) && 686 sc->sc_ctx_as[i] != NULL) { 687 fwohci_as_input(sc, sc->sc_ctx_as[i]); 688 sc->sc_ascnt.ev_count++; 689 } 690 } 691 } 692 } 693 } 694 695 #if 0 696 static int 697 fwohci_dnamem_alloc(struct fwohci_softc *sc, int size, int alignment, 698 bus_dmamap_t *mapp, caddr_t *kvap, int flags) 699 { 700 bus_dma_segment_t segs[1]; 701 int error, nsegs, steps; 702 703 steps = 0; 704 error = bus_dmamem_alloc(sc->sc_dmat, size, alignment, alignment, 705 segs, 1, &nsegs, flags); 706 if (error) 707 goto cleanup; 708 709 steps = 1; 710 error = bus_dmamem_map(sc->sc_dmat, segs, nsegs, segs[0].ds_len, 711 kvap, flags); 712 if (error) 713 goto cleanup; 714 715 if (error == 0) 716 error = bus_dmamap_create(sc->sc_dmat, size, 1, alignment, 717 size, flags, mapp); 718 if (error) 719 goto cleanup; 720 if (error == 0) 721 error = bus_dmamap_load(sc->sc_dmat, *mapp, *kvap, size, NULL, 722 flags); 723 if (error) 724 goto cleanup; 725 726 cleanup: 727 switch (steps) { 728 case 1: 729 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 730 } 731 732 return error; 733 } 734 #endif 735 736 int 737 fwohci_print(void *aux, const char *pnp) 738 { 739 char *name = aux; 740 741 if (pnp) 742 aprint_normal("%s at %s", name, pnp); 743 744 return UNCONF; 745 } 746 747 static void 748 fwohci_hw_init(struct fwohci_softc *sc) 749 { 750 int i; 751 u_int32_t val; 752 753 /* 754 * Software Reset. 755 */ 756 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 757 for (i = 0; i < OHCI_LOOP; i++) { 758 val = OHCI_CSR_READ(sc, OHCI_REG_HCControlClear); 759 if ((val & OHCI_HCControl_SoftReset) == 0) 760 break; 761 DELAY(10); 762 } 763 764 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LPS); 765 766 /* 767 * First, initilize CSRs with undefined value to default settings. 768 */ 769 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 770 val |= OHCI_BusOptions_ISC | OHCI_BusOptions_CMC; 771 #if 0 772 val |= OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC; 773 #else 774 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_IRMC); 775 #endif 776 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 777 for (i = 0; i < sc->sc_isoctx; i++) { 778 OHCI_SYNC_RX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 779 ~0); 780 } 781 for (i = 0; i < sc->sc_itctx; i++) { 782 OHCI_SYNC_TX_DMA_WRITE(sc, i, OHCI_SUBREG_ContextControlClear, 783 ~0); 784 } 785 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, ~0); 786 787 fwohci_configrom_init(sc); 788 fwohci_selfid_init(sc); 789 fwohci_buf_init_rx(sc); 790 fwohci_csr_init(sc); 791 792 /* 793 * Final CSR settings. 794 */ 795 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 796 OHCI_LinkControl_CycleTimerEnable | 797 OHCI_LinkControl_RcvSelfID | OHCI_LinkControl_RcvPhyPkt); 798 799 OHCI_CSR_WRITE(sc, OHCI_REG_ATRetries, 0x00000888); /*XXX*/ 800 801 /* clear receive filter */ 802 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiClear, ~0); 803 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoClear, ~0); 804 OHCI_CSR_WRITE(sc, OHCI_REG_AsynchronousRequestFilterHiSet, 0x80000000); 805 806 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, 807 OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable); 808 #if BYTE_ORDER == BIG_ENDIAN 809 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 810 OHCI_HCControl_NoByteSwapData); 811 #endif 812 813 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0); 814 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset | 815 OHCI_Int_SelfIDComplete | OHCI_Int_IsochRx | OHCI_Int_IsochTx | 816 OHCI_Int_RSPkt | OHCI_Int_RQPkt | OHCI_Int_ARRS | OHCI_Int_ARRQ | 817 OHCI_Int_RespTxComplete | OHCI_Int_ReqTxComplete); 818 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_CycleTooLong | 819 OHCI_Int_UnrecoverableError | OHCI_Int_CycleInconsistent | 820 OHCI_Int_LockRespErr | OHCI_Int_PostedWriteErr); 821 OHCI_CSR_WRITE(sc, OHCI_REG_IsoXmitIntMaskSet, ~0); 822 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntMaskSet, ~0); 823 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_MasterEnable); 824 825 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_LinkEnable); 826 827 /* 828 * Start the receivers 829 */ 830 fwohci_buf_start_rx(sc); 831 } 832 833 static void 834 fwohci_power(int why, void *arg) 835 { 836 struct fwohci_softc *sc = arg; 837 int s; 838 839 s = splbio(); 840 switch (why) { 841 case PWR_SUSPEND: 842 case PWR_STANDBY: 843 fwohci_shutdown(sc); 844 break; 845 case PWR_RESUME: 846 fwohci_hw_init(sc); 847 fwohci_phy_busreset(sc); 848 break; 849 case PWR_SOFTSUSPEND: 850 case PWR_SOFTSTANDBY: 851 case PWR_SOFTRESUME: 852 break; 853 } 854 splx(s); 855 } 856 857 static void 858 fwohci_shutdown(void *arg) 859 { 860 struct fwohci_softc *sc = arg; 861 u_int32_t val; 862 863 callout_stop(&sc->sc_selfid_callout); 864 /* disable all interrupt */ 865 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 866 fwohci_buf_stop_tx(sc); 867 fwohci_buf_stop_rx(sc); 868 val = OHCI_CSR_READ(sc, OHCI_REG_BusOptions); 869 val &= ~(OHCI_BusOptions_BMC | OHCI_BusOptions_ISC | 870 OHCI_BusOptions_CMC | OHCI_BusOptions_IRMC); 871 OHCI_CSR_WRITE(sc, OHCI_REG_BusOptions, val); 872 fwohci_phy_busreset(sc); 873 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LinkEnable); 874 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear, OHCI_HCControl_LPS); 875 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, OHCI_HCControl_SoftReset); 876 } 877 878 /* 879 * COMMON FUNCTIONS 880 */ 881 882 /* 883 * read the PHY Register. 884 */ 885 static u_int8_t 886 fwohci_phy_read(struct fwohci_softc *sc, u_int8_t reg) 887 { 888 int i; 889 u_int32_t val; 890 891 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, 892 OHCI_PhyControl_RdReg | (reg << OHCI_PhyControl_RegAddr_BITPOS)); 893 for (i = 0; i < OHCI_LOOP; i++) { 894 if (OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 895 OHCI_PhyControl_RdDone) 896 break; 897 DELAY(10); 898 } 899 val = OHCI_CSR_READ(sc, OHCI_REG_PhyControl); 900 return (val & OHCI_PhyControl_RdData) >> OHCI_PhyControl_RdData_BITPOS; 901 } 902 903 /* 904 * write the PHY Register. 905 */ 906 static void 907 fwohci_phy_write(struct fwohci_softc *sc, u_int8_t reg, u_int8_t val) 908 { 909 int i; 910 911 OHCI_CSR_WRITE(sc, OHCI_REG_PhyControl, OHCI_PhyControl_WrReg | 912 (reg << OHCI_PhyControl_RegAddr_BITPOS) | 913 (val << OHCI_PhyControl_WrData_BITPOS)); 914 for (i = 0; i < OHCI_LOOP; i++) { 915 if (!(OHCI_CSR_READ(sc, OHCI_REG_PhyControl) & 916 OHCI_PhyControl_WrReg)) 917 break; 918 DELAY(10); 919 } 920 } 921 922 /* 923 * Initiate Bus Reset 924 */ 925 static void 926 fwohci_phy_busreset(struct fwohci_softc *sc) 927 { 928 int s; 929 u_int8_t val; 930 931 s = splbio(); 932 OHCI_CSR_WRITE(sc, OHCI_REG_IntEventClear, 933 OHCI_Int_BusReset | OHCI_Int_SelfIDComplete); 934 OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset); 935 callout_stop(&sc->sc_selfid_callout); 936 val = fwohci_phy_read(sc, 1); 937 val = (val & 0x80) | /* preserve RHB (force root) */ 938 0x40 | /* Initiate Bus Reset */ 939 0x3f; /* default GAP count */ 940 fwohci_phy_write(sc, 1, val); 941 splx(s); 942 } 943 944 /* 945 * PHY Packet 946 */ 947 static void 948 fwohci_phy_input(struct fwohci_softc *sc, struct fwohci_pkt *pkt) 949 { 950 u_int32_t val; 951 952 val = pkt->fp_hdr[1]; 953 if (val != ~pkt->fp_hdr[2]) { 954 if (val == 0 && ((*pkt->fp_trail & 0x001f0000) >> 16) == 955 OHCI_CTXCTL_EVENT_BUS_RESET) { 956 DPRINTFN(1, ("fwohci_phy_input: BusReset: 0x%08x\n", 957 pkt->fp_hdr[2])); 958 } else { 959 printf("%s: phy packet corrupted (0x%08x, 0x%08x)\n", 960 sc->sc_sc1394.sc1394_dev.dv_xname, val, 961 pkt->fp_hdr[2]); 962 } 963 return; 964 } 965 #ifdef FW_DEBUG 966 if (fwdebug > 1) 967 fwohci_show_phypkt(sc, val); 968 #endif 969 } 970 971 /* 972 * Descriptor for context DMA. 973 */ 974 static int 975 fwohci_desc_alloc(struct fwohci_softc *sc) 976 { 977 int error, mapsize, dsize; 978 979 /* 980 * allocate descriptor buffer 981 */ 982 983 sc->sc_descsize = OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + 984 OHCI_BUF_ATRQ_CNT + OHCI_BUF_ATRS_CNT + 985 OHCI_BUF_IR_CNT * sc->sc_isoctx + 2; 986 dsize = sizeof(struct fwohci_desc) * sc->sc_descsize; 987 mapsize = howmany(sc->sc_descsize, NBBY); 988 sc->sc_descmap = malloc(mapsize, M_DEVBUF, M_WAITOK|M_ZERO); 989 990 if (sc->sc_descmap == NULL) { 991 printf("fwohci_desc_alloc: cannot get memory\n"); 992 return -1; 993 } 994 995 if ((error = bus_dmamem_alloc(sc->sc_dmat, dsize, PAGE_SIZE, 0, 996 &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 997 printf("%s: unable to allocate descriptor buffer, error = %d\n", 998 sc->sc_sc1394.sc1394_dev.dv_xname, error); 999 goto fail_0; 1000 } 1001 1002 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 1003 dsize, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT | BUS_DMA_WAITOK)) 1004 != 0) { 1005 printf("%s: unable to map descriptor buffer, error = %d\n", 1006 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1007 goto fail_1; 1008 } 1009 1010 if ((error = bus_dmamap_create(sc->sc_dmat, dsize, sc->sc_dnseg, 1011 dsize, 0, BUS_DMA_WAITOK, &sc->sc_ddmamap)) != 0) { 1012 printf("%s: unable to create descriptor buffer DMA map, " 1013 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 1014 goto fail_2; 1015 } 1016 1017 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 1018 dsize, NULL, BUS_DMA_WAITOK)) != 0) { 1019 printf("%s: unable to load descriptor buffer DMA map, " 1020 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, error); 1021 goto fail_3; 1022 } 1023 1024 return 0; 1025 1026 fail_3: 1027 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1028 fail_2: 1029 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, dsize); 1030 fail_1: 1031 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 1032 fail_0: 1033 return error; 1034 } 1035 1036 static struct fwohci_desc * 1037 fwohci_desc_get(struct fwohci_softc *sc, int ndesc) 1038 { 1039 int i, n; 1040 1041 for (n = 0; n <= sc->sc_descsize - ndesc; n++) { 1042 for (i = 0; ; i++) { 1043 if (i == ndesc) { 1044 for (i = 0; i < ndesc; i++) 1045 setbit(sc->sc_descmap, n + i); 1046 return sc->sc_desc + n; 1047 } 1048 if (isset(sc->sc_descmap, n + i)) 1049 break; 1050 } 1051 } 1052 return NULL; 1053 } 1054 1055 static void 1056 fwohci_desc_put(struct fwohci_softc *sc, struct fwohci_desc *fd, int ndesc) 1057 { 1058 int i, n; 1059 1060 n = fd - sc->sc_desc; 1061 for (i = 0; i < ndesc; i++, n++) { 1062 #ifdef DIAGNOSTIC 1063 if (isclr(sc->sc_descmap, n)) 1064 panic("fwohci_desc_put: duplicated free"); 1065 #endif 1066 clrbit(sc->sc_descmap, n); 1067 } 1068 } 1069 1070 /* 1071 * Asynchronous/Isochronous Transmit/Receive Context 1072 */ 1073 static int 1074 fwohci_ctx_alloc(struct fwohci_softc *sc, struct fwohci_ctx **fcp, 1075 int bufcnt, int ctx, int ctxtype) 1076 { 1077 int i, error; 1078 struct fwohci_ctx *fc; 1079 struct fwohci_buf *fb; 1080 struct fwohci_desc *fd; 1081 #if DOUBLEBUF 1082 int buf2cnt; 1083 #endif 1084 1085 fc = malloc(sizeof(*fc), M_DEVBUF, M_WAITOK|M_ZERO); 1086 LIST_INIT(&fc->fc_handler); 1087 TAILQ_INIT(&fc->fc_buf); 1088 fc->fc_ctx = ctx; 1089 fc->fc_buffers = fb = malloc(sizeof(*fb) * bufcnt, M_DEVBUF, M_WAITOK|M_ZERO); 1090 fc->fc_bufcnt = bufcnt; 1091 #if DOUBLEBUF 1092 TAILQ_INIT(&fc->fc_buf2); /* for isochronous */ 1093 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 1094 buf2cnt = bufcnt/2; 1095 bufcnt -= buf2cnt; 1096 if (buf2cnt == 0) { 1097 panic("cannot allocate iso buffer"); 1098 } 1099 } 1100 #endif 1101 for (i = 0; i < bufcnt; i++, fb++) { 1102 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 1103 goto fail; 1104 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 1105 error = ENOBUFS; 1106 goto fail; 1107 } 1108 fb->fb_desc = fd; 1109 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1110 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1111 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1112 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1113 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1114 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1115 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1116 } 1117 #if DOUBLEBUF 1118 if (ctxtype == FWOHCI_CTX_ISO_MULTI) { 1119 for (i = bufcnt; i < bufcnt + buf2cnt; i++, fb++) { 1120 if ((error = fwohci_buf_alloc(sc, fb)) != 0) 1121 goto fail; 1122 if ((fd = fwohci_desc_get(sc, 1)) == NULL) { 1123 error = ENOBUFS; 1124 goto fail; 1125 } 1126 fb->fb_desc = fd; 1127 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 1128 ((caddr_t)fd - (caddr_t)sc->sc_desc); 1129 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1130 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1131 BUS_DMASYNC_PREWRITE); 1132 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_STATUS | 1133 OHCI_DESC_INTR_ALWAYS | OHCI_DESC_BRANCH; 1134 fd->fd_reqcount = fb->fb_dmamap->dm_segs[0].ds_len; 1135 fd->fd_data = fb->fb_dmamap->dm_segs[0].ds_addr; 1136 TAILQ_INSERT_TAIL(&fc->fc_buf2, fb, fb_list); 1137 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1138 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1139 BUS_DMASYNC_POSTWRITE); 1140 } 1141 } 1142 #endif /* DOUBLEBUF */ 1143 fc->fc_type = ctxtype; 1144 *fcp = fc; 1145 return 0; 1146 1147 fail: 1148 while (i-- > 0) { 1149 fb--; 1150 if (fb->fb_desc) 1151 fwohci_desc_put(sc, fb->fb_desc, 1); 1152 fwohci_buf_free(sc, fb); 1153 } 1154 free(fc, M_DEVBUF); 1155 return error; 1156 } 1157 1158 static void 1159 fwohci_ctx_free(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1160 { 1161 struct fwohci_buf *fb; 1162 struct fwohci_handler *fh; 1163 1164 #if DOUBLEBUF 1165 if ((fc->fc_type == FWOHCI_CTX_ISO_MULTI) && 1166 (TAILQ_FIRST(&fc->fc_buf) > TAILQ_FIRST(&fc->fc_buf2))) { 1167 struct fwohci_buf_s fctmp; 1168 1169 fctmp = fc->fc_buf; 1170 fc->fc_buf = fc->fc_buf2; 1171 fc->fc_buf2 = fctmp; 1172 } 1173 #endif 1174 while ((fh = LIST_FIRST(&fc->fc_handler)) != NULL) 1175 fwohci_handler_set(sc, fh->fh_tcode, fh->fh_key1, fh->fh_key2, 1176 fh->fh_key3, NULL, NULL); 1177 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1178 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1179 if (fb->fb_desc) 1180 fwohci_desc_put(sc, fb->fb_desc, 1); 1181 fwohci_buf_free(sc, fb); 1182 } 1183 #if DOUBLEBUF 1184 while ((fb = TAILQ_FIRST(&fc->fc_buf2)) != NULL) { 1185 TAILQ_REMOVE(&fc->fc_buf2, fb, fb_list); 1186 if (fb->fb_desc) 1187 fwohci_desc_put(sc, fb->fb_desc, 1); 1188 fwohci_buf_free(sc, fb); 1189 } 1190 #endif /* DOUBLEBUF */ 1191 free(fc->fc_buffers, M_DEVBUF); 1192 free(fc, M_DEVBUF); 1193 } 1194 1195 static void 1196 fwohci_ctx_init(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1197 { 1198 struct fwohci_buf *fb, *nfb; 1199 struct fwohci_desc *fd; 1200 struct fwohci_handler *fh; 1201 int n; 1202 1203 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; fb = nfb) { 1204 nfb = TAILQ_NEXT(fb, fb_list); 1205 fb->fb_off = 0; 1206 fd = fb->fb_desc; 1207 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1208 fd->fd_rescount = fd->fd_reqcount; 1209 } 1210 1211 #if DOUBLEBUF 1212 for (fb = TAILQ_FIRST(&fc->fc_buf2); fb != NULL; fb = nfb) { 1213 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1214 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1215 BUS_DMASYNC_PREWRITE); 1216 nfb = TAILQ_NEXT(fb, fb_list); 1217 fb->fb_off = 0; 1218 fd = fb->fb_desc; 1219 fd->fd_branch = (nfb != NULL) ? (nfb->fb_daddr | 1) : 0; 1220 fd->fd_rescount = fd->fd_reqcount; 1221 bus_dmamap_sync(sc->sc_dmat, sc->sc_ddmamap, 1222 (caddr_t)fd - (caddr_t)sc->sc_desc, sizeof(struct fwohci_desc), 1223 BUS_DMASYNC_POSTWRITE); 1224 } 1225 #endif /* DOUBLEBUF */ 1226 1227 n = fc->fc_ctx; 1228 fb = TAILQ_FIRST(&fc->fc_buf); 1229 if (fc->fc_type != FWOHCI_CTX_ASYNC) { 1230 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1231 fb->fb_daddr | 1); 1232 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 1233 OHCI_CTXCTL_RX_BUFFER_FILL | 1234 OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE | 1235 OHCI_CTXCTL_RX_MULTI_CHAN_MODE | 1236 OHCI_CTXCTL_RX_DUAL_BUFFER_MODE); 1237 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 1238 OHCI_CTXCTL_RX_ISOCH_HEADER); 1239 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1240 OHCI_SYNC_RX_DMA_WRITE(sc, n, 1241 OHCI_SUBREG_ContextControlSet, 1242 OHCI_CTXCTL_RX_BUFFER_FILL); 1243 } 1244 fh = LIST_FIRST(&fc->fc_handler); 1245 1246 if (fh->fh_key1 == IEEE1394_ISO_CHANNEL_ANY) { 1247 OHCI_SYNC_RX_DMA_WRITE(sc, n, 1248 OHCI_SUBREG_ContextControlSet, 1249 OHCI_CTXCTL_RX_MULTI_CHAN_MODE); 1250 1251 /* Receive all the isochronous channels */ 1252 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiSet, 1253 0xffffffff); 1254 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoSet, 1255 0xffffffff); 1256 DPRINTF(("%s: CTXCTL 0x%08x\n", 1257 sc->sc_sc1394.sc1394_dev.dv_xname, 1258 OHCI_SYNC_RX_DMA_READ(sc, n, 1259 OHCI_SUBREG_ContextControlSet))); 1260 } 1261 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, 1262 (fh->fh_key2 << OHCI_CTXMATCH_TAG_BITPOS) | 1263 (fh->fh_key1 & IEEE1394_ISO_CHANNEL_MASK)); 1264 } else { 1265 OHCI_ASYNC_DMA_WRITE(sc, n, OHCI_SUBREG_CommandPtr, 1266 fb->fb_daddr | 1); 1267 } 1268 } 1269 1270 /* 1271 * DMA data buffer 1272 */ 1273 static int 1274 fwohci_buf_alloc(struct fwohci_softc *sc, struct fwohci_buf *fb) 1275 { 1276 int error; 1277 1278 if ((error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 1279 PAGE_SIZE, &fb->fb_seg, 1, &fb->fb_nseg, BUS_DMA_WAITOK)) != 0) { 1280 printf("%s: unable to allocate buffer, error = %d\n", 1281 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1282 goto fail_0; 1283 } 1284 1285 if ((error = bus_dmamem_map(sc->sc_dmat, &fb->fb_seg, 1286 fb->fb_nseg, PAGE_SIZE, &fb->fb_buf, BUS_DMA_WAITOK)) != 0) { 1287 printf("%s: unable to map buffer, error = %d\n", 1288 sc->sc_sc1394.sc1394_dev.dv_xname, error); 1289 goto fail_1; 1290 } 1291 1292 if ((error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, fb->fb_nseg, 1293 PAGE_SIZE, 0, BUS_DMA_WAITOK, &fb->fb_dmamap)) != 0) { 1294 printf("%s: unable to create buffer DMA map, " 1295 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1296 error); 1297 goto fail_2; 1298 } 1299 1300 if ((error = bus_dmamap_load(sc->sc_dmat, fb->fb_dmamap, 1301 fb->fb_buf, PAGE_SIZE, NULL, BUS_DMA_WAITOK)) != 0) { 1302 printf("%s: unable to load buffer DMA map, " 1303 "error = %d\n", sc->sc_sc1394.sc1394_dev.dv_xname, 1304 error); 1305 goto fail_3; 1306 } 1307 1308 return 0; 1309 1310 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1311 fail_3: 1312 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1313 fail_2: 1314 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1315 fail_1: 1316 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1317 fail_0: 1318 return error; 1319 } 1320 1321 static void 1322 fwohci_buf_free(struct fwohci_softc *sc, struct fwohci_buf *fb) 1323 { 1324 1325 bus_dmamap_unload(sc->sc_dmat, fb->fb_dmamap); 1326 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 1327 bus_dmamem_unmap(sc->sc_dmat, fb->fb_buf, PAGE_SIZE); 1328 bus_dmamem_free(sc->sc_dmat, &fb->fb_seg, fb->fb_nseg); 1329 } 1330 1331 static void 1332 fwohci_buf_init_rx(struct fwohci_softc *sc) 1333 { 1334 int i; 1335 1336 /* 1337 * Initialize for Asynchronous Receive Queue. 1338 */ 1339 fwohci_ctx_init(sc, sc->sc_ctx_arrq); 1340 fwohci_ctx_init(sc, sc->sc_ctx_arrs); 1341 1342 /* 1343 * Initialize for Isochronous Receive Queue. 1344 */ 1345 if (sc->sc_ctx_as != NULL) { 1346 for (i = 0; i < sc->sc_isoctx; i++) { 1347 if (sc->sc_ctx_as[i] != NULL) 1348 fwohci_ctx_init(sc, sc->sc_ctx_as[i]); 1349 } 1350 } 1351 } 1352 1353 static void 1354 fwohci_buf_start_rx(struct fwohci_softc *sc) 1355 { 1356 int i; 1357 1358 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1359 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1360 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1361 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1362 if (sc->sc_ctx_as != NULL) { 1363 for (i = 0; i < sc->sc_isoctx; i++) { 1364 if (sc->sc_ctx_as[i] != NULL) 1365 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1366 OHCI_SUBREG_ContextControlSet, 1367 OHCI_CTXCTL_RUN); 1368 } 1369 } 1370 } 1371 1372 static void 1373 fwohci_buf_stop_tx(struct fwohci_softc *sc) 1374 { 1375 int i; 1376 1377 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1378 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1379 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1380 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1381 1382 /* 1383 * Make sure the transmitter is stopped. 1384 */ 1385 for (i = 0; i < OHCI_LOOP; i++) { 1386 DELAY(10); 1387 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 1388 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1389 continue; 1390 if (OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 1391 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE) 1392 continue; 1393 break; 1394 } 1395 1396 /* 1397 * Initialize for Asynchronous Transmit Queue. 1398 */ 1399 fwohci_at_done(sc, sc->sc_ctx_atrq, 1); 1400 fwohci_at_done(sc, sc->sc_ctx_atrs, 1); 1401 } 1402 1403 static void 1404 fwohci_buf_stop_rx(struct fwohci_softc *sc) 1405 { 1406 int i; 1407 1408 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_REQUEST, 1409 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1410 OHCI_ASYNC_DMA_WRITE(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 1411 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1412 for (i = 0; i < sc->sc_isoctx; i++) { 1413 OHCI_SYNC_RX_DMA_WRITE(sc, i, 1414 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1415 } 1416 } 1417 1418 static void 1419 fwohci_buf_next(struct fwohci_softc *sc, struct fwohci_ctx *fc) 1420 { 1421 struct fwohci_buf *fb, *tfb; 1422 1423 #if DOUBLEBUF 1424 if (fc->fc_type != FWOHCI_CTX_ISO_MULTI) { 1425 #endif 1426 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 1427 if (fc->fc_type) { 1428 if (fb->fb_off == 0) 1429 break; 1430 } else { 1431 if (fb->fb_off != fb->fb_desc->fd_reqcount || 1432 fb->fb_desc->fd_rescount != 0) 1433 break; 1434 } 1435 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 1436 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1437 fb->fb_off = 0; 1438 fb->fb_desc->fd_branch = 0; 1439 tfb = TAILQ_LAST(&fc->fc_buf, fwohci_buf_s); 1440 tfb->fb_desc->fd_branch = fb->fb_daddr | 1; 1441 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 1442 } 1443 #if DOUBLEBUF 1444 } else { 1445 struct fwohci_buf_s fctmp; 1446 1447 /* cleaning buffer */ 1448 for (fb = TAILQ_FIRST(&fc->fc_buf); fb != NULL; 1449 fb = TAILQ_NEXT(fb, fb_list)) { 1450 fb->fb_off = 0; 1451 fb->fb_desc->fd_rescount = fb->fb_desc->fd_reqcount; 1452 } 1453 1454 /* rotating buffer */ 1455 fctmp = fc->fc_buf; 1456 fc->fc_buf = fc->fc_buf2; 1457 fc->fc_buf2 = fctmp; 1458 } 1459 #endif 1460 } 1461 1462 static int 1463 fwohci_buf_pktget(struct fwohci_softc *sc, struct fwohci_buf **fbp, caddr_t *pp, 1464 int len) 1465 { 1466 struct fwohci_buf *fb; 1467 struct fwohci_desc *fd; 1468 int bufend; 1469 1470 fb = *fbp; 1471 again: 1472 fd = fb->fb_desc; 1473 DPRINTFN(1, ("fwohci_buf_pktget: desc %ld, off %d, req %d, res %d," 1474 " len %d, avail %d\n", (long)(fd - sc->sc_desc), fb->fb_off, 1475 fd->fd_reqcount, fd->fd_rescount, len, 1476 fd->fd_reqcount - fd->fd_rescount - fb->fb_off)); 1477 bufend = fd->fd_reqcount - fd->fd_rescount; 1478 if (fb->fb_off >= bufend) { 1479 DPRINTFN(5, ("buf %x finish req %d res %d off %d ", 1480 fb->fb_desc->fd_data, fd->fd_reqcount, fd->fd_rescount, 1481 fb->fb_off)); 1482 if (fd->fd_rescount == 0) { 1483 *fbp = fb = TAILQ_NEXT(fb, fb_list); 1484 if (fb != NULL) 1485 goto again; 1486 } 1487 return 0; 1488 } 1489 if (fb->fb_off + len > bufend) 1490 len = bufend - fb->fb_off; 1491 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1492 BUS_DMASYNC_POSTREAD); 1493 *pp = fb->fb_buf + fb->fb_off; 1494 fb->fb_off += roundup(len, 4); 1495 return len; 1496 } 1497 1498 static int 1499 fwohci_buf_input(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1500 struct fwohci_pkt *pkt) 1501 { 1502 caddr_t p; 1503 struct fwohci_buf *fb; 1504 int len, count, i; 1505 #ifdef FW_DEBUG 1506 int tlabel; 1507 #endif 1508 1509 memset(pkt, 0, sizeof(*pkt)); 1510 pkt->fp_uio.uio_iov = pkt->fp_iov; 1511 pkt->fp_uio.uio_rw = UIO_WRITE; 1512 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1513 1514 /* get first quadlet */ 1515 fb = TAILQ_FIRST(&fc->fc_buf); 1516 count = 4; 1517 len = fwohci_buf_pktget(sc, &fb, &p, count); 1518 if (len <= 0) { 1519 DPRINTFN(1, ("fwohci_buf_input: no input for %d\n", 1520 fc->fc_ctx)); 1521 return 0; 1522 } 1523 pkt->fp_hdr[0] = *(u_int32_t *)p; 1524 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1525 switch (pkt->fp_tcode) { 1526 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1527 case IEEE1394_TCODE_READ_RESP_QUAD: 1528 pkt->fp_hlen = 12; 1529 pkt->fp_dlen = 4; 1530 break; 1531 case IEEE1394_TCODE_READ_REQ_BLOCK: 1532 pkt->fp_hlen = 16; 1533 pkt->fp_dlen = 0; 1534 break; 1535 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1536 case IEEE1394_TCODE_READ_RESP_BLOCK: 1537 case IEEE1394_TCODE_LOCK_REQ: 1538 case IEEE1394_TCODE_LOCK_RESP: 1539 pkt->fp_hlen = 16; 1540 break; 1541 case IEEE1394_TCODE_STREAM_DATA: 1542 #ifdef DIAGNOSTIC 1543 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) 1544 #endif 1545 { 1546 pkt->fp_hlen = 4; 1547 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1548 DPRINTFN(5, ("[%d]", pkt->fp_dlen)); 1549 break; 1550 } 1551 #ifdef DIAGNOSTIC 1552 else { 1553 printf("fwohci_buf_input: bad tcode: STREAM_DATA\n"); 1554 return 0; 1555 } 1556 #endif 1557 default: 1558 pkt->fp_hlen = 12; 1559 pkt->fp_dlen = 0; 1560 break; 1561 } 1562 1563 /* get header */ 1564 while (count < pkt->fp_hlen) { 1565 len = fwohci_buf_pktget(sc, &fb, &p, pkt->fp_hlen - count); 1566 if (len == 0) { 1567 printf("fwohci_buf_input: malformed input 1: %d\n", 1568 pkt->fp_hlen - count); 1569 return 0; 1570 } 1571 memcpy((caddr_t)pkt->fp_hdr + count, p, len); 1572 count += len; 1573 } 1574 if (pkt->fp_hlen == 16 && 1575 pkt->fp_tcode != IEEE1394_TCODE_READ_REQ_BLOCK) 1576 pkt->fp_dlen = pkt->fp_hdr[3] >> 16; 1577 #ifdef FW_DEBUG 1578 tlabel = (pkt->fp_hdr[0] & 0x0000fc00) >> 10; 1579 #endif 1580 DPRINTFN(1, ("fwohci_buf_input: tcode=0x%x, tlabel=0x%x, hlen=%d, " 1581 "dlen=%d\n", pkt->fp_tcode, tlabel, pkt->fp_hlen, pkt->fp_dlen)); 1582 1583 /* get data */ 1584 count = 0; 1585 i = 0; 1586 while (count < pkt->fp_dlen) { 1587 len = fwohci_buf_pktget(sc, &fb, 1588 (caddr_t *)&pkt->fp_iov[i].iov_base, 1589 pkt->fp_dlen - count); 1590 if (len == 0) { 1591 printf("fwohci_buf_input: malformed input 2: %d\n", 1592 pkt->fp_dlen - count); 1593 return 0; 1594 } 1595 pkt->fp_iov[i++].iov_len = len; 1596 count += len; 1597 } 1598 pkt->fp_uio.uio_iovcnt = i; 1599 pkt->fp_uio.uio_resid = count; 1600 1601 /* get trailer */ 1602 len = fwohci_buf_pktget(sc, &fb, (caddr_t *)&pkt->fp_trail, 1603 sizeof(*pkt->fp_trail)); 1604 if (len <= 0) { 1605 printf("fwohci_buf_input: malformed input 3: %d\n", 1606 pkt->fp_hlen - count); 1607 return 0; 1608 } 1609 return 1; 1610 } 1611 1612 static int 1613 fwohci_buf_input_ppb(struct fwohci_softc *sc, struct fwohci_ctx *fc, 1614 struct fwohci_pkt *pkt) 1615 { 1616 caddr_t p; 1617 int len; 1618 struct fwohci_buf *fb; 1619 struct fwohci_desc *fd; 1620 1621 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 1622 return fwohci_buf_input(sc, fc, pkt); 1623 } 1624 1625 memset(pkt, 0, sizeof(*pkt)); 1626 pkt->fp_uio.uio_iov = pkt->fp_iov; 1627 pkt->fp_uio.uio_rw = UIO_WRITE; 1628 pkt->fp_uio.uio_segflg = UIO_SYSSPACE; 1629 1630 for (fb = TAILQ_FIRST(&fc->fc_buf); ; fb = TAILQ_NEXT(fb, fb_list)) { 1631 if (fb == NULL) 1632 return 0; 1633 if (fb->fb_off == 0) 1634 break; 1635 } 1636 fd = fb->fb_desc; 1637 len = fd->fd_reqcount - fd->fd_rescount; 1638 if (len == 0) 1639 return 0; 1640 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, fb->fb_off, len, 1641 BUS_DMASYNC_POSTREAD); 1642 1643 p = fb->fb_buf; 1644 fb->fb_off += roundup(len, 4); 1645 if (len < 8) { 1646 printf("fwohci_buf_input_ppb: malformed input 1: %d\n", len); 1647 return 0; 1648 } 1649 1650 /* 1651 * get trailer first, may be bogus data unless status update 1652 * in descriptor is set. 1653 */ 1654 pkt->fp_trail = (u_int32_t *)p; 1655 *pkt->fp_trail = (*pkt->fp_trail & 0xffff) | (fd->fd_status << 16); 1656 pkt->fp_hdr[0] = ((u_int32_t *)p)[1]; 1657 pkt->fp_tcode = (pkt->fp_hdr[0] & 0x000000f0) >> 4; 1658 #ifdef DIAGNOSTIC 1659 if (pkt->fp_tcode != IEEE1394_TCODE_STREAM_DATA) { 1660 printf("fwohci_buf_input_ppb: bad tcode: 0x%x\n", 1661 pkt->fp_tcode); 1662 return 0; 1663 } 1664 #endif 1665 pkt->fp_hlen = 4; 1666 pkt->fp_dlen = pkt->fp_hdr[0] >> 16; 1667 p += 8; 1668 len -= 8; 1669 if (pkt->fp_dlen != len) { 1670 printf("fwohci_buf_input_ppb: malformed input 2: %d != %d\n", 1671 pkt->fp_dlen, len); 1672 return 0; 1673 } 1674 DPRINTFN(1, ("fwohci_buf_input_ppb: tcode=0x%x, hlen=%d, dlen=%d\n", 1675 pkt->fp_tcode, pkt->fp_hlen, pkt->fp_dlen)); 1676 pkt->fp_iov[0].iov_base = p; 1677 pkt->fp_iov[0].iov_len = len; 1678 pkt->fp_uio.uio_iovcnt = 0; 1679 pkt->fp_uio.uio_resid = len; 1680 return 1; 1681 } 1682 1683 static int 1684 fwohci_handler_set(struct fwohci_softc *sc, 1685 int tcode, u_int32_t key1, u_int32_t key2, u_int32_t key3, 1686 int (*handler)(struct fwohci_softc *, void *, struct fwohci_pkt *), 1687 void *arg) 1688 { 1689 struct fwohci_ctx *fc; 1690 struct fwohci_handler *fh; 1691 u_int64_t addr, naddr; 1692 u_int32_t off; 1693 int i, j; 1694 1695 if (tcode == IEEE1394_TCODE_STREAM_DATA && 1696 (((key1 & OHCI_ASYNC_STREAM) && sc->sc_ctx_as != NULL) 1697 || (key1 & OHCI_ASYNC_STREAM) == 0)) { 1698 int isasync = key1 & OHCI_ASYNC_STREAM; 1699 1700 key1 = key1 & IEEE1394_ISO_CHANNEL_ANY ? 1701 IEEE1394_ISO_CHANNEL_ANY : (key1 & IEEE1394_ISOCH_MASK); 1702 if (key1 & IEEE1394_ISO_CHANNEL_ANY) { 1703 printf("%s: key changed to %x\n", 1704 sc->sc_sc1394.sc1394_dev.dv_xname, key1); 1705 } 1706 j = sc->sc_isoctx; 1707 fh = NULL; 1708 1709 for (i = 0; i < sc->sc_isoctx; i++) { 1710 if ((fc = sc->sc_ctx_as[i]) == NULL) { 1711 if (j == sc->sc_isoctx) 1712 j = i; 1713 continue; 1714 } 1715 fh = LIST_FIRST(&fc->fc_handler); 1716 if (fh->fh_tcode == tcode && 1717 fh->fh_key1 == key1 && fh->fh_key2 == key2) 1718 break; 1719 fh = NULL; 1720 } 1721 if (fh == NULL) { 1722 if (handler == NULL) 1723 return 0; 1724 if (j == sc->sc_isoctx) { 1725 DPRINTF(("fwohci_handler_set: no more free " 1726 "context\n")); 1727 return ENOMEM; 1728 } 1729 if ((fc = sc->sc_ctx_as[j]) == NULL) { 1730 fwohci_ctx_alloc(sc, &fc, OHCI_BUF_IR_CNT, j, 1731 isasync ? FWOHCI_CTX_ISO_SINGLE : 1732 FWOHCI_CTX_ISO_MULTI); 1733 sc->sc_ctx_as[j] = fc; 1734 } 1735 } 1736 #ifdef FW_DEBUG 1737 if (fh == NULL && handler != NULL) { 1738 printf("use ir context %d\n", j); 1739 } else if (fh != NULL && handler == NULL) { 1740 printf("remove ir context %d\n", i); 1741 } 1742 #endif 1743 } else { 1744 switch (tcode) { 1745 case IEEE1394_TCODE_WRITE_REQ_QUAD: 1746 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 1747 case IEEE1394_TCODE_READ_REQ_QUAD: 1748 case IEEE1394_TCODE_READ_REQ_BLOCK: 1749 case IEEE1394_TCODE_LOCK_REQ: 1750 fc = sc->sc_ctx_arrq; 1751 break; 1752 case IEEE1394_TCODE_WRITE_RESP: 1753 case IEEE1394_TCODE_READ_RESP_QUAD: 1754 case IEEE1394_TCODE_READ_RESP_BLOCK: 1755 case IEEE1394_TCODE_LOCK_RESP: 1756 fc = sc->sc_ctx_arrs; 1757 break; 1758 default: 1759 return EIO; 1760 } 1761 naddr = ((u_int64_t)key1 << 32) + key2; 1762 1763 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 1764 fh = LIST_NEXT(fh, fh_list)) { 1765 if (fh->fh_tcode == tcode) { 1766 if (fh->fh_key1 == key1 && 1767 fh->fh_key2 == key2 && fh->fh_key3 == key3) 1768 break; 1769 /* Make sure it's not within a current range. */ 1770 addr = ((u_int64_t)fh->fh_key1 << 32) + 1771 fh->fh_key2; 1772 off = fh->fh_key3; 1773 if (key3 && 1774 (((naddr >= addr) && 1775 (naddr < (addr + off))) || 1776 (((naddr + key3) > addr) && 1777 ((naddr + key3) <= (addr + off))) || 1778 ((addr > naddr) && 1779 (addr < (naddr + key3))))) 1780 if (handler) 1781 return EEXIST; 1782 } 1783 } 1784 } 1785 if (handler == NULL) { 1786 if (fh != NULL) { 1787 LIST_REMOVE(fh, fh_list); 1788 free(fh, M_DEVBUF); 1789 } 1790 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1791 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1792 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 1793 sc->sc_ctx_as[fc->fc_ctx] = NULL; 1794 fwohci_ctx_free(sc, fc); 1795 } 1796 return 0; 1797 } 1798 if (fh == NULL) { 1799 fh = malloc(sizeof(*fh), M_DEVBUF, M_WAITOK); 1800 LIST_INSERT_HEAD(&fc->fc_handler, fh, fh_list); 1801 } 1802 fh->fh_tcode = tcode; 1803 fh->fh_key1 = key1; 1804 fh->fh_key2 = key2; 1805 fh->fh_key3 = key3; 1806 fh->fh_handler = handler; 1807 fh->fh_handarg = arg; 1808 DPRINTFN(1, ("fwohci_handler_set: ctx %d, tcode %x, key 0x%x, 0x%x, " 1809 "0x%x\n", fc->fc_ctx, tcode, key1, key2, key3)); 1810 1811 if (tcode == IEEE1394_TCODE_STREAM_DATA) { 1812 fwohci_ctx_init(sc, fc); 1813 DPRINTFN(1, ("fwohci_handler_set: SYNC desc %ld\n", 1814 (long)(TAILQ_FIRST(&fc->fc_buf)->fb_desc - sc->sc_desc))); 1815 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 1816 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 1817 } 1818 return 0; 1819 } 1820 1821 /* 1822 * static ieee1394_ir_tag_t 1823 * fwohci_ir_ctx_set(struct device *dev, int channel, int tagbm, 1824 * int bufnum, int maxsize, int flags) 1825 * 1826 * This function will return non-negative value if it succeeds. 1827 * This return value is pointer to the context of isochronous 1828 * transmission. This function will return NULL value if it 1829 * fails. 1830 */ 1831 ieee1394_ir_tag_t 1832 fwohci_ir_ctx_set(struct device *dev, int channel, int tagbm, 1833 int bufnum, int maxsize, int flags) 1834 { 1835 int i, openctx; 1836 struct fwohci_ir_ctx *irc; 1837 struct fwohci_softc *sc = (struct fwohci_softc *)dev; 1838 const char *xname = sc->sc_sc1394.sc1394_dev.dv_xname; 1839 1840 printf("%s: ir_ctx_set channel %d tagbm 0x%x maxsize %d bufnum %d\n", 1841 xname, channel, tagbm, maxsize, bufnum); 1842 /* 1843 * This loop will find the smallest vacant context and check 1844 * whether other channel uses the same channel. 1845 */ 1846 openctx = sc->sc_isoctx; 1847 for (i = 0; i < sc->sc_isoctx; ++i) { 1848 if (sc->sc_ctx_ir[i] == NULL) { 1849 /* 1850 * Find a vacant contet. If this has the 1851 * smallest context number, register it. 1852 */ 1853 if (openctx == sc->sc_isoctx) { 1854 openctx = i; 1855 } 1856 } else { 1857 /* 1858 * This context is used. Check whether this 1859 * context uses the same channel as ours. 1860 */ 1861 if (sc->sc_ctx_ir[i]->irc_channel == channel) { 1862 /* Using same channel. */ 1863 printf("%s: channel %d occupied by ctx%d\n", 1864 xname, channel, i); 1865 return NULL; 1866 } 1867 } 1868 } 1869 1870 /* 1871 * If there is a vacant context, allocate isochronous transmit 1872 * context for it. 1873 */ 1874 if (openctx != sc->sc_isoctx) { 1875 printf("%s using ctx %d for iso receive\n", xname, openctx); 1876 if ((irc = fwohci_ir_ctx_construct(sc, openctx, channel, 1877 tagbm, bufnum, maxsize, flags)) == NULL) { 1878 return NULL; 1879 } 1880 #ifndef IR_CTX_OPENTEST 1881 sc->sc_ctx_ir[openctx] = irc; 1882 #else 1883 fwohci_ir_ctx_destruct(irc); 1884 irc = NULL; 1885 #endif 1886 } else { 1887 printf("%s: cannot find any vacant contexts\n", xname); 1888 irc = NULL; 1889 } 1890 1891 return (ieee1394_ir_tag_t)irc; 1892 } 1893 1894 1895 /* 1896 * int fwohci_ir_ctx_clear(struct device *dev, ieee1394_ir_tag_t *ir) 1897 * 1898 * This function will return 0 if it succeed. Otherwise return 1899 * negative value. 1900 */ 1901 int 1902 fwohci_ir_ctx_clear(struct device *dev, ieee1394_ir_tag_t ir) 1903 { 1904 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)ir; 1905 struct fwohci_softc *sc = irc->irc_sc; 1906 int i; 1907 1908 if (sc->sc_ctx_ir[irc->irc_num] != irc) { 1909 printf("fwohci_ir_ctx_clear: irc differs %p %p\n", 1910 sc->sc_ctx_ir[irc->irc_num], irc); 1911 return -1; 1912 } 1913 1914 i = 0; 1915 while (irc->irc_status & IRC_STATUS_RUN) { 1916 tsleep((void *)irc, PWAIT|PCATCH, "IEEE1394 iso receive", 100); 1917 if (irc->irc_status & IRC_STATUS_RUN) { 1918 if (fwohci_ir_stop(irc) == 0) { 1919 irc->irc_status &= ~IRC_STATUS_RUN; 1920 } 1921 1922 } 1923 if (++i > 20) { 1924 u_int32_t reg 1925 = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 1926 OHCI_SUBREG_ContextControlSet); 1927 1928 printf("fwochi_ir_ctx_clear: " 1929 "Cannot stop iso receive engine\n"); 1930 printf("%s: intr IR_CommandPtr 0x%08x " 1931 "ContextCtrl 0x%08x%s%s%s%s\n", 1932 sc->sc_sc1394.sc1394_dev.dv_xname, 1933 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 1934 OHCI_SUBREG_CommandPtr), 1935 reg, 1936 reg & OHCI_CTXCTL_RUN ? " run" : "", 1937 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 1938 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 1939 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 1940 1941 return EBUSY; 1942 } 1943 } 1944 1945 printf("fwohci_ir_ctx_clear: DMA engine is stopped. get %d frames max queuelen %d pos %d\n", 1946 irc->irc_pktcount, irc->irc_maxqueuelen, irc->irc_maxqueuepos); 1947 1948 fwohci_ir_ctx_destruct(irc); 1949 1950 sc->sc_ctx_ir[irc->irc_num] = NULL; 1951 1952 return 0; 1953 } 1954 1955 1956 1957 1958 1959 1960 1961 1962 ieee1394_it_tag_t 1963 fwohci_it_set(struct ieee1394_softc *isc, int channel, int tagbm) 1964 { 1965 ieee1394_it_tag_t rv; 1966 int tag; 1967 1968 for (tag = 0; tagbm != 0 && (tagbm & 0x01) == 0; tagbm >>= 1, ++tag); 1969 1970 rv = fwohci_it_ctx_set((struct fwohci_softc *)isc, channel, tag, 488); 1971 1972 return rv; 1973 } 1974 1975 /* 1976 * static ieee1394_it_tag_t 1977 * fwohci_it_ctx_set(struct fwohci_softc *sc, 1978 * u_int32_t key1 (channel), u_int32_t key2 (tag), int maxsize) 1979 * 1980 * This function will return non-negative value if it succeeds. 1981 * This return value is pointer to the context of isochronous 1982 * transmission. This function will return NULL value if it 1983 * fails. 1984 */ 1985 static ieee1394_it_tag_t 1986 fwohci_it_ctx_set(struct fwohci_softc *sc, int channel, int tag, int maxsize) 1987 { 1988 int i, openctx; 1989 struct fwohci_it_ctx *itc; 1990 const char *xname = sc->sc_sc1394.sc1394_dev.dv_xname; 1991 #ifdef TEST_CHAIN 1992 extern int fwohci_test_chain(struct fwohci_it_ctx *); 1993 #endif /* TEST_CHAIN */ 1994 #ifdef TEST_WRITE 1995 extern void fwohci_test_write(struct fwohci_it_ctx *itc); 1996 #endif /* TEST_WRITE */ 1997 1998 printf("%s: it_ctx_set channel %d tag %d maxsize %d\n", 1999 xname, channel, tag, maxsize); 2000 2001 /* 2002 * This loop will find the smallest vacant context and check 2003 * whether other channel uses the same channel. 2004 */ 2005 openctx = sc->sc_itctx; 2006 for (i = 0; i < sc->sc_itctx; ++i) { 2007 if (sc->sc_ctx_it[i] == NULL) { 2008 /* 2009 * Find a vacant contet. If this has the 2010 * smallest context number, register it. 2011 */ 2012 if (openctx == sc->sc_itctx) { 2013 openctx = i; 2014 } 2015 } else { 2016 /* 2017 * This context is used. Check whether this 2018 * context uses the same channel as ours. 2019 */ 2020 if (sc->sc_ctx_it[i]->itc_channel == channel) { 2021 /* Using same channel. */ 2022 printf("%s: channel %d occupied by ctx%d\n", 2023 xname, channel, i); 2024 return NULL; 2025 } 2026 } 2027 } 2028 2029 /* 2030 * If there is a vacant context, allocate isochronous transmit 2031 * context for it. 2032 */ 2033 if (openctx != sc->sc_itctx) { 2034 printf("%s using ctx %d for iso trasmit\n", xname, openctx); 2035 if ((itc = fwohci_it_ctx_construct(sc, openctx, channel, 2036 tag, maxsize)) == NULL) { 2037 return NULL; 2038 } 2039 sc->sc_ctx_it[openctx] = itc; 2040 2041 #ifdef TEST_CHAIN 2042 fwohci_test_chain(itc); 2043 #endif /* TEST_CHAIN */ 2044 #ifdef TEST_WRITE 2045 fwohci_test_write(itc); 2046 itc = NULL; 2047 #endif /* TEST_WRITE */ 2048 2049 } else { 2050 printf("%s: cannot find any vacant contexts\n", xname); 2051 itc = NULL; 2052 } 2053 2054 return (ieee1394_it_tag_t)itc; 2055 } 2056 2057 2058 /* 2059 * int fwohci_it_ctx_clear(ieee1394_it_tag_t *it) 2060 * 2061 * This function will return 0 if it succeed. Otherwise return 2062 * negative value. 2063 */ 2064 int 2065 fwohci_it_ctx_clear(ieee1394_it_tag_t *it) 2066 { 2067 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 2068 struct fwohci_softc *sc = itc->itc_sc; 2069 int i; 2070 2071 if (sc->sc_ctx_it[itc->itc_num] != itc) { 2072 printf("fwohci_it_ctx_clear: itc differs %p %p\n", 2073 sc->sc_ctx_it[itc->itc_num], itc); 2074 return -1; 2075 } 2076 2077 fwohci_it_ctx_flush(it); 2078 2079 i = 0; 2080 while (itc->itc_flags & ITC_FLAGS_RUN) { 2081 tsleep((void *)itc, PWAIT|PCATCH, "IEEE1394 iso transmit", 100); 2082 if (itc->itc_flags & ITC_FLAGS_RUN) { 2083 u_int32_t reg; 2084 2085 reg = OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2086 OHCI_SUBREG_ContextControlSet); 2087 2088 if ((reg & OHCI_CTXCTL_WAKE) == 0) { 2089 itc->itc_flags &= ~ITC_FLAGS_RUN; 2090 printf("fwochi_it_ctx_clear: " 2091 "DMA engine stopped without intr\n"); 2092 } 2093 printf("%s: %d intr IT_CommandPtr 0x%08x " 2094 "ContextCtrl 0x%08x%s%s%s%s\n", 2095 sc->sc_sc1394.sc1394_dev.dv_xname, i, 2096 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2097 OHCI_SUBREG_CommandPtr), 2098 reg, 2099 reg & OHCI_CTXCTL_RUN ? " run" : "", 2100 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 2101 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 2102 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 2103 2104 2105 } 2106 if (++i > 20) { 2107 u_int32_t reg 2108 = OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2109 OHCI_SUBREG_ContextControlSet); 2110 2111 printf("fwochi_it_ctx_clear: " 2112 "Cannot stop iso transmit engine\n"); 2113 printf("%s: intr IT_CommandPtr 0x%08x " 2114 "ContextCtrl 0x%08x%s%s%s%s\n", 2115 sc->sc_sc1394.sc1394_dev.dv_xname, 2116 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 2117 OHCI_SUBREG_CommandPtr), 2118 reg, 2119 reg & OHCI_CTXCTL_RUN ? " run" : "", 2120 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 2121 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 2122 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 2123 2124 return EBUSY; 2125 } 2126 } 2127 2128 printf("fwohci_it_ctx_clear: DMA engine is stopped.\n"); 2129 2130 fwohci_it_ctx_destruct(itc); 2131 2132 sc->sc_ctx_it[itc->itc_num] = NULL; 2133 2134 2135 return 0; 2136 } 2137 2138 2139 2140 2141 2142 2143 /* 2144 * Asynchronous Receive Requests input frontend. 2145 */ 2146 static void 2147 fwohci_arrq_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 2148 { 2149 int rcode; 2150 u_int16_t len; 2151 u_int32_t key1, key2, off; 2152 u_int64_t addr, naddr; 2153 struct fwohci_handler *fh; 2154 struct fwohci_pkt pkt, res; 2155 2156 /* 2157 * Do not return if next packet is in the buffer, or the next 2158 * packet cannot be received until the next receive interrupt. 2159 */ 2160 while (fwohci_buf_input(sc, fc, &pkt)) { 2161 if (pkt.fp_tcode == OHCI_TCODE_PHY) { 2162 fwohci_phy_input(sc, &pkt); 2163 continue; 2164 } 2165 key1 = pkt.fp_hdr[1] & 0xffff; 2166 key2 = pkt.fp_hdr[2]; 2167 if ((pkt.fp_tcode == IEEE1394_TCODE_WRITE_REQ_BLOCK) || 2168 (pkt.fp_tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) { 2169 len = (pkt.fp_hdr[3] & 0xffff0000) >> 16; 2170 naddr = ((u_int64_t)key1 << 32) + key2; 2171 } else 2172 len = 0; 2173 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 2174 fh = LIST_NEXT(fh, fh_list)) { 2175 if (pkt.fp_tcode == fh->fh_tcode) { 2176 /* Assume length check happens in handler */ 2177 if (key1 == fh->fh_key1 && 2178 key2 == fh->fh_key2) { 2179 rcode = (*fh->fh_handler)(sc, 2180 fh->fh_handarg, &pkt); 2181 break; 2182 } 2183 addr = ((u_int64_t)fh->fh_key1 << 32) + 2184 fh->fh_key2; 2185 off = fh->fh_key3; 2186 /* Check for a range qualifier */ 2187 if (len && 2188 ((naddr >= addr) && (naddr < (addr + off)) 2189 && (naddr + len <= (addr + off)))) { 2190 rcode = (*fh->fh_handler)(sc, 2191 fh->fh_handarg, &pkt); 2192 break; 2193 } 2194 } 2195 } 2196 if (fh == NULL) { 2197 rcode = IEEE1394_RCODE_ADDRESS_ERROR; 2198 DPRINTFN(1, ("fwohci_arrq_input: no listener: tcode " 2199 "0x%x, addr=0x%04x %08x\n", pkt.fp_tcode, key1, 2200 key2)); 2201 DPRINTFN(2, ("fwohci_arrq_input: no listener: hdr[0]: " 2202 "0x%08x, hdr[1]: 0x%08x, hdr[2]: 0x%08x, hdr[3]: " 2203 "0x%08x\n", pkt.fp_hdr[0], pkt.fp_hdr[1], 2204 pkt.fp_hdr[2], pkt.fp_hdr[3])); 2205 } 2206 if (((*pkt.fp_trail & 0x001f0000) >> 16) != 2207 OHCI_CTXCTL_EVENT_ACK_PENDING) 2208 continue; 2209 if (rcode != -1) { 2210 memset(&res, 0, sizeof(res)); 2211 res.fp_uio.uio_rw = UIO_WRITE; 2212 res.fp_uio.uio_segflg = UIO_SYSSPACE; 2213 fwohci_atrs_output(sc, rcode, &pkt, &res); 2214 } 2215 } 2216 fwohci_buf_next(sc, fc); 2217 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2218 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 2219 } 2220 2221 2222 /* 2223 * Asynchronous Receive Response input frontend. 2224 */ 2225 static void 2226 fwohci_arrs_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 2227 { 2228 struct fwohci_pkt pkt; 2229 struct fwohci_handler *fh; 2230 u_int16_t srcid; 2231 int rcode, tlabel; 2232 2233 while (fwohci_buf_input(sc, fc, &pkt)) { 2234 srcid = pkt.fp_hdr[1] >> 16; 2235 rcode = (pkt.fp_hdr[1] & 0x0000f000) >> 12; 2236 tlabel = (pkt.fp_hdr[0] & 0x0000fc00) >> 10; 2237 DPRINTFN(1, ("fwohci_arrs_input: tcode 0x%x, from 0x%04x," 2238 " tlabel 0x%x, rcode 0x%x, hlen %d, dlen %d\n", 2239 pkt.fp_tcode, srcid, tlabel, rcode, pkt.fp_hlen, 2240 pkt.fp_dlen)); 2241 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 2242 fh = LIST_NEXT(fh, fh_list)) { 2243 if (pkt.fp_tcode == fh->fh_tcode && 2244 (srcid & OHCI_NodeId_NodeNumber) == fh->fh_key1 && 2245 tlabel == fh->fh_key2) { 2246 (*fh->fh_handler)(sc, fh->fh_handarg, &pkt); 2247 LIST_REMOVE(fh, fh_list); 2248 free(fh, M_DEVBUF); 2249 break; 2250 } 2251 } 2252 if (fh == NULL) 2253 DPRINTFN(1, ("fwohci_arrs_input: no listner\n")); 2254 } 2255 fwohci_buf_next(sc, fc); 2256 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2257 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 2258 } 2259 2260 /* 2261 * Isochronous Receive input frontend. 2262 */ 2263 static void 2264 fwohci_as_input(struct fwohci_softc *sc, struct fwohci_ctx *fc) 2265 { 2266 int rcode, chan, tag; 2267 struct iovec *iov; 2268 struct fwohci_handler *fh; 2269 struct fwohci_pkt pkt; 2270 2271 #if DOUBLEBUF 2272 if (fc->fc_type == FWOHCI_CTX_ISO_MULTI) { 2273 struct fwohci_buf *fb; 2274 int i; 2275 u_int32_t reg; 2276 2277 /* stop dma engine before read buffer */ 2278 reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, 2279 OHCI_SUBREG_ContextControlClear); 2280 DPRINTFN(5, ("ir_input %08x =>", reg)); 2281 if (reg & OHCI_CTXCTL_RUN) { 2282 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 2283 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2284 } 2285 DPRINTFN(5, (" %08x\n", OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlClear))); 2286 2287 i = 0; 2288 while ((reg = OHCI_SYNC_RX_DMA_READ(sc, fc->fc_ctx, OHCI_SUBREG_ContextControlSet)) & OHCI_CTXCTL_ACTIVE) { 2289 delay(10); 2290 if (++i > 10000) { 2291 printf("cannot stop dma engine 0x%08x\n", reg); 2292 return; 2293 } 2294 } 2295 2296 /* rotate dma buffer */ 2297 fb = TAILQ_FIRST(&fc->fc_buf2); 2298 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, OHCI_SUBREG_CommandPtr, 2299 fb->fb_daddr | 1); 2300 /* start dma engine */ 2301 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 2302 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 2303 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, 2304 (1 << fc->fc_ctx)); 2305 } 2306 #endif 2307 2308 while (fwohci_buf_input_ppb(sc, fc, &pkt)) { 2309 chan = (pkt.fp_hdr[0] & 0x00003f00) >> 8; 2310 tag = (pkt.fp_hdr[0] & 0x0000c000) >> 14; 2311 DPRINTFN(1, ("fwohci_as_input: hdr 0x%08x, tcode 0x%0x, hlen %d" 2312 ", dlen %d\n", pkt.fp_hdr[0], pkt.fp_tcode, pkt.fp_hlen, 2313 pkt.fp_dlen)); 2314 if (tag == IEEE1394_TAG_GASP && 2315 fc->fc_type == FWOHCI_CTX_ISO_SINGLE) { 2316 /* 2317 * The pkt with tag=3 is GASP format. 2318 * Move GASP header to header part. 2319 */ 2320 if (pkt.fp_dlen < 8) 2321 continue; 2322 iov = pkt.fp_iov; 2323 /* assuming pkt per buffer mode */ 2324 pkt.fp_hdr[1] = ntohl(((u_int32_t *)iov->iov_base)[0]); 2325 pkt.fp_hdr[2] = ntohl(((u_int32_t *)iov->iov_base)[1]); 2326 iov->iov_base = (caddr_t)iov->iov_base + 8; 2327 iov->iov_len -= 8; 2328 pkt.fp_hlen += 8; 2329 pkt.fp_dlen -= 8; 2330 } 2331 for (fh = LIST_FIRST(&fc->fc_handler); fh != NULL; 2332 fh = LIST_NEXT(fh, fh_list)) { 2333 if (pkt.fp_tcode == fh->fh_tcode && 2334 (chan == fh->fh_key1 || 2335 fh->fh_key1 == IEEE1394_ISO_CHANNEL_ANY) && 2336 ((1 << tag) & fh->fh_key2) != 0) { 2337 rcode = (*fh->fh_handler)(sc, fh->fh_handarg, 2338 &pkt); 2339 break; 2340 } 2341 } 2342 #ifdef FW_DEBUG 2343 if (fh == NULL) { 2344 DPRINTFN(1, ("fwohci_as_input: no handler\n")); 2345 } else { 2346 DPRINTFN(1, ("fwohci_as_input: rcode %d\n", rcode)); 2347 } 2348 #endif 2349 } 2350 fwohci_buf_next(sc, fc); 2351 2352 if (fc->fc_type == FWOHCI_CTX_ISO_SINGLE) { 2353 OHCI_SYNC_RX_DMA_WRITE(sc, fc->fc_ctx, 2354 OHCI_SUBREG_ContextControlSet, 2355 OHCI_CTXCTL_WAKE); 2356 } 2357 } 2358 2359 /* 2360 * Asynchronous Transmit common routine. 2361 */ 2362 static int 2363 fwohci_at_output(struct fwohci_softc *sc, struct fwohci_ctx *fc, 2364 struct fwohci_pkt *pkt) 2365 { 2366 struct fwohci_buf *fb; 2367 struct fwohci_desc *fd; 2368 struct mbuf *m, *m0; 2369 int i, ndesc, error, off, len; 2370 u_int32_t val; 2371 #ifdef FW_DEBUG 2372 struct iovec *iov; 2373 int tlabel = (pkt->fp_hdr[0] & 0x0000fc00) >> 10; 2374 #endif 2375 2376 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == IEEE1394_BCAST_PHY_ID) 2377 /* We can't send anything during selfid duration */ 2378 return EAGAIN; 2379 2380 #ifdef FW_DEBUG 2381 DPRINTFN(1, ("fwohci_at_output: tcode 0x%x, tlabel 0x%x hlen %d, " 2382 "dlen %d", pkt->fp_tcode, tlabel, pkt->fp_hlen, pkt->fp_dlen)); 2383 for (i = 0; i < pkt->fp_hlen/4; i++) 2384 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 2385 DPRINTFN(2, ("$")); 2386 for (ndesc = 0, iov = pkt->fp_iov; 2387 ndesc < pkt->fp_uio.uio_iovcnt; ndesc++, iov++) { 2388 for (i = 0; i < iov->iov_len; i++) 2389 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 2390 ((u_int8_t *)iov->iov_base)[i])); 2391 DPRINTFN(2, ("$")); 2392 } 2393 DPRINTFN(1, ("\n")); 2394 #endif 2395 2396 if ((m = pkt->fp_m) != NULL) { 2397 for (ndesc = 2; m != NULL; m = m->m_next) 2398 ndesc++; 2399 if (ndesc > OHCI_DESC_MAX) { 2400 m0 = NULL; 2401 ndesc = 2; 2402 for (off = 0; off < pkt->fp_dlen; off += len) { 2403 if (m0 == NULL) { 2404 MGETHDR(m0, M_DONTWAIT, MT_DATA); 2405 if (m0 != NULL) 2406 M_COPY_PKTHDR(m0, pkt->fp_m); 2407 m = m0; 2408 } else { 2409 MGET(m->m_next, M_DONTWAIT, MT_DATA); 2410 m = m->m_next; 2411 } 2412 if (m != NULL) 2413 MCLGET(m, M_DONTWAIT); 2414 if (m == NULL || (m->m_flags & M_EXT) == 0) { 2415 m_freem(m0); 2416 return ENOMEM; 2417 } 2418 len = pkt->fp_dlen - off; 2419 if (len > m->m_ext.ext_size) 2420 len = m->m_ext.ext_size; 2421 m_copydata(pkt->fp_m, off, len, 2422 mtod(m, caddr_t)); 2423 m->m_len = len; 2424 ndesc++; 2425 } 2426 m_freem(pkt->fp_m); 2427 pkt->fp_m = m0; 2428 } 2429 } else 2430 ndesc = 2 + pkt->fp_uio.uio_iovcnt; 2431 2432 if (ndesc > OHCI_DESC_MAX) 2433 return ENOBUFS; 2434 2435 fb = malloc(sizeof(*fb), M_DEVBUF, M_WAITOK); 2436 if (ndesc > 2) { 2437 if ((error = bus_dmamap_create(sc->sc_dmat, pkt->fp_dlen, 2438 OHCI_DESC_MAX - 2, pkt->fp_dlen, 0, BUS_DMA_WAITOK, 2439 &fb->fb_dmamap)) != 0) { 2440 fwohci_desc_put(sc, fb->fb_desc, ndesc); 2441 free(fb, M_DEVBUF); 2442 return error; 2443 } 2444 2445 if (pkt->fp_m != NULL) 2446 error = bus_dmamap_load_mbuf(sc->sc_dmat, fb->fb_dmamap, 2447 pkt->fp_m, BUS_DMA_WAITOK); 2448 else 2449 error = bus_dmamap_load_uio(sc->sc_dmat, fb->fb_dmamap, 2450 &pkt->fp_uio, BUS_DMA_WAITOK); 2451 if (error != 0) { 2452 DPRINTFN(1, ("Can't load DMA map: %d\n", error)); 2453 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 2454 fwohci_desc_put(sc, fb->fb_desc, ndesc); 2455 free(fb, M_DEVBUF); 2456 return error; 2457 } 2458 ndesc = fb->fb_dmamap->dm_nsegs + 2; 2459 2460 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, pkt->fp_dlen, 2461 BUS_DMASYNC_PREWRITE); 2462 } 2463 2464 fb->fb_nseg = ndesc; 2465 fb->fb_desc = fwohci_desc_get(sc, ndesc); 2466 if (fb->fb_desc == NULL) { 2467 free(fb, M_DEVBUF); 2468 return ENOBUFS; 2469 } 2470 fb->fb_daddr = sc->sc_ddmamap->dm_segs[0].ds_addr + 2471 ((caddr_t)fb->fb_desc - (caddr_t)sc->sc_desc); 2472 fb->fb_m = pkt->fp_m; 2473 fb->fb_callback = pkt->fp_callback; 2474 fb->fb_statuscb = pkt->fp_statuscb; 2475 fb->fb_statusarg = pkt->fp_statusarg; 2476 2477 fd = fb->fb_desc; 2478 fd->fd_flags = OHCI_DESC_IMMED; 2479 fd->fd_reqcount = pkt->fp_hlen; 2480 fd->fd_data = 0; 2481 fd->fd_branch = 0; 2482 fd->fd_status = 0; 2483 if (fc->fc_ctx == OHCI_CTX_ASYNC_TX_RESPONSE) { 2484 i = 3; /* XXX: 3 sec */ 2485 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 2486 fd->fd_timestamp = ((val >> 12) & 0x1fff) | 2487 ((((val >> 25) + i) & 0x7) << 13); 2488 } else 2489 fd->fd_timestamp = 0; 2490 memcpy(fd + 1, pkt->fp_hdr, pkt->fp_hlen); 2491 for (i = 0; i < ndesc - 2; i++) { 2492 fd = fb->fb_desc + 2 + i; 2493 fd->fd_flags = 0; 2494 fd->fd_reqcount = fb->fb_dmamap->dm_segs[i].ds_len; 2495 fd->fd_data = fb->fb_dmamap->dm_segs[i].ds_addr; 2496 fd->fd_branch = 0; 2497 fd->fd_status = 0; 2498 fd->fd_timestamp = 0; 2499 } 2500 fd->fd_flags |= OHCI_DESC_LAST | OHCI_DESC_BRANCH; 2501 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 2502 2503 #ifdef FW_DEBUG 2504 DPRINTFN(1, ("fwohci_at_output: desc %ld", 2505 (long)(fb->fb_desc - sc->sc_desc))); 2506 for (i = 0; i < ndesc * 4; i++) 2507 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 2508 ((u_int32_t *)fb->fb_desc)[i])); 2509 DPRINTFN(1, ("\n")); 2510 #endif 2511 2512 val = OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 2513 OHCI_SUBREG_ContextControlClear); 2514 2515 if (val & OHCI_CTXCTL_RUN) { 2516 if (fc->fc_branch == NULL) { 2517 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2518 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2519 goto run; 2520 } 2521 *fc->fc_branch = fb->fb_daddr | ndesc; 2522 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2523 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 2524 } else { 2525 run: 2526 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2527 OHCI_SUBREG_CommandPtr, fb->fb_daddr | ndesc); 2528 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2529 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 2530 } 2531 fc->fc_branch = &fd->fd_branch; 2532 2533 fc->fc_bufcnt++; 2534 TAILQ_INSERT_TAIL(&fc->fc_buf, fb, fb_list); 2535 pkt->fp_m = NULL; 2536 return 0; 2537 } 2538 2539 static void 2540 fwohci_at_done(struct fwohci_softc *sc, struct fwohci_ctx *fc, int force) 2541 { 2542 struct fwohci_buf *fb; 2543 struct fwohci_desc *fd; 2544 struct fwohci_pkt pkt; 2545 int i; 2546 2547 while ((fb = TAILQ_FIRST(&fc->fc_buf)) != NULL) { 2548 fd = fb->fb_desc; 2549 #ifdef FW_DEBUG 2550 DPRINTFN(1, ("fwohci_at_done: %sdesc %ld (%d)", 2551 force ? "force " : "", (long)(fd - sc->sc_desc), 2552 fb->fb_nseg)); 2553 for (i = 0; i < fb->fb_nseg * 4; i++) 2554 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", 2555 ((u_int32_t *)fd)[i])); 2556 DPRINTFN(1, ("\n")); 2557 #endif 2558 if (fb->fb_nseg > 2) 2559 fd += fb->fb_nseg - 1; 2560 if (!force && !(fd->fd_status & OHCI_CTXCTL_ACTIVE)) 2561 break; 2562 TAILQ_REMOVE(&fc->fc_buf, fb, fb_list); 2563 if (fc->fc_branch == &fd->fd_branch) { 2564 OHCI_ASYNC_DMA_WRITE(sc, fc->fc_ctx, 2565 OHCI_SUBREG_ContextControlClear, OHCI_CTXCTL_RUN); 2566 fc->fc_branch = NULL; 2567 for (i = 0; i < OHCI_LOOP; i++) { 2568 if (!(OHCI_ASYNC_DMA_READ(sc, fc->fc_ctx, 2569 OHCI_SUBREG_ContextControlClear) & 2570 OHCI_CTXCTL_ACTIVE)) 2571 break; 2572 DELAY(10); 2573 } 2574 } 2575 2576 if (fb->fb_statuscb) { 2577 memset(&pkt, 0, sizeof(pkt)); 2578 pkt.fp_status = fd->fd_status; 2579 memcpy(pkt.fp_hdr, fd + 1, sizeof(pkt.fp_hdr[0])); 2580 2581 /* Indicate this is just returning the status bits. */ 2582 pkt.fp_tcode = -1; 2583 (*fb->fb_statuscb)(sc, fb->fb_statusarg, &pkt); 2584 fb->fb_statuscb = NULL; 2585 fb->fb_statusarg = NULL; 2586 } 2587 fwohci_desc_put(sc, fb->fb_desc, fb->fb_nseg); 2588 if (fb->fb_nseg > 2) 2589 bus_dmamap_destroy(sc->sc_dmat, fb->fb_dmamap); 2590 fc->fc_bufcnt--; 2591 if (fb->fb_callback) { 2592 (*fb->fb_callback)(sc->sc_sc1394.sc1394_if, fb->fb_m); 2593 fb->fb_callback = NULL; 2594 } else if (fb->fb_m != NULL) 2595 m_freem(fb->fb_m); 2596 free(fb, M_DEVBUF); 2597 } 2598 } 2599 2600 /* 2601 * Asynchronous Transmit Reponse -- in response of request packet. 2602 */ 2603 static void 2604 fwohci_atrs_output(struct fwohci_softc *sc, int rcode, struct fwohci_pkt *req, 2605 struct fwohci_pkt *res) 2606 { 2607 2608 if (((*req->fp_trail & 0x001f0000) >> 16) != 2609 OHCI_CTXCTL_EVENT_ACK_PENDING) 2610 return; 2611 2612 res->fp_hdr[0] = (req->fp_hdr[0] & 0x0000fc00) | 0x00000100; 2613 res->fp_hdr[1] = (req->fp_hdr[1] & 0xffff0000) | (rcode << 12); 2614 switch (req->fp_tcode) { 2615 case IEEE1394_TCODE_WRITE_REQ_QUAD: 2616 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 2617 res->fp_tcode = IEEE1394_TCODE_WRITE_RESP; 2618 res->fp_hlen = 12; 2619 break; 2620 case IEEE1394_TCODE_READ_REQ_QUAD: 2621 res->fp_tcode = IEEE1394_TCODE_READ_RESP_QUAD; 2622 res->fp_hlen = 16; 2623 res->fp_dlen = 0; 2624 if (res->fp_uio.uio_iovcnt == 1 && res->fp_iov[0].iov_len == 4) 2625 res->fp_hdr[3] = 2626 *(u_int32_t *)res->fp_iov[0].iov_base; 2627 res->fp_uio.uio_iovcnt = 0; 2628 break; 2629 case IEEE1394_TCODE_READ_REQ_BLOCK: 2630 case IEEE1394_TCODE_LOCK_REQ: 2631 if (req->fp_tcode == IEEE1394_TCODE_LOCK_REQ) 2632 res->fp_tcode = IEEE1394_TCODE_LOCK_RESP; 2633 else 2634 res->fp_tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 2635 res->fp_hlen = 16; 2636 res->fp_dlen = res->fp_uio.uio_resid; 2637 res->fp_hdr[3] = res->fp_dlen << 16; 2638 break; 2639 } 2640 res->fp_hdr[0] |= (res->fp_tcode << 4); 2641 fwohci_at_output(sc, sc->sc_ctx_atrs, res); 2642 } 2643 2644 /* 2645 * APPLICATION LAYER SERVICES 2646 */ 2647 2648 /* 2649 * Retrieve Global UID from GUID ROM 2650 */ 2651 static int 2652 fwohci_guidrom_init(struct fwohci_softc *sc) 2653 { 2654 int i, n, off; 2655 u_int32_t val1, val2; 2656 2657 /* Extract the Global UID 2658 */ 2659 val1 = OHCI_CSR_READ(sc, OHCI_REG_GUIDHi); 2660 val2 = OHCI_CSR_READ(sc, OHCI_REG_GUIDLo); 2661 2662 if (val1 != 0 || val2 != 0) { 2663 sc->sc_sc1394.sc1394_guid[0] = (val1 >> 24) & 0xff; 2664 sc->sc_sc1394.sc1394_guid[1] = (val1 >> 16) & 0xff; 2665 sc->sc_sc1394.sc1394_guid[2] = (val1 >> 8) & 0xff; 2666 sc->sc_sc1394.sc1394_guid[3] = (val1 >> 0) & 0xff; 2667 sc->sc_sc1394.sc1394_guid[4] = (val2 >> 24) & 0xff; 2668 sc->sc_sc1394.sc1394_guid[5] = (val2 >> 16) & 0xff; 2669 sc->sc_sc1394.sc1394_guid[6] = (val2 >> 8) & 0xff; 2670 sc->sc_sc1394.sc1394_guid[7] = (val2 >> 0) & 0xff; 2671 } else { 2672 val1 = OHCI_CSR_READ(sc, OHCI_REG_Version); 2673 if ((val1 & OHCI_Version_GUID_ROM) == 0) 2674 return -1; 2675 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, OHCI_Guid_AddrReset); 2676 for (i = 0; i < OHCI_LOOP; i++) { 2677 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2678 if (!(val1 & OHCI_Guid_AddrReset)) 2679 break; 2680 DELAY(10); 2681 } 2682 off = OHCI_BITVAL(val1, OHCI_Guid_MiniROM) + 4; 2683 val2 = 0; 2684 for (n = 0; n < off + sizeof(sc->sc_sc1394.sc1394_guid); n++) { 2685 OHCI_CSR_WRITE(sc, OHCI_REG_Guid_Rom, 2686 OHCI_Guid_RdStart); 2687 for (i = 0; i < OHCI_LOOP; i++) { 2688 val1 = OHCI_CSR_READ(sc, OHCI_REG_Guid_Rom); 2689 if (!(val1 & OHCI_Guid_RdStart)) 2690 break; 2691 DELAY(10); 2692 } 2693 if (n < off) 2694 continue; 2695 val1 = OHCI_BITVAL(val1, OHCI_Guid_RdData); 2696 sc->sc_sc1394.sc1394_guid[n - off] = val1; 2697 val2 |= val1; 2698 } 2699 if (val2 == 0) 2700 return -1; 2701 } 2702 return 0; 2703 } 2704 2705 /* 2706 * Initialization for Configuration ROM (no DMA context) 2707 */ 2708 2709 #define CFR_MAXUNIT 20 2710 2711 struct configromctx { 2712 u_int32_t *ptr; 2713 int curunit; 2714 struct { 2715 u_int32_t *start; 2716 int length; 2717 u_int32_t *refer; 2718 int refunit; 2719 } unit[CFR_MAXUNIT]; 2720 }; 2721 2722 #define CFR_PUT_DATA4(cfr, d1, d2, d3, d4) \ 2723 (*(cfr)->ptr++ = (((d1)<<24) | ((d2)<<16) | ((d3)<<8) | (d4))) 2724 2725 #define CFR_PUT_DATA1(cfr, d) (*(cfr)->ptr++ = (d)) 2726 2727 #define CFR_PUT_VALUE(cfr, key, d) (*(cfr)->ptr++ = ((key)<<24) | (d)) 2728 2729 #define CFR_PUT_CRC(cfr, n) \ 2730 (*(cfr)->unit[n].start = ((cfr)->unit[n].length << 16) | \ 2731 fwohci_crc16((cfr)->unit[n].start + 1, (cfr)->unit[n].length)) 2732 2733 #define CFR_START_UNIT(cfr, n) \ 2734 do { \ 2735 if ((cfr)->unit[n].refer != NULL) { \ 2736 *(cfr)->unit[n].refer |= \ 2737 (cfr)->ptr - (cfr)->unit[n].refer; \ 2738 CFR_PUT_CRC(cfr, (cfr)->unit[n].refunit); \ 2739 } \ 2740 (cfr)->curunit = (n); \ 2741 (cfr)->unit[n].start = (cfr)->ptr++; \ 2742 } while (0 /* CONSTCOND */) 2743 2744 #define CFR_PUT_REFER(cfr, key, n) \ 2745 do { \ 2746 (cfr)->unit[n].refer = (cfr)->ptr; \ 2747 (cfr)->unit[n].refunit = (cfr)->curunit; \ 2748 *(cfr)->ptr++ = (key) << 24; \ 2749 } while (0 /* CONSTCOND */) 2750 2751 #define CFR_END_UNIT(cfr) \ 2752 do { \ 2753 (cfr)->unit[(cfr)->curunit].length = (cfr)->ptr - \ 2754 ((cfr)->unit[(cfr)->curunit].start + 1); \ 2755 CFR_PUT_CRC(cfr, (cfr)->curunit); \ 2756 } while (0 /* CONSTCOND */) 2757 2758 static u_int16_t 2759 fwohci_crc16(u_int32_t *ptr, int len) 2760 { 2761 int shift; 2762 u_int32_t crc, sum, data; 2763 2764 crc = 0; 2765 while (len-- > 0) { 2766 data = *ptr++; 2767 for (shift = 28; shift >= 0; shift -= 4) { 2768 sum = ((crc >> 12) ^ (data >> shift)) & 0x000f; 2769 crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum; 2770 } 2771 crc &= 0xffff; 2772 } 2773 return crc; 2774 } 2775 2776 static void 2777 fwohci_configrom_init(struct fwohci_softc *sc) 2778 { 2779 int i, val; 2780 struct fwohci_buf *fb; 2781 u_int32_t *hdr; 2782 struct configromctx cfr; 2783 2784 fb = &sc->sc_buf_cnfrom; 2785 memset(&cfr, 0, sizeof(cfr)); 2786 cfr.ptr = hdr = (u_int32_t *)fb->fb_buf; 2787 2788 /* headers */ 2789 CFR_START_UNIT(&cfr, 0); 2790 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusId)); 2791 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_BusOptions)); 2792 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDHi)); 2793 CFR_PUT_DATA1(&cfr, OHCI_CSR_READ(sc, OHCI_REG_GUIDLo)); 2794 CFR_END_UNIT(&cfr); 2795 /* copy info_length from crc_length */ 2796 *hdr |= (*hdr & 0x00ff0000) << 8; 2797 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMhdr, *hdr); 2798 2799 /* root directory */ 2800 CFR_START_UNIT(&cfr, 1); 2801 CFR_PUT_VALUE(&cfr, 0x03, 0x00005e); /* vendor id */ 2802 CFR_PUT_REFER(&cfr, 0x81, 2); /* textual descriptor offset */ 2803 CFR_PUT_VALUE(&cfr, 0x0c, 0x0083c0); /* node capability */ 2804 /* spt,64,fix,lst,drq */ 2805 #ifdef INET 2806 CFR_PUT_REFER(&cfr, 0xd1, 3); /* IPv4 unit directory */ 2807 #endif /* INET */ 2808 #ifdef INET6 2809 CFR_PUT_REFER(&cfr, 0xd1, 4); /* IPv6 unit directory */ 2810 #endif /* INET6 */ 2811 CFR_END_UNIT(&cfr); 2812 2813 CFR_START_UNIT(&cfr, 2); 2814 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2815 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2816 CFR_PUT_DATA4(&cfr, 'N', 'e', 't', 'B'); 2817 CFR_PUT_DATA4(&cfr, 'S', 'D', 0x00, 0x00); 2818 CFR_END_UNIT(&cfr); 2819 2820 #ifdef INET 2821 /* IPv4 unit directory */ 2822 CFR_START_UNIT(&cfr, 3); 2823 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2824 CFR_PUT_REFER(&cfr, 0x81, 6); /* textual descriptor offset */ 2825 CFR_PUT_VALUE(&cfr, 0x13, 0x000001); /* unit sw version */ 2826 CFR_PUT_REFER(&cfr, 0x81, 7); /* textual descriptor offset */ 2827 CFR_PUT_REFER(&cfr, 0x95, 8); /* Unit location */ 2828 CFR_END_UNIT(&cfr); 2829 2830 CFR_START_UNIT(&cfr, 6); 2831 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2832 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2833 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2834 CFR_END_UNIT(&cfr); 2835 2836 CFR_START_UNIT(&cfr, 7); 2837 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2838 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2839 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '4'); 2840 CFR_END_UNIT(&cfr); 2841 2842 CFR_START_UNIT(&cfr, 8); /* Spec's valid addr range. */ 2843 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2844 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2845 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2846 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2847 CFR_END_UNIT(&cfr); 2848 2849 #endif /* INET */ 2850 2851 #ifdef INET6 2852 /* IPv6 unit directory */ 2853 CFR_START_UNIT(&cfr, 4); 2854 CFR_PUT_VALUE(&cfr, 0x12, 0x00005e); /* unit spec id */ 2855 CFR_PUT_REFER(&cfr, 0x81, 9); /* textual descriptor offset */ 2856 CFR_PUT_VALUE(&cfr, 0x13, 0x000002); /* unit sw version */ 2857 /* XXX: TBA by IANA */ 2858 CFR_PUT_REFER(&cfr, 0x81, 10); /* textual descriptor offset */ 2859 CFR_PUT_REFER(&cfr, 0x95, 11); /* Unit location */ 2860 CFR_END_UNIT(&cfr); 2861 2862 CFR_START_UNIT(&cfr, 9); 2863 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2864 CFR_PUT_DATA1(&cfr, 0); /* minimal ASCII */ 2865 CFR_PUT_DATA4(&cfr, 'I', 'A', 'N', 'A'); 2866 CFR_END_UNIT(&cfr); 2867 2868 CFR_START_UNIT(&cfr, 10); 2869 CFR_PUT_VALUE(&cfr, 0, 0); /* textual descriptor */ 2870 CFR_PUT_DATA1(&cfr, 0); 2871 CFR_PUT_DATA4(&cfr, 'I', 'P', 'v', '6'); 2872 CFR_END_UNIT(&cfr); 2873 2874 CFR_START_UNIT(&cfr, 11); /* Spec's valid addr range. */ 2875 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2876 CFR_PUT_DATA1(&cfr, (FW_FIFO_LO | 0x1)); 2877 CFR_PUT_DATA1(&cfr, FW_FIFO_HI); 2878 CFR_PUT_DATA1(&cfr, FW_FIFO_LO); 2879 CFR_END_UNIT(&cfr); 2880 2881 #endif /* INET6 */ 2882 2883 fb->fb_off = cfr.ptr - hdr; 2884 #ifdef FW_DEBUG 2885 DPRINTF(("%s: Config ROM:", sc->sc_sc1394.sc1394_dev.dv_xname)); 2886 for (i = 0; i < fb->fb_off; i++) 2887 DPRINTF(("%s%08x", i&7?" ":"\n ", hdr[i])); 2888 DPRINTF(("\n")); 2889 #endif /* FW_DEBUG */ 2890 2891 /* 2892 * Make network byte order for DMA 2893 */ 2894 for (i = 0; i < fb->fb_off; i++) 2895 HTONL(hdr[i]); 2896 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2897 (caddr_t)cfr.ptr - fb->fb_buf, BUS_DMASYNC_PREWRITE); 2898 2899 OHCI_CSR_WRITE(sc, OHCI_REG_ConfigROMmap, 2900 fb->fb_dmamap->dm_segs[0].ds_addr); 2901 2902 /* This register is only valid on OHCI 1.1. */ 2903 val = OHCI_CSR_READ(sc, OHCI_REG_Version); 2904 if ((OHCI_Version_GET_Version(val) == 1) && 2905 (OHCI_Version_GET_Revision(val) == 1)) 2906 OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet, 2907 OHCI_HCControl_BIBImageValid); 2908 2909 /* Only allow quad reads of the rom. */ 2910 for (i = 0; i < fb->fb_off; i++) 2911 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 2912 CSR_BASE_HI, CSR_BASE_LO + CSR_CONFIG_ROM + (i * 4), 0, 2913 fwohci_configrom_input, NULL); 2914 } 2915 2916 static int 2917 fwohci_configrom_input(struct fwohci_softc *sc, void *arg, 2918 struct fwohci_pkt *pkt) 2919 { 2920 struct fwohci_pkt res; 2921 u_int32_t loc, *rom; 2922 2923 /* This will be used as an array index so size accordingly. */ 2924 loc = pkt->fp_hdr[2] - (CSR_BASE_LO + CSR_CONFIG_ROM); 2925 if ((loc & 0x03) != 0) { 2926 /* alignment error */ 2927 return IEEE1394_RCODE_ADDRESS_ERROR; 2928 } 2929 else 2930 loc /= 4; 2931 rom = (u_int32_t *)sc->sc_buf_cnfrom.fb_buf; 2932 2933 DPRINTFN(1, ("fwohci_configrom_input: ConfigRom[0x%04x]: 0x%08x\n", loc, 2934 ntohl(rom[loc]))); 2935 2936 memset(&res, 0, sizeof(res)); 2937 res.fp_hdr[3] = rom[loc]; 2938 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 2939 return -1; 2940 } 2941 2942 /* 2943 * SelfID buffer (no DMA context) 2944 */ 2945 static void 2946 fwohci_selfid_init(struct fwohci_softc *sc) 2947 { 2948 struct fwohci_buf *fb; 2949 2950 fb = &sc->sc_buf_selfid; 2951 #ifdef DIAGNOSTIC 2952 if ((fb->fb_dmamap->dm_segs[0].ds_addr & 0x7ff) != 0) 2953 panic("fwohci_selfid_init: not aligned: %ld (%ld) %p", 2954 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_addr, 2955 (unsigned long)fb->fb_dmamap->dm_segs[0].ds_len, fb->fb_buf); 2956 #endif 2957 memset(fb->fb_buf, 0, fb->fb_dmamap->dm_segs[0].ds_len); 2958 bus_dmamap_sync(sc->sc_dmat, fb->fb_dmamap, 0, 2959 fb->fb_dmamap->dm_segs[0].ds_len, BUS_DMASYNC_PREREAD); 2960 2961 OHCI_CSR_WRITE(sc, OHCI_REG_SelfIDBuffer, 2962 fb->fb_dmamap->dm_segs[0].ds_addr); 2963 } 2964 2965 static int 2966 fwohci_selfid_input(struct fwohci_softc *sc) 2967 { 2968 int i; 2969 u_int32_t count, val, gen; 2970 u_int32_t *buf; 2971 2972 buf = (u_int32_t *)sc->sc_buf_selfid.fb_buf; 2973 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 2974 again: 2975 if (val & OHCI_SelfID_Error) { 2976 printf("%s: SelfID Error\n", sc->sc_sc1394.sc1394_dev.dv_xname); 2977 return -1; 2978 } 2979 count = OHCI_BITVAL(val, OHCI_SelfID_Size); 2980 2981 bus_dmamap_sync(sc->sc_dmat, sc->sc_buf_selfid.fb_dmamap, 2982 0, count << 2, BUS_DMASYNC_POSTREAD); 2983 gen = OHCI_BITVAL(buf[0], OHCI_SelfID_Gen); 2984 2985 #ifdef FW_DEBUG 2986 DPRINTFN(1, ("%s: SelfID: 0x%08x", sc->sc_sc1394.sc1394_dev.dv_xname, 2987 val)); 2988 for (i = 0; i < count; i++) 2989 DPRINTFN(2, ("%s%08x", i&7?" ":"\n ", buf[i])); 2990 DPRINTFN(1, ("\n")); 2991 #endif /* FW_DEBUG */ 2992 2993 for (i = 1; i < count; i += 2) { 2994 if (buf[i] != ~buf[i + 1]) 2995 break; 2996 if (buf[i] & 0x00000001) 2997 continue; /* more pkt */ 2998 if (buf[i] & 0x00800000) 2999 continue; /* external id */ 3000 sc->sc_rootid = (buf[i] & 0x3f000000) >> 24; 3001 if ((buf[i] & 0x00400800) == 0x00400800) 3002 sc->sc_irmid = sc->sc_rootid; 3003 } 3004 3005 val = OHCI_CSR_READ(sc, OHCI_REG_SelfIDCount); 3006 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != gen) { 3007 if (OHCI_BITVAL(val, OHCI_SelfID_Gen) != 3008 OHCI_BITVAL(buf[0], OHCI_SelfID_Gen)) 3009 goto again; 3010 DPRINTF(("%s: SelfID Gen mismatch (%d, %d)\n", 3011 sc->sc_sc1394.sc1394_dev.dv_xname, gen, 3012 OHCI_BITVAL(val, OHCI_SelfID_Gen))); 3013 return -1; 3014 } 3015 if (i != count) { 3016 printf("%s: SelfID corrupted (%d, 0x%08x, 0x%08x)\n", 3017 sc->sc_sc1394.sc1394_dev.dv_xname, i, buf[i], buf[i + 1]); 3018 #if 1 3019 if (i == 1 && buf[i] == 0 && buf[i + 1] == 0) { 3020 /* 3021 * XXX: CXD3222 sometimes fails to DMA 3022 * selfid packet?? 3023 */ 3024 sc->sc_rootid = (count - 1) / 2 - 1; 3025 sc->sc_irmid = sc->sc_rootid; 3026 } else 3027 #endif 3028 return -1; 3029 } 3030 3031 val = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 3032 if ((val & OHCI_NodeId_IDValid) == 0) { 3033 sc->sc_nodeid = 0xffff; /* invalid */ 3034 printf("%s: nodeid is invalid\n", 3035 sc->sc_sc1394.sc1394_dev.dv_xname); 3036 return -1; 3037 } 3038 sc->sc_nodeid = val & 0xffff; 3039 sc->sc_sc1394.sc1394_node_id = sc->sc_nodeid & OHCI_NodeId_NodeNumber; 3040 3041 DPRINTF(("%s: nodeid=0x%04x(%d), rootid=%d, irmid=%d\n", 3042 sc->sc_sc1394.sc1394_dev.dv_xname, sc->sc_nodeid, 3043 sc->sc_nodeid & OHCI_NodeId_NodeNumber, sc->sc_rootid, 3044 sc->sc_irmid)); 3045 3046 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) > sc->sc_rootid) 3047 return -1; 3048 3049 if ((sc->sc_nodeid & OHCI_NodeId_NodeNumber) == sc->sc_rootid) 3050 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlSet, 3051 OHCI_LinkControl_CycleMaster); 3052 else 3053 OHCI_CSR_WRITE(sc, OHCI_REG_LinkControlClear, 3054 OHCI_LinkControl_CycleMaster); 3055 return 0; 3056 } 3057 3058 /* 3059 * some CSRs are handled by driver. 3060 */ 3061 static void 3062 fwohci_csr_init(struct fwohci_softc *sc) 3063 { 3064 int i; 3065 static u_int32_t csr[] = { 3066 CSR_STATE_CLEAR, CSR_STATE_SET, CSR_SB_CYCLE_TIME, 3067 CSR_SB_BUS_TIME, CSR_SB_BUSY_TIMEOUT, CSR_SB_BUS_MANAGER_ID, 3068 CSR_SB_CHANNEL_AVAILABLE_HI, CSR_SB_CHANNEL_AVAILABLE_LO, 3069 CSR_SB_BROADCAST_CHANNEL 3070 }; 3071 3072 for (i = 0; i < sizeof(csr) / sizeof(csr[0]); i++) { 3073 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_QUAD, 3074 CSR_BASE_HI, CSR_BASE_LO + csr[i], 0, fwohci_csr_input, 3075 NULL); 3076 fwohci_handler_set(sc, IEEE1394_TCODE_READ_REQ_QUAD, 3077 CSR_BASE_HI, CSR_BASE_LO + csr[i], 0, fwohci_csr_input, 3078 NULL); 3079 } 3080 sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] = 31; /*XXX*/ 3081 } 3082 3083 static int 3084 fwohci_csr_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3085 { 3086 struct fwohci_pkt res; 3087 u_int32_t reg; 3088 3089 /* 3090 * XXX need to do special functionality other than just r/w... 3091 */ 3092 reg = pkt->fp_hdr[2] - CSR_BASE_LO; 3093 3094 if ((reg & 0x03) != 0) { 3095 /* alignment error */ 3096 return IEEE1394_RCODE_ADDRESS_ERROR; 3097 } 3098 DPRINTFN(1, ("fwohci_csr_input: CSR[0x%04x]: 0x%08x", reg, 3099 *(u_int32_t *)(&sc->sc_csr[reg]))); 3100 if (pkt->fp_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) { 3101 DPRINTFN(1, (" -> 0x%08x\n", 3102 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base))); 3103 *(u_int32_t *)&sc->sc_csr[reg] = 3104 ntohl(*(u_int32_t *)pkt->fp_iov[0].iov_base); 3105 } else { 3106 DPRINTFN(1, ("\n")); 3107 res.fp_hdr[3] = htonl(*(u_int32_t *)&sc->sc_csr[reg]); 3108 res.fp_iov[0].iov_base = &res.fp_hdr[3]; 3109 res.fp_iov[0].iov_len = 4; 3110 res.fp_uio.uio_resid = 4; 3111 res.fp_uio.uio_iovcnt = 1; 3112 fwohci_atrs_output(sc, IEEE1394_RCODE_COMPLETE, pkt, &res); 3113 return -1; 3114 } 3115 return IEEE1394_RCODE_COMPLETE; 3116 } 3117 3118 /* 3119 * Mapping between nodeid and unique ID (EUI-64). 3120 * 3121 * Track old mappings and simply update their devices with the new id's when 3122 * they match an existing EUI. This allows proper renumeration of the bus. 3123 */ 3124 static void 3125 fwohci_uid_collect(struct fwohci_softc *sc) 3126 { 3127 int i; 3128 struct fwohci_uidtbl *fu; 3129 struct ieee1394_softc *iea; 3130 3131 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 3132 iea->sc1394_node_id = 0xffff; 3133 3134 if (sc->sc_uidtbl != NULL) 3135 free(sc->sc_uidtbl, M_DEVBUF); 3136 sc->sc_uidtbl = malloc(sizeof(*fu) * (sc->sc_rootid + 1), M_DEVBUF, 3137 M_NOWAIT|M_ZERO); /* XXX M_WAITOK requires locks */ 3138 if (sc->sc_uidtbl == NULL) 3139 return; 3140 3141 for (i = 0, fu = sc->sc_uidtbl; i <= sc->sc_rootid; i++, fu++) { 3142 if (i == (sc->sc_nodeid & OHCI_NodeId_NodeNumber)) { 3143 memcpy(fu->fu_uid, sc->sc_sc1394.sc1394_guid, 8); 3144 fu->fu_valid = 3; 3145 3146 iea = (struct ieee1394_softc *)sc->sc_sc1394.sc1394_if; 3147 if (iea) { 3148 iea->sc1394_node_id = i; 3149 DPRINTF(("%s: Updating nodeid to %d\n", 3150 iea->sc1394_dev.dv_xname, 3151 iea->sc1394_node_id)); 3152 } 3153 } else { 3154 fu->fu_valid = 0; 3155 fwohci_uid_req(sc, i); 3156 } 3157 } 3158 if (sc->sc_rootid == 0) 3159 fwohci_check_nodes(sc); 3160 } 3161 3162 static void 3163 fwohci_uid_req(struct fwohci_softc *sc, int phyid) 3164 { 3165 struct fwohci_pkt pkt; 3166 3167 memset(&pkt, 0, sizeof(pkt)); 3168 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3169 pkt.fp_hlen = 12; 3170 pkt.fp_dlen = 0; 3171 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3172 (pkt.fp_tcode << 4); 3173 pkt.fp_hdr[1] = ((0xffc0 | phyid) << 16) | CSR_BASE_HI; 3174 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 12; 3175 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 3176 sc->sc_tlabel, 0, fwohci_uid_input, (void *)0); 3177 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3178 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3179 3180 pkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3181 (pkt.fp_tcode << 4); 3182 pkt.fp_hdr[2] = CSR_BASE_LO + CSR_CONFIG_ROM + 16; 3183 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, phyid, 3184 sc->sc_tlabel, 0, fwohci_uid_input, (void *)1); 3185 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3186 fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3187 } 3188 3189 static int 3190 fwohci_uid_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *res) 3191 { 3192 struct fwohci_uidtbl *fu; 3193 struct ieee1394_softc *iea; 3194 struct ieee1394_attach_args fwa; 3195 int i, n, done, rcode, found; 3196 3197 found = 0; 3198 3199 n = (res->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 3200 rcode = (res->fp_hdr[1] & 0x0000f000) >> 12; 3201 if (rcode != IEEE1394_RCODE_COMPLETE || 3202 sc->sc_uidtbl == NULL || 3203 n > sc->sc_rootid) 3204 return 0; 3205 fu = &sc->sc_uidtbl[n]; 3206 if (arg == 0) { 3207 memcpy(fu->fu_uid, res->fp_iov[0].iov_base, 4); 3208 fu->fu_valid |= 0x1; 3209 } else { 3210 memcpy(fu->fu_uid + 4, res->fp_iov[0].iov_base, 4); 3211 fu->fu_valid |= 0x2; 3212 } 3213 #ifdef FW_DEBUG 3214 if (fu->fu_valid == 0x3) 3215 DPRINTFN(1, ("fwohci_uid_input: " 3216 "Node %d, UID %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", n, 3217 fu->fu_uid[0], fu->fu_uid[1], fu->fu_uid[2], fu->fu_uid[3], 3218 fu->fu_uid[4], fu->fu_uid[5], fu->fu_uid[6], fu->fu_uid[7])); 3219 #endif 3220 if (fu->fu_valid == 0x3) { 3221 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) 3222 if (memcmp(iea->sc1394_guid, fu->fu_uid, 8) == 0) { 3223 found = 1; 3224 iea->sc1394_node_id = n; 3225 DPRINTF(("%s: Updating nodeid to %d\n", 3226 iea->sc1394_dev.dv_xname, 3227 iea->sc1394_node_id)); 3228 if (iea->sc1394_callback.sc1394_reset) 3229 iea->sc1394_callback.sc1394_reset(iea, 3230 iea->sc1394_callback.sc1394_resetarg); 3231 break; 3232 } 3233 if (!found) { 3234 strcpy(fwa.name, "fwnode"); 3235 memcpy(fwa.uid, fu->fu_uid, 8); 3236 fwa.nodeid = n; 3237 iea = (struct ieee1394_softc *) 3238 config_found_sm(&sc->sc_sc1394.sc1394_dev, &fwa, 3239 fwohci_print, fwohci_submatch); 3240 if (iea != NULL) 3241 LIST_INSERT_HEAD(&sc->sc_nodelist, iea, 3242 sc1394_node); 3243 } 3244 } 3245 done = 1; 3246 3247 for (i = 0; i < sc->sc_rootid + 1; i++) { 3248 fu = &sc->sc_uidtbl[i]; 3249 if (fu->fu_valid != 0x3) { 3250 done = 0; 3251 break; 3252 } 3253 } 3254 if (done) 3255 fwohci_check_nodes(sc); 3256 3257 return 0; 3258 } 3259 3260 static void 3261 fwohci_check_nodes(struct fwohci_softc *sc) 3262 { 3263 struct device *detach = NULL; 3264 struct ieee1394_softc *iea; 3265 3266 LIST_FOREACH(iea, &sc->sc_nodelist, sc1394_node) { 3267 3268 /* 3269 * Have to defer detachment until the next 3270 * loop iteration since config_detach 3271 * free's the softc and the loop iterator 3272 * needs data from the softc to move 3273 * forward. 3274 */ 3275 3276 if (detach) { 3277 config_detach(detach, 0); 3278 detach = NULL; 3279 } 3280 if (iea->sc1394_node_id == 0xffff) { 3281 detach = (struct device *)iea; 3282 LIST_REMOVE(iea, sc1394_node); 3283 } 3284 } 3285 if (detach) 3286 config_detach(detach, 0); 3287 } 3288 3289 static int 3290 fwohci_uid_lookup(struct fwohci_softc *sc, const u_int8_t *uid) 3291 { 3292 struct fwohci_uidtbl *fu; 3293 int n; 3294 static const u_int8_t bcast[] = 3295 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3296 3297 fu = sc->sc_uidtbl; 3298 if (fu == NULL) { 3299 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 3300 return IEEE1394_BCAST_PHY_ID; 3301 fwohci_uid_collect(sc); /* try to get */ 3302 return -1; 3303 } 3304 for (n = 0; n <= sc->sc_rootid; n++, fu++) { 3305 if (fu->fu_valid == 0x3 && memcmp(fu->fu_uid, uid, 8) == 0) 3306 return n; 3307 } 3308 if (memcmp(uid, bcast, sizeof(bcast)) == 0) 3309 return IEEE1394_BCAST_PHY_ID; 3310 for (n = 0, fu = sc->sc_uidtbl; n <= sc->sc_rootid; n++, fu++) { 3311 if (fu->fu_valid != 0x3) { 3312 /* 3313 * XXX: need timer before retransmission 3314 */ 3315 fwohci_uid_req(sc, n); 3316 } 3317 } 3318 return -1; 3319 } 3320 3321 /* 3322 * functions to support network interface 3323 */ 3324 static int 3325 fwohci_if_inreg(struct device *self, u_int32_t offhi, u_int32_t offlo, 3326 void (*handler)(struct device *, struct mbuf *)) 3327 { 3328 struct fwohci_softc *sc = (struct fwohci_softc *)self; 3329 3330 fwohci_handler_set(sc, IEEE1394_TCODE_WRITE_REQ_BLOCK, offhi, offlo, 0, 3331 handler ? fwohci_if_input : NULL, handler); 3332 fwohci_handler_set(sc, IEEE1394_TCODE_STREAM_DATA, 3333 (sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & IEEE1394_ISOCH_MASK) | 3334 OHCI_ASYNC_STREAM, 3335 1 << IEEE1394_TAG_GASP, 0, 3336 handler ? fwohci_if_input : NULL, handler); 3337 return 0; 3338 } 3339 3340 static int 3341 fwohci_if_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3342 { 3343 int n, len; 3344 struct mbuf *m; 3345 struct iovec *iov; 3346 void (*handler)(struct device *, struct mbuf *) = arg; 3347 3348 #ifdef FW_DEBUG 3349 int i; 3350 DPRINTFN(1, ("fwohci_if_input: tcode=0x%x, dlen=%d", pkt->fp_tcode, 3351 pkt->fp_dlen)); 3352 for (i = 0; i < pkt->fp_hlen/4; i++) 3353 DPRINTFN(2, ("%s%08x", i?" ":"\n ", pkt->fp_hdr[i])); 3354 DPRINTFN(2, ("$")); 3355 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 3356 iov = &pkt->fp_iov[n]; 3357 for (i = 0; i < iov->iov_len; i++) 3358 DPRINTFN(2, ("%s%02x", (i%32)?((i%4)?"":" "):"\n ", 3359 ((u_int8_t *)iov->iov_base)[i])); 3360 DPRINTFN(2, ("$")); 3361 } 3362 DPRINTFN(1, ("\n")); 3363 #endif /* FW_DEBUG */ 3364 len = pkt->fp_dlen; 3365 MGETHDR(m, M_DONTWAIT, MT_DATA); 3366 if (m == NULL) 3367 return IEEE1394_RCODE_COMPLETE; 3368 m->m_len = 16; 3369 if (len + m->m_len > MHLEN) { 3370 MCLGET(m, M_DONTWAIT); 3371 if ((m->m_flags & M_EXT) == 0) { 3372 m_freem(m); 3373 return IEEE1394_RCODE_COMPLETE; 3374 } 3375 } 3376 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 3377 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 3378 sc->sc_uidtbl[n].fu_valid != 0x3) { 3379 printf("%s: packet from unknown node: phy id %d\n", 3380 sc->sc_sc1394.sc1394_dev.dv_xname, n); 3381 m_freem(m); 3382 fwohci_uid_req(sc, n); 3383 return IEEE1394_RCODE_COMPLETE; 3384 } 3385 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 3386 if (pkt->fp_tcode == IEEE1394_TCODE_STREAM_DATA) { 3387 m->m_flags |= M_BCAST; 3388 mtod(m, u_int32_t *)[2] = mtod(m, u_int32_t *)[3] = 0; 3389 } else { 3390 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 3391 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 3392 } 3393 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 3394 mtod(m, u_int8_t *)[9] = 3395 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 3396 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 3397 3398 m->m_pkthdr.rcvif = NULL; /* set in child */ 3399 m->m_pkthdr.len = len + m->m_len; 3400 /* 3401 * We may use receive buffer by external mbuf instead of copy here. 3402 * But asynchronous receive buffer must be operate in buffer fill 3403 * mode, so that each receive buffer will shared by multiple mbufs. 3404 * If upper layer doesn't free mbuf soon, e.g. application program 3405 * is suspended, buffer must be reallocated. 3406 * Isochronous buffer must be operate in packet buffer mode, and 3407 * it is easy to map receive buffer to external mbuf. But it is 3408 * used for broadcast/multicast only, and is expected not so 3409 * performance sensitive for now. 3410 * XXX: The performance may be important for multicast case, 3411 * so we should revisit here later. 3412 * -- onoe 3413 */ 3414 n = 0; 3415 iov = pkt->fp_uio.uio_iov; 3416 while (len > 0) { 3417 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 3418 iov->iov_len); 3419 m->m_len += iov->iov_len; 3420 len -= iov->iov_len; 3421 iov++; 3422 } 3423 (*handler)(sc->sc_sc1394.sc1394_if, m); 3424 return IEEE1394_RCODE_COMPLETE; 3425 } 3426 3427 static int 3428 fwohci_if_input_iso(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3429 { 3430 int n, len; 3431 int chan, tag; 3432 struct mbuf *m; 3433 struct iovec *iov; 3434 void (*handler)(struct device *, struct mbuf *) = arg; 3435 #ifdef FW_DEBUG 3436 int i; 3437 #endif 3438 3439 chan = (pkt->fp_hdr[0] & 0x00003f00) >> 8; 3440 tag = (pkt->fp_hdr[0] & 0x0000c000) >> 14; 3441 #ifdef FW_DEBUG 3442 DPRINTFN(1, ("fwohci_if_input_iso: " 3443 "tcode=0x%x, chan=%d, tag=%x, dlen=%d", 3444 pkt->fp_tcode, chan, tag, pkt->fp_dlen)); 3445 for (i = 0; i < pkt->fp_hlen/4; i++) 3446 DPRINTFN(2, ("%s%08x", i?" ":"\n\t", pkt->fp_hdr[i])); 3447 DPRINTFN(2, ("$")); 3448 for (n = 0, len = pkt->fp_dlen; len > 0; len -= i, n++){ 3449 iov = &pkt->fp_iov[n]; 3450 for (i = 0; i < iov->iov_len; i++) 3451 DPRINTFN(2, ("%s%02x", 3452 (i%32)?((i%4)?"":" "):"\n\t", 3453 ((u_int8_t *)iov->iov_base)[i])); 3454 DPRINTFN(2, ("$")); 3455 } 3456 DPRINTFN(2, ("\n")); 3457 #endif /* FW_DEBUG */ 3458 len = pkt->fp_dlen; 3459 MGETHDR(m, M_DONTWAIT, MT_DATA); 3460 if (m == NULL) 3461 return IEEE1394_RCODE_COMPLETE; 3462 m->m_len = 16; 3463 if (m->m_len + len > MHLEN) { 3464 MCLGET(m, M_DONTWAIT); 3465 if ((m->m_flags & M_EXT) == 0) { 3466 m_freem(m); 3467 return IEEE1394_RCODE_COMPLETE; 3468 } 3469 } 3470 3471 m->m_flags |= M_BCAST; 3472 3473 if (tag == IEEE1394_TAG_GASP) { 3474 n = (pkt->fp_hdr[1] >> 16) & OHCI_NodeId_NodeNumber; 3475 if (sc->sc_uidtbl == NULL || n > sc->sc_rootid || 3476 sc->sc_uidtbl[n].fu_valid != 0x3) { 3477 printf("%s: packet from unknown node: phy id %d\n", 3478 sc->sc_sc1394.sc1394_dev.dv_xname, n); 3479 m_freem(m); 3480 return IEEE1394_RCODE_COMPLETE; 3481 } 3482 memcpy(mtod(m, caddr_t), sc->sc_uidtbl[n].fu_uid, 8); 3483 mtod(m, u_int32_t *)[2] = htonl(pkt->fp_hdr[1]); 3484 mtod(m, u_int32_t *)[3] = htonl(pkt->fp_hdr[2]); 3485 mtod(m, u_int8_t *)[8] = n; /*XXX: node id for debug */ 3486 mtod(m, u_int8_t *)[9] = 3487 (*pkt->fp_trail >> (16 + OHCI_CTXCTL_SPD_BITPOS)) & 3488 ((1 << OHCI_CTXCTL_SPD_BITLEN) - 1); 3489 } 3490 mtod(m, u_int8_t *)[14] = chan; 3491 mtod(m, u_int8_t *)[15] = tag; 3492 3493 3494 m->m_pkthdr.rcvif = NULL; /* set in child */ 3495 m->m_pkthdr.len = len + m->m_len; 3496 /* 3497 * We may use receive buffer by external mbuf instead of copy here. 3498 * But asynchronous receive buffer must be operate in buffer fill 3499 * mode, so that each receive buffer will shared by multiple mbufs. 3500 * If upper layer doesn't free mbuf soon, e.g. application program 3501 * is suspended, buffer must be reallocated. 3502 * Isochronous buffer must be operate in packet buffer mode, and 3503 * it is easy to map receive buffer to external mbuf. But it is 3504 * used for broadcast/multicast only, and is expected not so 3505 * performance sensitive for now. 3506 * XXX: The performance may be important for multicast case, 3507 * so we should revisit here later. 3508 * -- onoe 3509 */ 3510 n = 0; 3511 iov = pkt->fp_uio.uio_iov; 3512 while (len > 0) { 3513 memcpy(mtod(m, caddr_t) + m->m_len, iov->iov_base, 3514 iov->iov_len); 3515 m->m_len += iov->iov_len; 3516 len -= iov->iov_len; 3517 iov++; 3518 } 3519 (*handler)(sc->sc_sc1394.sc1394_if, m); 3520 return IEEE1394_RCODE_COMPLETE; 3521 } 3522 3523 3524 3525 static int 3526 fwohci_if_output(struct device *self, struct mbuf *m0, 3527 void (*callback)(struct device *, struct mbuf *)) 3528 { 3529 struct fwohci_softc *sc = (struct fwohci_softc *)self; 3530 struct fwohci_pkt pkt; 3531 u_int8_t *p; 3532 int n, error, spd, hdrlen, maxrec; 3533 #ifdef FW_DEBUG 3534 struct mbuf *m; 3535 #endif 3536 3537 p = mtod(m0, u_int8_t *); 3538 if (m0->m_flags & (M_BCAST | M_MCAST)) { 3539 spd = IEEE1394_SPD_S100; /*XXX*/ 3540 maxrec = 512; /*XXX*/ 3541 hdrlen = 8; 3542 } else { 3543 n = fwohci_uid_lookup(sc, p); 3544 if (n < 0) { 3545 printf("%s: nodeid unknown:" 3546 " %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 3547 sc->sc_sc1394.sc1394_dev.dv_xname, 3548 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); 3549 error = EHOSTUNREACH; 3550 goto end; 3551 } 3552 if (n == IEEE1394_BCAST_PHY_ID) { 3553 printf("%s: broadcast with !M_MCAST\n", 3554 sc->sc_sc1394.sc1394_dev.dv_xname); 3555 #ifdef FW_DEBUG 3556 DPRINTFN(2, ("packet:")); 3557 for (m = m0; m != NULL; m = m->m_next) { 3558 for (n = 0; n < m->m_len; n++) 3559 DPRINTFN(2, ("%s%02x", (n%32)? 3560 ((n%4)?"":" "):"\n ", 3561 mtod(m, u_int8_t *)[n])); 3562 DPRINTFN(2, ("$")); 3563 } 3564 DPRINTFN(2, ("\n")); 3565 #endif 3566 error = EHOSTUNREACH; 3567 goto end; 3568 } 3569 maxrec = 2 << p[8]; 3570 spd = p[9]; 3571 hdrlen = 0; 3572 } 3573 if (spd > sc->sc_sc1394.sc1394_link_speed) { 3574 DPRINTF(("fwohci_if_output: spd (%d) is faster than %d\n", 3575 spd, sc->sc_sc1394.sc1394_link_speed)); 3576 spd = sc->sc_sc1394.sc1394_link_speed; 3577 } 3578 if (maxrec > (512 << spd)) { 3579 DPRINTF(("fwohci_if_output: maxrec (%d) is larger for spd (%d)" 3580 "\n", maxrec, spd)); 3581 maxrec = 512 << spd; 3582 } 3583 while (maxrec > sc->sc_sc1394.sc1394_max_receive) { 3584 DPRINTF(("fwohci_if_output: maxrec (%d) is larger than" 3585 " %d\n", maxrec, sc->sc_sc1394.sc1394_max_receive)); 3586 maxrec >>= 1; 3587 } 3588 if (maxrec < 512) { 3589 DPRINTF(("fwohci_if_output: maxrec (%d) is smaller than " 3590 "minimum\n", maxrec)); 3591 maxrec = 512; 3592 } 3593 3594 m_adj(m0, 16 - hdrlen); 3595 if (m0->m_pkthdr.len > maxrec) { 3596 DPRINTF(("fwohci_if_output: packet too big: hdr %d, pktlen " 3597 "%d, maxrec %d\n", hdrlen, m0->m_pkthdr.len, maxrec)); 3598 error = E2BIG; /*XXX*/ 3599 goto end; 3600 } 3601 3602 memset(&pkt, 0, sizeof(pkt)); 3603 pkt.fp_uio.uio_iov = pkt.fp_iov; 3604 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3605 pkt.fp_uio.uio_rw = UIO_WRITE; 3606 if (m0->m_flags & (M_BCAST | M_MCAST)) { 3607 /* construct GASP header */ 3608 p = mtod(m0, u_int8_t *); 3609 p[0] = sc->sc_nodeid >> 8; 3610 p[1] = sc->sc_nodeid & 0xff; 3611 p[2] = 0x00; p[3] = 0x00; p[4] = 0x5e; 3612 p[5] = 0x00; p[6] = 0x00; p[7] = 0x01; 3613 pkt.fp_tcode = IEEE1394_TCODE_STREAM_DATA; 3614 pkt.fp_hlen = 8; 3615 pkt.fp_hdr[0] = (spd << 16) | (IEEE1394_TAG_GASP << 14) | 3616 ((sc->sc_csr[CSR_SB_BROADCAST_CHANNEL] & 3617 OHCI_NodeId_NodeNumber) << 8); 3618 pkt.fp_hdr[1] = m0->m_pkthdr.len << 16; 3619 } else { 3620 pkt.fp_tcode = IEEE1394_TCODE_WRITE_REQ_BLOCK; 3621 pkt.fp_hlen = 16; 3622 pkt.fp_hdr[0] = 0x00800100 | (sc->sc_tlabel << 10) | 3623 (spd << 16); 3624 pkt.fp_hdr[1] = 3625 (((sc->sc_nodeid & OHCI_NodeId_BusNumber) | n) << 16) | 3626 (p[10] << 8) | p[11]; 3627 pkt.fp_hdr[2] = (p[12]<<24) | (p[13]<<16) | (p[14]<<8) | p[15]; 3628 pkt.fp_hdr[3] = m0->m_pkthdr.len << 16; 3629 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3630 } 3631 pkt.fp_hdr[0] |= (pkt.fp_tcode << 4); 3632 pkt.fp_dlen = m0->m_pkthdr.len; 3633 pkt.fp_m = m0; 3634 pkt.fp_callback = callback; 3635 error = fwohci_at_output(sc, sc->sc_ctx_atrq, &pkt); 3636 m0 = pkt.fp_m; 3637 end: 3638 if (m0 != NULL) { 3639 if (callback) 3640 (*callback)(sc->sc_sc1394.sc1394_if, m0); 3641 else 3642 m_freem(m0); 3643 } 3644 return error; 3645 } 3646 3647 /* 3648 * High level routines to provide abstraction to attaching layers to 3649 * send/receive data. 3650 */ 3651 3652 /* 3653 * These break down into 4 routines as follows: 3654 * 3655 * int fwohci_read(struct ieee1394_abuf *) 3656 * 3657 * This routine will attempt to read a region from the requested node. 3658 * A callback must be provided which will be called when either the completed 3659 * read is done or an unrecoverable error occurs. This is mainly a convenience 3660 * routine since it will encapsulate retrying a region as quadlet vs. block 3661 * reads and recombining all the returned data. This could also be done with a 3662 * series of write/inreg's for each packet sent. 3663 * 3664 * int fwohci_write(struct ieee1394_abuf *) 3665 * 3666 * The work horse main entry point for putting packets on the bus. This is the 3667 * generalized interface for fwnode/etc code to put packets out onto the bus. 3668 * It accepts all standard ieee1394 tcodes (XXX: only a few today) and 3669 * optionally will callback via a func pointer to the calling code with the 3670 * resulting ACK code from the packet. If the ACK code is to be ignored (i.e. 3671 * no cb) then the write routine will take care of free'ing the abuf since the 3672 * fwnode/etc code won't have any knowledge of when to do this. This allows for 3673 * simple one-off packets to be sent from the upper-level code without worrying 3674 * about a callback for cleanup. 3675 * 3676 * int fwohci_inreg(struct ieee1394_abuf *, int) 3677 * 3678 * This is very simple. It evals the abuf passed in and registers an internal 3679 * handler as the callback for packets received for that operation. 3680 * The integer argument specifies whether on a block read/write operation to 3681 * allow sub-regions to be read/written (in block form) as well. 3682 * 3683 * XXX: This whole structure needs to be redone as a list of regions and 3684 * operations allowed on those regions. 3685 * 3686 * int fwohci_unreg(struct ieee1394_abuf *, int) 3687 * 3688 * This simply unregisters the respective callback done via inreg for items 3689 * which only need to register an area for a one-time operation (like a status 3690 * buffer a remote node will write to when the current operation is done). The 3691 * int argument specifies the same behavior as inreg, except in reverse (i.e. 3692 * it unregisters). 3693 */ 3694 3695 static int 3696 fwohci_read(struct ieee1394_abuf *ab) 3697 { 3698 struct fwohci_pkt pkt; 3699 struct ieee1394_softc *sc = ab->ab_req; 3700 struct fwohci_softc *psc = 3701 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3702 struct fwohci_cb *fcb; 3703 u_int32_t high, lo; 3704 int rv, tcode; 3705 3706 /* Have to have a callback when reading. */ 3707 if (ab->ab_cb == NULL) 3708 return -1; 3709 3710 fcb = malloc(sizeof(struct fwohci_cb), M_DEVBUF, M_WAITOK); 3711 fcb->ab = ab; 3712 fcb->count = 0; 3713 fcb->abuf_valid = 1; 3714 3715 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3716 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3717 3718 memset(&pkt, 0, sizeof(pkt)); 3719 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3720 pkt.fp_hdr[2] = lo; 3721 pkt.fp_dlen = 0; 3722 3723 if (ab->ab_length == 4) { 3724 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3725 tcode = IEEE1394_TCODE_READ_RESP_QUAD; 3726 pkt.fp_hlen = 12; 3727 } else { 3728 pkt.fp_tcode = IEEE1394_TCODE_READ_REQ_BLOCK; 3729 pkt.fp_hlen = 16; 3730 tcode = IEEE1394_TCODE_READ_RESP_BLOCK; 3731 pkt.fp_hdr[3] = (ab->ab_length << 16); 3732 } 3733 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3734 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3735 3736 pkt.fp_statusarg = fcb; 3737 pkt.fp_statuscb = fwohci_read_resp; 3738 3739 rv = fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3740 psc->sc_tlabel, 0, fwohci_read_resp, fcb); 3741 if (rv) 3742 return rv; 3743 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3744 if (rv) 3745 fwohci_handler_set(psc, tcode, ab->ab_req->sc1394_node_id, 3746 psc->sc_tlabel, 0, NULL, NULL); 3747 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3748 fcb->count = 1; 3749 return rv; 3750 } 3751 3752 static int 3753 fwohci_write(struct ieee1394_abuf *ab) 3754 { 3755 struct fwohci_pkt pkt; 3756 struct ieee1394_softc *sc = ab->ab_req; 3757 struct fwohci_softc *psc = 3758 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 3759 u_int32_t high, lo; 3760 int rv; 3761 3762 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_BLOCK) { 3763 if (ab->ab_length > IEEE1394_MAX_REC(sc->sc1394_max_receive)) { 3764 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 3765 return E2BIG; 3766 } 3767 } 3768 3769 if (ab->ab_length > 3770 IEEE1394_MAX_ASYNCH_FOR_SPEED(sc->sc1394_link_speed)) { 3771 DPRINTF(("Packet too large: %d\n", ab->ab_length)); 3772 return E2BIG; 3773 } 3774 3775 if (ab->ab_data && ab->ab_uio) 3776 panic("Can't call with uio and data set"); 3777 if ((ab->ab_data == NULL) && (ab->ab_uio == NULL)) 3778 panic("One of either ab_data or ab_uio must be set"); 3779 3780 memset(&pkt, 0, sizeof(pkt)); 3781 3782 pkt.fp_tcode = ab->ab_tcode; 3783 if (ab->ab_data) { 3784 pkt.fp_uio.uio_iov = pkt.fp_iov; 3785 pkt.fp_uio.uio_segflg = UIO_SYSSPACE; 3786 pkt.fp_uio.uio_rw = UIO_WRITE; 3787 } else 3788 memcpy(&pkt.fp_uio, ab->ab_uio, sizeof(struct uio)); 3789 3790 pkt.fp_statusarg = ab; 3791 pkt.fp_statuscb = fwohci_write_ack; 3792 3793 switch (ab->ab_tcode) { 3794 case IEEE1394_TCODE_WRITE_RESP: 3795 pkt.fp_hlen = 12; 3796 case IEEE1394_TCODE_READ_RESP_QUAD: 3797 case IEEE1394_TCODE_READ_RESP_BLOCK: 3798 if (!pkt.fp_hlen) 3799 pkt.fp_hlen = 16; 3800 high = ab->ab_retlen; 3801 ab->ab_retlen = 0; 3802 lo = 0; 3803 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3804 (ab->ab_tlabel << 10) | (pkt.fp_tcode << 4); 3805 break; 3806 default: 3807 pkt.fp_hlen = 16; 3808 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3809 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3810 pkt.fp_hdr[0] = 0x00000100 | (sc->sc1394_link_speed << 16) | 3811 (psc->sc_tlabel << 10) | (pkt.fp_tcode << 4); 3812 psc->sc_tlabel = (psc->sc_tlabel + 1) & 0x3f; 3813 break; 3814 } 3815 3816 pkt.fp_hdr[1] = ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3817 pkt.fp_hdr[2] = lo; 3818 if (pkt.fp_hlen == 16) { 3819 if (ab->ab_length == 4) { 3820 pkt.fp_hdr[3] = ab->ab_data[0]; 3821 pkt.fp_dlen = 0; 3822 } else { 3823 pkt.fp_hdr[3] = (ab->ab_length << 16); 3824 pkt.fp_dlen = ab->ab_length; 3825 if (ab->ab_data) { 3826 pkt.fp_uio.uio_iovcnt = 1; 3827 pkt.fp_uio.uio_resid = ab->ab_length; 3828 pkt.fp_iov[0].iov_base = ab->ab_data; 3829 pkt.fp_iov[0].iov_len = ab->ab_length; 3830 } 3831 } 3832 } 3833 switch (ab->ab_tcode) { 3834 case IEEE1394_TCODE_WRITE_RESP: 3835 case IEEE1394_TCODE_READ_RESP_QUAD: 3836 case IEEE1394_TCODE_READ_RESP_BLOCK: 3837 rv = fwohci_at_output(psc, psc->sc_ctx_atrs, &pkt); 3838 break; 3839 default: 3840 rv = fwohci_at_output(psc, psc->sc_ctx_atrq, &pkt); 3841 break; 3842 } 3843 return rv; 3844 } 3845 3846 static int 3847 fwohci_read_resp(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 3848 { 3849 struct fwohci_cb *fcb = arg; 3850 struct ieee1394_abuf *ab = fcb->ab; 3851 struct fwohci_pkt newpkt; 3852 u_int32_t *cur, high, lo; 3853 int i, tcode, rcode, status, rv; 3854 3855 /* 3856 * Both the ACK handling and normal response callbacks are handled here. 3857 * The main reason for this is the various error conditions that can 3858 * occur trying to block read some areas and the ways that gets reported 3859 * back to calling station. This is a variety of ACK codes, responses, 3860 * etc which makes it much more difficult to process if both aren't 3861 * handled here. 3862 */ 3863 3864 /* Check for status packet. */ 3865 3866 if (pkt->fp_tcode == -1) { 3867 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 3868 rcode = -1; 3869 tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 3870 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3871 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 3872 DPRINTFN(2, ("Got status packet: 0x%02x\n", 3873 (unsigned int)status)); 3874 fcb->count--; 3875 3876 /* 3877 * Got all the ack's back and the buffer is invalid (i.e. the 3878 * callback has been called. Clean up. 3879 */ 3880 3881 if (fcb->abuf_valid == 0) { 3882 if (fcb->count == 0) 3883 free(fcb, M_DEVBUF); 3884 return IEEE1394_RCODE_COMPLETE; 3885 } 3886 } else { 3887 status = -1; 3888 tcode = pkt->fp_tcode; 3889 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 3890 } 3891 3892 /* 3893 * Some area's (like the config rom want to be read as quadlets only. 3894 * 3895 * The current ideas to try are: 3896 * 3897 * Got an ACK_TYPE_ERROR on a block read. 3898 * 3899 * Got either RCODE_TYPE or RCODE_ADDRESS errors in a block read 3900 * response. 3901 * 3902 * In all cases construct a new packet for a quadlet read and let 3903 * mutli_resp handle the iteration over the space. 3904 */ 3905 3906 if (((status == OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR) && 3907 (tcode == IEEE1394_TCODE_READ_REQ_BLOCK)) || 3908 (((rcode == IEEE1394_RCODE_TYPE_ERROR) || 3909 (rcode == IEEE1394_RCODE_ADDRESS_ERROR)) && 3910 (tcode == IEEE1394_TCODE_READ_RESP_BLOCK))) { 3911 3912 /* Read the area in quadlet chunks (internally track this). */ 3913 3914 memset(&newpkt, 0, sizeof(newpkt)); 3915 3916 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 3917 lo = (ab->ab_addr & 0x00000000ffffffffULL); 3918 3919 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 3920 newpkt.fp_hlen = 12; 3921 newpkt.fp_dlen = 0; 3922 newpkt.fp_hdr[1] = 3923 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 3924 newpkt.fp_hdr[2] = lo; 3925 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 3926 (newpkt.fp_tcode << 4); 3927 3928 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3929 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 0, 3930 fwohci_read_multi_resp, fcb); 3931 if (rv) { 3932 (*ab->ab_cb)(ab, -1); 3933 goto cleanup; 3934 } 3935 newpkt.fp_statusarg = fcb; 3936 newpkt.fp_statuscb = fwohci_read_resp; 3937 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 3938 if (rv) { 3939 fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 3940 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 0, NULL, 3941 NULL); 3942 (*ab->ab_cb)(ab, -1); 3943 goto cleanup; 3944 } 3945 fcb->count++; 3946 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 3947 return IEEE1394_RCODE_COMPLETE; 3948 } else if ((rcode != -1) || ((status != -1) && 3949 (status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 3950 (status != OHCI_CTXCTL_EVENT_ACK_PENDING))) { 3951 3952 /* 3953 * Recombine all the iov data into 1 chunk for higher 3954 * level code. 3955 */ 3956 3957 if (rcode != -1) { 3958 cur = ab->ab_data; 3959 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 3960 /* 3961 * Make sure and don't exceed the buffer 3962 * allocated for return. 3963 */ 3964 if ((ab->ab_retlen + pkt->fp_iov[i].iov_len) > 3965 ab->ab_length) { 3966 memcpy(cur, pkt->fp_iov[i].iov_base, 3967 (ab->ab_length - ab->ab_retlen)); 3968 ab->ab_retlen = ab->ab_length; 3969 break; 3970 } 3971 memcpy(cur, pkt->fp_iov[i].iov_base, 3972 pkt->fp_iov[i].iov_len); 3973 cur += pkt->fp_iov[i].iov_len; 3974 ab->ab_retlen += pkt->fp_iov[i].iov_len; 3975 } 3976 } 3977 if (status != -1) 3978 /* XXX: Need a complete tlabel interface. */ 3979 for (i = 0; i < 64; i++) 3980 fwohci_handler_set(sc, 3981 IEEE1394_TCODE_READ_RESP_QUAD, 3982 ab->ab_req->sc1394_node_id, i, 0, NULL, 3983 NULL); 3984 (*ab->ab_cb)(ab, rcode); 3985 goto cleanup; 3986 } else 3987 /* Good ack packet. */ 3988 return IEEE1394_RCODE_COMPLETE; 3989 3990 /* Can't get here unless ab->ab_cb has been called. */ 3991 3992 cleanup: 3993 fcb->abuf_valid = 0; 3994 if (fcb->count == 0) 3995 free(fcb, M_DEVBUF); 3996 return IEEE1394_RCODE_COMPLETE; 3997 } 3998 3999 static int 4000 fwohci_read_multi_resp(struct fwohci_softc *sc, void *arg, 4001 struct fwohci_pkt *pkt) 4002 { 4003 struct fwohci_cb *fcb = arg; 4004 struct ieee1394_abuf *ab = fcb->ab; 4005 struct fwohci_pkt newpkt; 4006 u_int32_t high, lo; 4007 int rcode, rv; 4008 4009 /* 4010 * Bad return codes from the wire, just return what's already in the 4011 * buf. 4012 */ 4013 4014 /* Make sure a response packet didn't arrive after a bad ACK. */ 4015 if (fcb->abuf_valid == 0) 4016 return IEEE1394_RCODE_COMPLETE; 4017 4018 rcode = (pkt->fp_hdr[1] & 0x0000f000) >> 12; 4019 4020 if (rcode) { 4021 (*ab->ab_cb)(ab, rcode); 4022 goto cleanup; 4023 } 4024 4025 if ((ab->ab_retlen + pkt->fp_iov[0].iov_len) > ab->ab_length) { 4026 memcpy(((char *)ab->ab_data + ab->ab_retlen), 4027 pkt->fp_iov[0].iov_base, (ab->ab_length - ab->ab_retlen)); 4028 ab->ab_retlen = ab->ab_length; 4029 } else { 4030 memcpy(((char *)ab->ab_data + ab->ab_retlen), 4031 pkt->fp_iov[0].iov_base, 4); 4032 ab->ab_retlen += 4; 4033 } 4034 /* Still more, loop and read 4 more bytes. */ 4035 if (ab->ab_retlen < ab->ab_length) { 4036 memset(&newpkt, 0, sizeof(newpkt)); 4037 4038 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 4039 lo = (ab->ab_addr & 0x00000000ffffffffULL) + ab->ab_retlen; 4040 4041 newpkt.fp_tcode = IEEE1394_TCODE_READ_REQ_QUAD; 4042 newpkt.fp_hlen = 12; 4043 newpkt.fp_dlen = 0; 4044 newpkt.fp_hdr[1] = 4045 ((0xffc0 | ab->ab_req->sc1394_node_id) << 16) | high; 4046 newpkt.fp_hdr[2] = lo; 4047 newpkt.fp_hdr[0] = 0x00000100 | (sc->sc_tlabel << 10) | 4048 (newpkt.fp_tcode << 4); 4049 4050 newpkt.fp_statusarg = fcb; 4051 newpkt.fp_statuscb = fwohci_read_resp; 4052 4053 /* 4054 * Bad return code. Just give up and return what's 4055 * come in now. 4056 */ 4057 rv = fwohci_handler_set(sc, IEEE1394_TCODE_READ_RESP_QUAD, 4058 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 0, 4059 fwohci_read_multi_resp, fcb); 4060 if (rv) 4061 (*ab->ab_cb)(ab, -1); 4062 else { 4063 rv = fwohci_at_output(sc, sc->sc_ctx_atrq, &newpkt); 4064 if (rv) { 4065 fwohci_handler_set(sc, 4066 IEEE1394_TCODE_READ_RESP_QUAD, 4067 ab->ab_req->sc1394_node_id, sc->sc_tlabel, 4068 0, NULL, NULL); 4069 (*ab->ab_cb)(ab, -1); 4070 } else { 4071 sc->sc_tlabel = (sc->sc_tlabel + 1) & 0x3f; 4072 fcb->count++; 4073 return IEEE1394_RCODE_COMPLETE; 4074 } 4075 } 4076 } else 4077 (*ab->ab_cb)(ab, IEEE1394_RCODE_COMPLETE); 4078 4079 cleanup: 4080 /* Can't get here unless ab_cb has been called. */ 4081 fcb->abuf_valid = 0; 4082 if (fcb->count == 0) 4083 free(fcb, M_DEVBUF); 4084 return IEEE1394_RCODE_COMPLETE; 4085 } 4086 4087 static int 4088 fwohci_write_ack(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 4089 { 4090 struct ieee1394_abuf *ab = arg; 4091 u_int16_t status; 4092 4093 4094 status = pkt->fp_status & OHCI_DESC_STATUS_ACK_MASK; 4095 if ((status != OHCI_CTXCTL_EVENT_ACK_COMPLETE) && 4096 (status != OHCI_CTXCTL_EVENT_ACK_PENDING)) 4097 DPRINTF(("Got status packet: 0x%02x\n", 4098 (unsigned int)status)); 4099 4100 /* No callback means this level should free the buffers. */ 4101 if (ab->ab_cb) 4102 (*ab->ab_cb)(ab, status); 4103 else { 4104 if (ab->ab_data) 4105 free(ab->ab_data, M_1394DATA); 4106 free(ab, M_1394DATA); 4107 } 4108 return IEEE1394_RCODE_COMPLETE; 4109 } 4110 4111 static int 4112 fwohci_inreg(struct ieee1394_abuf *ab, int allow) 4113 { 4114 struct ieee1394_softc *sc = ab->ab_req; 4115 struct fwohci_softc *psc = 4116 (struct fwohci_softc *)sc->sc1394_dev.dv_parent; 4117 u_int32_t high, lo; 4118 int rv; 4119 4120 high = ((ab->ab_addr & 0x0000ffff00000000ULL) >> 32); 4121 lo = (ab->ab_addr & 0x00000000ffffffffULL); 4122 4123 rv = 0; 4124 switch (ab->ab_tcode) { 4125 case IEEE1394_TCODE_READ_REQ_QUAD: 4126 case IEEE1394_TCODE_WRITE_REQ_QUAD: 4127 if (ab->ab_cb) 4128 rv = fwohci_handler_set(psc, ab->ab_tcode, high, lo, 0, 4129 fwohci_parse_input, ab); 4130 else 4131 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 0, NULL, 4132 NULL); 4133 break; 4134 case IEEE1394_TCODE_READ_REQ_BLOCK: 4135 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 4136 if (allow) { 4137 if (ab->ab_cb) { 4138 rv = fwohci_handler_set(psc, ab->ab_tcode, 4139 high, lo, ab->ab_length, 4140 fwohci_parse_input, ab); 4141 if (rv) 4142 fwohci_handler_set(psc, ab->ab_tcode, 4143 high, lo, ab->ab_length, NULL, 4144 NULL); 4145 ab->ab_subok = 1; 4146 } else 4147 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 4148 ab->ab_length, NULL, NULL); 4149 } else { 4150 if (ab->ab_cb) 4151 rv = fwohci_handler_set(psc, ab->ab_tcode, high, 4152 lo, 0, fwohci_parse_input, ab); 4153 else 4154 fwohci_handler_set(psc, ab->ab_tcode, high, lo, 4155 0, NULL, NULL); 4156 } 4157 break; 4158 default: 4159 DPRINTF(("Invalid registration tcode: %d\n", ab->ab_tcode)); 4160 return -1; 4161 break; 4162 } 4163 return rv; 4164 } 4165 4166 static int 4167 fwohci_unreg(struct ieee1394_abuf *ab, int allow) 4168 { 4169 void *save; 4170 int rv; 4171 4172 save = ab->ab_cb; 4173 ab->ab_cb = NULL; 4174 rv = fwohci_inreg(ab, allow); 4175 ab->ab_cb = save; 4176 return rv; 4177 } 4178 4179 static int 4180 fwohci_parse_input(struct fwohci_softc *sc, void *arg, struct fwohci_pkt *pkt) 4181 { 4182 struct ieee1394_abuf *ab = (struct ieee1394_abuf *)arg; 4183 u_int64_t addr; 4184 u_int8_t *cur; 4185 int i, count, ret; 4186 4187 ab->ab_tcode = (pkt->fp_hdr[0] >> 4) & 0xf; 4188 ab->ab_tlabel = (pkt->fp_hdr[0] >> 10) & 0x3f; 4189 addr = (((u_int64_t)(pkt->fp_hdr[1] & 0xffff) << 32) | pkt->fp_hdr[2]); 4190 4191 /* Make sure it's always 0 in case this gets reused multiple times. */ 4192 ab->ab_retlen = 0; 4193 4194 switch (ab->ab_tcode) { 4195 case IEEE1394_TCODE_READ_REQ_QUAD: 4196 ab->ab_retlen = 4; 4197 /* Response's (if required) will come from callback code */ 4198 ret = -1; 4199 break; 4200 case IEEE1394_TCODE_READ_REQ_BLOCK: 4201 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 4202 if (ab->ab_subok) { 4203 if ((addr + ab->ab_retlen) > 4204 (ab->ab_addr + ab->ab_length)) 4205 return IEEE1394_RCODE_ADDRESS_ERROR; 4206 } else 4207 if (ab->ab_retlen != ab->ab_length) 4208 return IEEE1394_RCODE_ADDRESS_ERROR; 4209 /* Response's (if required) will come from callback code */ 4210 ret = -1; 4211 break; 4212 case IEEE1394_TCODE_WRITE_REQ_QUAD: 4213 ab->ab_retlen = 4; 4214 /* Fall through. */ 4215 4216 case IEEE1394_TCODE_WRITE_REQ_BLOCK: 4217 if (!ab->ab_retlen) 4218 ab->ab_retlen = (pkt->fp_hdr[3] >> 16) & 0xffff; 4219 if (ab->ab_subok) { 4220 if ((addr + ab->ab_retlen) > 4221 (ab->ab_addr + ab->ab_length)) 4222 return IEEE1394_RCODE_ADDRESS_ERROR; 4223 } else 4224 if (ab->ab_retlen > ab->ab_length) 4225 return IEEE1394_RCODE_ADDRESS_ERROR; 4226 4227 if (ab->ab_tcode == IEEE1394_TCODE_WRITE_REQ_QUAD) 4228 ab->ab_data[0] = pkt->fp_hdr[3]; 4229 else { 4230 count = 0; 4231 cur = (u_int8_t *)ab->ab_data + (addr - ab->ab_addr); 4232 for (i = 0; i < pkt->fp_uio.uio_iovcnt; i++) { 4233 memcpy(cur, pkt->fp_iov[i].iov_base, 4234 pkt->fp_iov[i].iov_len); 4235 cur += pkt->fp_iov[i].iov_len; 4236 count += pkt->fp_iov[i].iov_len; 4237 } 4238 if (ab->ab_retlen != count) 4239 panic("Packet claims %d length " 4240 "but only %d bytes returned\n", 4241 ab->ab_retlen, count); 4242 } 4243 ret = IEEE1394_RCODE_COMPLETE; 4244 break; 4245 default: 4246 panic("Got a callback for a tcode that wasn't requested: %d", 4247 ab->ab_tcode); 4248 break; 4249 } 4250 if (ab->ab_cb) { 4251 ab->ab_retaddr = addr; 4252 ab->ab_cb(ab, IEEE1394_RCODE_COMPLETE); 4253 } 4254 return ret; 4255 } 4256 4257 static int 4258 fwohci_submatch(struct device *parent, struct cfdata *cf, void *aux) 4259 { 4260 struct ieee1394_attach_args *fwa = aux; 4261 4262 /* Both halves must be filled in for a match. */ 4263 if ((cf->fwbuscf_idhi == FWBUS_UNK_IDHI && 4264 cf->fwbuscf_idlo == FWBUS_UNK_IDLO) || 4265 (cf->fwbuscf_idhi == ntohl(*((u_int32_t *)&fwa->uid[0])) && 4266 cf->fwbuscf_idlo == ntohl(*((u_int32_t *)&fwa->uid[4])))) 4267 return (config_match(parent, cf, aux)); 4268 return 0; 4269 } 4270 4271 int 4272 fwohci_detach(struct fwohci_softc *sc, int flags) 4273 { 4274 int rv = 0; 4275 4276 if (sc->sc_sc1394.sc1394_if != NULL) 4277 rv = config_detach(sc->sc_sc1394.sc1394_if, flags); 4278 if (rv != 0) 4279 return (rv); 4280 4281 callout_stop(&sc->sc_selfid_callout); 4282 4283 if (sc->sc_powerhook != NULL) 4284 powerhook_disestablish(sc->sc_powerhook); 4285 if (sc->sc_shutdownhook != NULL) 4286 shutdownhook_disestablish(sc->sc_shutdownhook); 4287 4288 return (rv); 4289 } 4290 4291 int 4292 fwohci_activate(struct device *self, enum devact act) 4293 { 4294 struct fwohci_softc *sc = (struct fwohci_softc *)self; 4295 int s, rv = 0; 4296 4297 s = splhigh(); 4298 switch (act) { 4299 case DVACT_ACTIVATE: 4300 rv = EOPNOTSUPP; 4301 break; 4302 4303 case DVACT_DEACTIVATE: 4304 if (sc->sc_sc1394.sc1394_if != NULL) 4305 rv = config_deactivate(sc->sc_sc1394.sc1394_if); 4306 break; 4307 } 4308 splx(s); 4309 4310 return (rv); 4311 } 4312 4313 #ifdef FW_DEBUG 4314 static void 4315 fwohci_show_intr(struct fwohci_softc *sc, u_int32_t intmask) 4316 { 4317 4318 printf("%s: intmask=0x%08x:", sc->sc_sc1394.sc1394_dev.dv_xname, 4319 intmask); 4320 if (intmask & OHCI_Int_CycleTooLong) 4321 printf(" CycleTooLong"); 4322 if (intmask & OHCI_Int_UnrecoverableError) 4323 printf(" UnrecoverableError"); 4324 if (intmask & OHCI_Int_CycleInconsistent) 4325 printf(" CycleInconsistent"); 4326 if (intmask & OHCI_Int_BusReset) 4327 printf(" BusReset"); 4328 if (intmask & OHCI_Int_SelfIDComplete) 4329 printf(" SelfIDComplete"); 4330 if (intmask & OHCI_Int_LockRespErr) 4331 printf(" LockRespErr"); 4332 if (intmask & OHCI_Int_PostedWriteErr) 4333 printf(" PostedWriteErr"); 4334 if (intmask & OHCI_Int_ReqTxComplete) 4335 printf(" ReqTxComplete(0x%04x)", 4336 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_REQUEST, 4337 OHCI_SUBREG_ContextControlClear)); 4338 if (intmask & OHCI_Int_RespTxComplete) 4339 printf(" RespTxComplete(0x%04x)", 4340 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_TX_RESPONSE, 4341 OHCI_SUBREG_ContextControlClear)); 4342 if (intmask & OHCI_Int_ARRS) 4343 printf(" ARRS(0x%04x)", 4344 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 4345 OHCI_SUBREG_ContextControlClear)); 4346 if (intmask & OHCI_Int_ARRQ) 4347 printf(" ARRQ(0x%04x)", 4348 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 4349 OHCI_SUBREG_ContextControlClear)); 4350 if (intmask & OHCI_Int_IsochRx) 4351 printf(" IsochRx(0x%08x)", 4352 OHCI_CSR_READ(sc, OHCI_REG_IsoRecvIntEventClear)); 4353 if (intmask & OHCI_Int_IsochTx) 4354 printf(" IsochTx(0x%08x)", 4355 OHCI_CSR_READ(sc, OHCI_REG_IsoXmitIntEventClear)); 4356 if (intmask & OHCI_Int_RQPkt) 4357 printf(" RQPkt(0x%04x)", 4358 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_REQUEST, 4359 OHCI_SUBREG_ContextControlClear)); 4360 if (intmask & OHCI_Int_RSPkt) 4361 printf(" RSPkt(0x%04x)", 4362 OHCI_ASYNC_DMA_READ(sc, OHCI_CTX_ASYNC_RX_RESPONSE, 4363 OHCI_SUBREG_ContextControlClear)); 4364 printf("\n"); 4365 } 4366 4367 static void 4368 fwohci_show_phypkt(struct fwohci_softc *sc, u_int32_t val) 4369 { 4370 u_int8_t key, phyid; 4371 4372 key = (val & 0xc0000000) >> 30; 4373 phyid = (val & 0x3f000000) >> 24; 4374 printf("%s: PHY packet from %d: ", 4375 sc->sc_sc1394.sc1394_dev.dv_xname, phyid); 4376 switch (key) { 4377 case 0: 4378 printf("PHY Config:"); 4379 if (val & 0x00800000) 4380 printf(" ForceRoot"); 4381 if (val & 0x00400000) 4382 printf(" Gap=%x", (val & 0x003f0000) >> 16); 4383 printf("\n"); 4384 break; 4385 case 1: 4386 printf("Link-on\n"); 4387 break; 4388 case 2: 4389 printf("SelfID:"); 4390 if (val & 0x00800000) { 4391 printf(" #%d", (val & 0x00700000) >> 20); 4392 } else { 4393 if (val & 0x00400000) 4394 printf(" LinkActive"); 4395 printf(" Gap=%x", (val & 0x003f0000) >> 16); 4396 printf(" Spd=S%d", 100 << ((val & 0x0000c000) >> 14)); 4397 if (val & 0x00000800) 4398 printf(" Cont"); 4399 if (val & 0x00000002) 4400 printf(" InitiateBusReset"); 4401 } 4402 if (val & 0x00000001) 4403 printf(" +"); 4404 printf("\n"); 4405 break; 4406 default: 4407 printf("unknown: 0x%08x\n", val); 4408 break; 4409 } 4410 } 4411 #endif /* FW_DEBUG */ 4412 4413 #if 0 4414 void fwohci_dumpreg(struct ieee1394_softc *, struct fwiso_regdump *); 4415 4416 void 4417 fwohci_dumpreg(struct ieee1394_softc *isc, struct fwiso_regdump *fr) 4418 { 4419 struct fwohci_softc *sc = (struct fwohci_softc *)isc; 4420 #if 0 4421 u_int32_t val; 4422 4423 printf("%s: dump reg\n", isc->sc1394_dev.dv_xname); 4424 printf("\tNodeID reg 0x%08x\n", 4425 OHCI_CSR_READ(sc, OHCI_REG_NodeId)); 4426 val = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 4427 printf("\tIsoCounter 0x%08x, %d %d %d", val, 4428 (val >> 25) & 0xfe, (val >> 12) & 0x1fff, val & 0xfff); 4429 val = OHCI_CSR_READ(sc, OHCI_REG_IntMaskSet); 4430 printf(" IntMask 0x%08x, %s\n", val, 4431 val & OHCI_Int_IsochTx ? "isoTx" : ""); 4432 4433 val = OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_ContextControlSet); 4434 printf("\tIT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 4435 OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_CommandPtr), 4436 val, 4437 val & OHCI_CTXCTL_RUN ? " run" : "", 4438 val & OHCI_CTXCTL_WAKE ? " wake" : "", 4439 val & OHCI_CTXCTL_DEAD ? " dead" : "", 4440 val & OHCI_CTXCTL_ACTIVE ? " active" : ""); 4441 #endif 4442 4443 fr->fr_nodeid = OHCI_CSR_READ(sc, OHCI_REG_NodeId); 4444 fr->fr_isocounter = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 4445 fr->fr_intmask = OHCI_CSR_READ(sc, OHCI_REG_IntMaskSet); 4446 fr->fr_it0_commandptr = OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_CommandPtr); 4447 fr->fr_it0_contextctrl = OHCI_SYNC_TX_DMA_READ(sc, 0, OHCI_SUBREG_ContextControlSet); 4448 4449 4450 } 4451 #endif 4452 4453 4454 u_int16_t 4455 fwohci_cycletimer(struct fwohci_softc *sc) 4456 { 4457 u_int32_t reg; 4458 4459 reg = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 4460 4461 return (reg >> 12)&0xffff; 4462 } 4463 4464 4465 u_int16_t 4466 fwohci_it_cycletimer(ieee1394_it_tag_t it) 4467 { 4468 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 4469 4470 return fwohci_cycletimer(itc->itc_sc); 4471 } 4472 4473 4474 4475 4476 4477 /* 4478 * return value: if positive value, number of DMA buffer segments. If 4479 * negative value, error happens. Never zero. 4480 */ 4481 static int 4482 fwohci_misc_dmabuf_alloc(bus_dma_tag_t dmat, int dsize, int segno, 4483 bus_dma_segment_t *segp, bus_dmamap_t *dmapp, void **mapp, 4484 const char *xname) 4485 { 4486 int nsegs; 4487 int error; 4488 4489 printf("fwohci_misc_desc_alloc: dsize %d segno %d\n", dsize, segno); 4490 4491 if ((error = bus_dmamem_alloc(dmat, dsize, PAGE_SIZE, 0, 4492 segp, segno, &nsegs, 0)) != 0) { 4493 printf("%s: unable to allocate descriptor buffer, error = %d\n", 4494 xname, error); 4495 goto fail_0; 4496 } 4497 4498 DPRINTF(("fwohci_misc_desc_alloc: %d segment[s]\n", nsegs)); 4499 4500 if ((error = bus_dmamem_map(dmat, segp, nsegs, dsize, (caddr_t *)mapp, 4501 BUS_DMA_COHERENT | BUS_DMA_WAITOK)) != 0) { 4502 printf("%s: unable to map descriptor buffer, error = %d\n", 4503 xname, error); 4504 goto fail_1; 4505 } 4506 4507 DPRINTF(("fwohci_misc_desc_alloc: %s map ok\n", xname)); 4508 4509 #ifdef FWOHCI_DEBUG 4510 { 4511 int loop; 4512 4513 for (loop = 0; loop < nsegs; ++loop) { 4514 printf("\t%.2d: 0x%lx - 0x%lx\n", loop, 4515 (long)segp[loop].ds_addr, 4516 (long)segp[loop].ds_addr + segp[loop].ds_len - 1); 4517 } 4518 } 4519 #endif /* FWOHCI_DEBUG */ 4520 4521 if ((error = bus_dmamap_create(dmat, dsize, nsegs, dsize, 4522 0, BUS_DMA_WAITOK, dmapp)) != 0) { 4523 printf("%s: unable to create descriptor buffer DMA map, " 4524 "error = %d\n", xname, error); 4525 goto fail_2; 4526 } 4527 4528 DPRINTF(("fwohci_misc_dmabuf_alloc: bus_dmamem_create success\n")); 4529 4530 if ((error = bus_dmamap_load(dmat, *dmapp, *mapp, dsize, NULL, 4531 BUS_DMA_WAITOK)) != 0) { 4532 printf("%s: unable to load descriptor buffer DMA map, " 4533 "error = %d\n", xname, error); 4534 goto fail_3; 4535 } 4536 4537 DPRINTF(("fwohci_it_desc_alloc: bus_dmamem_load success\n")); 4538 4539 return nsegs; 4540 4541 fail_3: 4542 bus_dmamap_destroy(dmat, *dmapp); 4543 fail_2: 4544 bus_dmamem_unmap(dmat, *mapp, dsize); 4545 fail_1: 4546 bus_dmamem_free(dmat, segp, nsegs); 4547 fail_0: 4548 return error; 4549 } 4550 4551 4552 static void 4553 fwohci_misc_dmabuf_free(bus_dma_tag_t dmat, int dsize, int nsegs, 4554 bus_dma_segment_t *segp, bus_dmamap_t *dmapp, caddr_t map) 4555 { 4556 bus_dmamap_destroy(dmat, *dmapp); 4557 bus_dmamem_unmap(dmat, map, dsize); 4558 bus_dmamem_free(dmat, segp, nsegs); 4559 } 4560 4561 4562 4563 4564 /* 4565 * Isochronous receive service 4566 */ 4567 4568 /* 4569 * static struct fwohci_ir_ctx * 4570 * fwohci_ir_ctx_construct(struct fwohci_softc *sc, int no, int ch, int tagbm, 4571 * int bufnum, int maxsize, int flags) 4572 */ 4573 static struct fwohci_ir_ctx * 4574 fwohci_ir_ctx_construct(struct fwohci_softc *sc, int no, int ch, int tagbm, 4575 int bufnum, int maxsize, int flags) 4576 { 4577 struct fwohci_ir_ctx *irc; 4578 int i; 4579 4580 printf("fwohci_ir_construct(%s, %d, %d, %x, %d, %d\n", 4581 sc->sc_sc1394.sc1394_dev.dv_xname, no, ch, tagbm, bufnum, maxsize); 4582 4583 if ((irc = malloc(sizeof(*irc), M_DEVBUF, M_WAITOK|M_ZERO)) == NULL) { 4584 return NULL; 4585 } 4586 4587 irc->irc_sc = sc; 4588 4589 irc->irc_num = no; 4590 irc->irc_status = 0; 4591 4592 irc->irc_channel = ch; 4593 irc->irc_tagbm = tagbm; 4594 4595 irc->irc_desc_num = bufnum; 4596 4597 irc->irc_flags = flags; 4598 4599 /* add header */ 4600 maxsize += 8; 4601 /* rounding up */ 4602 for (i = 32; i < maxsize; i <<= 1); 4603 printf("fwohci_ir_ctx_construct: maxsize %d => %d\n", 4604 maxsize, i); 4605 4606 maxsize = i; 4607 4608 irc->irc_maxsize = maxsize; 4609 irc->irc_buf_totalsize = bufnum * maxsize; 4610 4611 if (fwohci_ir_buf_setup(irc)) { 4612 /* cannot alloc descriptor */ 4613 return NULL; 4614 } 4615 4616 irc->irc_readtop = irc->irc_desc_map; 4617 irc->irc_writeend = irc->irc_desc_map + irc->irc_desc_num - 1; 4618 irc->irc_savedbranch = irc->irc_writeend->fd_branch; 4619 irc->irc_writeend->fd_branch = 0; 4620 /* sync */ 4621 4622 if (fwohci_ir_stop(irc) || fwohci_ir_init(irc)) { 4623 return NULL; 4624 } 4625 4626 irc->irc_status |= IRC_STATUS_READY; 4627 4628 return irc; 4629 } 4630 4631 4632 4633 /* 4634 * static void fwohci_ir_ctx_destruct(struct fwohci_ir_ctx *irc) 4635 * 4636 * This function release all DMA buffers and itself. 4637 */ 4638 static void 4639 fwohci_ir_ctx_destruct(struct fwohci_ir_ctx *irc) 4640 { 4641 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, irc->irc_buf_totalsize, 4642 irc->irc_buf_nsegs, irc->irc_buf_segs, 4643 &irc->irc_buf_dmamap, (caddr_t)irc->irc_buf); 4644 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4645 irc->irc_desc_size, 4646 irc->irc_desc_nsegs, &irc->irc_desc_seg, 4647 &irc->irc_desc_dmamap, (caddr_t)irc->irc_desc_map); 4648 4649 free(irc, M_DEVBUF); 4650 } 4651 4652 4653 4654 4655 /* 4656 * static int fwohci_ir_buf_setup(struct fwohci_ir_ctx *irc) 4657 * 4658 * Allocates descriptors for context DMA dedicated for 4659 * isochronous receive. 4660 * 4661 * This function returns 0 (zero) if it succeeds. Otherwise, 4662 * return negative value. 4663 */ 4664 static int 4665 fwohci_ir_buf_setup(struct fwohci_ir_ctx *irc) 4666 { 4667 int nsegs; 4668 struct fwohci_desc *fd; 4669 u_int32_t branch; 4670 int bufno = 0; /* DMA segment */ 4671 bus_size_t bufused = 0; /* offset in a DMA segment */ 4672 4673 irc->irc_desc_size = irc->irc_desc_num * sizeof(struct fwohci_desc); 4674 4675 nsegs = fwohci_misc_dmabuf_alloc(irc->irc_sc->sc_dmat, 4676 irc->irc_desc_size, 1, &irc->irc_desc_seg, &irc->irc_desc_dmamap, 4677 (void **)&irc->irc_desc_map, 4678 irc->irc_sc->sc_sc1394.sc1394_dev.dv_xname); 4679 4680 if (nsegs < 0) { 4681 printf("fwohci_ir_buf_alloc: cannot get descriptor\n"); 4682 return -1; 4683 } 4684 irc->irc_desc_nsegs = nsegs; 4685 4686 nsegs = fwohci_misc_dmabuf_alloc(irc->irc_sc->sc_dmat, 4687 irc->irc_buf_totalsize, 16, irc->irc_buf_segs, 4688 &irc->irc_buf_dmamap, (void **)&irc->irc_buf, 4689 irc->irc_sc->sc_sc1394.sc1394_dev.dv_xname); 4690 4691 if (nsegs < 0) { 4692 printf("fwohci_ir_buf_alloc: cannot get DMA buffer\n"); 4693 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4694 irc->irc_desc_size, 4695 irc->irc_desc_nsegs, &irc->irc_desc_seg, 4696 &irc->irc_desc_dmamap, (caddr_t)irc->irc_desc_map); 4697 return -1; 4698 } 4699 irc->irc_buf_nsegs = nsegs; 4700 4701 branch = irc->irc_desc_dmamap->dm_segs[0].ds_addr 4702 + sizeof(struct fwohci_desc); 4703 bufno = 0; 4704 bufused = 0; 4705 4706 for (fd = irc->irc_desc_map; 4707 fd < irc->irc_desc_map + irc->irc_desc_num; ++fd) { 4708 fd->fd_flags = OHCI_DESC_INPUT | OHCI_DESC_LAST 4709 | OHCI_DESC_STATUS | OHCI_DESC_BRANCH; 4710 if (irc->irc_flags & IEEE1394_IR_SHORTDELAY) { 4711 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 4712 } 4713 #if 0 4714 if ((fd - irc->irc_desc_map) % 64 == 0) { 4715 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 4716 } 4717 #endif 4718 fd->fd_reqcount = irc->irc_maxsize; 4719 fd->fd_status = fd->fd_rescount = 0; 4720 4721 fd->fd_branch = branch | 0x01; 4722 branch += sizeof(struct fwohci_desc); 4723 4724 /* physical addr to data? */ 4725 fd->fd_data = 4726 (u_int32_t)((irc->irc_buf_segs[bufno].ds_addr + bufused)); 4727 bufused += irc->irc_maxsize; 4728 if (bufused > irc->irc_buf_segs[bufno].ds_len) { 4729 bufused = 0; 4730 if (++bufno == irc->irc_buf_nsegs) { 4731 /* fail */ 4732 printf("fwohci_ir_buf_setup fail\n"); 4733 4734 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4735 irc->irc_desc_size, 4736 irc->irc_desc_nsegs, &irc->irc_desc_seg, 4737 &irc->irc_desc_dmamap, 4738 (caddr_t)irc->irc_desc_map); 4739 fwohci_misc_dmabuf_free(irc->irc_sc->sc_dmat, 4740 irc->irc_buf_totalsize, 4741 irc->irc_buf_nsegs, irc->irc_buf_segs, 4742 &irc->irc_buf_dmamap, 4743 (caddr_t)irc->irc_buf); 4744 return -1; 4745 } 4746 } 4747 4748 #ifdef FWOHCI_DEBUG 4749 if (fd < irc->irc_desc_map + 4 4750 || (fd > irc->irc_desc_map + irc->irc_desc_num - 4)) { 4751 printf("fwohci_ir_buf_setup: desc %d %p buf %08x" 4752 " size %d branch %08x\n", 4753 fd - irc->irc_desc_map, fd, fd->fd_data, 4754 fd->fd_reqcount, fd->fd_branch); 4755 } 4756 #endif /* FWOHCI_DEBUG */ 4757 } 4758 4759 --fd; 4760 fd->fd_branch = irc->irc_desc_dmamap->dm_segs[0].ds_addr | 1; 4761 DPRINTF(("fwohci_ir_buf_setup: desc %d %p buf %08x size %d branch %08x\n", 4762 fd - irc->irc_desc_map, fd, fd->fd_data, fd->fd_reqcount, 4763 fd->fd_branch)); 4764 4765 return 0; 4766 } 4767 4768 4769 4770 /* 4771 * static void fwohci_ir_init(struct fwohci_ir_ctx *irc) 4772 * 4773 * This function initialise DMA engine. 4774 */ 4775 static int 4776 fwohci_ir_init(struct fwohci_ir_ctx *irc) 4777 { 4778 struct fwohci_softc *sc = irc->irc_sc; 4779 int n = irc->irc_num; 4780 u_int32_t ctxmatch; 4781 4782 ctxmatch = irc->irc_channel & IEEE1394_ISO_CHANNEL_MASK; 4783 4784 if (irc->irc_channel & IEEE1394_ISO_CHANNEL_ANY) { 4785 OHCI_SYNC_RX_DMA_WRITE(sc, n, 4786 OHCI_SUBREG_ContextControlSet, 4787 OHCI_CTXCTL_RX_MULTI_CHAN_MODE); 4788 4789 /* Receive all the isochronous channels */ 4790 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskHiSet, 0xffffffff); 4791 OHCI_CSR_WRITE(sc, OHCI_REG_IRMultiChanMaskLoSet, 0xffffffff); 4792 ctxmatch = 0; 4793 } 4794 4795 ctxmatch |= ((irc->irc_tagbm & 0x0f) << OHCI_CTXMATCH_TAG_BITPOS); 4796 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextMatch, ctxmatch); 4797 4798 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlClear, 4799 OHCI_CTXCTL_RX_BUFFER_FILL | OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE); 4800 OHCI_SYNC_RX_DMA_WRITE(sc, n, OHCI_SUBREG_ContextControlSet, 4801 OHCI_CTXCTL_RX_ISOCH_HEADER); 4802 4803 printf("fwohci_ir_init\n"); 4804 4805 return 0; 4806 } 4807 4808 4809 /* 4810 * static int fwohci_ir_start(struct fwohci_ir_ctx *irc) 4811 * 4812 * This function starts DMA engine. This function must call 4813 * after fwohci_ir_init() and active bit of context control 4814 * register negated. This function will not check it. 4815 */ 4816 static int 4817 fwohci_ir_start(struct fwohci_ir_ctx *irc) 4818 { 4819 struct fwohci_softc *sc = irc->irc_sc; 4820 int startidx = irc->irc_readtop - irc->irc_desc_map; 4821 u_int32_t startaddr; 4822 4823 startaddr = irc->irc_desc_dmamap->dm_segs[0].ds_addr 4824 + sizeof(struct fwohci_desc)*startidx; 4825 4826 OHCI_SYNC_RX_DMA_WRITE(sc, irc->irc_num, OHCI_SUBREG_CommandPtr, 4827 startaddr | 1); 4828 OHCI_CSR_WRITE(sc, OHCI_REG_IsoRecvIntEventClear, 4829 (1 << irc->irc_num)); 4830 OHCI_SYNC_RX_DMA_WRITE(sc, irc->irc_num, 4831 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 4832 4833 printf("fwohci_ir_start: CmdPtr %08x Ctx %08x startidx %d\n", 4834 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, OHCI_SUBREG_CommandPtr), 4835 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, OHCI_SUBREG_ContextControlSet), 4836 startidx); 4837 4838 irc->irc_status &= ~IRC_STATUS_READY; 4839 irc->irc_status |= IRC_STATUS_RUN; 4840 4841 if ((irc->irc_flags & IEEE1394_IR_TRIGGER_CIP_SYNC) == 0) { 4842 irc->irc_status |= IRC_STATUS_RECEIVE; 4843 } 4844 4845 return 0; 4846 } 4847 4848 4849 4850 /* 4851 * static int fwohci_ir_stop(struct fwohci_ir_ctx *irc) 4852 * 4853 * This function stops DMA engine. 4854 */ 4855 static int 4856 fwohci_ir_stop(struct fwohci_ir_ctx *irc) 4857 { 4858 struct fwohci_softc *sc = irc->irc_sc; 4859 int i; 4860 4861 printf("fwohci_ir_stop\n"); 4862 4863 OHCI_SYNC_RX_DMA_WRITE(sc, irc->irc_num, 4864 OHCI_SUBREG_ContextControlClear, 4865 OHCI_CTXCTL_RUN | OHCI_CTXCTL_DEAD); 4866 4867 i = 0; 4868 while (OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4869 OHCI_SUBREG_ContextControlSet) & OHCI_CTXCTL_ACTIVE) { 4870 #if 0 4871 u_int32_t reg = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4872 OHCI_SUBREG_ContextControlClear); 4873 4874 printf("%s: %d intr IR_CommandPtr 0x%08x " 4875 "ContextCtrl 0x%08x%s%s%s%s\n", 4876 sc->sc_sc1394.sc1394_dev.dv_xname, i, 4877 OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4878 OHCI_SUBREG_CommandPtr), 4879 reg, 4880 reg & OHCI_CTXCTL_RUN ? " run" : "", 4881 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 4882 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 4883 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 4884 #endif 4885 if (i > 20) { 4886 printf("fwohci_ir_stop: %s does not stop\n", 4887 sc->sc_sc1394.sc1394_dev.dv_xname); 4888 return 1; 4889 } 4890 DELAY(10); 4891 } 4892 4893 irc->irc_status &= ~IRC_STATUS_RUN; 4894 4895 return 0; 4896 } 4897 4898 4899 4900 4901 4902 4903 static void 4904 fwohci_ir_intr(struct fwohci_softc *sc, struct fwohci_ir_ctx *irc) 4905 { 4906 const char *xname = sc->sc_sc1394.sc1394_dev.dv_xname; 4907 u_int32_t cmd, ctx; 4908 int idx; 4909 struct fwohci_desc *fd; 4910 4911 sc->sc_isocnt.ev_count++; 4912 4913 if (!(irc->irc_status & IRC_STATUS_RUN)) { 4914 printf("fwohci_ir_intr: not running\n"); 4915 return; 4916 } 4917 4918 bus_dmamap_sync(sc->sc_dmat, irc->irc_desc_dmamap, 4919 0, irc->irc_desc_size, BUS_DMASYNC_PREREAD); 4920 4921 ctx = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4922 OHCI_SUBREG_ContextControlSet); 4923 4924 cmd = OHCI_SYNC_RX_DMA_READ(sc, irc->irc_num, 4925 OHCI_SUBREG_CommandPtr); 4926 4927 #define OHCI_CTXCTL_RUNNING (OHCI_CTXCTL_RUN|OHCI_CTXCTL_ACTIVE) 4928 #define OHCI_CTXCTL_RUNNING_MASK (OHCI_CTXCTL_RUNNING|OHCI_CTXCTL_DEAD) 4929 4930 idx = (cmd & 0xfffffff8) - (u_int32_t)irc->irc_desc_dmamap->dm_segs[0].ds_addr; 4931 idx /= sizeof(struct fwohci_desc); 4932 4933 if ((ctx & OHCI_CTXCTL_RUNNING_MASK) == OHCI_CTXCTL_RUNNING) { 4934 if (irc->irc_waitchan != NULL) { 4935 DPRINTF(("fwohci_ir_intr: wakeup " 4936 "ctx %d CmdPtr %08x Ctxctl %08x idx %d\n", 4937 irc->irc_num, cmd, ctx, idx)); 4938 #ifdef FWOHCI_WAIT_DEBUG 4939 irc->irc_cycle[1] = fwohci_cycletimer(irc->irc_sc); 4940 #endif 4941 wakeup((void *)irc->irc_waitchan); 4942 } 4943 selwakeup(&irc->irc_sel); 4944 return; 4945 } 4946 4947 fd = irc->irc_desc_map + idx; 4948 4949 printf("fwohci_ir_intr: %s error " 4950 "ctx %d CmdPtr %08x Ctxctl %08x idx %d\n", xname, 4951 irc->irc_num, cmd, ctx, idx); 4952 printf("\tfd flag %x branch %x stat %x rescnt %x total pkt %d\n", 4953 fd->fd_flags, fd->fd_branch, fd->fd_status,fd->fd_rescount, 4954 irc->irc_pktcount); 4955 } 4956 4957 4958 4959 4960 /* 4961 * static int fwohci_ir_ctx_packetnum(struct fwohci_ir_ctx *irc) 4962 * 4963 * This function obtains the lenth of descriptors with data. 4964 */ 4965 static int 4966 fwohci_ir_ctx_packetnum(struct fwohci_ir_ctx *irc) 4967 { 4968 struct fwohci_desc *fd = irc->irc_readtop; 4969 int i = 0; 4970 4971 /* XXX SYNC */ 4972 while (fd->fd_status != 0) { 4973 if (fd == irc->irc_readtop && i > 0) { 4974 printf("descriptor filled %d at %d\n", i, 4975 irc->irc_pktcount); 4976 #ifdef FWOHCI_WAIT_DEBUG 4977 irc->irc_cycle[2] = fwohci_cycletimer(irc->irc_sc); 4978 printf("cycletimer %d:%d %d:%d %d:%d\n", 4979 irc->irc_cycle[0]>>13, irc->irc_cycle[0]&0x1fff, 4980 irc->irc_cycle[1]>>13, irc->irc_cycle[1]&0x1fff, 4981 irc->irc_cycle[2]>>13, irc->irc_cycle[2]&0x1fff); 4982 #endif 4983 4984 break; 4985 } 4986 4987 ++i; 4988 ++fd; 4989 if (fd == irc->irc_desc_map + irc->irc_desc_num) { 4990 fd = irc->irc_desc_map; 4991 } 4992 4993 } 4994 4995 return i; 4996 } 4997 4998 4999 5000 5001 /* 5002 * int fwohci_ir_read(struct device *dev, ieee1394_ir_tag_t tag, 5003 * struct uio *uio, int headoffs, int flags) 5004 * 5005 * This function reads data from fwohci's isochronous receive 5006 * buffer. 5007 */ 5008 int 5009 fwohci_ir_read(struct device *dev, ieee1394_ir_tag_t tag, struct uio *uio, 5010 int headoffs, int flags) 5011 { 5012 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)tag; 5013 int packetnum; 5014 int copylen, hdrshim, fwisohdrsiz; 5015 struct fwohci_desc *fd, *fdprev; 5016 u_int8_t *data; 5017 int status = 0; 5018 u_int32_t tmpbranch; 5019 int pktcount_prev = irc->irc_pktcount; 5020 #ifdef FW_DEBUG 5021 int totalread = 0; 5022 #endif 5023 5024 if (irc->irc_status & IRC_STATUS_READY) { 5025 printf("fwohci_ir_read: starting iso read engine\n"); 5026 fwohci_ir_start(irc); 5027 } 5028 5029 packetnum = fwohci_ir_ctx_packetnum(irc); 5030 5031 DPRINTF(("fwohci_ir_read resid %d DMA buf %d\n", 5032 uio->uio_resid, packetnum)); 5033 5034 if (packetnum == 0) { 5035 return EAGAIN; 5036 } 5037 5038 #ifdef USEDRAIN 5039 if (packetnum > irc->irc_desc_num - irc->irc_desc_num/4) { 5040 packetnum -= fwohci_ir_ctx_drain(irc); 5041 if (irc->irc_pktcount != 0) { 5042 printf("fwohci_ir_read overrun %d\n", 5043 irc->irc_pktcount); 5044 } 5045 } 5046 #endif /* USEDRAIN */ 5047 5048 fd = irc->irc_readtop; 5049 5050 #if 0 5051 if ((irc->irc_status & IRC_STATUS_RECEIVE) == 0 5052 && irc->irc_flags & IEEE1394_IR_TRIGGER_CIP_SYNC) { 5053 unsigned int s; 5054 int i = 0; 5055 5056 fdprev = fd; 5057 while (fd->fd_status != 0) { 5058 s = data[14] << 8; 5059 s |= data[15]; 5060 5061 if (s != 0x0000ffffu) { 5062 DPRINTF(("find header %x at %d\n", 5063 s, irc->irc_pktcount)); 5064 irc->irc_status |= IRC_STATUS_RECEIVE; 5065 break; 5066 } 5067 5068 fd->fd_rescount = 0; 5069 fd->fd_status = 0; 5070 5071 fdprev = fd; 5072 if (++fd == irc->irc_desc_map + irc->irc_desc_num) { 5073 fd = irc->irc_desc_map; 5074 data = irc->irc_buf; 5075 } 5076 ++i; 5077 } 5078 5079 /* XXX SYNC */ 5080 if (i > 0) { 5081 tmpbranch = fdprev->fd_branch; 5082 fdprev->fd_branch = 0; 5083 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5084 irc->irc_writeend = fdprev; 5085 irc->irc_savedbranch = tmpbranch; 5086 } 5087 /* XXX SYNC */ 5088 5089 if (fd->fd_status == 0) { 5090 return EAGAIN; 5091 } 5092 } 5093 #endif 5094 5095 hdrshim = 8; 5096 fwisohdrsiz = 0; 5097 data = irc->irc_buf + (fd - irc->irc_desc_map) * irc->irc_maxsize; 5098 if (irc->irc_flags & IEEE1394_IR_NEEDHEADER) { 5099 fwisohdrsiz = sizeof(struct fwiso_header); 5100 } 5101 5102 while (fd->fd_status != 0 && 5103 (copylen = fd->fd_reqcount - fd->fd_rescount - hdrshim - headoffs) 5104 + fwisohdrsiz < uio->uio_resid) { 5105 5106 DPRINTF(("pkt %04x:%04x uiomove %p, %d\n", 5107 fd->fd_status, fd->fd_rescount, 5108 (void *)(data + 8 + headoffs), copylen)); 5109 if ((irc->irc_status & IRC_STATUS_RECEIVE) == 0) { 5110 DPRINTF(("[%d]", copylen)); 5111 if (irc->irc_pktcount > 1000) { 5112 printf("no header found\n"); 5113 status = EIO; 5114 break; /* XXX */ 5115 } 5116 } else { 5117 DPRINTF(("<%d>", copylen)); 5118 } 5119 5120 if ((irc->irc_status & IRC_STATUS_RECEIVE) == 0 5121 && irc->irc_flags & IEEE1394_IR_TRIGGER_CIP_SYNC 5122 && copylen > 0) { 5123 unsigned int s; 5124 5125 s = data[14] << 8; 5126 s |= data[15]; 5127 5128 if (s != 0x0000ffffu) { 5129 DPRINTF(("find header %x at %d\n", 5130 s, irc->irc_pktcount)); 5131 irc->irc_status |= IRC_STATUS_RECEIVE; 5132 } 5133 } 5134 5135 if (irc->irc_status & IRC_STATUS_RECEIVE) { 5136 if (copylen > 0) { 5137 if (irc->irc_flags & IEEE1394_IR_NEEDHEADER) { 5138 struct fwiso_header fh; 5139 5140 fh.fh_timestamp = htonl((*(u_int32_t *)data) & 0xffff); 5141 fh.fh_speed = htonl((fd->fd_status >> 5)& 0x00000007); 5142 fh.fh_capture_size = htonl(copylen + 4); 5143 fh.fh_iso_header = htonl(*(u_int32_t *)(data + 4)); 5144 status = uiomove((void *)&fh, 5145 sizeof(fh), uio); 5146 if (status != 0) { 5147 /* An error happens */ 5148 printf("uio error in hdr\n"); 5149 break; 5150 } 5151 } 5152 status = uiomove((void *)(data + 8 + headoffs), 5153 copylen, uio); 5154 if (status != 0) { 5155 /* An error happens */ 5156 printf("uio error\n"); 5157 break; 5158 } 5159 #ifdef FW_DEBUG 5160 totalread += copylen; 5161 #endif 5162 } 5163 } 5164 5165 fd->fd_rescount = 0; 5166 fd->fd_status = 0; 5167 5168 #if 0 5169 /* advance writeend pointer and fill branch */ 5170 5171 tmpbranch = fd->fd_branch; 5172 fd->fd_branch = 0; 5173 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5174 irc->irc_writeend = fd; 5175 irc->irc_savedbranch = tmpbranch; 5176 #endif 5177 fdprev = fd; 5178 5179 data += irc->irc_maxsize; 5180 if (++fd == irc->irc_desc_map + irc->irc_desc_num) { 5181 fd = irc->irc_desc_map; 5182 data = irc->irc_buf; 5183 } 5184 ++irc->irc_pktcount; 5185 } 5186 5187 #if 1 5188 if (irc->irc_pktcount != pktcount_prev) { 5189 /* XXX SYNC */ 5190 tmpbranch = fdprev->fd_branch; 5191 fdprev->fd_branch = 0; 5192 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5193 irc->irc_writeend = fdprev; 5194 irc->irc_savedbranch = tmpbranch; 5195 /* XXX SYNC */ 5196 } 5197 #endif 5198 5199 if (!(OHCI_SYNC_RX_DMA_READ(irc->irc_sc, irc->irc_num, 5200 OHCI_SUBREG_ContextControlClear) & OHCI_CTXCTL_ACTIVE)) { 5201 /* do wake */ 5202 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5203 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_WAKE); 5204 } 5205 5206 if (packetnum > irc->irc_maxqueuelen) { 5207 irc->irc_maxqueuelen = packetnum; 5208 irc->irc_maxqueuepos = irc->irc_pktcount; 5209 } 5210 5211 if (irc->irc_pktcount == pktcount_prev) { 5212 #if 0 5213 printf("fwohci_ir_read: process 0 packet, total %d\n", 5214 irc->irc_pktcount); 5215 if (++pktfail > 30) { 5216 return 0; 5217 } 5218 #endif 5219 return EAGAIN; 5220 } 5221 5222 irc->irc_readtop = fd; 5223 5224 DPRINTF(("fwochi_ir_read: process %d packet, total %d\n", 5225 totalread, irc->irc_pktcount)); 5226 5227 return status; 5228 } 5229 5230 5231 5232 5233 /* 5234 * int fwohci_ir_wait(struct device *dev, ieee1394_ir_tag_t tag, 5235 * void *wchan, char *name) 5236 * 5237 * This function waits till new data comes. 5238 */ 5239 int 5240 fwohci_ir_wait(struct device *dev, ieee1394_ir_tag_t tag, void *wchan, char *name) 5241 { 5242 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)tag; 5243 struct fwohci_desc *fd; 5244 int pktnum; 5245 int stat; 5246 5247 if ((pktnum = fwohci_ir_ctx_packetnum(irc)) > 4) { 5248 DPRINTF(("fwohci_ir_wait enough data %d\n", pktnum)); 5249 return 0; 5250 } 5251 5252 fd = irc->irc_readtop + 32; 5253 if (fd >= irc->irc_desc_map + irc->irc_desc_num) { 5254 fd -= irc->irc_desc_num; 5255 } 5256 5257 irc->irc_waitchan = wchan; 5258 if ((irc->irc_flags & IEEE1394_IR_SHORTDELAY) == 0) { 5259 fd->fd_flags |= OHCI_DESC_INTR_ALWAYS; 5260 DPRINTF(("fwohci_ir_wait stops %d set intr %d\n", 5261 irc->irc_readtop - irc->irc_desc_map, 5262 fd - irc->irc_desc_map)); 5263 /* XXX SYNC */ 5264 } 5265 5266 #ifdef FWOHCI_WAIT_DEBUG 5267 irc->irc_cycle[0] = fwohci_cycletimer(irc->irc_sc); 5268 #endif 5269 5270 irc->irc_status |= IRC_STATUS_SLEEPING; 5271 if ((stat = tsleep(wchan, PCATCH|PRIBIO, name, hz*10)) != 0) { 5272 irc->irc_waitchan = NULL; 5273 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 5274 if (stat == EWOULDBLOCK) { 5275 printf("fwohci_ir_wait: timeout\n"); 5276 return EIO; 5277 } else { 5278 return EINTR; 5279 } 5280 } 5281 5282 irc->irc_waitchan = NULL; 5283 if ((irc->irc_flags & IEEE1394_IR_SHORTDELAY) == 0) { 5284 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 5285 /* XXX SYNC */ 5286 } 5287 5288 DPRINTF(("fwohci_ir_wait: wakeup\n")); 5289 5290 return 0; 5291 } 5292 5293 5294 5295 5296 /* 5297 * int fwohci_ir_select(struct device *dev, ieee1394_ir_tag_t tag, 5298 * struct proc *p) 5299 * 5300 * This function returns the number of packets in queue. 5301 */ 5302 int 5303 fwohci_ir_select(struct device *dev, ieee1394_ir_tag_t tag, struct proc *p) 5304 { 5305 struct fwohci_ir_ctx *irc = (struct fwohci_ir_ctx *)tag; 5306 int pktnum; 5307 5308 if (irc->irc_status & IRC_STATUS_READY) { 5309 printf("fwohci_ir_select: starting iso read engine\n"); 5310 fwohci_ir_start(irc); 5311 } 5312 5313 if ((pktnum = fwohci_ir_ctx_packetnum(irc)) == 0) { 5314 selrecord(p, &irc->irc_sel); 5315 } 5316 5317 return pktnum; 5318 } 5319 5320 5321 5322 #ifdef USEDRAIN 5323 /* 5324 * int fwohci_ir_ctx_drain(struct fwohci_ir_ctx *irc) 5325 * 5326 * This function will drain all the packets in receive DMA 5327 * buffer. 5328 */ 5329 static int 5330 fwohci_ir_ctx_drain(struct fwohci_ir_ctx *irc) 5331 { 5332 struct fwohci_desc *fd = irc->irc_readtop; 5333 u_int32_t reg; 5334 int count = 0; 5335 5336 reg = OHCI_SYNC_RX_DMA_READ(irc->irc_sc, irc->irc_num, 5337 OHCI_SUBREG_ContextControlClear); 5338 5339 printf("fwohci_ir_ctx_drain ctx%s%s%s%s\n", 5340 reg & OHCI_CTXCTL_RUN ? " run" : "", 5341 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5342 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5343 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5344 5345 if ((reg & OHCI_CTXCTL_RUNNING_MASK) == OHCI_CTXCTL_RUN) { 5346 /* DMA engine is stopped */ 5347 u_int32_t startadr; 5348 5349 for (fd = irc->irc_desc_map; 5350 fd < irc->irc_desc_map + irc->irc_desc_num; 5351 ++fd) { 5352 fd->fd_status = 0; 5353 } 5354 5355 /* Restore branch addr of the last descriptor */ 5356 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5357 5358 irc->irc_readtop = irc->irc_desc_map; 5359 irc->irc_writeend = irc->irc_desc_map + irc->irc_desc_num - 1; 5360 irc->irc_savedbranch = irc->irc_writeend->fd_branch; 5361 irc->irc_writeend->fd_branch = 0; 5362 5363 count = irc->irc_desc_num; 5364 5365 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5366 OHCI_SUBREG_ContextControlClear, 5367 OHCI_CTXCTL_RUN | OHCI_CTXCTL_DEAD); 5368 5369 startadr = (u_int32_t)irc->irc_desc_dmamap->dm_segs[0].ds_addr; 5370 5371 printf("fwohci_ir_ctx_drain: remove %d pkts\n", count); 5372 5373 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5374 OHCI_SUBREG_CommandPtr, startadr | 1); 5375 5376 OHCI_SYNC_RX_DMA_WRITE(irc->irc_sc, irc->irc_num, 5377 OHCI_SUBREG_ContextControlSet, OHCI_CTXCTL_RUN); 5378 } else { 5379 const int removecount = irc->irc_desc_num/2; 5380 u_int32_t tmpbranch; 5381 5382 for (count = 0; count < removecount; ++count) { 5383 if (fd->fd_status == 0) { 5384 break; 5385 } 5386 5387 fd->fd_status = 0; 5388 5389 tmpbranch = fd->fd_branch; 5390 fd->fd_branch = 0; 5391 irc->irc_writeend->fd_branch = irc->irc_savedbranch; 5392 irc->irc_writeend = fd; 5393 irc->irc_savedbranch = tmpbranch; 5394 5395 if (++fd == irc->irc_desc_map + irc->irc_desc_num) { 5396 fd = irc->irc_desc_map; 5397 } 5398 ++count; 5399 } 5400 5401 printf("fwohci_ir_ctx_drain: remove %d pkts\n", count); 5402 } 5403 5404 return count; 5405 } 5406 #endif /* USEDRAIN */ 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 /* 5417 * service routines for isochronous transmit 5418 */ 5419 5420 5421 struct fwohci_it_ctx * 5422 fwohci_it_ctx_construct(struct fwohci_softc *sc, int no, int ch, int tag, int maxsize) 5423 { 5424 struct fwohci_it_ctx *itc; 5425 size_t dmastrsize; 5426 struct fwohci_it_dmabuf *dmastr; 5427 struct fwohci_desc *desc; 5428 bus_addr_t descphys; 5429 int nodesc; 5430 int i, j; 5431 5432 if ((itc = malloc(sizeof(*itc), M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) { 5433 return itc; 5434 } 5435 5436 itc->itc_num = no; 5437 itc->itc_flags = 0; 5438 itc->itc_sc = sc; 5439 itc->itc_bufnum = FWOHCI_IT_BUFNUM; 5440 5441 itc->itc_channel = ch; 5442 itc->itc_tag = tag; 5443 itc->itc_speed = OHCI_CTXCTL_SPD_100; /* XXX */ 5444 5445 itc->itc_outpkt = 0; 5446 5447 itc->itc_maxsize = maxsize; 5448 5449 dmastrsize = sizeof(struct fwohci_it_dmabuf)*itc->itc_bufnum; 5450 5451 if ((dmastr = malloc(dmastrsize, M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) { 5452 goto error_1; 5453 } 5454 itc->itc_buf = dmastr; 5455 5456 /* 5457 * Get memory for descriptors. One buffer will have 256 5458 * packet entry and 1 trailing descriptor for writing scratch. 5459 * 4-byte space for scratch. 5460 */ 5461 itc->itc_descsize = (256*3 + 1)*itc->itc_bufnum; 5462 5463 if (fwohci_it_desc_alloc(itc)) { 5464 printf("%s: cannot get enough memory for descriptor\n", 5465 sc->sc_sc1394.sc1394_dev.dv_xname); 5466 goto error_2; 5467 } 5468 5469 /* prepare DMA buffer */ 5470 nodesc = itc->itc_descsize/itc->itc_bufnum; 5471 desc = (struct fwohci_desc *)itc->itc_descmap; 5472 descphys = itc->itc_dseg.ds_addr; 5473 5474 for (i = 0; i < itc->itc_bufnum; ++i) { 5475 5476 if (fwohci_itd_construct(itc, &dmastr[i], i, desc, 5477 descphys, nodesc, 5478 itc->itc_maxsize, itc->itc_scratch_paddr)) { 5479 goto error_3; 5480 } 5481 desc += nodesc; 5482 descphys += sizeof(struct fwohci_desc)*nodesc; 5483 } 5484 5485 #if 1 5486 itc->itc_buf_start = itc->itc_buf; 5487 itc->itc_buf_end = itc->itc_buf; 5488 itc->itc_buf_linkend = itc->itc_buf; 5489 #else 5490 itc->itc_bufidx_start = 0; 5491 itc->itc_bufidx_end = 0; 5492 itc->itc_bufidx_linkend = 0; 5493 #endif 5494 itc->itc_buf_cnt = 0; 5495 itc->itc_waitchan = NULL; 5496 *itc->itc_scratch = 0xffffffff; 5497 5498 return itc; 5499 5500 error_3: 5501 for (j = 0; j < i; ++j) { 5502 fwohci_itd_destruct(&dmastr[j]); 5503 } 5504 fwohci_it_desc_free(itc); 5505 error_2: 5506 free(itc->itc_buf, M_DEVBUF); 5507 error_1: 5508 free(itc, M_DEVBUF); 5509 5510 return NULL; 5511 } 5512 5513 5514 5515 void 5516 fwohci_it_ctx_destruct(struct fwohci_it_ctx *itc) 5517 { 5518 int i; 5519 5520 for (i = 0; i < itc->itc_bufnum; ++i) { 5521 fwohci_itd_destruct(&itc->itc_buf[i]); 5522 } 5523 5524 fwohci_it_desc_free(itc); 5525 free(itc, M_DEVBUF); 5526 } 5527 5528 5529 /* 5530 * static int fwohci_it_desc_alloc(struct fwohci_it_ctx *itc) 5531 * 5532 * Allocates descriptors for context DMA dedicated for 5533 * isochronous transmit. 5534 * 5535 * This function returns 0 (zero) if it succeeds. Otherwise, 5536 * return negative value. 5537 */ 5538 static int 5539 fwohci_it_desc_alloc(struct fwohci_it_ctx *itc) 5540 { 5541 bus_dma_tag_t dmat = itc->itc_sc->sc_dmat; 5542 const char *xname = itc->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 5543 int error, dsize; 5544 5545 /* add for scratch */ 5546 itc->itc_descsize++; 5547 5548 /* rounding up to 256 */ 5549 if ((itc->itc_descsize & 0x0ff) != 0) { 5550 itc->itc_descsize = 5551 (itc->itc_descsize & ~0x0ff) + 0x100; 5552 } 5553 /* remove for scratch */ 5554 5555 itc->itc_descsize--; 5556 printf("%s: fwohci_it_desc_alloc will allocate %d descs\n", 5557 xname, itc->itc_descsize); 5558 5559 /* 5560 * allocate descriptor buffer 5561 */ 5562 dsize = sizeof(struct fwohci_desc) * itc->itc_descsize; 5563 5564 printf("%s: fwohci_it_desc_alloc: descriptor %d, dsize %d\n", 5565 xname, itc->itc_descsize, dsize); 5566 5567 if ((error = bus_dmamem_alloc(dmat, dsize, PAGE_SIZE, 0, 5568 &itc->itc_dseg, 1, &itc->itc_dnsegs, 0)) != 0) { 5569 printf("%s: unable to allocate descriptor buffer, error = %d\n", 5570 xname, error); 5571 goto fail_0; 5572 } 5573 5574 printf("fwohci_it_desc_alloc: %d segment[s]\n", itc->itc_dnsegs); 5575 5576 if ((error = bus_dmamem_map(dmat, &itc->itc_dseg, 5577 itc->itc_dnsegs, dsize, (caddr_t *)&itc->itc_descmap, 5578 BUS_DMA_COHERENT | BUS_DMA_WAITOK)) != 0) { 5579 printf("%s: unable to map descriptor buffer, error = %d\n", 5580 xname, error); 5581 goto fail_1; 5582 } 5583 5584 printf("fwohci_it_desc_alloc: bus_dmamem_map success dseg %lx:%lx\n", 5585 (long)itc->itc_dseg.ds_addr, (long)itc->itc_dseg.ds_len); 5586 5587 if ((error = bus_dmamap_create(dmat, dsize, itc->itc_dnsegs, 5588 dsize, 0, BUS_DMA_WAITOK, &itc->itc_ddmamap)) != 0) { 5589 printf("%s: unable to create descriptor buffer DMA map, " 5590 "error = %d\n", xname, error); 5591 goto fail_2; 5592 } 5593 5594 printf("fwohci_it_desc_alloc: bus_dmamem_create success\n"); 5595 5596 { 5597 int loop; 5598 5599 for (loop = 0; loop < itc->itc_ddmamap->dm_nsegs; ++loop) { 5600 printf("\t%.2d: 0x%lx - 0x%lx\n", loop, 5601 (long)itc->itc_ddmamap->dm_segs[loop].ds_addr, 5602 (long)itc->itc_ddmamap->dm_segs[loop].ds_addr + 5603 (long)itc->itc_ddmamap->dm_segs[loop].ds_len - 1); 5604 } 5605 } 5606 5607 if ((error = bus_dmamap_load(dmat, itc->itc_ddmamap, 5608 itc->itc_descmap, dsize, NULL, BUS_DMA_WAITOK)) != 0) { 5609 printf("%s: unable to load descriptor buffer DMA map, " 5610 "error = %d\n", xname, error); 5611 goto fail_3; 5612 } 5613 5614 printf("%s: fwohci_it_desc_alloc: get DMA memory phys:0x%08x vm:%p\n", 5615 xname, (int)itc->itc_ddmamap->dm_segs[0].ds_addr, itc->itc_descmap); 5616 5617 itc->itc_scratch = (u_int32_t *)(itc->itc_descmap 5618 + (sizeof(struct fwohci_desc))*itc->itc_descsize); 5619 itc->itc_scratch_paddr = 5620 itc->itc_ddmamap->dm_segs[0].ds_addr 5621 + (sizeof(struct fwohci_desc))*itc->itc_descsize; 5622 5623 printf("%s: scratch %p, 0x%x\n", xname, itc->itc_scratch, 5624 (int)itc->itc_scratch_paddr); 5625 5626 /* itc->itc_scratch_paddr = vtophys(itc->itc_scratch); */ 5627 5628 return 0; 5629 5630 fail_3: 5631 bus_dmamap_destroy(dmat, itc->itc_ddmamap); 5632 fail_2: 5633 bus_dmamem_unmap(dmat, (caddr_t)itc->itc_descmap, dsize); 5634 fail_1: 5635 bus_dmamem_free(dmat, &itc->itc_dseg, itc->itc_dnsegs); 5636 fail_0: 5637 itc->itc_dnsegs = 0; 5638 itc->itc_descmap = NULL; 5639 return error; 5640 } 5641 5642 5643 static void 5644 fwohci_it_desc_free(struct fwohci_it_ctx *itc) 5645 { 5646 bus_dma_tag_t dmat = itc->itc_sc->sc_dmat; 5647 int dsize = sizeof(struct fwohci_desc) * itc->itc_descsize + 4; 5648 5649 bus_dmamap_destroy(dmat, itc->itc_ddmamap); 5650 bus_dmamem_unmap(dmat, (caddr_t)itc->itc_descmap, dsize); 5651 bus_dmamem_free(dmat, &itc->itc_dseg, itc->itc_dnsegs); 5652 5653 itc->itc_dnsegs = 0; 5654 itc->itc_descmap = NULL; 5655 } 5656 5657 5658 5659 /* 5660 * int fwohci_it_ctx_writedata(ieee1394_it_tag_t it, int ndata, 5661 * struct ieee1394_it_datalist *itdata, int flags) 5662 * 5663 * This function will write packet data to DMA buffer in the 5664 * context. This function will parse ieee1394_it_datalist 5665 * command and fill DMA buffer. This function will return the 5666 * number of written packets, or error code if the return value 5667 * is negative. 5668 * 5669 * When this funtion returns positive value but smaller than 5670 * ndata, it reaches at the ent of DMA buffer. 5671 */ 5672 int 5673 fwohci_it_ctx_writedata(ieee1394_it_tag_t it, int ndata, 5674 struct ieee1394_it_datalist *itdata, int flags) 5675 { 5676 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 5677 int rv; 5678 int writepkt = 0; 5679 struct fwohci_it_dmabuf *itd; 5680 int i = 0; 5681 5682 itd = itc->itc_buf_end; 5683 5684 while (ndata > 0) { 5685 int s; 5686 5687 if (fwohci_itd_isfull(itd) || fwohci_itd_islocked(itd)) { 5688 if (itc->itc_buf_cnt == itc->itc_bufnum) { 5689 /* no space to write */ 5690 printf("sleeping: start linkend end %d %d %d " 5691 "bufcnt %d\n", 5692 itc->itc_buf_start->itd_num, 5693 itc->itc_buf_linkend->itd_num, 5694 itc->itc_buf_end->itd_num, 5695 itc->itc_buf_cnt); 5696 5697 itc->itc_waitchan = itc; 5698 if (tsleep((void *)itc->itc_waitchan, 5699 PCATCH, "fwohci it", 0) == EWOULDBLOCK) { 5700 itc->itc_waitchan = NULL; 5701 printf("fwohci0 signal\n"); 5702 break; 5703 } 5704 printf("waking: start linkend end %d %d %d\n", 5705 itc->itc_buf_start->itd_num, 5706 itc->itc_buf_linkend->itd_num, 5707 itc->itc_buf_end->itd_num); 5708 5709 itc->itc_waitchan = itc; 5710 i = 0; 5711 } else { 5712 /* 5713 * Use next buffer. This DMA buffer is full 5714 * or locked. 5715 */ 5716 INC_BUF(itc, itd); 5717 } 5718 } 5719 5720 if (++i > 10) { 5721 panic("why loop so much %d", itc->itc_buf_cnt); 5722 break; 5723 } 5724 5725 s = splbio(); 5726 5727 if (fwohci_itd_hasdata(itd) == 0) { 5728 ++itc->itc_buf_cnt; 5729 DPRINTF(("<buf cnt %d>\n", itc->itc_buf_cnt)); 5730 } 5731 5732 rv = fwohci_itd_writedata(itd, ndata, itdata); 5733 DPRINTF(("fwohci_it_ctx_writedata: buf %d ndata %d rv %d\n", 5734 itd->itd_num, ndata, rv)); 5735 5736 if (itc->itc_buf_start == itc->itc_buf_linkend 5737 && (itc->itc_flags & ITC_FLAGS_RUN) != 0) { 5738 5739 #ifdef DEBUG_USERADD 5740 printf("fwohci_it_ctx_writedata: emergency!\n"); 5741 #endif 5742 if (itc->itc_buf_linkend != itc->itc_buf_end 5743 && fwohci_itd_hasdata(itc->itc_buf_end)) { 5744 struct fwohci_it_dmabuf *itdn = itc->itc_buf_linkend; 5745 5746 INC_BUF(itc, itdn); 5747 printf("connecting %d after %d\n", 5748 itdn->itd_num, 5749 itc->itc_buf_linkend->itd_num); 5750 if (fwohci_itd_link(itc->itc_buf_linkend, itdn)) { 5751 printf("fwohci_it_ctx_writedata:" 5752 " cannot link correctly\n"); 5753 splx(s); 5754 return -1; 5755 } 5756 itc->itc_buf_linkend = itdn; 5757 } 5758 } 5759 5760 splx(s); 5761 5762 if (rv < 0) { 5763 /* some errors happend */ 5764 break; 5765 } 5766 5767 writepkt += rv; 5768 ndata -= rv; 5769 itdata += rv; 5770 itc->itc_buf_end = itd; 5771 } 5772 5773 /* Start DMA engine if stopped */ 5774 if ((itc->itc_flags & ITC_FLAGS_RUN) == 0) { 5775 if (itc->itc_buf_cnt > itc->itc_bufnum - 1 || flags) { 5776 /* run */ 5777 printf("fwohci_itc_ctl_writedata: DMA engine start\n"); 5778 fwohci_it_ctx_run(itc); 5779 } 5780 } 5781 5782 return writepkt; 5783 } 5784 5785 5786 5787 static void 5788 fwohci_it_ctx_run(struct fwohci_it_ctx *itc) 5789 { 5790 struct fwohci_softc *sc = itc->itc_sc; 5791 int ctx = itc->itc_num; 5792 struct fwohci_it_dmabuf *itd 5793 = (struct fwohci_it_dmabuf *)itc->itc_buf_start; 5794 u_int32_t reg; 5795 int i; 5796 5797 if (itc->itc_flags & ITC_FLAGS_RUN) { 5798 return; 5799 } 5800 itc->itc_flags |= ITC_FLAGS_RUN; 5801 5802 /* 5803 * dirty, but I can't imagine better place to save branch addr 5804 * of top DMA buffer and substitute 0 to it. 5805 */ 5806 itd->itd_savedbranch = itd->itd_lastdesc->fd_branch; 5807 itd->itd_lastdesc->fd_branch = 0; 5808 5809 if (itc->itc_buf_cnt > 1) { 5810 struct fwohci_it_dmabuf *itdn = itd; 5811 5812 #if 0 5813 INC_BUF(itc, itdn); 5814 5815 if (fwohci_itd_link(itd, itdn)) { 5816 printf("fwohci_it_ctx_run: cannot link correctly\n"); 5817 return; 5818 } 5819 itc->itc_buf_linkend = itdn; 5820 #else 5821 for (;;) { 5822 INC_BUF(itc, itdn); 5823 5824 if (itdn == itc->itc_buf_end) { 5825 break; 5826 } 5827 if (fwohci_itd_link(itd, itdn)) { 5828 printf("fwohci_it_ctx_run: cannot link\n"); 5829 return; 5830 } 5831 itd = itdn; 5832 } 5833 itc->itc_buf_linkend = itd; 5834 #endif 5835 } else { 5836 itd->itd_lastdesc->fd_flags |= OHCI_DESC_INTR_ALWAYS; 5837 itc->itc_buf_linkend = itc->itc_buf_end; 5838 itc->itc_buf_end->itd_flags |= ITD_FLAGS_LOCK; 5839 5840 /* sanity check */ 5841 if (itc->itc_buf_end != itc->itc_buf_start) { 5842 printf("buf start & end differs %p %p\n", 5843 itc->itc_buf_end, itc->itc_buf_start); 5844 } 5845 #if 0 5846 { 5847 u_int32_t *fdp; 5848 u_int32_t adr; 5849 int i; 5850 5851 printf("fwohci_it_ctx_run: itc_buf_cnt 1, DMA buf %d\n", 5852 itd->itd_num); 5853 printf(" last desc %p npacket %d, %d 0x%04x%04x", 5854 itd->itd_lastdesc, itd->itd_npacket, 5855 (itd->itd_lastdesc - itd->itd_desc)/3, 5856 itd->itd_lastdesc->fd_flags, 5857 itd->itd_lastdesc->fd_reqcount); 5858 fdp = (u_int32_t *)itd->itd_desc; 5859 adr = (u_int32_t)itd->itd_desc_phys; /* XXX */ 5860 5861 for (i = 0; i < 7*4; ++i) { 5862 if (i % 4 == 0) { 5863 printf("\n%x:", adr + 4*i); 5864 } 5865 printf(" %08x", fdp[i]); 5866 } 5867 5868 if (itd->itd_npacket > 4) { 5869 printf("\n..."); 5870 i = (itd->itd_npacket - 2)*12 + 4; 5871 } else { 5872 i = 2*12 + 4; 5873 } 5874 for (;i < itd->itd_npacket*12 + 4; ++i) { 5875 if (i % 4 == 0) { 5876 printf("\n%x:", adr + 4*i); 5877 } 5878 printf(" %08x", fdp[i]); 5879 } 5880 printf("\n"); 5881 } 5882 #endif 5883 } 5884 { 5885 struct fwohci_desc *fd; 5886 5887 printf("fwohci_it_ctx_run: link start linkend end %d %d %d\n", 5888 itc->itc_buf_start->itd_num, 5889 itc->itc_buf_linkend->itd_num, 5890 itc->itc_buf_end->itd_num); 5891 5892 fd = itc->itc_buf_start->itd_desc; 5893 if ((fd->fd_flags & 0xff00) != OHCI_DESC_STORE_VALUE) { 5894 printf("fwohci_it_ctx_run: start buf not with STORE\n"); 5895 } 5896 fd += 3; 5897 if ((fd->fd_flags & OHCI_DESC_INTR_ALWAYS) == 0) { 5898 printf("fwohci_it_ctx_run: start buf does not have intr\n"); 5899 } 5900 5901 fd = itc->itc_buf_linkend->itd_desc; 5902 if ((fd->fd_flags & 0xff00) != OHCI_DESC_STORE_VALUE) { 5903 printf("fwohci_it_ctx_run: linkend buf not with STORE\n"); 5904 } 5905 fd += 3; 5906 if ((fd->fd_flags & OHCI_DESC_INTR_ALWAYS) == 0) { 5907 printf("fwohci_it_ctx_run: linkend buf does not have intr\n"); 5908 } 5909 } 5910 5911 *itc->itc_scratch = 0xffffffff; 5912 5913 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_ContextControlClear, 5914 0xffff0000); 5915 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_ContextControlSet); 5916 5917 printf("fwohci_it_ctx_run start for ctx %d\n", ctx); 5918 printf("%s: bfr IT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 5919 sc->sc_sc1394.sc1394_dev.dv_xname, 5920 OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_CommandPtr), 5921 reg, 5922 reg & OHCI_CTXCTL_RUN ? " run" : "", 5923 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5924 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5925 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5926 5927 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_ContextControlClear, 5928 OHCI_CTXCTL_RUN); 5929 5930 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_ContextControlSet); 5931 i = 0; 5932 while (reg & (OHCI_CTXCTL_ACTIVE | OHCI_CTXCTL_RUN)) { 5933 delay(100); 5934 if (++i > 1000) { 5935 printf("%s: cannot stop iso transmit engine\n", 5936 sc->sc_sc1394.sc1394_dev.dv_xname); 5937 break; 5938 } 5939 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, 5940 OHCI_SUBREG_ContextControlSet); 5941 } 5942 5943 printf("%s: itm IT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 5944 sc->sc_sc1394.sc1394_dev.dv_xname, 5945 OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_CommandPtr), 5946 reg, 5947 reg & OHCI_CTXCTL_RUN ? " run" : "", 5948 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5949 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5950 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5951 5952 printf("%s: writing CommandPtr to 0x%08x\n", 5953 sc->sc_sc1394.sc1394_dev.dv_xname, 5954 (int)itc->itc_buf_start->itd_desc_phys); 5955 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_CommandPtr, 5956 fwohci_itd_list_head(itc->itc_buf_start) | 4); 5957 5958 OHCI_SYNC_TX_DMA_WRITE(sc, ctx, OHCI_SUBREG_ContextControlSet, 5959 OHCI_CTXCTL_RUN | OHCI_CTXCTL_WAKE); 5960 5961 reg = OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_ContextControlSet); 5962 5963 printf("%s: aft IT_CommandPtr 0x%08x ContextCtrl 0x%08x%s%s%s%s\n", 5964 sc->sc_sc1394.sc1394_dev.dv_xname, 5965 OHCI_SYNC_TX_DMA_READ(sc, ctx, OHCI_SUBREG_CommandPtr), 5966 reg, 5967 reg & OHCI_CTXCTL_RUN ? " run" : "", 5968 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 5969 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 5970 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 5971 } 5972 5973 5974 5975 int 5976 fwohci_it_ctx_flush(ieee1394_it_tag_t it) 5977 { 5978 struct fwohci_it_ctx *itc = (struct fwohci_it_ctx *)it; 5979 int rv = 0; 5980 5981 if ((itc->itc_flags & ITC_FLAGS_RUN) == 0 5982 && itc->itc_buf_cnt > 0) { 5983 printf("fwohci_it_ctx_flush: %s flushing\n", 5984 itc->itc_sc->sc_sc1394.sc1394_dev.dv_xname); 5985 5986 fwohci_it_ctx_run(itc); 5987 rv = 1; 5988 } 5989 5990 return rv; 5991 } 5992 5993 5994 /* 5995 * static void fwohci_it_intr(struct fwohci_softc *sc, 5996 * struct fwochi_it_ctx *itc) 5997 * 5998 * This function is the interrupt handler for isochronous 5999 * transmit interrupt. This function will 1) unlink used 6000 * (already transmitted) buffers, 2) link new filled buffers, if 6001 * necessary and 3) say some free dma buffers exist to 6002 * fwiso_write() 6003 */ 6004 static void 6005 fwohci_it_intr(struct fwohci_softc *sc, struct fwohci_it_ctx *itc) 6006 { 6007 struct fwohci_it_dmabuf *itd, *newstartbuf; 6008 u_int16_t scratchval; 6009 u_int32_t reg; 6010 6011 reg = OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, 6012 OHCI_SUBREG_ContextControlSet); 6013 6014 /* print out debug info */ 6015 #ifdef FW_DEBUG 6016 printf("fwohci_it_intr: CTX %d\n", itc->itc_num); 6017 6018 printf("fwohci_it_intr: %s: IT_CommandPtr 0x%08x " 6019 "ContextCtrl 0x%08x%s%s%s%s\n", 6020 sc->sc_sc1394.sc1394_dev.dv_xname, 6021 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, OHCI_SUBREG_CommandPtr), 6022 reg, 6023 reg & OHCI_CTXCTL_RUN ? " run" : "", 6024 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 6025 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 6026 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 6027 printf("fwohci_it_intr: %s: scratch %x start %d end %d valid %d\n", 6028 sc->sc_sc1394.sc1394_dev.dv_xname, *itc->itc_scratch, 6029 itc->itc_buf_start->itd_num, itc->itc_buf_end->itd_num, 6030 itc->itc_buf_cnt); 6031 { 6032 u_int32_t reg 6033 = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 6034 printf("\t\tIsoCounter 0x%08x, %d %d %d\n", reg, 6035 (reg >> 25) & 0xfe, (reg >> 12) & 0x1fff, reg & 0xfff); 6036 } 6037 #endif /* FW_DEBUG */ 6038 /* end print out debug info */ 6039 6040 scratchval = (*itc->itc_scratch) & 0x0000ffff; 6041 *itc->itc_scratch = 0xffffffff; 6042 6043 if ((reg & OHCI_CTXCTL_ACTIVE) == 0 && scratchval != 0xffff) { 6044 /* DMA engine has been stopped */ 6045 printf("DMA engine stopped\n"); 6046 printf("fwohci_it_intr: %s: IT_CommandPtr 0x%08x " 6047 "ContextCtrl 0x%08x%s%s%s%s\n", 6048 sc->sc_sc1394.sc1394_dev.dv_xname, 6049 OHCI_SYNC_TX_DMA_READ(sc, itc->itc_num, OHCI_SUBREG_CommandPtr), 6050 reg, 6051 reg & OHCI_CTXCTL_RUN ? " run" : "", 6052 reg & OHCI_CTXCTL_WAKE ? " wake" : "", 6053 reg & OHCI_CTXCTL_DEAD ? " dead" : "", 6054 reg & OHCI_CTXCTL_ACTIVE ? " active" : ""); 6055 printf("fwohci_it_intr: %s: scratch %x start %d end %d valid %d\n", 6056 sc->sc_sc1394.sc1394_dev.dv_xname, *itc->itc_scratch, 6057 itc->itc_buf_start->itd_num, itc->itc_buf_end->itd_num, 6058 itc->itc_buf_cnt); 6059 { 6060 u_int32_t reg 6061 = OHCI_CSR_READ(sc, OHCI_REG_IsochronousCycleTimer); 6062 printf("\t\tIsoCounter 0x%08x, %d %d %d\n", reg, 6063 (reg >> 25) & 0xfe, (reg >> 12) & 0x1fff, reg & 0xfff); 6064 } 6065 printf("\t\tbranch of lastdesc 0x%08x\n", 6066 itc->itc_buf_start->itd_lastdesc->fd_branch); 6067 6068 scratchval = 0xffff; 6069 itc->itc_flags &= ~ITC_FLAGS_RUN; 6070 } 6071 6072 /* unlink old buffers */ 6073 if (scratchval != 0xffff) { 6074 /* normal path */ 6075 newstartbuf = &itc->itc_buf[scratchval]; 6076 } else { 6077 /* DMA engine stopped */ 6078 newstartbuf = itc->itc_buf_linkend; 6079 INC_BUF(itc, newstartbuf); 6080 } 6081 6082 itd = (struct fwohci_it_dmabuf *)itc->itc_buf_start; 6083 itc->itc_buf_start = newstartbuf; 6084 while (itd != newstartbuf) { 6085 itc->itc_outpkt += itd->itd_npacket; 6086 fwohci_itd_unlink(itd); 6087 INC_BUF(itc, itd); 6088 --itc->itc_buf_cnt; 6089 DPRINTF(("<buf cnt %d>\n", itc->itc_buf_cnt)); 6090 } 6091 6092 #ifdef DEBUG_USERADD 6093 if (scratchval != 0xffff) { 6094 printf("fwohci0: intr start %d dataend %d %d\n", scratchval, 6095 itc->itc_buf_end->itd_num, itc->itc_outpkt); 6096 } 6097 #endif 6098 6099 if (scratchval == 0xffff) { 6100 /* no data supplied */ 6101 printf("fwohci_it_intr: no it data. output total %d\n", 6102 itc->itc_outpkt); 6103 6104 if (itc->itc_buf_cnt > 0) { 6105 printf("fwohci_it_intr: it DMA stops " 6106 "w/ valid databuf %d buf %d data %d" 6107 " intr reg 0x%08x\n", 6108 itc->itc_buf_cnt, 6109 itc->itc_buf_end->itd_num, 6110 fwohci_itd_hasdata(itc->itc_buf_end), 6111 OHCI_CSR_READ(sc, OHCI_REG_IntEventSet)); 6112 } else { 6113 /* All the data gone */ 6114 itc->itc_buf_start 6115 = itc->itc_buf_end 6116 = itc->itc_buf_linkend 6117 = &itc->itc_buf[0]; 6118 printf("fwohci_it_intr: all packets gone\n"); 6119 } 6120 6121 itc->itc_flags &= ~ITC_FLAGS_RUN; 6122 6123 OHCI_SYNC_TX_DMA_WRITE(sc, itc->itc_num, 6124 OHCI_SUBREG_ContextControlClear, 0xffffffff); 6125 OHCI_SYNC_TX_DMA_WRITE(sc, itc->itc_num, 6126 OHCI_SUBREG_CommandPtr, 0); 6127 OHCI_SYNC_TX_DMA_WRITE(sc, itc->itc_num, 6128 OHCI_SUBREG_ContextControlClear, 0x1f); 6129 6130 /* send message */ 6131 if (itc->itc_waitchan != NULL) { 6132 wakeup((void *)itc->itc_waitchan); 6133 } 6134 6135 return; 6136 } 6137 6138 #if 0 6139 /* unlink old buffers */ 6140 newstartbuf = &itc->itc_buf[scratchval]; 6141 6142 itd = (struct fwohci_it_dmabuf *)itc->itc_buf_start; 6143 itc->itc_buf_start = newstartbuf; 6144 while (itd != newstartbuf) { 6145 itc->itc_outpkt += itd->itd_npacket; 6146 fwohci_itd_unlink(itd); 6147 INC_BUF(itc, itd); 6148 --itc->itc_buf_cnt; 6149 DPRINTF(("<buf cnt %d>\n", itc->itc_buf_cnt)); 6150 } 6151 #endif 6152 6153 /* sanity check */ 6154 { 6155 int startidx, endidx, linkendidx; 6156 6157 startidx = itc->itc_buf_start->itd_num; 6158 endidx = itc->itc_buf_end->itd_num; 6159 linkendidx = itc->itc_buf_linkend->itd_num; 6160 6161 if (startidx < endidx) { 6162 if (linkendidx < startidx 6163 || endidx < linkendidx) { 6164 printf("funny, linkend is not between start " 6165 "and end [%d, %d]: %d\n", 6166 startidx, endidx, linkendidx); 6167 } 6168 } else if (startidx > endidx) { 6169 if (linkendidx < startidx 6170 && endidx < linkendidx) { 6171 printf("funny, linkend is not between start " 6172 "and end [%d, %d]: %d\n", 6173 startidx, endidx, linkendidx); 6174 } 6175 } else { 6176 if (linkendidx != startidx) { 6177 printf("funny, linkend is not between start " 6178 "and end [%d, %d]: %d\n", 6179 startidx, endidx, linkendidx); 6180 } 6181 6182 } 6183 } 6184 6185 /* link if some valid DMA buffers exist */ 6186 if (itc->itc_buf_cnt > 1 6187 && itc->itc_buf_linkend != itc->itc_buf_end) { 6188 struct fwohci_it_dmabuf *itdprev; 6189 int i; 6190 6191 DPRINTF(("CTX %d: start linkend dataend bufs %d, %d, %d, %d\n", 6192 itc->itc_num, 6193 itc->itc_buf_start->itd_num, 6194 itc->itc_buf_linkend->itd_num, 6195 itc->itc_buf_end->itd_num, 6196 itc->itc_buf_cnt)); 6197 6198 itd = itdprev = itc->itc_buf_linkend; 6199 INC_BUF(itc, itd); 6200 6201 #if 0 6202 if (fwohci_itd_isfilled(itd) || itc->itc_buf_cnt == 2) { 6203 while (itdprev != itc->itc_buf_end) { 6204 6205 if (fwohci_itd_link(itdprev, itd)) { 6206 break; 6207 } 6208 6209 itdprev = itd; 6210 INC_BUF(itc, itd); 6211 } 6212 itc->itc_buf_linkend = itdprev; 6213 } 6214 #endif 6215 i = 0; 6216 while (itdprev != itc->itc_buf_end) { 6217 if (!fwohci_itd_isfilled(itd) && itc->itc_buf_cnt > 2) { 6218 break; 6219 } 6220 6221 if (fwohci_itd_link(itdprev, itd)) { 6222 break; 6223 } 6224 6225 itdprev = itd; 6226 INC_BUF(itc, itd); 6227 6228 itc->itc_buf_linkend = itdprev; 6229 ++i; 6230 } 6231 6232 if (i > 0) { 6233 DPRINTF(("CTX %d: start linkend dataend bufs %d, %d, %d, %d\n", 6234 itc->itc_num, 6235 itc->itc_buf_start->itd_num, 6236 itc->itc_buf_linkend->itd_num, 6237 itc->itc_buf_end->itd_num, 6238 itc->itc_buf_cnt)); 6239 } 6240 } else { 6241 struct fwohci_it_dmabuf *le; 6242 6243 le = itc->itc_buf_linkend; 6244 6245 printf("CTX %d: start linkend dataend bufs %d, %d, %d, %d no buffer added\n", 6246 itc->itc_num, 6247 itc->itc_buf_start->itd_num, 6248 itc->itc_buf_linkend->itd_num, 6249 itc->itc_buf_end->itd_num, 6250 itc->itc_buf_cnt); 6251 printf("\tlast descriptor %s %04x %08x\n", 6252 le->itd_lastdesc->fd_flags & OHCI_DESC_INTR_ALWAYS ? "intr" : "", 6253 le->itd_lastdesc->fd_flags, 6254 le->itd_lastdesc->fd_branch); 6255 } 6256 6257 /* send message */ 6258 if (itc->itc_waitchan != NULL) { 6259 /* */ 6260 wakeup((void *)itc->itc_waitchan); 6261 } 6262 } 6263 6264 6265 6266 /* 6267 * int fwohci_itd_construct(struct fwohci_it_ctx *itc, 6268 * struct fwohci_it_dmabuf *itd, int num, 6269 * struct fwohci_desc *desc, bus_addr_t phys, 6270 * int descsize, int maxsize, paddr_t scratch) 6271 * 6272 * 6273 * 6274 */ 6275 int 6276 fwohci_itd_construct(struct fwohci_it_ctx *itc, struct fwohci_it_dmabuf *itd, 6277 int num, struct fwohci_desc *desc, bus_addr_t phys, int descsize, 6278 int maxsize, paddr_t scratch) 6279 { 6280 const char *xname = itc->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 6281 struct fwohci_desc *fd; 6282 struct fwohci_desc *descend; 6283 int npkt; 6284 int bufno = 0; /* DMA segment */ 6285 bus_size_t bufused = 0; /* offset in a DMA segment */ 6286 int roundsize; 6287 int tag = itc->itc_tag; 6288 int ch = itc->itc_channel; 6289 6290 itd->itd_ctx = itc; 6291 itd->itd_num = num; 6292 6293 if (descsize > 1024*3) { 6294 printf("%s: fwohci_itd_construct[%d] descsize %d too big\n", 6295 xname, num, descsize); 6296 return -1; 6297 } 6298 6299 itd->itd_desc = desc; 6300 itd->itd_descsize = descsize; 6301 itd->itd_desc_phys = phys; 6302 6303 itd->itd_lastdesc = desc; 6304 itd->itd_npacket = 0; 6305 6306 printf("%s: fwohci_itd_construct[%d] desc %p descsize %d, maxsize %d\n", 6307 xname, itd->itd_num, itd->itd_desc, itd->itd_descsize, maxsize); 6308 6309 if (descsize < 4) { 6310 /* too small descriptor array. at least 4 */ 6311 return -1; 6312 } 6313 6314 /* count up how many packet can handle */ 6315 itd->itd_maxpacket = (descsize - 1)/3; 6316 6317 /* rounding up to power of 2. minimum 16 */ 6318 roundsize = 16; 6319 for (roundsize = 16; roundsize < maxsize; roundsize <<= 1); 6320 itd->itd_maxsize = roundsize; 6321 6322 printf("\t\tdesc%d [%x, %lx]\n", itd->itd_num, 6323 (u_int32_t)phys, 6324 (unsigned long)((u_int32_t)phys 6325 + (itd->itd_maxpacket*3 + 1)*sizeof(struct fwohci_desc))); 6326 printf("%s: fwohci_itd_construct[%d] npkt %d maxsize round up to %d\n", 6327 xname, itd->itd_num, itd->itd_maxpacket, itd->itd_maxsize); 6328 6329 /* obtain DMA buffer */ 6330 if (fwohci_itd_dmabuf_alloc(itd)) { 6331 /* cannot allocate memory for DMA buffer */ 6332 return -1; 6333 } 6334 6335 /* 6336 * make descriptor chain 6337 * 6338 * First descriptor group has a STORE_VALUE, OUTPUT_IMMEDIATE 6339 * and OUTPUT_LAST descriptors Second and after that, a 6340 * descriptor group has an OUTPUT_IMMEDIATE and an OUTPUT_LAST 6341 * descriptor. 6342 */ 6343 descend = desc + descsize; 6344 6345 /* set store value descriptor for 1st descriptor group */ 6346 desc->fd_flags = OHCI_DESC_STORE_VALUE; 6347 desc->fd_reqcount = num; /* write number of DMA buffer class */ 6348 desc->fd_data = scratch; /* at physical memory 'scratch' */ 6349 desc->fd_branch = 0; 6350 desc->fd_status = desc->fd_rescount = 0; 6351 6352 itd->itd_store = desc; 6353 itd->itd_store_phys = phys; 6354 6355 ++desc; 6356 phys += 16; 6357 6358 npkt = 0; 6359 /* make OUTPUT_DESC chain for packets */ 6360 for (fd = desc; fd + 2 < descend; fd += 3, ++npkt) { 6361 struct fwohci_desc *fi = fd; 6362 struct fwohci_desc *fl = fd + 2; 6363 u_int32_t *fi_data = (u_int32_t *)(fd + 1); 6364 6365 #if 0 6366 if (npkt > itd->itd_maxpacket - 3) { 6367 printf("%s: %3d fi fl %p %p\n", xname, npkt, fi,fl); 6368 } 6369 #endif 6370 6371 fi->fd_reqcount = 8; /* data size for OHCI command */ 6372 fi->fd_flags = OHCI_DESC_IMMED; 6373 fi->fd_data = 0; 6374 fi->fd_branch = 0; /* branch for error */ 6375 fi->fd_status = fi->fd_rescount = 0; 6376 6377 /* channel and tag is unchanged */ 6378 *fi_data = OHCI_ITHEADER_VAL(TAG, tag) | 6379 OHCI_ITHEADER_VAL(CHAN, ch) | 6380 OHCI_ITHEADER_VAL(TCODE, IEEE1394_TCODE_STREAM_DATA); 6381 *++fi_data = 0; 6382 *++fi_data = 0; 6383 *++fi_data = 0; 6384 6385 fl->fd_flags = OHCI_DESC_OUTPUT | OHCI_DESC_LAST | 6386 OHCI_DESC_BRANCH; 6387 fl->fd_branch = 6388 (phys + sizeof(struct fwohci_desc)*(npkt + 1)*3) | 0x03; 6389 fl->fd_status = fl->fd_rescount = 0; 6390 6391 #ifdef FW_DEBUG 6392 if (npkt > itd->itd_maxpacket - 3) { 6393 DPRINTF(("%s: %3d fi fl fl branch %p %p 0x%x\n", 6394 xname, npkt, fi, fl, (int)fl->fd_branch)); 6395 } 6396 #endif 6397 6398 /* physical addr to data? */ 6399 fl->fd_data = 6400 (u_int32_t)((itd->itd_seg[bufno].ds_addr + bufused)); 6401 bufused += itd->itd_maxsize; 6402 if (bufused > itd->itd_seg[bufno].ds_len) { 6403 bufused = 0; 6404 if (++bufno == itd->itd_nsegs) { 6405 /* fail */ 6406 break; 6407 } 6408 } 6409 } 6410 6411 #if 0 6412 if (itd->itd_num == 0) { 6413 u_int32_t *fdp; 6414 u_int32_t adr; 6415 int i = 0; 6416 6417 fdp = (u_int32_t *)itd->itd_desc; 6418 adr = (u_int32_t)itd->itd_desc_phys; /* XXX */ 6419 6420 printf("fwohci_itd_construct: audit DMA desc chain. %d\n", 6421 itd->itd_maxpacket); 6422 for (i = 0; i < itd->itd_maxpacket*12 + 4; ++i) { 6423 if (i % 4 == 0) { 6424 printf("\n%x:", adr + 4*i); 6425 } 6426 printf(" %08x", fdp[i]); 6427 } 6428 printf("\n"); 6429 6430 } 6431 #endif 6432 /* last branch should be 0 */ 6433 --fd; 6434 fd->fd_branch = 0; 6435 6436 printf("%s: pkt %d %d maxdesc %p\n", 6437 xname, npkt, itd->itd_maxpacket, descend); 6438 6439 return 0; 6440 } 6441 6442 void 6443 fwohci_itd_destruct(struct fwohci_it_dmabuf *itd) 6444 { 6445 const char *xname = itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 6446 6447 printf("%s: fwohci_itd_destruct %d\n", xname, itd->itd_num); 6448 6449 fwohci_itd_dmabuf_free(itd); 6450 } 6451 6452 6453 /* 6454 * static int fwohci_itd_dmabuf_alloc(struct fwohci_it_dmabuf *itd) 6455 * 6456 * This function allocates DMA memory for fwohci_it_dmabuf. This 6457 * function will return 0 when it succeeds and return non-zero 6458 * value when it fails. 6459 */ 6460 static int 6461 fwohci_itd_dmabuf_alloc(struct fwohci_it_dmabuf *itd) 6462 { 6463 const char *xname = itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname; 6464 bus_dma_tag_t dmat = itd->itd_ctx->itc_sc->sc_dmat; 6465 6466 int dmasize = itd->itd_maxsize * itd->itd_maxpacket; 6467 int error; 6468 6469 DPRINTF(("%s: fwohci_itd_dmabuf_alloc[%d] dmasize %d maxpkt %d\n", 6470 xname, itd->itd_num, dmasize, itd->itd_maxpacket)); 6471 6472 if ((error = bus_dmamem_alloc(dmat, dmasize, PAGE_SIZE, 0, 6473 itd->itd_seg, FWOHCI_MAX_ITDATASEG, &itd->itd_nsegs, 0)) != 0) { 6474 printf("%s: unable to allocate data buffer, error = %d\n", 6475 xname, error); 6476 goto fail_0; 6477 } 6478 6479 /* checking memory range */ 6480 #ifdef FW_DEBUG 6481 { 6482 int loop; 6483 6484 for (loop = 0; loop < itd->itd_nsegs; ++loop) { 6485 DPRINTF(("\t%.2d: 0x%lx - 0x%lx\n", loop, 6486 (long)itd->itd_seg[loop].ds_addr, 6487 (long)itd->itd_seg[loop].ds_addr 6488 + (long)itd->itd_seg[loop].ds_len - 1)); 6489 } 6490 } 6491 #endif 6492 6493 if ((error = bus_dmamem_map(dmat, itd->itd_seg, itd->itd_nsegs, 6494 dmasize, (caddr_t *)&itd->itd_buf, 6495 BUS_DMA_COHERENT | BUS_DMA_WAITOK)) != 0) { 6496 printf("%s: unable to map data buffer, error = %d\n", 6497 xname, error); 6498 goto fail_1; 6499 } 6500 6501 DPRINTF(("fwohci_it_data_alloc[%d]: bus_dmamem_map addr %p\n", 6502 itd->itd_num, itd->itd_buf)); 6503 6504 if ((error = bus_dmamap_create(dmat, /*chunklen*/dmasize, 6505 itd->itd_nsegs, dmasize, 0, BUS_DMA_WAITOK, 6506 &itd->itd_dmamap)) != 0) { 6507 printf("%s: unable to create data buffer DMA map, " 6508 "error = %d\n", xname, error); 6509 goto fail_2; 6510 } 6511 6512 DPRINTF(("fwohci_it_data_alloc: bus_dmamem_create\n")); 6513 6514 if ((error = bus_dmamap_load(dmat, itd->itd_dmamap, 6515 itd->itd_buf, dmasize, NULL, BUS_DMA_WAITOK)) != 0) { 6516 printf("%s: unable to load data buffer DMA map, error = %d\n", 6517 xname, error); 6518 goto fail_3; 6519 } 6520 6521 DPRINTF(("fwohci_itd_dmabuf_alloc: load DMA memory vm %p\n", 6522 itd->itd_buf)); 6523 DPRINTF(("\tmapsize %ld nsegs %d\n", 6524 (long)itd->itd_dmamap->dm_mapsize, itd->itd_dmamap->dm_nsegs)); 6525 6526 #ifdef FW_DEBUG 6527 { 6528 int loop; 6529 6530 for (loop = 0; loop < itd->itd_dmamap->dm_nsegs; ++loop) { 6531 DPRINTF(("\t%.2d: 0x%lx - 0x%lx\n", loop, 6532 (long)itd->itd_dmamap->dm_segs[loop].ds_addr, 6533 (long)itd->itd_dmamap->dm_segs[loop].ds_addr + 6534 (long)itd->itd_dmamap->dm_segs[loop].ds_len - 1)); 6535 } 6536 } 6537 #endif 6538 6539 return 0; 6540 6541 fail_3: 6542 bus_dmamap_destroy(dmat, itd->itd_dmamap); 6543 fail_2: 6544 bus_dmamem_unmap(dmat, (caddr_t)itd->itd_buf, dmasize); 6545 fail_1: 6546 bus_dmamem_free(dmat, itd->itd_seg, itd->itd_nsegs); 6547 fail_0: 6548 itd->itd_nsegs = 0; 6549 itd->itd_maxpacket = 0; 6550 return error; 6551 } 6552 6553 /* 6554 * static void fwohci_itd_dmabuf_free(struct fwohci_it_dmabuf *itd) 6555 * 6556 * This function will release memory resource allocated by 6557 * fwohci_itd_dmabuf_alloc(). 6558 */ 6559 static void 6560 fwohci_itd_dmabuf_free(struct fwohci_it_dmabuf *itd) 6561 { 6562 bus_dma_tag_t dmat = itd->itd_ctx->itc_sc->sc_dmat; 6563 int dmasize = itd->itd_maxsize * itd->itd_maxpacket; 6564 6565 bus_dmamap_destroy(dmat, itd->itd_dmamap); 6566 bus_dmamem_unmap(dmat, (caddr_t)itd->itd_buf, dmasize); 6567 bus_dmamem_free(dmat, itd->itd_seg, itd->itd_nsegs); 6568 6569 itd->itd_nsegs = 0; 6570 itd->itd_maxpacket = 0; 6571 } 6572 6573 6574 6575 /* 6576 * int fwohci_itd_link(struct fwohci_it_dmabuf *itd, 6577 * struct fwohci_it_dmabuf *itdc) 6578 * 6579 * This function will concatinate two descriptor chains in dmabuf 6580 * itd and itdc. The descriptor link in itdc follows one in itd. 6581 * This function will move interrrupt packet from the end of itd 6582 * to the top of itdc. 6583 * 6584 * This function will return 0 whel this funcion suceeds. If an 6585 * error happens, return a negative value. 6586 */ 6587 int 6588 fwohci_itd_link(struct fwohci_it_dmabuf *itd, struct fwohci_it_dmabuf *itdc) 6589 { 6590 struct fwohci_desc *fd1, *fdc; 6591 6592 if (itdc->itd_lastdesc == itdc->itd_desc) { 6593 /* no valid data */ 6594 printf("fwohci_itd_link: no data\n"); 6595 return -1; 6596 } 6597 6598 if (itdc->itd_flags & ITD_FLAGS_LOCK) { 6599 /* used already */ 6600 printf("fwohci_itd_link: link locked\n"); 6601 return -1; 6602 } 6603 itdc->itd_flags |= ITD_FLAGS_LOCK; 6604 /* for the first one */ 6605 itd->itd_flags |= ITD_FLAGS_LOCK; 6606 6607 DPRINTF(("linking %d after %d: add %d pkts\n", 6608 itdc->itd_num, itd->itd_num, itdc->itd_npacket)); 6609 6610 /* XXX: should sync cache */ 6611 6612 fd1 = itd->itd_lastdesc; 6613 fdc = itdc->itd_desc + 3; /* OUTPUT_LAST in the first descriptor */ 6614 6615 /* sanity check */ 6616 #define OUTPUT_LAST_DESC (OHCI_DESC_OUTPUT | OHCI_DESC_LAST | OHCI_DESC_BRANCH) 6617 if ((fd1->fd_flags & OUTPUT_LAST_DESC) != OUTPUT_LAST_DESC) { 6618 printf("funny! not OUTPUT_LAST descriptor %p\n", fd1); 6619 } 6620 if (itd->itd_lastdesc - itd->itd_desc != 3 * itd->itd_npacket) { 6621 printf("funny! packet number inconsistency %ld <=> %ld\n", 6622 (long)(itd->itd_lastdesc - itd->itd_desc), 6623 (long)(3*itd->itd_npacket)); 6624 } 6625 6626 fd1->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6627 fdc->fd_flags |= OHCI_DESC_INTR_ALWAYS; 6628 fd1->fd_branch = itdc->itd_desc_phys | 4; 6629 6630 itdc->itd_lastdesc->fd_flags |= OHCI_DESC_INTR_ALWAYS; 6631 /* save branch addr of lastdesc and substitute 0 to it */ 6632 itdc->itd_savedbranch = itdc->itd_lastdesc->fd_branch; 6633 itdc->itd_lastdesc->fd_branch = 0; 6634 6635 DPRINTF(("%s: link (%d %d), add pkt %d/%d branch 0x%x next saved 0x%x\n", 6636 itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname, 6637 itd->itd_num, itdc->itd_num, 6638 itdc->itd_npacket, itdc->itd_maxpacket, 6639 (int)fd1->fd_branch, (int)itdc->itd_savedbranch)); 6640 6641 /* XXX: should sync cache */ 6642 6643 return 0; 6644 } 6645 6646 6647 /* 6648 * int fwohci_itd_unlink(struct fwohci_it_dmabuf *itd) 6649 * 6650 * This function will unlink the descriptor chain from valid link 6651 * of descriptors. The target descriptor is specified by the 6652 * arguent. 6653 */ 6654 int 6655 fwohci_itd_unlink(struct fwohci_it_dmabuf *itd) 6656 { 6657 struct fwohci_desc *fd; 6658 6659 /* XXX: should sync cache */ 6660 6661 fd = itd->itd_lastdesc; 6662 6663 fd->fd_branch = itd->itd_savedbranch; 6664 DPRINTF(("%s: unlink buf %d branch restored 0x%x\n", 6665 itd->itd_ctx->itc_sc->sc_sc1394.sc1394_dev.dv_xname, 6666 itd->itd_num, (int)fd->fd_branch)); 6667 6668 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6669 itd->itd_lastdesc = itd->itd_desc; 6670 6671 fd = itd->itd_desc + 3; /* 1st OUTPUT_LAST */ 6672 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6673 6674 /* XXX: should sync cache */ 6675 6676 itd->itd_npacket = 0; 6677 itd->itd_lastdesc = itd->itd_desc; 6678 itd->itd_flags &= ~ITD_FLAGS_LOCK; 6679 6680 return 0; 6681 } 6682 6683 6684 /* 6685 * static int fwohci_itd_writedata(struct fwohci_it_dmabuf *, int ndata, 6686 * struct ieee1394_it_datalist *); 6687 * 6688 * This function will return the number of written data, or 6689 * negative value if an error happens 6690 */ 6691 int 6692 fwohci_itd_writedata(struct fwohci_it_dmabuf *itd, int ndata, 6693 struct ieee1394_it_datalist *itdata) 6694 { 6695 int writepkt; 6696 int i; 6697 u_int8_t *p; 6698 struct fwohci_desc *fd; 6699 u_int32_t *fd_idata; 6700 const int dspace = 6701 itd->itd_maxpacket - itd->itd_npacket < ndata ? 6702 itd->itd_maxpacket - itd->itd_npacket : ndata; 6703 6704 if (itd->itd_flags & ITD_FLAGS_LOCK || dspace == 0) { 6705 /* it is locked: cannot write anything */ 6706 if (itd->itd_flags & ITD_FLAGS_LOCK) { 6707 DPRINTF(("fwohci_itd_writedata: buf %d lock flag %s," 6708 " dspace %d\n", 6709 itd->itd_num, 6710 itd->itd_flags & ITD_FLAGS_LOCK ? "ON" : "OFF", 6711 dspace)); 6712 return 0; /* not an error */ 6713 } 6714 } 6715 6716 /* sanity check */ 6717 if (itd->itd_maxpacket < itd->itd_npacket) { 6718 printf("fwohci_itd_writedata: funny! # pkt > maxpkt" 6719 "%d %d\n", itd->itd_npacket, itd->itd_maxpacket); 6720 } 6721 6722 p = itd->itd_buf + itd->itd_maxsize * itd->itd_npacket; 6723 fd = itd->itd_lastdesc; 6724 6725 DPRINTF(("fwohci_itd_writedata(%d[%p], %d, 0x%p) invoked:\n", 6726 itd->itd_num, itd, ndata, itdata)); 6727 6728 for (writepkt = 0; writepkt < dspace; ++writepkt) { 6729 u_int8_t *p1 = p; 6730 int cpysize; 6731 int totalsize = 0; 6732 6733 DPRINTF(("writing %d ", writepkt)); 6734 6735 for (i = 0; i < 4; ++i) { 6736 switch (itdata->it_cmd[i]&IEEE1394_IT_CMD_MASK) { 6737 case IEEE1394_IT_CMD_IMMED: 6738 memcpy(p1, &itdata->it_u[i].id_data, 8); 6739 p1 += 8; 6740 totalsize += 8; 6741 break; 6742 case IEEE1394_IT_CMD_PTR: 6743 cpysize = itdata->it_cmd[i]&IEEE1394_IT_CMD_SIZE; 6744 DPRINTF(("fwohci_itd_writedata: cpy %d %p\n", 6745 cpysize, itdata->it_u[i].id_addr)); 6746 if (totalsize + cpysize > itd->itd_maxsize) { 6747 /* error: too big size */ 6748 break; 6749 } 6750 memcpy(p1, itdata->it_u[i].id_addr, cpysize); 6751 totalsize += cpysize; 6752 break; 6753 case IEEE1394_IT_CMD_NOP: 6754 break; 6755 default: 6756 /* unknown command */ 6757 break; 6758 } 6759 } 6760 6761 /* only for DV test */ 6762 if (totalsize != 488) { 6763 printf("error: totalsize %d at %d\n", 6764 totalsize, writepkt); 6765 } 6766 6767 DPRINTF(("totalsize %d ", totalsize)); 6768 6769 /* fill iso command in OUTPUT_IMMED descriptor */ 6770 6771 /* XXX: sync cache */ 6772 fd += 2; /* next to first descriptor */ 6773 fd_idata = (u_int32_t *)fd; 6774 6775 /* 6776 * Umm, should tag, channel and tcode be written 6777 * previously in itd_construct? 6778 */ 6779 #if 0 6780 *fd_idata = OHCI_ITHEADER_VAL(TAG, tag) | 6781 OHCI_ITHEADER_VAL(CHAN, ch) | 6782 OHCI_ITHEADER_VAL(TCODE, IEEE1394_TCODE_STREAM_DATA); 6783 #endif 6784 *++fd_idata = totalsize << 16; 6785 6786 /* fill data in OUTPUT_LAST descriptor */ 6787 ++fd; 6788 /* intr check... */ 6789 if (fd->fd_flags & OHCI_DESC_INTR_ALWAYS) { 6790 printf("uncleared INTR flag in desc %ld\n", 6791 (long)(fd - itd->itd_desc - 1)/3); 6792 } 6793 fd->fd_flags &= ~OHCI_DESC_INTR_ALWAYS; 6794 6795 if ((fd - itd->itd_desc - 1)/3 != itd->itd_maxpacket - 1) { 6796 u_int32_t bcal; 6797 6798 bcal = (fd - itd->itd_desc + 1)*sizeof(struct fwohci_desc) + (u_int32_t)itd->itd_desc_phys; 6799 if (bcal != (fd->fd_branch & 0xfffffff0)) { 6800 6801 printf("uum, branch differ at %d, %x %x %ld/%d\n", 6802 itd->itd_num, 6803 bcal, 6804 fd->fd_branch, 6805 (long)((fd - itd->itd_desc - 1)/3), 6806 itd->itd_maxpacket); 6807 } 6808 } else { 6809 /* the last pcaket */ 6810 if (fd->fd_branch != 0) { 6811 printf("uum, branch differ at %d, %x %x %ld/%d\n", 6812 itd->itd_num, 6813 0, 6814 fd->fd_branch, 6815 (long)((fd - itd->itd_desc - 1)/3), 6816 itd->itd_maxpacket); 6817 } 6818 } 6819 6820 /* sanity check */ 6821 if (fd->fd_flags != OUTPUT_LAST_DESC) { 6822 printf("fwohci_itd_writedata: dmabuf %d desc inconsistent %d\n", 6823 itd->itd_num, writepkt + itd->itd_npacket); 6824 break; 6825 } 6826 fd->fd_reqcount = totalsize; 6827 /* XXX: sync cache */ 6828 6829 ++itdata; 6830 p += itd->itd_maxsize; 6831 } 6832 6833 DPRINTF(("loop start %d, %d times %d\n", 6834 itd->itd_npacket, dspace, writepkt)); 6835 6836 itd->itd_npacket += writepkt; 6837 itd->itd_lastdesc = fd; 6838 6839 return writepkt; 6840 } 6841 6842 6843 6844 6845 6846 int 6847 fwohci_itd_isfilled(struct fwohci_it_dmabuf *itd) 6848 { 6849 6850 return itd->itd_npacket*2 > itd->itd_maxpacket ? 1 : 0; 6851 } 6852
Indexes created Fri Sep 26 20:09:58 GMT 2025