fwohci.c revision 1.89
1 /* $NetBSD: fwohci.c,v 1.89 2005/07/11 15:37:00 kiyohara Exp $ */ 2 /*- 3 * Copyright (c) 2003 Hidetoshi Shimokawa 4 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the acknowledgement as bellow: 17 * 18 * This product includes software developed by K. Kobayashi and H. Shimokawa 19 * 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 32 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $ 36 * 37 */ 38 39 #define ATRQ_CH 0 40 #define ATRS_CH 1 41 #define ARRQ_CH 2 42 #define ARRS_CH 3 43 #define ITX_CH 4 44 #define IRX_CH 0x24 45 46 #if defined(__FreeBSD__) 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/bus.h> 54 #include <sys/kernel.h> 55 #include <sys/conf.h> 56 #include <sys/endian.h> 57 #include <sys/ktr.h> 58 59 #include <machine/bus.h> 60 61 #if defined(__DragonFly__) || __FreeBSD_version < 500000 62 #include <machine/clock.h> /* for DELAY() */ 63 #endif 64 65 #ifdef __DragonFly__ 66 #include "fw_port.h" 67 #include "firewire.h" 68 #include "firewirereg.h" 69 #include "fwdma.h" 70 #include "fwohcireg.h" 71 #include "fwohcivar.h" 72 #include "firewire_phy.h" 73 #else 74 #include <dev/firewire/fw_port.h> 75 #include <dev/firewire/firewire.h> 76 #include <dev/firewire/firewirereg.h> 77 #include <dev/firewire/fwdma.h> 78 #include <dev/firewire/fwohcireg.h> 79 #include <dev/firewire/fwohcivar.h> 80 #include <dev/firewire/firewire_phy.h> 81 #endif 82 #elif defined(__NetBSD__) 83 #include <sys/param.h> 84 #include <sys/device.h> 85 #include <sys/errno.h> 86 #include <sys/conf.h> 87 #include <sys/kernel.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/proc.h> 91 #include <sys/reboot.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 95 #include <machine/bus.h> 96 97 #include <dev/ieee1394/fw_port.h> 98 #include <dev/ieee1394/firewire.h> 99 #include <dev/ieee1394/firewirereg.h> 100 #include <dev/ieee1394/fwdma.h> 101 #include <dev/ieee1394/fwohcireg.h> 102 #include <dev/ieee1394/fwohcivar.h> 103 #include <dev/ieee1394/firewire_phy.h> 104 #endif 105 106 #undef OHCI_DEBUG 107 108 static int nocyclemaster = 0; 109 #if defined(__FreeBSD__) 110 SYSCTL_DECL(_hw_firewire); 111 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 112 "Do not send cycle start packets"); 113 #elif defined(__NetBSD__) 114 /* 115 * Setup sysctl(3) MIB, hw.fwohci.* 116 * 117 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 118 */ 119 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 120 { 121 int rc; 122 const struct sysctlnode *node; 123 124 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 125 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 126 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 127 goto err; 128 } 129 130 if ((rc = sysctl_createv(clog, 0, NULL, &node, 131 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 132 SYSCTL_DESCR("fwohci controls"), 133 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 134 goto err; 135 } 136 137 /* fwohci no cyclemaster flag */ 138 if ((rc = sysctl_createv(clog, 0, NULL, &node, 139 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 140 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 141 NULL, 0, &nocyclemaster, 142 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 143 goto err; 144 } 145 return; 146 147 err: 148 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 149 } 150 #endif 151 152 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 153 "STOR","LOAD","NOP ","STOP",}; 154 155 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 156 "UNDEF","REG","SYS","DEV"}; 157 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 158 char fwohcicode[32][0x20]={ 159 "No stat","Undef","long","miss Ack err", 160 "underrun","overrun","desc err", "data read err", 161 "data write err","bus reset","timeout","tcode err", 162 "Undef","Undef","unknown event","flushed", 163 "Undef","ack complete","ack pend","Undef", 164 "ack busy_X","ack busy_A","ack busy_B","Undef", 165 "Undef","Undef","Undef","ack tardy", 166 "Undef","ack data_err","ack type_err",""}; 167 168 #define MAX_SPEED 3 169 extern char *linkspeed[]; 170 uint32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 171 172 static struct tcode_info tinfo[] = { 173 /* hdr_len block flag*/ 174 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 175 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 176 /* 2 WRES */ {12, FWTI_RES}, 177 /* 3 XXX */ { 0, 0}, 178 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 179 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 180 /* 6 RRESQ */ {16, FWTI_RES}, 181 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 182 /* 8 CYCS */ { 0, 0}, 183 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 184 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 185 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 186 /* c XXX */ { 0, 0}, 187 /* d XXX */ { 0, 0}, 188 /* e PHY */ {12, FWTI_REQ}, 189 /* f XXX */ { 0, 0} 190 }; 191 192 #define OHCI_WRITE_SIGMASK 0xffff0000 193 #define OHCI_READ_SIGMASK 0xffff0000 194 195 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 196 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 197 198 static void fwohci_ibr (struct firewire_comm *); 199 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 200 static void fwohci_db_free (struct fwohci_dbch *); 201 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 202 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 203 static void fwohci_start_atq (struct firewire_comm *); 204 static void fwohci_start_ats (struct firewire_comm *); 205 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 206 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 207 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 208 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 209 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 210 static int fwohci_irx_enable (struct firewire_comm *, int); 211 static int fwohci_irx_disable (struct firewire_comm *, int); 212 #if BYTE_ORDER == BIG_ENDIAN 213 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 214 #endif 215 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 216 static int fwohci_itx_disable (struct firewire_comm *, int); 217 static void fwohci_timeout (void *); 218 static void fwohci_set_intr (struct firewire_comm *, int); 219 220 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 221 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 222 static void dump_db (struct fwohci_softc *, uint32_t); 223 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 224 static void dump_dma (struct fwohci_softc *, uint32_t); 225 static uint32_t fwohci_cyctimer (struct firewire_comm *); 226 static void fwohci_rbuf_update (struct fwohci_softc *, int); 227 static void fwohci_tbuf_update (struct fwohci_softc *, int); 228 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 229 #if FWOHCI_TASKQUEUE 230 static void fwohci_complete(void *, int); 231 #endif 232 #if defined(__NetBSD__) 233 static void fwohci_power(int, void *); 234 int fwohci_print(void *, const char *); 235 #endif 236 237 /* 238 * memory allocated for DMA programs 239 */ 240 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 241 242 #define NDB FWMAXQUEUE 243 244 #define OHCI_VERSION 0x00 245 #define OHCI_ATRETRY 0x08 246 #define OHCI_CROMHDR 0x18 247 #define OHCI_BUS_OPT 0x20 248 #define OHCI_BUSIRMC (1 << 31) 249 #define OHCI_BUSCMC (1 << 30) 250 #define OHCI_BUSISC (1 << 29) 251 #define OHCI_BUSBMC (1 << 28) 252 #define OHCI_BUSPMC (1 << 27) 253 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 254 OHCI_BUSBMC | OHCI_BUSPMC 255 256 #define OHCI_EUID_HI 0x24 257 #define OHCI_EUID_LO 0x28 258 259 #define OHCI_CROMPTR 0x34 260 #define OHCI_HCCCTL 0x50 261 #define OHCI_HCCCTLCLR 0x54 262 #define OHCI_AREQHI 0x100 263 #define OHCI_AREQHICLR 0x104 264 #define OHCI_AREQLO 0x108 265 #define OHCI_AREQLOCLR 0x10c 266 #define OHCI_PREQHI 0x110 267 #define OHCI_PREQHICLR 0x114 268 #define OHCI_PREQLO 0x118 269 #define OHCI_PREQLOCLR 0x11c 270 #define OHCI_PREQUPPER 0x120 271 272 #define OHCI_SID_BUF 0x64 273 #define OHCI_SID_CNT 0x68 274 #define OHCI_SID_ERR (1 << 31) 275 #define OHCI_SID_CNT_MASK 0xffc 276 277 #define OHCI_IT_STAT 0x90 278 #define OHCI_IT_STATCLR 0x94 279 #define OHCI_IT_MASK 0x98 280 #define OHCI_IT_MASKCLR 0x9c 281 282 #define OHCI_IR_STAT 0xa0 283 #define OHCI_IR_STATCLR 0xa4 284 #define OHCI_IR_MASK 0xa8 285 #define OHCI_IR_MASKCLR 0xac 286 287 #define OHCI_LNKCTL 0xe0 288 #define OHCI_LNKCTLCLR 0xe4 289 290 #define OHCI_PHYACCESS 0xec 291 #define OHCI_CYCLETIMER 0xf0 292 293 #define OHCI_DMACTL(off) (off) 294 #define OHCI_DMACTLCLR(off) (off + 4) 295 #define OHCI_DMACMD(off) (off + 0xc) 296 #define OHCI_DMAMATCH(off) (off + 0x10) 297 298 #define OHCI_ATQOFF 0x180 299 #define OHCI_ATQCTL OHCI_ATQOFF 300 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 301 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 302 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 303 304 #define OHCI_ATSOFF 0x1a0 305 #define OHCI_ATSCTL OHCI_ATSOFF 306 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 307 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 308 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 309 310 #define OHCI_ARQOFF 0x1c0 311 #define OHCI_ARQCTL OHCI_ARQOFF 312 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 313 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 314 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 315 316 #define OHCI_ARSOFF 0x1e0 317 #define OHCI_ARSCTL OHCI_ARSOFF 318 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 319 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 320 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 321 322 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 323 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 324 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 325 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 326 327 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 328 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 329 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 330 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 331 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 332 333 #if defined(__FreeBSD__) 334 d_ioctl_t fwohci_ioctl; 335 #elif defined(__NetBSD__) 336 extern struct cfdriver fwohci_cd; 337 dev_type_ioctl(fwohci_ioctl); 338 #endif 339 340 /* 341 * Communication with PHY device 342 */ 343 static uint32_t 344 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 345 { 346 uint32_t fun; 347 348 addr &= 0xf; 349 data &= 0xff; 350 351 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 352 OWRITE(sc, OHCI_PHYACCESS, fun); 353 DELAY(100); 354 355 return(fwphy_rddata( sc, addr)); 356 } 357 358 static uint32_t 359 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 360 { 361 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 362 int i; 363 uint32_t bm; 364 365 #define OHCI_CSR_DATA 0x0c 366 #define OHCI_CSR_COMP 0x10 367 #define OHCI_CSR_CONT 0x14 368 #define OHCI_BUS_MANAGER_ID 0 369 370 OWRITE(sc, OHCI_CSR_DATA, node); 371 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 372 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 373 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 374 DELAY(10); 375 bm = OREAD(sc, OHCI_CSR_DATA); 376 if((bm & 0x3f) == 0x3f) 377 bm = node; 378 if (firewire_debug) 379 device_printf(sc->fc.dev, 380 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 381 382 return(bm); 383 } 384 385 static uint32_t 386 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 387 { 388 uint32_t fun, stat; 389 u_int i, retry = 0; 390 391 addr &= 0xf; 392 #define MAX_RETRY 100 393 again: 394 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 395 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 396 OWRITE(sc, OHCI_PHYACCESS, fun); 397 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 398 fun = OREAD(sc, OHCI_PHYACCESS); 399 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 400 break; 401 DELAY(100); 402 } 403 if(i >= MAX_RETRY) { 404 if (firewire_debug) 405 device_printf(sc->fc.dev, "phy read failed(1).\n"); 406 if (++retry < MAX_RETRY) { 407 DELAY(100); 408 goto again; 409 } 410 } 411 /* Make sure that SCLK is started */ 412 stat = OREAD(sc, FWOHCI_INTSTAT); 413 if ((stat & OHCI_INT_REG_FAIL) != 0 || 414 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 415 if (firewire_debug) 416 device_printf(sc->fc.dev, "phy read failed(2).\n"); 417 if (++retry < MAX_RETRY) { 418 DELAY(100); 419 goto again; 420 } 421 } 422 if (firewire_debug || retry >= MAX_RETRY) 423 device_printf(sc->fc.dev, 424 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 425 #undef MAX_RETRY 426 return((fun >> PHYDEV_RDDATA )& 0xff); 427 } 428 /* Device specific ioctl. */ 429 FW_IOCTL(fwohci) 430 { 431 FW_IOCTL_START; 432 struct fwohci_softc *fc; 433 int err = 0; 434 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 435 uint32_t *dmach = (uint32_t *) data; 436 437 if(sc == NULL){ 438 return(EINVAL); 439 } 440 fc = (struct fwohci_softc *)sc->fc; 441 442 if (!data) 443 return(EINVAL); 444 445 switch (cmd) { 446 case FWOHCI_WRREG: 447 #define OHCI_MAX_REG 0x800 448 if(reg->addr <= OHCI_MAX_REG){ 449 OWRITE(fc, reg->addr, reg->data); 450 reg->data = OREAD(fc, reg->addr); 451 }else{ 452 err = EINVAL; 453 } 454 break; 455 case FWOHCI_RDREG: 456 if(reg->addr <= OHCI_MAX_REG){ 457 reg->data = OREAD(fc, reg->addr); 458 }else{ 459 err = EINVAL; 460 } 461 break; 462 /* Read DMA descriptors for debug */ 463 case DUMPDMA: 464 if(*dmach <= OHCI_MAX_DMA_CH ){ 465 dump_dma(fc, *dmach); 466 dump_db(fc, *dmach); 467 }else{ 468 err = EINVAL; 469 } 470 break; 471 /* Read/Write Phy registers */ 472 #define OHCI_MAX_PHY_REG 0xf 473 case FWOHCI_RDPHYREG: 474 if (reg->addr <= OHCI_MAX_PHY_REG) 475 reg->data = fwphy_rddata(fc, reg->addr); 476 else 477 err = EINVAL; 478 break; 479 case FWOHCI_WRPHYREG: 480 if (reg->addr <= OHCI_MAX_PHY_REG) 481 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 482 else 483 err = EINVAL; 484 break; 485 default: 486 err = EINVAL; 487 break; 488 } 489 return err; 490 } 491 492 static int 493 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 494 { 495 uint32_t reg, reg2; 496 int e1394a = 1; 497 /* 498 * probe PHY parameters 499 * 0. to prove PHY version, whether compliance of 1394a. 500 * 1. to probe maximum speed supported by the PHY and 501 * number of port supported by core-logic. 502 * It is not actually available port on your PC . 503 */ 504 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 505 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 506 507 if((reg >> 5) != 7 ){ 508 sc->fc.mode &= ~FWPHYASYST; 509 sc->fc.nport = reg & FW_PHY_NP; 510 sc->fc.speed = reg & FW_PHY_SPD >> 6; 511 if (sc->fc.speed > MAX_SPEED) { 512 device_printf(dev, "invalid speed %d (fixed to %d).\n", 513 sc->fc.speed, MAX_SPEED); 514 sc->fc.speed = MAX_SPEED; 515 } 516 device_printf(dev, 517 "Phy 1394 only %s, %d ports.\n", 518 linkspeed[sc->fc.speed], sc->fc.nport); 519 }else{ 520 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 521 sc->fc.mode |= FWPHYASYST; 522 sc->fc.nport = reg & FW_PHY_NP; 523 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 524 if (sc->fc.speed > MAX_SPEED) { 525 device_printf(dev, "invalid speed %d (fixed to %d).\n", 526 sc->fc.speed, MAX_SPEED); 527 sc->fc.speed = MAX_SPEED; 528 } 529 device_printf(dev, 530 "Phy 1394a available %s, %d ports.\n", 531 linkspeed[sc->fc.speed], sc->fc.nport); 532 533 /* check programPhyEnable */ 534 reg2 = fwphy_rddata(sc, 5); 535 #if 0 536 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 537 #else /* XXX force to enable 1394a */ 538 if (e1394a) { 539 #endif 540 if (firewire_debug) 541 device_printf(dev, 542 "Enable 1394a Enhancements\n"); 543 /* enable EAA EMC */ 544 reg2 |= 0x03; 545 /* set aPhyEnhanceEnable */ 546 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 547 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 548 } else { 549 /* for safe */ 550 reg2 &= ~0x83; 551 } 552 reg2 = fwphy_wrdata(sc, 5, reg2); 553 } 554 555 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 556 if((reg >> 5) == 7 ){ 557 reg = fwphy_rddata(sc, 4); 558 reg |= 1 << 6; 559 fwphy_wrdata(sc, 4, reg); 560 reg = fwphy_rddata(sc, 4); 561 } 562 return 0; 563 } 564 565 566 void 567 fwohci_reset(struct fwohci_softc *sc, device_t dev) 568 { 569 int i, max_rec, speed; 570 uint32_t reg, reg2; 571 struct fwohcidb_tr *db_tr; 572 573 /* Disable interrupts */ 574 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 575 576 /* Now stopping all DMA channels */ 577 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 578 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 579 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 580 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 581 582 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 583 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 584 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 585 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 586 } 587 588 /* FLUSH FIFO and reset Transmitter/Reciever */ 589 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 590 if (firewire_debug) 591 device_printf(dev, "resetting OHCI..."); 592 i = 0; 593 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 594 if (i++ > 100) break; 595 DELAY(1000); 596 } 597 if (firewire_debug) 598 printf("done (loop=%d)\n", i); 599 600 /* Probe phy */ 601 fwohci_probe_phy(sc, dev); 602 603 /* Probe link */ 604 reg = OREAD(sc, OHCI_BUS_OPT); 605 reg2 = reg | OHCI_BUSFNC; 606 max_rec = (reg & 0x0000f000) >> 12; 607 speed = (reg & 0x00000007); 608 device_printf(dev, "Link %s, max_rec %d bytes.\n", 609 linkspeed[speed], MAXREC(max_rec)); 610 /* XXX fix max_rec */ 611 sc->fc.maxrec = sc->fc.speed + 8; 612 if (max_rec != sc->fc.maxrec) { 613 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 614 device_printf(dev, "max_rec %d -> %d\n", 615 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 616 } 617 if (firewire_debug) 618 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 619 OWRITE(sc, OHCI_BUS_OPT, reg2); 620 621 /* Initialize registers */ 622 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 623 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 624 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 625 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 626 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 627 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 628 629 /* Enable link */ 630 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 631 632 /* Force to start async RX DMA */ 633 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 634 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 635 fwohci_rx_enable(sc, &sc->arrq); 636 fwohci_rx_enable(sc, &sc->arrs); 637 638 /* Initialize async TX */ 639 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 640 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 641 642 /* AT Retries */ 643 OWRITE(sc, FWOHCI_RETRY, 644 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 645 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 646 647 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 648 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 649 sc->atrq.bottom = sc->atrq.top; 650 sc->atrs.bottom = sc->atrs.top; 651 652 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 653 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 654 db_tr->xfer = NULL; 655 } 656 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 657 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 658 db_tr->xfer = NULL; 659 } 660 661 662 /* Enable interrupts */ 663 OWRITE(sc, FWOHCI_INTMASK, 664 OHCI_INT_ERR | OHCI_INT_PHY_SID 665 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 666 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 667 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 668 fwohci_set_intr(&sc->fc, 1); 669 670 } 671 672 int 673 fwohci_init(struct fwohci_softc *sc, device_t dev) 674 { 675 int i, mver; 676 uint32_t reg; 677 uint8_t ui[8]; 678 679 #if FWOHCI_TASKQUEUE 680 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 681 #endif 682 683 /* OHCI version */ 684 reg = OREAD(sc, OHCI_VERSION); 685 mver = (reg >> 16) & 0xff; 686 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 687 mver, reg & 0xff, (reg>>24) & 1); 688 if (mver < 1 || mver > 9) { 689 device_printf(dev, "invalid OHCI version\n"); 690 return (ENXIO); 691 } 692 693 /* Available Isochronous DMA channel probe */ 694 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 695 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 696 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 697 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 698 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 699 for (i = 0; i < 0x20; i++) 700 if ((reg & (1 << i)) == 0) 701 break; 702 sc->fc.nisodma = i; 703 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 704 if (i == 0) 705 return (ENXIO); 706 707 sc->fc.arq = &sc->arrq.xferq; 708 sc->fc.ars = &sc->arrs.xferq; 709 sc->fc.atq = &sc->atrq.xferq; 710 sc->fc.ats = &sc->atrs.xferq; 711 712 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 713 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 714 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 715 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 716 717 sc->arrq.xferq.start = NULL; 718 sc->arrs.xferq.start = NULL; 719 sc->atrq.xferq.start = fwohci_start_atq; 720 sc->atrs.xferq.start = fwohci_start_ats; 721 722 sc->arrq.xferq.buf = NULL; 723 sc->arrs.xferq.buf = NULL; 724 sc->atrq.xferq.buf = NULL; 725 sc->atrs.xferq.buf = NULL; 726 727 sc->arrq.xferq.dmach = -1; 728 sc->arrs.xferq.dmach = -1; 729 sc->atrq.xferq.dmach = -1; 730 sc->atrs.xferq.dmach = -1; 731 732 sc->arrq.ndesc = 1; 733 sc->arrs.ndesc = 1; 734 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 735 sc->atrs.ndesc = 2; 736 737 sc->arrq.ndb = NDB; 738 sc->arrs.ndb = NDB / 2; 739 sc->atrq.ndb = NDB; 740 sc->atrs.ndb = NDB / 2; 741 742 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 743 sc->fc.it[i] = &sc->it[i].xferq; 744 sc->fc.ir[i] = &sc->ir[i].xferq; 745 sc->it[i].xferq.dmach = i; 746 sc->ir[i].xferq.dmach = i; 747 sc->it[i].ndb = 0; 748 sc->ir[i].ndb = 0; 749 } 750 751 sc->fc.tcode = tinfo; 752 sc->fc.dev = dev; 753 754 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 755 &sc->crom_dma, BUS_DMA_WAITOK); 756 if(sc->fc.config_rom == NULL){ 757 device_printf(dev, "config_rom alloc failed."); 758 return ENOMEM; 759 } 760 761 #if 0 762 bzero(&sc->fc.config_rom[0], CROMSIZE); 763 sc->fc.config_rom[1] = 0x31333934; 764 sc->fc.config_rom[2] = 0xf000a002; 765 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 766 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 767 sc->fc.config_rom[5] = 0; 768 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 769 770 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 771 #endif 772 773 774 /* SID recieve buffer must align 2^11 */ 775 #define OHCI_SIDSIZE (1 << 11) 776 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 777 &sc->sid_dma, BUS_DMA_WAITOK); 778 if (sc->sid_buf == NULL) { 779 device_printf(dev, "sid_buf alloc failed."); 780 return ENOMEM; 781 } 782 783 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 784 &sc->dummy_dma, BUS_DMA_WAITOK); 785 786 if (sc->dummy_dma.v_addr == NULL) { 787 device_printf(dev, "dummy_dma alloc failed."); 788 return ENOMEM; 789 } 790 791 fwohci_db_init(sc, &sc->arrq); 792 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 793 return ENOMEM; 794 795 fwohci_db_init(sc, &sc->arrs); 796 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 797 return ENOMEM; 798 799 fwohci_db_init(sc, &sc->atrq); 800 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 801 return ENOMEM; 802 803 fwohci_db_init(sc, &sc->atrs); 804 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 805 return ENOMEM; 806 807 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 808 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 809 for( i = 0 ; i < 8 ; i ++) 810 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 811 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 812 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 813 814 sc->fc.ioctl = fwohci_ioctl; 815 sc->fc.cyctimer = fwohci_cyctimer; 816 sc->fc.set_bmr = fwohci_set_bus_manager; 817 sc->fc.ibr = fwohci_ibr; 818 sc->fc.irx_enable = fwohci_irx_enable; 819 sc->fc.irx_disable = fwohci_irx_disable; 820 821 sc->fc.itx_enable = fwohci_itxbuf_enable; 822 sc->fc.itx_disable = fwohci_itx_disable; 823 #if BYTE_ORDER == BIG_ENDIAN 824 sc->fc.irx_post = fwohci_irx_post; 825 #else 826 sc->fc.irx_post = NULL; 827 #endif 828 sc->fc.itx_post = NULL; 829 sc->fc.timeout = fwohci_timeout; 830 sc->fc.poll = fwohci_poll; 831 sc->fc.set_intr = fwohci_set_intr; 832 833 sc->intmask = sc->irstat = sc->itstat = 0; 834 835 fw_init(&sc->fc); 836 fwohci_reset(sc, dev); 837 FWOHCI_INIT_END; 838 839 return 0; 840 } 841 842 void 843 fwohci_timeout(void *arg) 844 { 845 struct fwohci_softc *sc; 846 847 sc = (struct fwohci_softc *)arg; 848 } 849 850 uint32_t 851 fwohci_cyctimer(struct firewire_comm *fc) 852 { 853 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 854 return(OREAD(sc, OHCI_CYCLETIMER)); 855 } 856 857 FWOHCI_DETACH() 858 { 859 int i; 860 861 FWOHCI_DETACH_START; 862 if (sc->sid_buf != NULL) 863 fwdma_free(&sc->fc, &sc->sid_dma); 864 if (sc->fc.config_rom != NULL) 865 fwdma_free(&sc->fc, &sc->crom_dma); 866 867 fwohci_db_free(&sc->arrq); 868 fwohci_db_free(&sc->arrs); 869 870 fwohci_db_free(&sc->atrq); 871 fwohci_db_free(&sc->atrs); 872 873 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 874 fwohci_db_free(&sc->it[i]); 875 fwohci_db_free(&sc->ir[i]); 876 } 877 FWOHCI_DETACH_END; 878 879 return 0; 880 } 881 882 #define LAST_DB(dbtr, db) do { \ 883 struct fwohcidb_tr *_dbtr = (dbtr); \ 884 int _cnt = _dbtr->dbcnt; \ 885 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 886 } while (0) 887 888 static void 889 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 890 { 891 struct fwohcidb_tr *db_tr; 892 struct fwohcidb *db; 893 bus_dma_segment_t *s; 894 int i; 895 896 db_tr = (struct fwohcidb_tr *)arg; 897 db = &db_tr->db[db_tr->dbcnt]; 898 if (error) { 899 if (firewire_debug || error != EFBIG) 900 printf("fwohci_execute_db: error=%d\n", error); 901 return; 902 } 903 for (i = 0; i < nseg; i++) { 904 s = &segs[i]; 905 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 906 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 907 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 908 db++; 909 db_tr->dbcnt++; 910 } 911 } 912 913 static void 914 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 915 bus_size_t size, int error) 916 { 917 fwohci_execute_db(arg, segs, nseg, error); 918 } 919 920 static void 921 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 922 { 923 int i, s; 924 int tcode, hdr_len, pl_off; 925 int fsegment = -1; 926 uint32_t off; 927 struct fw_xfer *xfer; 928 struct fw_pkt *fp; 929 struct fwohci_txpkthdr *ohcifp; 930 struct fwohcidb_tr *db_tr; 931 struct fwohcidb *db; 932 uint32_t *ld; 933 struct tcode_info *info; 934 static int maxdesc=0; 935 936 if(&sc->atrq == dbch){ 937 off = OHCI_ATQOFF; 938 }else if(&sc->atrs == dbch){ 939 off = OHCI_ATSOFF; 940 }else{ 941 return; 942 } 943 944 if (dbch->flags & FWOHCI_DBCH_FULL) 945 return; 946 947 s = splfw(); 948 fwdma_sync_multiseg_all(dbch->am, 949 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 950 db_tr = dbch->top; 951 txloop: 952 xfer = STAILQ_FIRST(&dbch->xferq.q); 953 if(xfer == NULL){ 954 goto kick; 955 } 956 if(dbch->xferq.queued == 0 ){ 957 device_printf(sc->fc.dev, "TX queue empty\n"); 958 } 959 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 960 db_tr->xfer = xfer; 961 xfer->state = FWXF_START; 962 963 fp = &xfer->send.hdr; 964 tcode = fp->mode.common.tcode; 965 966 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 967 info = &tinfo[tcode]; 968 hdr_len = pl_off = info->hdr_len; 969 970 ld = &ohcifp->mode.ld[0]; 971 ld[0] = ld[1] = ld[2] = ld[3] = 0; 972 for( i = 0 ; i < pl_off ; i+= 4) 973 ld[i/4] = fp->mode.ld[i/4]; 974 975 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 976 if (tcode == FWTCODE_STREAM ){ 977 hdr_len = 8; 978 ohcifp->mode.stream.len = fp->mode.stream.len; 979 } else if (tcode == FWTCODE_PHY) { 980 hdr_len = 12; 981 ld[1] = fp->mode.ld[1]; 982 ld[2] = fp->mode.ld[2]; 983 ohcifp->mode.common.spd = 0; 984 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 985 } else { 986 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 987 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 988 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 989 } 990 db = &db_tr->db[0]; 991 FWOHCI_DMA_WRITE(db->db.desc.cmd, 992 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 993 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 994 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 995 /* Specify bound timer of asy. responce */ 996 if(&sc->atrs == dbch){ 997 FWOHCI_DMA_WRITE(db->db.desc.res, 998 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 999 } 1000 #if BYTE_ORDER == BIG_ENDIAN 1001 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1002 hdr_len = 12; 1003 for (i = 0; i < hdr_len/4; i ++) 1004 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1005 #endif 1006 1007 again: 1008 db_tr->dbcnt = 2; 1009 db = &db_tr->db[db_tr->dbcnt]; 1010 if (xfer->send.pay_len > 0) { 1011 int err; 1012 /* handle payload */ 1013 if (xfer->mbuf == NULL) { 1014 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1015 &xfer->send.payload[0], xfer->send.pay_len, 1016 fwohci_execute_db, db_tr, 1017 BUS_DMA_WAITOK); 1018 } else { 1019 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1020 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1021 db_tr->dma_map, xfer->mbuf, 1022 fwohci_execute_db2, db_tr, 1023 BUS_DMA_WAITOK); 1024 if (err == EFBIG) { 1025 struct mbuf *m0; 1026 1027 if (firewire_debug) 1028 device_printf(sc->fc.dev, "EFBIG.\n"); 1029 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1030 if (m0 != NULL) { 1031 m_copydata(xfer->mbuf, 0, 1032 xfer->mbuf->m_pkthdr.len, 1033 mtod(m0, caddr_t)); 1034 m0->m_len = m0->m_pkthdr.len = 1035 xfer->mbuf->m_pkthdr.len; 1036 m_freem(xfer->mbuf); 1037 xfer->mbuf = m0; 1038 goto again; 1039 } 1040 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1041 } 1042 } 1043 if (err) 1044 printf("dmamap_load: err=%d\n", err); 1045 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1046 BUS_DMASYNC_PREWRITE); 1047 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1048 for (i = 2; i < db_tr->dbcnt; i++) 1049 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1050 OHCI_OUTPUT_MORE); 1051 #endif 1052 } 1053 if (maxdesc < db_tr->dbcnt) { 1054 maxdesc = db_tr->dbcnt; 1055 if (firewire_debug) 1056 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1057 } 1058 /* last db */ 1059 LAST_DB(db_tr, db); 1060 FWOHCI_DMA_SET(db->db.desc.cmd, 1061 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1062 FWOHCI_DMA_WRITE(db->db.desc.depend, 1063 STAILQ_NEXT(db_tr, link)->bus_addr); 1064 1065 if(fsegment == -1 ) 1066 fsegment = db_tr->dbcnt; 1067 if (dbch->pdb_tr != NULL) { 1068 LAST_DB(dbch->pdb_tr, db); 1069 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1070 } 1071 dbch->pdb_tr = db_tr; 1072 db_tr = STAILQ_NEXT(db_tr, link); 1073 if(db_tr != dbch->bottom){ 1074 goto txloop; 1075 } else { 1076 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1077 dbch->flags |= FWOHCI_DBCH_FULL; 1078 } 1079 kick: 1080 /* kick asy q */ 1081 fwdma_sync_multiseg_all(dbch->am, 1082 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1083 1084 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1085 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1086 } else { 1087 if (firewire_debug) 1088 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1089 OREAD(sc, OHCI_DMACTL(off))); 1090 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1091 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1092 dbch->xferq.flag |= FWXFERQ_RUNNING; 1093 } 1094 CTR0(KTR_DEV, "start kick done"); 1095 CTR0(KTR_DEV, "start kick done2"); 1096 1097 dbch->top = db_tr; 1098 splx(s); 1099 return; 1100 } 1101 1102 static void 1103 fwohci_start_atq(struct firewire_comm *fc) 1104 { 1105 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1106 fwohci_start( sc, &(sc->atrq)); 1107 return; 1108 } 1109 1110 static void 1111 fwohci_start_ats(struct firewire_comm *fc) 1112 { 1113 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1114 fwohci_start( sc, &(sc->atrs)); 1115 return; 1116 } 1117 1118 void 1119 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1120 { 1121 int s, ch, err = 0; 1122 struct fwohcidb_tr *tr; 1123 struct fwohcidb *db; 1124 struct fw_xfer *xfer; 1125 uint32_t off; 1126 u_int stat, status; 1127 int packets; 1128 struct firewire_comm *fc = (struct firewire_comm *)sc; 1129 1130 if(&sc->atrq == dbch){ 1131 off = OHCI_ATQOFF; 1132 ch = ATRQ_CH; 1133 }else if(&sc->atrs == dbch){ 1134 off = OHCI_ATSOFF; 1135 ch = ATRS_CH; 1136 }else{ 1137 return; 1138 } 1139 s = splfw(); 1140 tr = dbch->bottom; 1141 packets = 0; 1142 fwdma_sync_multiseg_all(dbch->am, 1143 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1144 while(dbch->xferq.queued > 0){ 1145 LAST_DB(tr, db); 1146 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1147 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1148 if (fc->status != FWBUSRESET) 1149 /* maybe out of order?? */ 1150 goto out; 1151 } 1152 if (tr->xfer->send.pay_len > 0) { 1153 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1154 BUS_DMASYNC_POSTWRITE); 1155 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1156 } 1157 #if 1 1158 if (firewire_debug > 1) 1159 dump_db(sc, ch); 1160 #endif 1161 if(status & OHCI_CNTL_DMA_DEAD) { 1162 /* Stop DMA */ 1163 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1164 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1165 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1166 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1167 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1168 } 1169 stat = status & FWOHCIEV_MASK; 1170 switch(stat){ 1171 case FWOHCIEV_ACKPEND: 1172 CTR0(KTR_DEV, "txd: ack pending"); 1173 /* fall through */ 1174 case FWOHCIEV_ACKCOMPL: 1175 err = 0; 1176 break; 1177 case FWOHCIEV_ACKBSA: 1178 case FWOHCIEV_ACKBSB: 1179 case FWOHCIEV_ACKBSX: 1180 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1181 err = EBUSY; 1182 break; 1183 case FWOHCIEV_FLUSHED: 1184 case FWOHCIEV_ACKTARD: 1185 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1186 err = EAGAIN; 1187 break; 1188 case FWOHCIEV_MISSACK: 1189 case FWOHCIEV_UNDRRUN: 1190 case FWOHCIEV_OVRRUN: 1191 case FWOHCIEV_DESCERR: 1192 case FWOHCIEV_DTRDERR: 1193 case FWOHCIEV_TIMEOUT: 1194 case FWOHCIEV_TCODERR: 1195 case FWOHCIEV_UNKNOWN: 1196 case FWOHCIEV_ACKDERR: 1197 case FWOHCIEV_ACKTERR: 1198 default: 1199 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1200 stat, fwohcicode[stat]); 1201 err = EINVAL; 1202 break; 1203 } 1204 if (tr->xfer != NULL) { 1205 xfer = tr->xfer; 1206 CTR0(KTR_DEV, "txd"); 1207 if (xfer->state == FWXF_RCVD) { 1208 #if 0 1209 if (firewire_debug) 1210 printf("already rcvd\n"); 1211 #endif 1212 fw_xfer_done(xfer); 1213 } else { 1214 xfer->state = FWXF_SENT; 1215 if (err == EBUSY && fc->status != FWBUSRESET) { 1216 xfer->state = FWXF_BUSY; 1217 xfer->resp = err; 1218 xfer->recv.pay_len = 0; 1219 fw_xfer_done(xfer); 1220 } else if (stat != FWOHCIEV_ACKPEND) { 1221 if (stat != FWOHCIEV_ACKCOMPL) 1222 xfer->state = FWXF_SENTERR; 1223 xfer->resp = err; 1224 xfer->recv.pay_len = 0; 1225 fw_xfer_done(xfer); 1226 } 1227 } 1228 /* 1229 * The watchdog timer takes care of split 1230 * transcation timeout for ACKPEND case. 1231 */ 1232 } else { 1233 printf("this shouldn't happen\n"); 1234 } 1235 dbch->xferq.queued --; 1236 tr->xfer = NULL; 1237 1238 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1239 packets ++; 1240 tr = STAILQ_NEXT(tr, link); 1241 dbch->bottom = tr; 1242 if (dbch->bottom == dbch->top) { 1243 /* we reaches the end of context program */ 1244 if (firewire_debug && dbch->xferq.queued > 0) 1245 printf("queued > 0\n"); 1246 break; 1247 } 1248 } 1249 out: 1250 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1251 printf("make free slot\n"); 1252 dbch->flags &= ~FWOHCI_DBCH_FULL; 1253 fwohci_start(sc, dbch); 1254 } 1255 fwdma_sync_multiseg_all( 1256 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1257 splx(s); 1258 } 1259 1260 static void 1261 fwohci_db_free(struct fwohci_dbch *dbch) 1262 { 1263 struct fwohcidb_tr *db_tr; 1264 int idb; 1265 1266 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1267 return; 1268 1269 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1270 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1271 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1272 db_tr->buf != NULL) { 1273 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1274 db_tr->buf, dbch->xferq.psize); 1275 db_tr->buf = NULL; 1276 } else if (db_tr->dma_map != NULL) 1277 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1278 } 1279 dbch->ndb = 0; 1280 db_tr = STAILQ_FIRST(&dbch->db_trq); 1281 fwdma_free_multiseg(dbch->am); 1282 free(db_tr, M_FW); 1283 STAILQ_INIT(&dbch->db_trq); 1284 dbch->flags &= ~FWOHCI_DBCH_INIT; 1285 } 1286 1287 static void 1288 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1289 { 1290 int idb; 1291 struct fwohcidb_tr *db_tr; 1292 1293 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1294 goto out; 1295 1296 /* create dma_tag for buffers */ 1297 #define MAX_REQCOUNT 0xffff 1298 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1299 /*alignment*/ 1, /*boundary*/ 0, 1300 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1301 /*highaddr*/ BUS_SPACE_MAXADDR, 1302 /*filter*/NULL, /*filterarg*/NULL, 1303 /*maxsize*/ dbch->xferq.psize, 1304 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1305 /*maxsegsz*/ MAX_REQCOUNT, 1306 /*flags*/ 0, 1307 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1308 /*lockfunc*/busdma_lock_mutex, 1309 /*lockarg*/&Giant, 1310 #endif 1311 &dbch->dmat)) 1312 return; 1313 1314 /* allocate DB entries and attach one to each DMA channels */ 1315 /* DB entry must start at 16 bytes bounary. */ 1316 STAILQ_INIT(&dbch->db_trq); 1317 db_tr = (struct fwohcidb_tr *) 1318 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1319 M_FW, M_WAITOK | M_ZERO); 1320 if(db_tr == NULL){ 1321 printf("fwohci_db_init: malloc(1) failed\n"); 1322 return; 1323 } 1324 1325 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1326 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1327 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1328 if (dbch->am == NULL) { 1329 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1330 free(db_tr, M_FW); 1331 return; 1332 } 1333 /* Attach DB to DMA ch. */ 1334 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1335 db_tr->dbcnt = 0; 1336 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1337 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1338 /* create dmamap for buffers */ 1339 /* XXX do we need 4bytes alignment tag? */ 1340 /* XXX don't alloc dma_map for AR */ 1341 if (bus_dmamap_create(sc->fc.dmat, dbch->xferq.psize, 1342 dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, MAX_REQCOUNT, 1343 0, BUS_DMA_NOWAIT, &db_tr->dma_map) != 0) { 1344 printf("bus_dmamap_create failed\n"); 1345 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1346 fwohci_db_free(dbch); 1347 return; 1348 } 1349 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1350 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1351 if (idb % dbch->xferq.bnpacket == 0) 1352 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1353 ].start = (caddr_t)db_tr; 1354 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1355 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1356 ].end = (caddr_t)db_tr; 1357 } 1358 db_tr++; 1359 } 1360 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1361 = STAILQ_FIRST(&dbch->db_trq); 1362 out: 1363 dbch->xferq.queued = 0; 1364 dbch->pdb_tr = NULL; 1365 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1366 dbch->bottom = dbch->top; 1367 dbch->flags = FWOHCI_DBCH_INIT; 1368 } 1369 1370 static int 1371 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1372 { 1373 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1374 int sleepch; 1375 1376 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1377 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1378 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1379 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1380 /* XXX we cannot free buffers until the DMA really stops */ 1381 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1382 fwohci_db_free(&sc->it[dmach]); 1383 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1384 return 0; 1385 } 1386 1387 static int 1388 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1389 { 1390 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1391 int sleepch; 1392 1393 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1394 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1395 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1396 /* XXX we cannot free buffers until the DMA really stops */ 1397 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1398 fwohci_db_free(&sc->ir[dmach]); 1399 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1400 return 0; 1401 } 1402 1403 #if BYTE_ORDER == BIG_ENDIAN 1404 static void 1405 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1406 { 1407 qld[0] = FWOHCI_DMA_READ(qld[0]); 1408 return; 1409 } 1410 #endif 1411 1412 static int 1413 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1414 { 1415 int err = 0; 1416 int idb, z, i, dmach = 0, ldesc; 1417 uint32_t off = 0; 1418 struct fwohcidb_tr *db_tr; 1419 struct fwohcidb *db; 1420 1421 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1422 err = EINVAL; 1423 return err; 1424 } 1425 z = dbch->ndesc; 1426 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1427 if( &sc->it[dmach] == dbch){ 1428 off = OHCI_ITOFF(dmach); 1429 break; 1430 } 1431 } 1432 if(off == 0){ 1433 err = EINVAL; 1434 return err; 1435 } 1436 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1437 return err; 1438 dbch->xferq.flag |= FWXFERQ_RUNNING; 1439 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1440 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1441 } 1442 db_tr = dbch->top; 1443 for (idb = 0; idb < dbch->ndb; idb ++) { 1444 fwohci_add_tx_buf(dbch, db_tr, idb); 1445 if(STAILQ_NEXT(db_tr, link) == NULL){ 1446 break; 1447 } 1448 db = db_tr->db; 1449 ldesc = db_tr->dbcnt - 1; 1450 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1451 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1452 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1453 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1454 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1455 FWOHCI_DMA_SET( 1456 db[ldesc].db.desc.cmd, 1457 OHCI_INTERRUPT_ALWAYS); 1458 /* OHCI 1.1 and above */ 1459 FWOHCI_DMA_SET( 1460 db[0].db.desc.cmd, 1461 OHCI_INTERRUPT_ALWAYS); 1462 } 1463 } 1464 db_tr = STAILQ_NEXT(db_tr, link); 1465 } 1466 FWOHCI_DMA_CLEAR( 1467 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1468 return err; 1469 } 1470 1471 static int 1472 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1473 { 1474 int err = 0; 1475 int idb, z, i, dmach = 0, ldesc; 1476 uint32_t off = 0; 1477 struct fwohcidb_tr *db_tr; 1478 struct fwohcidb *db; 1479 1480 z = dbch->ndesc; 1481 if(&sc->arrq == dbch){ 1482 off = OHCI_ARQOFF; 1483 }else if(&sc->arrs == dbch){ 1484 off = OHCI_ARSOFF; 1485 }else{ 1486 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1487 if( &sc->ir[dmach] == dbch){ 1488 off = OHCI_IROFF(dmach); 1489 break; 1490 } 1491 } 1492 } 1493 if(off == 0){ 1494 err = EINVAL; 1495 return err; 1496 } 1497 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1498 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1499 return err; 1500 }else{ 1501 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1502 err = EBUSY; 1503 return err; 1504 } 1505 } 1506 dbch->xferq.flag |= FWXFERQ_RUNNING; 1507 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1508 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1509 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1510 } 1511 db_tr = dbch->top; 1512 for (idb = 0; idb < dbch->ndb; idb ++) { 1513 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1514 if (STAILQ_NEXT(db_tr, link) == NULL) 1515 break; 1516 db = db_tr->db; 1517 ldesc = db_tr->dbcnt - 1; 1518 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1519 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1520 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1521 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1522 FWOHCI_DMA_SET( 1523 db[ldesc].db.desc.cmd, 1524 OHCI_INTERRUPT_ALWAYS); 1525 FWOHCI_DMA_CLEAR( 1526 db[ldesc].db.desc.depend, 1527 0xf); 1528 } 1529 } 1530 db_tr = STAILQ_NEXT(db_tr, link); 1531 } 1532 FWOHCI_DMA_CLEAR( 1533 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1534 dbch->buf_offset = 0; 1535 fwdma_sync_multiseg_all(dbch->am, 1536 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1537 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1538 return err; 1539 }else{ 1540 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1541 } 1542 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1543 return err; 1544 } 1545 1546 static int 1547 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1548 { 1549 int sec, cycle, cycle_match; 1550 1551 cycle = cycle_now & 0x1fff; 1552 sec = cycle_now >> 13; 1553 #define CYCLE_MOD 0x10 1554 #if 1 1555 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1556 #else 1557 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1558 #endif 1559 cycle = cycle + CYCLE_DELAY; 1560 if (cycle >= 8000) { 1561 sec ++; 1562 cycle -= 8000; 1563 } 1564 cycle = roundup2(cycle, CYCLE_MOD); 1565 if (cycle >= 8000) { 1566 sec ++; 1567 if (cycle == 8000) 1568 cycle = 0; 1569 else 1570 cycle = CYCLE_MOD; 1571 } 1572 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1573 1574 return(cycle_match); 1575 } 1576 1577 static int 1578 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1579 { 1580 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1581 int err = 0; 1582 unsigned short tag, ich; 1583 struct fwohci_dbch *dbch; 1584 int cycle_match, cycle_now, s, ldesc; 1585 uint32_t stat; 1586 struct fw_bulkxfer *first, *chunk, *prev; 1587 struct fw_xferq *it; 1588 1589 dbch = &sc->it[dmach]; 1590 it = &dbch->xferq; 1591 1592 tag = (it->flag >> 6) & 3; 1593 ich = it->flag & 0x3f; 1594 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1595 dbch->ndb = it->bnpacket * it->bnchunk; 1596 dbch->ndesc = 3; 1597 fwohci_db_init(sc, dbch); 1598 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1599 return ENOMEM; 1600 err = fwohci_tx_enable(sc, dbch); 1601 } 1602 if(err) 1603 return err; 1604 1605 ldesc = dbch->ndesc - 1; 1606 s = splfw(); 1607 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1608 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1609 struct fwohcidb *db; 1610 1611 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1612 BUS_DMASYNC_PREWRITE); 1613 fwohci_txbufdb(sc, dmach, chunk); 1614 if (prev != NULL) { 1615 db = ((struct fwohcidb_tr *)(prev->end))->db; 1616 #if 0 /* XXX necessary? */ 1617 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1618 OHCI_BRANCH_ALWAYS); 1619 #endif 1620 #if 0 /* if bulkxfer->npacket changes */ 1621 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1622 ((struct fwohcidb_tr *) 1623 (chunk->start))->bus_addr | dbch->ndesc; 1624 #else 1625 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1626 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1627 #endif 1628 } 1629 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1630 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1631 prev = chunk; 1632 } 1633 fwdma_sync_multiseg_all(dbch->am, 1634 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1635 splx(s); 1636 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1637 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1638 printf("stat 0x%x\n", stat); 1639 1640 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1641 return 0; 1642 1643 #if 0 1644 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1645 #endif 1646 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1647 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1648 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1649 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1650 1651 first = STAILQ_FIRST(&it->stdma); 1652 OWRITE(sc, OHCI_ITCMD(dmach), 1653 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1654 if (firewire_debug > 1) { 1655 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1656 #if 1 1657 dump_dma(sc, ITX_CH + dmach); 1658 #endif 1659 } 1660 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1661 #if 1 1662 /* Don't start until all chunks are buffered */ 1663 if (STAILQ_FIRST(&it->stfree) != NULL) 1664 goto out; 1665 #endif 1666 #if 1 1667 /* Clear cycle match counter bits */ 1668 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1669 1670 /* 2bit second + 13bit cycle */ 1671 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1672 cycle_match = fwohci_next_cycle(fc, cycle_now); 1673 1674 OWRITE(sc, OHCI_ITCTL(dmach), 1675 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1676 | OHCI_CNTL_DMA_RUN); 1677 #else 1678 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1679 #endif 1680 if (firewire_debug > 1) { 1681 printf("cycle_match: 0x%04x->0x%04x\n", 1682 cycle_now, cycle_match); 1683 dump_dma(sc, ITX_CH + dmach); 1684 dump_db(sc, ITX_CH + dmach); 1685 } 1686 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1687 device_printf(sc->fc.dev, 1688 "IT DMA underrun (0x%08x)\n", stat); 1689 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1690 } 1691 out: 1692 return err; 1693 } 1694 1695 static int 1696 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1697 { 1698 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1699 int err = 0, s, ldesc; 1700 unsigned short tag, ich; 1701 uint32_t stat; 1702 struct fwohci_dbch *dbch; 1703 struct fwohcidb_tr *db_tr; 1704 struct fw_bulkxfer *first, *prev, *chunk; 1705 struct fw_xferq *ir; 1706 1707 dbch = &sc->ir[dmach]; 1708 ir = &dbch->xferq; 1709 1710 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1711 tag = (ir->flag >> 6) & 3; 1712 ich = ir->flag & 0x3f; 1713 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1714 1715 ir->queued = 0; 1716 dbch->ndb = ir->bnpacket * ir->bnchunk; 1717 dbch->ndesc = 2; 1718 fwohci_db_init(sc, dbch); 1719 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1720 return ENOMEM; 1721 err = fwohci_rx_enable(sc, dbch); 1722 } 1723 if(err) 1724 return err; 1725 1726 first = STAILQ_FIRST(&ir->stfree); 1727 if (first == NULL) { 1728 device_printf(fc->dev, "IR DMA no free chunk\n"); 1729 return 0; 1730 } 1731 1732 ldesc = dbch->ndesc - 1; 1733 s = splfw(); 1734 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1735 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1736 struct fwohcidb *db; 1737 1738 #if 1 /* XXX for if_fwe */ 1739 if (chunk->mbuf != NULL) { 1740 db_tr = (struct fwohcidb_tr *)(chunk->start); 1741 db_tr->dbcnt = 1; 1742 err = fw_bus_dmamap_load_mbuf( 1743 dbch->dmat, db_tr->dma_map, 1744 chunk->mbuf, fwohci_execute_db2, db_tr, 1745 BUS_DMA_WAITOK); 1746 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1747 OHCI_UPDATE | OHCI_INPUT_LAST | 1748 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1749 } 1750 #endif 1751 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1752 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1753 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1754 if (prev != NULL) { 1755 db = ((struct fwohcidb_tr *)(prev->end))->db; 1756 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1757 } 1758 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1759 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1760 prev = chunk; 1761 } 1762 fwdma_sync_multiseg_all(dbch->am, 1763 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1764 splx(s); 1765 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1766 if (stat & OHCI_CNTL_DMA_ACTIVE) 1767 return 0; 1768 if (stat & OHCI_CNTL_DMA_RUN) { 1769 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1770 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1771 } 1772 1773 if (firewire_debug) 1774 printf("start IR DMA 0x%x\n", stat); 1775 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1776 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1777 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1778 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1779 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1780 OWRITE(sc, OHCI_IRCMD(dmach), 1781 ((struct fwohcidb_tr *)(first->start))->bus_addr 1782 | dbch->ndesc); 1783 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1784 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1785 #if 0 1786 dump_db(sc, IRX_CH + dmach); 1787 #endif 1788 return err; 1789 } 1790 1791 FWOHCI_STOP() 1792 { 1793 FWOHCI_STOP_START; 1794 u_int i; 1795 1796 /* Now stopping all DMA channel */ 1797 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1798 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1799 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1800 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1801 1802 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1803 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1804 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1805 } 1806 1807 /* FLUSH FIFO and reset Transmitter/Reciever */ 1808 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1809 1810 /* Stop interrupt */ 1811 OWRITE(sc, FWOHCI_INTMASKCLR, 1812 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1813 | OHCI_INT_PHY_INT 1814 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1815 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1816 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1817 | OHCI_INT_PHY_BUS_R); 1818 1819 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1820 fw_drain_txq(&sc->fc); 1821 1822 /* XXX Link down? Bus reset? */ 1823 FWOHCI_STOP_RETURN(0); 1824 } 1825 1826 #if defined(__NetBSD__) 1827 static void 1828 fwohci_power(int why, void *arg) 1829 { 1830 struct fwohci_softc *sc = arg; 1831 int s; 1832 1833 s = splbio(); 1834 switch (why) { 1835 case PWR_SUSPEND: 1836 case PWR_STANDBY: 1837 fwohci_stop(arg); 1838 break; 1839 case PWR_RESUME: 1840 fwohci_resume(sc, sc->fc.dev); 1841 break; 1842 case PWR_SOFTSUSPEND: 1843 case PWR_SOFTSTANDBY: 1844 case PWR_SOFTRESUME: 1845 break; 1846 } 1847 splx(s); 1848 } 1849 #endif 1850 1851 int 1852 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1853 { 1854 int i; 1855 struct fw_xferq *ir; 1856 struct fw_bulkxfer *chunk; 1857 1858 fwohci_reset(sc, dev); 1859 /* XXX resume isochronous receive automatically. (how about TX?) */ 1860 for(i = 0; i < sc->fc.nisodma; i ++) { 1861 ir = &sc->ir[i].xferq; 1862 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1863 device_printf(sc->fc.dev, 1864 "resume iso receive ch: %d\n", i); 1865 ir->flag &= ~FWXFERQ_RUNNING; 1866 /* requeue stdma to stfree */ 1867 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1868 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1869 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1870 } 1871 sc->fc.irx_enable(&sc->fc, i); 1872 } 1873 } 1874 1875 #if defined(__FreeBSD__) 1876 bus_generic_resume(dev); 1877 #endif 1878 sc->fc.ibr(&sc->fc); 1879 return 0; 1880 } 1881 1882 #define ACK_ALL 1883 static void 1884 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1885 { 1886 uint32_t irstat, itstat; 1887 u_int i; 1888 struct firewire_comm *fc = (struct firewire_comm *)sc; 1889 1890 CTR0(KTR_DEV, "fwohci_intr_body"); 1891 #ifdef OHCI_DEBUG 1892 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1893 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1894 stat & OHCI_INT_EN ? "DMA_EN ":"", 1895 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1896 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1897 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1898 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1899 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1900 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1901 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1902 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1903 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1904 stat & OHCI_INT_PHY_SID ? "SID ":"", 1905 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1906 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1907 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1908 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1909 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1910 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1911 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1912 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1913 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1914 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1915 stat, OREAD(sc, FWOHCI_INTMASK) 1916 ); 1917 #endif 1918 /* Bus reset */ 1919 if(stat & OHCI_INT_PHY_BUS_R ){ 1920 if (fc->status == FWBUSRESET) 1921 goto busresetout; 1922 /* Disable bus reset interrupt until sid recv. */ 1923 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1924 1925 device_printf(fc->dev, "BUS reset\n"); 1926 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1927 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1928 1929 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1930 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1931 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1932 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1933 1934 #ifndef ACK_ALL 1935 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1936 #endif 1937 fw_busreset(fc); 1938 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1939 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1940 } 1941 busresetout: 1942 if((stat & OHCI_INT_DMA_IR )){ 1943 #ifndef ACK_ALL 1944 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1945 #endif 1946 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1947 irstat = sc->irstat; 1948 sc->irstat = 0; 1949 #else 1950 irstat = atomic_readandclear_int(&sc->irstat); 1951 #endif 1952 for(i = 0; i < fc->nisodma ; i++){ 1953 struct fwohci_dbch *dbch; 1954 1955 if((irstat & (1 << i)) != 0){ 1956 dbch = &sc->ir[i]; 1957 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1958 device_printf(sc->fc.dev, 1959 "dma(%d) not active\n", i); 1960 continue; 1961 } 1962 fwohci_rbuf_update(sc, i); 1963 } 1964 } 1965 } 1966 if((stat & OHCI_INT_DMA_IT )){ 1967 #ifndef ACK_ALL 1968 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1969 #endif 1970 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1971 itstat = sc->itstat; 1972 sc->itstat = 0; 1973 #else 1974 itstat = atomic_readandclear_int(&sc->itstat); 1975 #endif 1976 for(i = 0; i < fc->nisodma ; i++){ 1977 if((itstat & (1 << i)) != 0){ 1978 fwohci_tbuf_update(sc, i); 1979 } 1980 } 1981 } 1982 if((stat & OHCI_INT_DMA_PRRS )){ 1983 #ifndef ACK_ALL 1984 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1985 #endif 1986 #if 0 1987 dump_dma(sc, ARRS_CH); 1988 dump_db(sc, ARRS_CH); 1989 #endif 1990 fwohci_arcv(sc, &sc->arrs, count); 1991 } 1992 if((stat & OHCI_INT_DMA_PRRQ )){ 1993 #ifndef ACK_ALL 1994 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1995 #endif 1996 #if 0 1997 dump_dma(sc, ARRQ_CH); 1998 dump_db(sc, ARRQ_CH); 1999 #endif 2000 fwohci_arcv(sc, &sc->arrq, count); 2001 } 2002 if (stat & OHCI_INT_CYC_LOST) { 2003 if (sc->cycle_lost >= 0) 2004 sc->cycle_lost ++; 2005 if (sc->cycle_lost > 10) { 2006 sc->cycle_lost = -1; 2007 #if 0 2008 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2009 #endif 2010 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2011 device_printf(fc->dev, "too many cycle lost, " 2012 "no cycle master presents?\n"); 2013 } 2014 } 2015 if(stat & OHCI_INT_PHY_SID){ 2016 uint32_t *buf, node_id; 2017 int plen; 2018 2019 #ifndef ACK_ALL 2020 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2021 #endif 2022 /* Enable bus reset interrupt */ 2023 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2024 /* Allow async. request to us */ 2025 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2026 /* XXX insecure ?? */ 2027 /* allow from all nodes */ 2028 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2029 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2030 /* 0 to 4GB regison */ 2031 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2032 /* Set ATRetries register */ 2033 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2034 /* 2035 ** Checking whether the node is root or not. If root, turn on 2036 ** cycle master. 2037 */ 2038 node_id = OREAD(sc, FWOHCI_NODEID); 2039 plen = OREAD(sc, OHCI_SID_CNT); 2040 2041 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2042 node_id, (plen >> 16) & 0xff); 2043 if (!(node_id & OHCI_NODE_VALID)) { 2044 printf("Bus reset failure\n"); 2045 goto sidout; 2046 } 2047 2048 /* cycle timer */ 2049 sc->cycle_lost = 0; 2050 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2051 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2052 printf("CYCLEMASTER mode\n"); 2053 OWRITE(sc, OHCI_LNKCTL, 2054 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2055 } else { 2056 printf("non CYCLEMASTER mode\n"); 2057 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2058 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2059 } 2060 2061 fc->nodeid = node_id & 0x3f; 2062 2063 if (plen & OHCI_SID_ERR) { 2064 device_printf(fc->dev, "SID Error\n"); 2065 goto sidout; 2066 } 2067 plen &= OHCI_SID_CNT_MASK; 2068 if (plen < 4 || plen > OHCI_SIDSIZE) { 2069 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2070 goto sidout; 2071 } 2072 plen -= 4; /* chop control info */ 2073 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2074 if (buf == NULL) { 2075 device_printf(fc->dev, "malloc failed\n"); 2076 goto sidout; 2077 } 2078 for (i = 0; i < plen / 4; i ++) 2079 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2080 #if defined(__NetBSD__) && defined(macppc) 2081 /* XXX required as bootdisk for macppc. */ 2082 delay(500000); 2083 #endif 2084 #if 1 /* XXX needed?? */ 2085 /* pending all pre-bus_reset packets */ 2086 fwohci_txd(sc, &sc->atrq); 2087 fwohci_txd(sc, &sc->atrs); 2088 fwohci_arcv(sc, &sc->arrs, -1); 2089 fwohci_arcv(sc, &sc->arrq, -1); 2090 fw_drain_txq(fc); 2091 #endif 2092 fw_sidrcv(fc, buf, plen); 2093 free(buf, M_FW); 2094 } 2095 sidout: 2096 if((stat & OHCI_INT_DMA_ATRQ )){ 2097 #ifndef ACK_ALL 2098 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2099 #endif 2100 fwohci_txd(sc, &(sc->atrq)); 2101 } 2102 if((stat & OHCI_INT_DMA_ATRS )){ 2103 #ifndef ACK_ALL 2104 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2105 #endif 2106 fwohci_txd(sc, &(sc->atrs)); 2107 } 2108 if((stat & OHCI_INT_PW_ERR )){ 2109 #ifndef ACK_ALL 2110 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2111 #endif 2112 device_printf(fc->dev, "posted write error\n"); 2113 } 2114 if((stat & OHCI_INT_ERR )){ 2115 #ifndef ACK_ALL 2116 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2117 #endif 2118 device_printf(fc->dev, "unrecoverable error\n"); 2119 } 2120 if((stat & OHCI_INT_PHY_INT)) { 2121 #ifndef ACK_ALL 2122 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2123 #endif 2124 device_printf(fc->dev, "phy int\n"); 2125 } 2126 2127 CTR0(KTR_DEV, "fwohci_intr_body done"); 2128 return; 2129 } 2130 2131 #if FWOHCI_TASKQUEUE 2132 static void 2133 fwohci_complete(void *arg, int pending) 2134 { 2135 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2136 uint32_t stat; 2137 2138 again: 2139 stat = atomic_readandclear_int(&sc->intstat); 2140 if (stat) { 2141 FW_LOCK; 2142 fwohci_intr_body(sc, stat, -1); 2143 FW_UNLOCK; 2144 } else 2145 return; 2146 goto again; 2147 } 2148 #endif 2149 2150 static uint32_t 2151 fwochi_check_stat(struct fwohci_softc *sc) 2152 { 2153 uint32_t stat, irstat, itstat; 2154 2155 stat = OREAD(sc, FWOHCI_INTSTAT); 2156 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2157 if (stat == 0xffffffff) { 2158 device_printf(sc->fc.dev, 2159 "device physically ejected?\n"); 2160 return(stat); 2161 } 2162 #ifdef ACK_ALL 2163 if (stat) 2164 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2165 #endif 2166 if (stat & OHCI_INT_DMA_IR) { 2167 irstat = OREAD(sc, OHCI_IR_STAT); 2168 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2169 atomic_set_int(&sc->irstat, irstat); 2170 } 2171 if (stat & OHCI_INT_DMA_IT) { 2172 itstat = OREAD(sc, OHCI_IT_STAT); 2173 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2174 atomic_set_int(&sc->itstat, itstat); 2175 } 2176 return(stat); 2177 } 2178 2179 FW_INTR(fwohci) 2180 { 2181 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2182 uint32_t stat; 2183 #if !FWOHCI_TASKQUEUE 2184 uint32_t bus_reset = 0; 2185 #endif 2186 2187 if (!(sc->intmask & OHCI_INT_EN)) { 2188 /* polling mode */ 2189 FW_INTR_RETURN(0); 2190 } 2191 2192 #if !FWOHCI_TASKQUEUE 2193 again: 2194 #endif 2195 CTR0(KTR_DEV, "fwohci_intr"); 2196 stat = fwochi_check_stat(sc); 2197 if (stat == 0 || stat == 0xffffffff) 2198 FW_INTR_RETURN(1); 2199 #if FWOHCI_TASKQUEUE 2200 atomic_set_int(&sc->intstat, stat); 2201 /* XXX mask bus reset intr. during bus reset phase */ 2202 if (stat) 2203 #if 1 2204 taskqueue_enqueue_fast(taskqueue_fast, 2205 &sc->fwohci_task_complete); 2206 #else 2207 taskqueue_enqueue(taskqueue_swi, 2208 &sc->fwohci_task_complete); 2209 #endif 2210 #else 2211 /* We cannot clear bus reset event during bus reset phase */ 2212 if ((stat & ~bus_reset) == 0) 2213 FW_INTR_RETURN(1); 2214 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2215 fwohci_intr_body(sc, stat, -1); 2216 goto again; 2217 #endif 2218 CTR0(KTR_DEV, "fwohci_intr end"); 2219 } 2220 2221 void 2222 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2223 { 2224 int s; 2225 uint32_t stat; 2226 struct fwohci_softc *sc; 2227 2228 2229 sc = (struct fwohci_softc *)fc; 2230 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2231 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2232 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2233 #if 0 2234 if (!quick) { 2235 #else 2236 if (1) { 2237 #endif 2238 stat = fwochi_check_stat(sc); 2239 if (stat == 0 || stat == 0xffffffff) 2240 return; 2241 } 2242 s = splfw(); 2243 fwohci_intr_body(sc, stat, count); 2244 splx(s); 2245 } 2246 2247 static void 2248 fwohci_set_intr(struct firewire_comm *fc, int enable) 2249 { 2250 struct fwohci_softc *sc; 2251 2252 sc = (struct fwohci_softc *)fc; 2253 if (firewire_debug) 2254 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2255 if (enable) { 2256 sc->intmask |= OHCI_INT_EN; 2257 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2258 } else { 2259 sc->intmask &= ~OHCI_INT_EN; 2260 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2261 } 2262 } 2263 2264 static void 2265 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2266 { 2267 struct firewire_comm *fc = &sc->fc; 2268 struct fwohcidb *db; 2269 struct fw_bulkxfer *chunk; 2270 struct fw_xferq *it; 2271 uint32_t stat, count; 2272 int s, w=0, ldesc; 2273 2274 it = fc->it[dmach]; 2275 ldesc = sc->it[dmach].ndesc - 1; 2276 s = splfw(); /* unnecessary ? */ 2277 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2278 if (firewire_debug) 2279 dump_db(sc, ITX_CH + dmach); 2280 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2281 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2282 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2283 >> OHCI_STATUS_SHIFT; 2284 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2285 /* timestamp */ 2286 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2287 & OHCI_COUNT_MASK; 2288 if (stat == 0) 2289 break; 2290 STAILQ_REMOVE_HEAD(&it->stdma, link); 2291 switch (stat & FWOHCIEV_MASK){ 2292 case FWOHCIEV_ACKCOMPL: 2293 #if 0 2294 device_printf(fc->dev, "0x%08x\n", count); 2295 #endif 2296 break; 2297 default: 2298 device_printf(fc->dev, 2299 "Isochronous transmit err %02x(%s)\n", 2300 stat, fwohcicode[stat & 0x1f]); 2301 } 2302 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2303 w++; 2304 } 2305 splx(s); 2306 if (w) 2307 wakeup(it); 2308 } 2309 2310 static void 2311 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2312 { 2313 struct firewire_comm *fc = &sc->fc; 2314 struct fwohcidb_tr *db_tr; 2315 struct fw_bulkxfer *chunk; 2316 struct fw_xferq *ir; 2317 uint32_t stat; 2318 int s, w=0, ldesc; 2319 2320 ir = fc->ir[dmach]; 2321 ldesc = sc->ir[dmach].ndesc - 1; 2322 #if 0 2323 dump_db(sc, dmach); 2324 #endif 2325 s = splfw(); 2326 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2327 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2328 db_tr = (struct fwohcidb_tr *)chunk->end; 2329 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2330 >> OHCI_STATUS_SHIFT; 2331 if (stat == 0) 2332 break; 2333 2334 if (chunk->mbuf != NULL) { 2335 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2336 BUS_DMASYNC_POSTREAD); 2337 fw_bus_dmamap_unload( 2338 sc->ir[dmach].dmat, db_tr->dma_map); 2339 } else if (ir->buf != NULL) { 2340 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2341 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2342 } else { 2343 /* XXX */ 2344 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2345 } 2346 2347 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2348 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2349 switch (stat & FWOHCIEV_MASK) { 2350 case FWOHCIEV_ACKCOMPL: 2351 chunk->resp = 0; 2352 break; 2353 default: 2354 chunk->resp = EINVAL; 2355 device_printf(fc->dev, 2356 "Isochronous receive err %02x(%s)\n", 2357 stat, fwohcicode[stat & 0x1f]); 2358 } 2359 w++; 2360 } 2361 splx(s); 2362 if (w) { 2363 if (ir->flag & FWXFERQ_HANDLER) 2364 ir->hand(ir); 2365 else 2366 wakeup(ir); 2367 } 2368 } 2369 2370 void 2371 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2372 { 2373 uint32_t off, cntl, stat, cmd, match; 2374 2375 if(ch == 0){ 2376 off = OHCI_ATQOFF; 2377 }else if(ch == 1){ 2378 off = OHCI_ATSOFF; 2379 }else if(ch == 2){ 2380 off = OHCI_ARQOFF; 2381 }else if(ch == 3){ 2382 off = OHCI_ARSOFF; 2383 }else if(ch < IRX_CH){ 2384 off = OHCI_ITCTL(ch - ITX_CH); 2385 }else{ 2386 off = OHCI_IRCTL(ch - IRX_CH); 2387 } 2388 cntl = stat = OREAD(sc, off); 2389 cmd = OREAD(sc, off + 0xc); 2390 match = OREAD(sc, off + 0x10); 2391 2392 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2393 ch, 2394 cntl, 2395 cmd, 2396 match); 2397 stat &= 0xffff ; 2398 if (stat) { 2399 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2400 ch, 2401 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2402 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2403 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2404 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2405 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2406 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2407 fwohcicode[stat & 0x1f], 2408 stat & 0x1f 2409 ); 2410 }else{ 2411 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2412 } 2413 } 2414 2415 void 2416 dump_db(struct fwohci_softc *sc, uint32_t ch) 2417 { 2418 struct fwohci_dbch *dbch; 2419 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2420 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2421 int idb, jdb; 2422 uint32_t cmd, off; 2423 if(ch == 0){ 2424 off = OHCI_ATQOFF; 2425 dbch = &sc->atrq; 2426 }else if(ch == 1){ 2427 off = OHCI_ATSOFF; 2428 dbch = &sc->atrs; 2429 }else if(ch == 2){ 2430 off = OHCI_ARQOFF; 2431 dbch = &sc->arrq; 2432 }else if(ch == 3){ 2433 off = OHCI_ARSOFF; 2434 dbch = &sc->arrs; 2435 }else if(ch < IRX_CH){ 2436 off = OHCI_ITCTL(ch - ITX_CH); 2437 dbch = &sc->it[ch - ITX_CH]; 2438 }else { 2439 off = OHCI_IRCTL(ch - IRX_CH); 2440 dbch = &sc->ir[ch - IRX_CH]; 2441 } 2442 cmd = OREAD(sc, off + 0xc); 2443 2444 if( dbch->ndb == 0 ){ 2445 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2446 return; 2447 } 2448 pp = dbch->top; 2449 prev = pp->db; 2450 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2451 cp = STAILQ_NEXT(pp, link); 2452 if(cp == NULL){ 2453 curr = NULL; 2454 goto outdb; 2455 } 2456 np = STAILQ_NEXT(cp, link); 2457 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2458 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2459 curr = cp->db; 2460 if(np != NULL){ 2461 next = np->db; 2462 }else{ 2463 next = NULL; 2464 } 2465 goto outdb; 2466 } 2467 } 2468 pp = STAILQ_NEXT(pp, link); 2469 if(pp == NULL){ 2470 curr = NULL; 2471 goto outdb; 2472 } 2473 prev = pp->db; 2474 } 2475 outdb: 2476 if( curr != NULL){ 2477 #if 0 2478 printf("Prev DB %d\n", ch); 2479 print_db(pp, prev, ch, dbch->ndesc); 2480 #endif 2481 printf("Current DB %d\n", ch); 2482 print_db(cp, curr, ch, dbch->ndesc); 2483 #if 0 2484 printf("Next DB %d\n", ch); 2485 print_db(np, next, ch, dbch->ndesc); 2486 #endif 2487 }else{ 2488 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2489 } 2490 return; 2491 } 2492 2493 void 2494 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2495 uint32_t ch, uint32_t hogemax) 2496 { 2497 fwohcireg_t stat; 2498 int i, key; 2499 uint32_t cmd, res; 2500 2501 if(db == NULL){ 2502 printf("No Descriptor is found\n"); 2503 return; 2504 } 2505 2506 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2507 ch, 2508 "Current", 2509 "OP ", 2510 "KEY", 2511 "INT", 2512 "BR ", 2513 "len", 2514 "Addr", 2515 "Depend", 2516 "Stat", 2517 "Cnt"); 2518 for( i = 0 ; i <= hogemax ; i ++){ 2519 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2520 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2521 key = cmd & OHCI_KEY_MASK; 2522 stat = res >> OHCI_STATUS_SHIFT; 2523 #if defined(__DragonFly__) || \ 2524 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2525 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2526 db_tr->bus_addr, 2527 #else 2528 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2529 (uintmax_t)db_tr->bus_addr, 2530 #endif 2531 dbcode[(cmd >> 28) & 0xf], 2532 dbkey[(cmd >> 24) & 0x7], 2533 dbcond[(cmd >> 20) & 0x3], 2534 dbcond[(cmd >> 18) & 0x3], 2535 cmd & OHCI_COUNT_MASK, 2536 FWOHCI_DMA_READ(db[i].db.desc.addr), 2537 FWOHCI_DMA_READ(db[i].db.desc.depend), 2538 stat, 2539 res & OHCI_COUNT_MASK); 2540 if(stat & 0xff00){ 2541 printf(" %s%s%s%s%s%s %s(%x)\n", 2542 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2543 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2544 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2545 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2546 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2547 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2548 fwohcicode[stat & 0x1f], 2549 stat & 0x1f 2550 ); 2551 }else{ 2552 printf(" Nostat\n"); 2553 } 2554 if(key == OHCI_KEY_ST2 ){ 2555 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2556 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2557 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2558 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2559 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2560 } 2561 if(key == OHCI_KEY_DEVICE){ 2562 return; 2563 } 2564 if((cmd & OHCI_BRANCH_MASK) 2565 == OHCI_BRANCH_ALWAYS){ 2566 return; 2567 } 2568 if((cmd & OHCI_CMD_MASK) 2569 == OHCI_OUTPUT_LAST){ 2570 return; 2571 } 2572 if((cmd & OHCI_CMD_MASK) 2573 == OHCI_INPUT_LAST){ 2574 return; 2575 } 2576 if(key == OHCI_KEY_ST2 ){ 2577 i++; 2578 } 2579 } 2580 return; 2581 } 2582 2583 void 2584 fwohci_ibr(struct firewire_comm *fc) 2585 { 2586 struct fwohci_softc *sc; 2587 uint32_t fun; 2588 2589 device_printf(fc->dev, "Initiate bus reset\n"); 2590 sc = (struct fwohci_softc *)fc; 2591 2592 /* 2593 * Make sure our cached values from the config rom are 2594 * initialised. 2595 */ 2596 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2597 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2598 2599 /* 2600 * Set root hold-off bit so that non cyclemaster capable node 2601 * shouldn't became the root node. 2602 */ 2603 #if 1 2604 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2605 fun |= FW_PHY_IBR | FW_PHY_RHB; 2606 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2607 #else /* Short bus reset */ 2608 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2609 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2610 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2611 #endif 2612 } 2613 2614 void 2615 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2616 { 2617 struct fwohcidb_tr *db_tr, *fdb_tr; 2618 struct fwohci_dbch *dbch; 2619 struct fwohcidb *db; 2620 struct fw_pkt *fp; 2621 struct fwohci_txpkthdr *ohcifp; 2622 unsigned short chtag; 2623 int idb; 2624 2625 dbch = &sc->it[dmach]; 2626 chtag = sc->it[dmach].xferq.flag & 0xff; 2627 2628 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2629 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2630 /* 2631 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2632 */ 2633 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2634 db = db_tr->db; 2635 fp = (struct fw_pkt *)db_tr->buf; 2636 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2637 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2638 ohcifp->mode.common.spd = 0 & 0x7; 2639 ohcifp->mode.stream.len = fp->mode.stream.len; 2640 ohcifp->mode.stream.chtag = chtag; 2641 ohcifp->mode.stream.tcode = 0xa; 2642 #if BYTE_ORDER == BIG_ENDIAN 2643 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2644 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2645 #endif 2646 2647 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2648 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2649 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2650 #if 0 /* if bulkxfer->npackets changes */ 2651 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2652 | OHCI_UPDATE 2653 | OHCI_BRANCH_ALWAYS; 2654 db[0].db.desc.depend = 2655 = db[dbch->ndesc - 1].db.desc.depend 2656 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2657 #else 2658 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2659 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2660 #endif 2661 bulkxfer->end = (caddr_t)db_tr; 2662 db_tr = STAILQ_NEXT(db_tr, link); 2663 } 2664 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2665 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2666 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2667 #if 0 /* if bulkxfer->npackets changes */ 2668 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2669 /* OHCI 1.1 and above */ 2670 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2671 #endif 2672 /* 2673 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2674 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2675 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2676 */ 2677 return; 2678 } 2679 2680 static int 2681 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2682 int poffset) 2683 { 2684 struct fwohcidb *db = db_tr->db; 2685 struct fw_xferq *it; 2686 int err = 0; 2687 2688 it = &dbch->xferq; 2689 if(it->buf == 0){ 2690 err = EINVAL; 2691 return err; 2692 } 2693 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2694 db_tr->dbcnt = 3; 2695 2696 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2697 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2698 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2699 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2700 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2701 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2702 2703 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2704 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2705 #if 1 2706 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2707 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2708 #endif 2709 return 0; 2710 } 2711 2712 int 2713 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2714 int poffset, struct fwdma_alloc *dummy_dma) 2715 { 2716 struct fwohcidb *db = db_tr->db; 2717 struct fw_xferq *ir; 2718 int i, ldesc; 2719 bus_addr_t dbuf[2]; 2720 int dsiz[2]; 2721 2722 ir = &dbch->xferq; 2723 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2724 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2725 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2726 if (db_tr->buf == NULL) 2727 return(ENOMEM); 2728 db_tr->dbcnt = 1; 2729 dsiz[0] = ir->psize; 2730 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2731 BUS_DMASYNC_PREREAD); 2732 } else { 2733 db_tr->dbcnt = 0; 2734 if (dummy_dma != NULL) { 2735 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2736 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2737 } 2738 dsiz[db_tr->dbcnt] = ir->psize; 2739 if (ir->buf != NULL) { 2740 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2741 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2742 } 2743 db_tr->dbcnt++; 2744 } 2745 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2746 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2747 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2748 if (ir->flag & FWXFERQ_STREAM) { 2749 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2750 } 2751 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2752 } 2753 ldesc = db_tr->dbcnt - 1; 2754 if (ir->flag & FWXFERQ_STREAM) { 2755 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2756 } 2757 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2758 return 0; 2759 } 2760 2761 2762 static int 2763 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2764 { 2765 struct fw_pkt *fp0; 2766 uint32_t ld0; 2767 int slen, hlen; 2768 #if BYTE_ORDER == BIG_ENDIAN 2769 int i; 2770 #endif 2771 2772 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2773 #if 0 2774 printf("ld0: x%08x\n", ld0); 2775 #endif 2776 fp0 = (struct fw_pkt *)&ld0; 2777 /* determine length to swap */ 2778 switch (fp0->mode.common.tcode) { 2779 case FWTCODE_WRES: 2780 CTR0(KTR_DEV, "WRES"); 2781 case FWTCODE_RREQQ: 2782 case FWTCODE_WREQQ: 2783 case FWTCODE_RRESQ: 2784 case FWOHCITCODE_PHY: 2785 slen = 12; 2786 break; 2787 case FWTCODE_RREQB: 2788 case FWTCODE_WREQB: 2789 case FWTCODE_LREQ: 2790 case FWTCODE_RRESB: 2791 case FWTCODE_LRES: 2792 slen = 16; 2793 break; 2794 default: 2795 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2796 return(0); 2797 } 2798 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2799 if (hlen > len) { 2800 if (firewire_debug) 2801 printf("splitted header\n"); 2802 return(-hlen); 2803 } 2804 #if BYTE_ORDER == BIG_ENDIAN 2805 for(i = 0; i < slen/4; i ++) 2806 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2807 #endif 2808 return(hlen); 2809 } 2810 2811 static int 2812 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2813 { 2814 struct tcode_info *info; 2815 int r; 2816 2817 info = &tinfo[fp->mode.common.tcode]; 2818 r = info->hdr_len + sizeof(uint32_t); 2819 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2820 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2821 2822 if (r == sizeof(uint32_t)) { 2823 /* XXX */ 2824 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2825 fp->mode.common.tcode); 2826 return (-1); 2827 } 2828 2829 if (r > dbch->xferq.psize) { 2830 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2831 return (-1); 2832 /* panic ? */ 2833 } 2834 2835 return r; 2836 } 2837 2838 static void 2839 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2840 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2841 { 2842 struct fwohcidb *db = &db_tr->db[0]; 2843 2844 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2845 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2846 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2847 fwdma_sync_multiseg_all(dbch->am, 2848 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2849 dbch->bottom = db_tr; 2850 2851 if (wake) 2852 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2853 } 2854 2855 static void 2856 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2857 { 2858 struct fwohcidb_tr *db_tr; 2859 struct iovec vec[2]; 2860 struct fw_pkt pktbuf; 2861 int nvec; 2862 struct fw_pkt *fp; 2863 uint8_t *ld; 2864 uint32_t stat, off, status, event; 2865 u_int spd; 2866 int len, plen, hlen, pcnt, offset; 2867 int s; 2868 caddr_t buf; 2869 int resCount; 2870 2871 CTR0(KTR_DEV, "fwohci_arv"); 2872 2873 if(&sc->arrq == dbch){ 2874 off = OHCI_ARQOFF; 2875 }else if(&sc->arrs == dbch){ 2876 off = OHCI_ARSOFF; 2877 }else{ 2878 return; 2879 } 2880 2881 s = splfw(); 2882 db_tr = dbch->top; 2883 pcnt = 0; 2884 /* XXX we cannot handle a packet which lies in more than two buf */ 2885 fwdma_sync_multiseg_all(dbch->am, 2886 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2887 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2888 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2889 while (status & OHCI_CNTL_DMA_ACTIVE) { 2890 #if 0 2891 2892 if (off == OHCI_ARQOFF) 2893 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2894 db_tr->bus_addr, status, resCount); 2895 #endif 2896 len = dbch->xferq.psize - resCount; 2897 ld = (uint8_t *)db_tr->buf; 2898 if (dbch->pdb_tr == NULL) { 2899 len -= dbch->buf_offset; 2900 ld += dbch->buf_offset; 2901 } 2902 if (len > 0) 2903 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2904 BUS_DMASYNC_POSTREAD); 2905 while (len > 0 ) { 2906 if (count >= 0 && count-- == 0) 2907 goto out; 2908 if(dbch->pdb_tr != NULL){ 2909 /* we have a fragment in previous buffer */ 2910 int rlen; 2911 2912 offset = dbch->buf_offset; 2913 if (offset < 0) 2914 offset = - offset; 2915 buf = dbch->pdb_tr->buf + offset; 2916 rlen = dbch->xferq.psize - offset; 2917 if (firewire_debug) 2918 printf("rlen=%d, offset=%d\n", 2919 rlen, dbch->buf_offset); 2920 if (dbch->buf_offset < 0) { 2921 /* splitted in header, pull up */ 2922 char *p; 2923 2924 p = (char *)&pktbuf; 2925 bcopy(buf, p, rlen); 2926 p += rlen; 2927 /* this must be too long but harmless */ 2928 rlen = sizeof(pktbuf) - rlen; 2929 if (rlen < 0) 2930 printf("why rlen < 0\n"); 2931 bcopy(db_tr->buf, p, rlen); 2932 ld += rlen; 2933 len -= rlen; 2934 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2935 if (hlen <= 0) { 2936 printf("hlen < 0 shouldn't happen"); 2937 goto err; 2938 } 2939 offset = sizeof(pktbuf); 2940 vec[0].iov_base = (char *)&pktbuf; 2941 vec[0].iov_len = offset; 2942 } else { 2943 /* splitted in payload */ 2944 offset = rlen; 2945 vec[0].iov_base = buf; 2946 vec[0].iov_len = rlen; 2947 } 2948 fp=(struct fw_pkt *)vec[0].iov_base; 2949 nvec = 1; 2950 } else { 2951 /* no fragment in previous buffer */ 2952 fp=(struct fw_pkt *)ld; 2953 hlen = fwohci_arcv_swap(fp, len); 2954 if (hlen == 0) 2955 goto err; 2956 if (hlen < 0) { 2957 dbch->pdb_tr = db_tr; 2958 dbch->buf_offset = - dbch->buf_offset; 2959 /* sanity check */ 2960 if (resCount != 0) { 2961 printf("resCount=%d hlen=%d\n", 2962 resCount, hlen); 2963 goto err; 2964 } 2965 goto out; 2966 } 2967 offset = 0; 2968 nvec = 0; 2969 } 2970 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2971 if (plen < 0) { 2972 /* minimum header size + trailer 2973 = sizeof(fw_pkt) so this shouldn't happens */ 2974 printf("plen(%d) is negative! offset=%d\n", 2975 plen, offset); 2976 goto err; 2977 } 2978 if (plen > 0) { 2979 len -= plen; 2980 if (len < 0) { 2981 dbch->pdb_tr = db_tr; 2982 if (firewire_debug) 2983 printf("splitted payload\n"); 2984 /* sanity check */ 2985 if (resCount != 0) { 2986 printf("resCount=%d plen=%d" 2987 " len=%d\n", 2988 resCount, plen, len); 2989 goto err; 2990 } 2991 goto out; 2992 } 2993 vec[nvec].iov_base = ld; 2994 vec[nvec].iov_len = plen; 2995 nvec ++; 2996 ld += plen; 2997 } 2998 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2999 if (nvec == 0) 3000 printf("nvec == 0\n"); 3001 3002 /* DMA result-code will be written at the tail of packet */ 3003 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3004 #if 0 3005 printf("plen: %d, stat %x\n", 3006 plen ,stat); 3007 #endif 3008 spd = (stat >> 21) & 0x3; 3009 event = (stat >> 16) & 0x1f; 3010 switch (event) { 3011 case FWOHCIEV_ACKPEND: 3012 #if 0 3013 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3014 #endif 3015 /* fall through */ 3016 case FWOHCIEV_ACKCOMPL: 3017 { 3018 struct fw_rcv_buf rb; 3019 3020 if ((vec[nvec-1].iov_len -= 3021 sizeof(struct fwohci_trailer)) == 0) 3022 nvec--; 3023 rb.fc = &sc->fc; 3024 rb.vec = vec; 3025 rb.nvec = nvec; 3026 rb.spd = spd; 3027 fw_rcv(&rb); 3028 break; 3029 } 3030 case FWOHCIEV_BUSRST: 3031 if (sc->fc.status != FWBUSRESET) 3032 printf("got BUSRST packet!?\n"); 3033 break; 3034 default: 3035 device_printf(sc->fc.dev, 3036 "Async DMA Receive error err=%02x %s" 3037 " plen=%d offset=%d len=%d status=0x%08x" 3038 " tcode=0x%x, stat=0x%08x\n", 3039 event, fwohcicode[event], plen, 3040 dbch->buf_offset, len, 3041 OREAD(sc, OHCI_DMACTL(off)), 3042 fp->mode.common.tcode, stat); 3043 #if 1 /* XXX */ 3044 goto err; 3045 #endif 3046 break; 3047 } 3048 pcnt ++; 3049 if (dbch->pdb_tr != NULL) { 3050 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3051 off, 1); 3052 dbch->pdb_tr = NULL; 3053 } 3054 3055 } 3056 out: 3057 if (resCount == 0) { 3058 /* done on this buffer */ 3059 if (dbch->pdb_tr == NULL) { 3060 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3061 dbch->buf_offset = 0; 3062 } else 3063 if (dbch->pdb_tr != db_tr) 3064 printf("pdb_tr != db_tr\n"); 3065 db_tr = STAILQ_NEXT(db_tr, link); 3066 fwdma_sync_multiseg_all(dbch->am, 3067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3068 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3069 >> OHCI_STATUS_SHIFT; 3070 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3071 & OHCI_COUNT_MASK; 3072 /* XXX check buffer overrun */ 3073 dbch->top = db_tr; 3074 } else { 3075 dbch->buf_offset = dbch->xferq.psize - resCount; 3076 fw_bus_dmamap_sync( 3077 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3078 break; 3079 } 3080 /* XXX make sure DMA is not dead */ 3081 } 3082 #if 0 3083 if (pcnt < 1) 3084 printf("fwohci_arcv: no packets\n"); 3085 #endif 3086 fwdma_sync_multiseg_all(dbch->am, 3087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3088 splx(s); 3089 return; 3090 3091 err: 3092 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3093 OREAD(sc, OHCI_DMACTL(off))); 3094 dbch->pdb_tr = NULL; 3095 /* skip until resCount != 0 */ 3096 printf(" skip buffer"); 3097 while (resCount == 0) { 3098 printf(" #"); 3099 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3100 db_tr = STAILQ_NEXT(db_tr, link); 3101 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3102 & OHCI_COUNT_MASK; 3103 } 3104 printf(" done\n"); 3105 dbch->top = db_tr; 3106 dbch->buf_offset = dbch->xferq.psize - resCount; 3107 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3108 fwdma_sync_multiseg_all( 3109 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3110 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3111 splx(s); 3112 } 3113 #if defined(__NetBSD__) 3114 3115 int 3116 fwohci_print(void *aux, const char *pnp) 3117 { 3118 char *name = aux; 3119 3120 if (pnp) 3121 aprint_normal("%s at %s", name, pnp); 3122 3123 return UNCONF; 3124 } 3125 #endif 3126
Indexes created Fri Sep 26 20:09:58 GMT 2025