fwohci.c revision 1.90
1 /* $NetBSD: fwohci.c,v 1.90 2005/07/20 15:11:57 drochner Exp $ */ 2 /*- 3 * Copyright (c) 2003 Hidetoshi Shimokawa 4 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the acknowledgement as bellow: 17 * 18 * This product includes software developed by K. Kobayashi and H. Shimokawa 19 * 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 32 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $ 36 * 37 */ 38 39 #define ATRQ_CH 0 40 #define ATRS_CH 1 41 #define ARRQ_CH 2 42 #define ARRS_CH 3 43 #define ITX_CH 4 44 #define IRX_CH 0x24 45 46 #if defined(__FreeBSD__) 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/bus.h> 54 #include <sys/kernel.h> 55 #include <sys/conf.h> 56 #include <sys/endian.h> 57 #include <sys/ktr.h> 58 59 #include <machine/bus.h> 60 61 #if defined(__DragonFly__) || __FreeBSD_version < 500000 62 #include <machine/clock.h> /* for DELAY() */ 63 #endif 64 65 #ifdef __DragonFly__ 66 #include "fw_port.h" 67 #include "firewire.h" 68 #include "firewirereg.h" 69 #include "fwdma.h" 70 #include "fwohcireg.h" 71 #include "fwohcivar.h" 72 #include "firewire_phy.h" 73 #else 74 #include <dev/firewire/fw_port.h> 75 #include <dev/firewire/firewire.h> 76 #include <dev/firewire/firewirereg.h> 77 #include <dev/firewire/fwdma.h> 78 #include <dev/firewire/fwohcireg.h> 79 #include <dev/firewire/fwohcivar.h> 80 #include <dev/firewire/firewire_phy.h> 81 #endif 82 #elif defined(__NetBSD__) 83 #include <sys/param.h> 84 #include <sys/device.h> 85 #include <sys/errno.h> 86 #include <sys/conf.h> 87 #include <sys/kernel.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/proc.h> 91 #include <sys/reboot.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 95 #include <machine/bus.h> 96 97 #include <dev/ieee1394/fw_port.h> 98 #include <dev/ieee1394/firewire.h> 99 #include <dev/ieee1394/firewirereg.h> 100 #include <dev/ieee1394/fwdma.h> 101 #include <dev/ieee1394/fwohcireg.h> 102 #include <dev/ieee1394/fwohcivar.h> 103 #include <dev/ieee1394/firewire_phy.h> 104 #endif 105 106 #undef OHCI_DEBUG 107 108 static int nocyclemaster = 0; 109 #if defined(__FreeBSD__) 110 SYSCTL_DECL(_hw_firewire); 111 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 112 "Do not send cycle start packets"); 113 #elif defined(__NetBSD__) 114 /* 115 * Setup sysctl(3) MIB, hw.fwohci.* 116 * 117 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 118 */ 119 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 120 { 121 int rc; 122 const struct sysctlnode *node; 123 124 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 125 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 126 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 127 goto err; 128 } 129 130 if ((rc = sysctl_createv(clog, 0, NULL, &node, 131 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 132 SYSCTL_DESCR("fwohci controls"), 133 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 134 goto err; 135 } 136 137 /* fwohci no cyclemaster flag */ 138 if ((rc = sysctl_createv(clog, 0, NULL, &node, 139 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 140 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 141 NULL, 0, &nocyclemaster, 142 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 143 goto err; 144 } 145 return; 146 147 err: 148 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 149 } 150 #endif 151 152 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 153 "STOR","LOAD","NOP ","STOP", 154 "", "", "", "", "", "", "", ""}; 155 156 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 157 "UNDEF","REG","SYS","DEV"}; 158 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 159 static const char * const fwohcicode[32] = { 160 "No stat","Undef","long","miss Ack err", 161 "underrun","overrun","desc err", "data read err", 162 "data write err","bus reset","timeout","tcode err", 163 "Undef","Undef","unknown event","flushed", 164 "Undef","ack complete","ack pend","Undef", 165 "ack busy_X","ack busy_A","ack busy_B","Undef", 166 "Undef","Undef","Undef","ack tardy", 167 "Undef","ack data_err","ack type_err",""}; 168 169 #define MAX_SPEED 3 170 extern const char *fw_linkspeed[]; 171 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 172 173 static const struct tcode_info tinfo[] = { 174 /* hdr_len block flag*/ 175 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 176 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 177 /* 2 WRES */ {12, FWTI_RES}, 178 /* 3 XXX */ { 0, 0}, 179 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 180 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 181 /* 6 RRESQ */ {16, FWTI_RES}, 182 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 183 /* 8 CYCS */ { 0, 0}, 184 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 185 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 186 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 187 /* c XXX */ { 0, 0}, 188 /* d XXX */ { 0, 0}, 189 /* e PHY */ {12, FWTI_REQ}, 190 /* f XXX */ { 0, 0} 191 }; 192 193 #define OHCI_WRITE_SIGMASK 0xffff0000 194 #define OHCI_READ_SIGMASK 0xffff0000 195 196 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 197 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 198 199 static void fwohci_ibr (struct firewire_comm *); 200 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 201 static void fwohci_db_free (struct fwohci_dbch *); 202 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 203 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 204 static void fwohci_start_atq (struct firewire_comm *); 205 static void fwohci_start_ats (struct firewire_comm *); 206 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 207 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 208 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 209 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 210 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 211 static int fwohci_irx_enable (struct firewire_comm *, int); 212 static int fwohci_irx_disable (struct firewire_comm *, int); 213 #if BYTE_ORDER == BIG_ENDIAN 214 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 215 #endif 216 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 217 static int fwohci_itx_disable (struct firewire_comm *, int); 218 static void fwohci_timeout (void *); 219 static void fwohci_set_intr (struct firewire_comm *, int); 220 221 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 222 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 223 static void dump_db (struct fwohci_softc *, uint32_t); 224 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 225 static void dump_dma (struct fwohci_softc *, uint32_t); 226 static uint32_t fwohci_cyctimer (struct firewire_comm *); 227 static void fwohci_rbuf_update (struct fwohci_softc *, int); 228 static void fwohci_tbuf_update (struct fwohci_softc *, int); 229 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 230 #if FWOHCI_TASKQUEUE 231 static void fwohci_complete(void *, int); 232 #endif 233 #if defined(__NetBSD__) 234 static void fwohci_power(int, void *); 235 int fwohci_print(void *, const char *); 236 #endif 237 238 /* 239 * memory allocated for DMA programs 240 */ 241 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 242 243 #define NDB FWMAXQUEUE 244 245 #define OHCI_VERSION 0x00 246 #define OHCI_ATRETRY 0x08 247 #define OHCI_CROMHDR 0x18 248 #define OHCI_BUS_OPT 0x20 249 #define OHCI_BUSIRMC (1 << 31) 250 #define OHCI_BUSCMC (1 << 30) 251 #define OHCI_BUSISC (1 << 29) 252 #define OHCI_BUSBMC (1 << 28) 253 #define OHCI_BUSPMC (1 << 27) 254 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 255 OHCI_BUSBMC | OHCI_BUSPMC 256 257 #define OHCI_EUID_HI 0x24 258 #define OHCI_EUID_LO 0x28 259 260 #define OHCI_CROMPTR 0x34 261 #define OHCI_HCCCTL 0x50 262 #define OHCI_HCCCTLCLR 0x54 263 #define OHCI_AREQHI 0x100 264 #define OHCI_AREQHICLR 0x104 265 #define OHCI_AREQLO 0x108 266 #define OHCI_AREQLOCLR 0x10c 267 #define OHCI_PREQHI 0x110 268 #define OHCI_PREQHICLR 0x114 269 #define OHCI_PREQLO 0x118 270 #define OHCI_PREQLOCLR 0x11c 271 #define OHCI_PREQUPPER 0x120 272 273 #define OHCI_SID_BUF 0x64 274 #define OHCI_SID_CNT 0x68 275 #define OHCI_SID_ERR (1 << 31) 276 #define OHCI_SID_CNT_MASK 0xffc 277 278 #define OHCI_IT_STAT 0x90 279 #define OHCI_IT_STATCLR 0x94 280 #define OHCI_IT_MASK 0x98 281 #define OHCI_IT_MASKCLR 0x9c 282 283 #define OHCI_IR_STAT 0xa0 284 #define OHCI_IR_STATCLR 0xa4 285 #define OHCI_IR_MASK 0xa8 286 #define OHCI_IR_MASKCLR 0xac 287 288 #define OHCI_LNKCTL 0xe0 289 #define OHCI_LNKCTLCLR 0xe4 290 291 #define OHCI_PHYACCESS 0xec 292 #define OHCI_CYCLETIMER 0xf0 293 294 #define OHCI_DMACTL(off) (off) 295 #define OHCI_DMACTLCLR(off) (off + 4) 296 #define OHCI_DMACMD(off) (off + 0xc) 297 #define OHCI_DMAMATCH(off) (off + 0x10) 298 299 #define OHCI_ATQOFF 0x180 300 #define OHCI_ATQCTL OHCI_ATQOFF 301 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 302 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 303 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 304 305 #define OHCI_ATSOFF 0x1a0 306 #define OHCI_ATSCTL OHCI_ATSOFF 307 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 308 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 309 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 310 311 #define OHCI_ARQOFF 0x1c0 312 #define OHCI_ARQCTL OHCI_ARQOFF 313 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 314 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 315 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 316 317 #define OHCI_ARSOFF 0x1e0 318 #define OHCI_ARSCTL OHCI_ARSOFF 319 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 320 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 321 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 322 323 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 324 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 325 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 326 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 327 328 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 329 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 330 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 331 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 332 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 333 334 #if defined(__FreeBSD__) 335 d_ioctl_t fwohci_ioctl; 336 #elif defined(__NetBSD__) 337 extern struct cfdriver fwohci_cd; 338 dev_type_ioctl(fwohci_ioctl); 339 #endif 340 341 /* 342 * Communication with PHY device 343 */ 344 static uint32_t 345 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 346 { 347 uint32_t fun; 348 349 addr &= 0xf; 350 data &= 0xff; 351 352 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 353 OWRITE(sc, OHCI_PHYACCESS, fun); 354 DELAY(100); 355 356 return(fwphy_rddata( sc, addr)); 357 } 358 359 static uint32_t 360 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 361 { 362 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 363 int i; 364 uint32_t bm; 365 366 #define OHCI_CSR_DATA 0x0c 367 #define OHCI_CSR_COMP 0x10 368 #define OHCI_CSR_CONT 0x14 369 #define OHCI_BUS_MANAGER_ID 0 370 371 OWRITE(sc, OHCI_CSR_DATA, node); 372 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 373 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 374 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 375 DELAY(10); 376 bm = OREAD(sc, OHCI_CSR_DATA); 377 if((bm & 0x3f) == 0x3f) 378 bm = node; 379 if (firewire_debug) 380 device_printf(sc->fc.dev, 381 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 382 383 return(bm); 384 } 385 386 static uint32_t 387 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 388 { 389 uint32_t fun, stat; 390 u_int i, retry = 0; 391 392 addr &= 0xf; 393 #define MAX_RETRY 100 394 again: 395 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 396 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 397 OWRITE(sc, OHCI_PHYACCESS, fun); 398 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 399 fun = OREAD(sc, OHCI_PHYACCESS); 400 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 401 break; 402 DELAY(100); 403 } 404 if(i >= MAX_RETRY) { 405 if (firewire_debug) 406 device_printf(sc->fc.dev, "phy read failed(1).\n"); 407 if (++retry < MAX_RETRY) { 408 DELAY(100); 409 goto again; 410 } 411 } 412 /* Make sure that SCLK is started */ 413 stat = OREAD(sc, FWOHCI_INTSTAT); 414 if ((stat & OHCI_INT_REG_FAIL) != 0 || 415 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 416 if (firewire_debug) 417 device_printf(sc->fc.dev, "phy read failed(2).\n"); 418 if (++retry < MAX_RETRY) { 419 DELAY(100); 420 goto again; 421 } 422 } 423 if (firewire_debug || retry >= MAX_RETRY) 424 device_printf(sc->fc.dev, 425 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 426 #undef MAX_RETRY 427 return((fun >> PHYDEV_RDDATA )& 0xff); 428 } 429 /* Device specific ioctl. */ 430 FW_IOCTL(fwohci) 431 { 432 FW_IOCTL_START; 433 struct fwohci_softc *fc; 434 int err = 0; 435 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 436 uint32_t *dmach = (uint32_t *) data; 437 438 if(sc == NULL){ 439 return(EINVAL); 440 } 441 fc = (struct fwohci_softc *)sc->fc; 442 443 if (!data) 444 return(EINVAL); 445 446 switch (cmd) { 447 case FWOHCI_WRREG: 448 #define OHCI_MAX_REG 0x800 449 if(reg->addr <= OHCI_MAX_REG){ 450 OWRITE(fc, reg->addr, reg->data); 451 reg->data = OREAD(fc, reg->addr); 452 }else{ 453 err = EINVAL; 454 } 455 break; 456 case FWOHCI_RDREG: 457 if(reg->addr <= OHCI_MAX_REG){ 458 reg->data = OREAD(fc, reg->addr); 459 }else{ 460 err = EINVAL; 461 } 462 break; 463 /* Read DMA descriptors for debug */ 464 case DUMPDMA: 465 if(*dmach <= OHCI_MAX_DMA_CH ){ 466 dump_dma(fc, *dmach); 467 dump_db(fc, *dmach); 468 }else{ 469 err = EINVAL; 470 } 471 break; 472 /* Read/Write Phy registers */ 473 #define OHCI_MAX_PHY_REG 0xf 474 case FWOHCI_RDPHYREG: 475 if (reg->addr <= OHCI_MAX_PHY_REG) 476 reg->data = fwphy_rddata(fc, reg->addr); 477 else 478 err = EINVAL; 479 break; 480 case FWOHCI_WRPHYREG: 481 if (reg->addr <= OHCI_MAX_PHY_REG) 482 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 483 else 484 err = EINVAL; 485 break; 486 default: 487 err = EINVAL; 488 break; 489 } 490 return err; 491 } 492 493 static int 494 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 495 { 496 uint32_t reg, reg2; 497 int e1394a = 1; 498 /* 499 * probe PHY parameters 500 * 0. to prove PHY version, whether compliance of 1394a. 501 * 1. to probe maximum speed supported by the PHY and 502 * number of port supported by core-logic. 503 * It is not actually available port on your PC . 504 */ 505 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 506 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 507 508 if((reg >> 5) != 7 ){ 509 sc->fc.mode &= ~FWPHYASYST; 510 sc->fc.nport = reg & FW_PHY_NP; 511 sc->fc.speed = reg & FW_PHY_SPD >> 6; 512 if (sc->fc.speed > MAX_SPEED) { 513 device_printf(dev, "invalid speed %d (fixed to %d).\n", 514 sc->fc.speed, MAX_SPEED); 515 sc->fc.speed = MAX_SPEED; 516 } 517 device_printf(dev, 518 "Phy 1394 only %s, %d ports.\n", 519 fw_linkspeed[sc->fc.speed], sc->fc.nport); 520 }else{ 521 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 522 sc->fc.mode |= FWPHYASYST; 523 sc->fc.nport = reg & FW_PHY_NP; 524 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 525 if (sc->fc.speed > MAX_SPEED) { 526 device_printf(dev, "invalid speed %d (fixed to %d).\n", 527 sc->fc.speed, MAX_SPEED); 528 sc->fc.speed = MAX_SPEED; 529 } 530 device_printf(dev, 531 "Phy 1394a available %s, %d ports.\n", 532 fw_linkspeed[sc->fc.speed], sc->fc.nport); 533 534 /* check programPhyEnable */ 535 reg2 = fwphy_rddata(sc, 5); 536 #if 0 537 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 538 #else /* XXX force to enable 1394a */ 539 if (e1394a) { 540 #endif 541 if (firewire_debug) 542 device_printf(dev, 543 "Enable 1394a Enhancements\n"); 544 /* enable EAA EMC */ 545 reg2 |= 0x03; 546 /* set aPhyEnhanceEnable */ 547 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 548 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 549 } else { 550 /* for safe */ 551 reg2 &= ~0x83; 552 } 553 reg2 = fwphy_wrdata(sc, 5, reg2); 554 } 555 556 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 557 if((reg >> 5) == 7 ){ 558 reg = fwphy_rddata(sc, 4); 559 reg |= 1 << 6; 560 fwphy_wrdata(sc, 4, reg); 561 reg = fwphy_rddata(sc, 4); 562 } 563 return 0; 564 } 565 566 567 void 568 fwohci_reset(struct fwohci_softc *sc, device_t dev) 569 { 570 int i, max_rec, speed; 571 uint32_t reg, reg2; 572 struct fwohcidb_tr *db_tr; 573 574 /* Disable interrupts */ 575 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 576 577 /* Now stopping all DMA channels */ 578 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 579 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 580 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 581 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 582 583 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 584 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 585 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 586 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 587 } 588 589 /* FLUSH FIFO and reset Transmitter/Reciever */ 590 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 591 if (firewire_debug) 592 device_printf(dev, "resetting OHCI..."); 593 i = 0; 594 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 595 if (i++ > 100) break; 596 DELAY(1000); 597 } 598 if (firewire_debug) 599 printf("done (loop=%d)\n", i); 600 601 /* Probe phy */ 602 fwohci_probe_phy(sc, dev); 603 604 /* Probe link */ 605 reg = OREAD(sc, OHCI_BUS_OPT); 606 reg2 = reg | OHCI_BUSFNC; 607 max_rec = (reg & 0x0000f000) >> 12; 608 speed = (reg & 0x00000007); 609 device_printf(dev, "Link %s, max_rec %d bytes.\n", 610 fw_linkspeed[speed], MAXREC(max_rec)); 611 /* XXX fix max_rec */ 612 sc->fc.maxrec = sc->fc.speed + 8; 613 if (max_rec != sc->fc.maxrec) { 614 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 615 device_printf(dev, "max_rec %d -> %d\n", 616 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 617 } 618 if (firewire_debug) 619 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 620 OWRITE(sc, OHCI_BUS_OPT, reg2); 621 622 /* Initialize registers */ 623 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 624 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 625 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 626 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 627 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 628 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 629 630 /* Enable link */ 631 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 632 633 /* Force to start async RX DMA */ 634 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 635 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 636 fwohci_rx_enable(sc, &sc->arrq); 637 fwohci_rx_enable(sc, &sc->arrs); 638 639 /* Initialize async TX */ 640 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 641 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 642 643 /* AT Retries */ 644 OWRITE(sc, FWOHCI_RETRY, 645 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 646 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 647 648 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 649 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 650 sc->atrq.bottom = sc->atrq.top; 651 sc->atrs.bottom = sc->atrs.top; 652 653 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 654 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 655 db_tr->xfer = NULL; 656 } 657 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 658 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 659 db_tr->xfer = NULL; 660 } 661 662 663 /* Enable interrupts */ 664 OWRITE(sc, FWOHCI_INTMASK, 665 OHCI_INT_ERR | OHCI_INT_PHY_SID 666 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 667 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 668 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 669 fwohci_set_intr(&sc->fc, 1); 670 671 } 672 673 int 674 fwohci_init(struct fwohci_softc *sc, device_t dev) 675 { 676 int i, mver; 677 uint32_t reg; 678 uint8_t ui[8]; 679 680 #if FWOHCI_TASKQUEUE 681 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 682 #endif 683 684 /* OHCI version */ 685 reg = OREAD(sc, OHCI_VERSION); 686 mver = (reg >> 16) & 0xff; 687 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 688 mver, reg & 0xff, (reg>>24) & 1); 689 if (mver < 1 || mver > 9) { 690 device_printf(dev, "invalid OHCI version\n"); 691 return (ENXIO); 692 } 693 694 /* Available Isochronous DMA channel probe */ 695 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 696 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 697 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 698 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 699 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 700 for (i = 0; i < 0x20; i++) 701 if ((reg & (1 << i)) == 0) 702 break; 703 sc->fc.nisodma = i; 704 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 705 if (i == 0) 706 return (ENXIO); 707 708 sc->fc.arq = &sc->arrq.xferq; 709 sc->fc.ars = &sc->arrs.xferq; 710 sc->fc.atq = &sc->atrq.xferq; 711 sc->fc.ats = &sc->atrs.xferq; 712 713 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 714 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 715 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 716 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 717 718 sc->arrq.xferq.start = NULL; 719 sc->arrs.xferq.start = NULL; 720 sc->atrq.xferq.start = fwohci_start_atq; 721 sc->atrs.xferq.start = fwohci_start_ats; 722 723 sc->arrq.xferq.buf = NULL; 724 sc->arrs.xferq.buf = NULL; 725 sc->atrq.xferq.buf = NULL; 726 sc->atrs.xferq.buf = NULL; 727 728 sc->arrq.xferq.dmach = -1; 729 sc->arrs.xferq.dmach = -1; 730 sc->atrq.xferq.dmach = -1; 731 sc->atrs.xferq.dmach = -1; 732 733 sc->arrq.ndesc = 1; 734 sc->arrs.ndesc = 1; 735 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 736 sc->atrs.ndesc = 2; 737 738 sc->arrq.ndb = NDB; 739 sc->arrs.ndb = NDB / 2; 740 sc->atrq.ndb = NDB; 741 sc->atrs.ndb = NDB / 2; 742 743 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 744 sc->fc.it[i] = &sc->it[i].xferq; 745 sc->fc.ir[i] = &sc->ir[i].xferq; 746 sc->it[i].xferq.dmach = i; 747 sc->ir[i].xferq.dmach = i; 748 sc->it[i].ndb = 0; 749 sc->ir[i].ndb = 0; 750 } 751 752 sc->fc.tcode = tinfo; 753 sc->fc.dev = dev; 754 755 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 756 &sc->crom_dma, BUS_DMA_WAITOK); 757 if(sc->fc.config_rom == NULL){ 758 device_printf(dev, "config_rom alloc failed."); 759 return ENOMEM; 760 } 761 762 #if 0 763 bzero(&sc->fc.config_rom[0], CROMSIZE); 764 sc->fc.config_rom[1] = 0x31333934; 765 sc->fc.config_rom[2] = 0xf000a002; 766 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 767 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 768 sc->fc.config_rom[5] = 0; 769 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 770 771 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 772 #endif 773 774 775 /* SID recieve buffer must align 2^11 */ 776 #define OHCI_SIDSIZE (1 << 11) 777 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 778 &sc->sid_dma, BUS_DMA_WAITOK); 779 if (sc->sid_buf == NULL) { 780 device_printf(dev, "sid_buf alloc failed."); 781 return ENOMEM; 782 } 783 784 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 785 &sc->dummy_dma, BUS_DMA_WAITOK); 786 787 if (sc->dummy_dma.v_addr == NULL) { 788 device_printf(dev, "dummy_dma alloc failed."); 789 return ENOMEM; 790 } 791 792 fwohci_db_init(sc, &sc->arrq); 793 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 794 return ENOMEM; 795 796 fwohci_db_init(sc, &sc->arrs); 797 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 798 return ENOMEM; 799 800 fwohci_db_init(sc, &sc->atrq); 801 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 802 return ENOMEM; 803 804 fwohci_db_init(sc, &sc->atrs); 805 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 806 return ENOMEM; 807 808 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 809 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 810 for( i = 0 ; i < 8 ; i ++) 811 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 812 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 813 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 814 815 sc->fc.ioctl = fwohci_ioctl; 816 sc->fc.cyctimer = fwohci_cyctimer; 817 sc->fc.set_bmr = fwohci_set_bus_manager; 818 sc->fc.ibr = fwohci_ibr; 819 sc->fc.irx_enable = fwohci_irx_enable; 820 sc->fc.irx_disable = fwohci_irx_disable; 821 822 sc->fc.itx_enable = fwohci_itxbuf_enable; 823 sc->fc.itx_disable = fwohci_itx_disable; 824 #if BYTE_ORDER == BIG_ENDIAN 825 sc->fc.irx_post = fwohci_irx_post; 826 #else 827 sc->fc.irx_post = NULL; 828 #endif 829 sc->fc.itx_post = NULL; 830 sc->fc.timeout = fwohci_timeout; 831 sc->fc.poll = fwohci_poll; 832 sc->fc.set_intr = fwohci_set_intr; 833 834 sc->intmask = sc->irstat = sc->itstat = 0; 835 836 fw_init(&sc->fc); 837 fwohci_reset(sc, dev); 838 FWOHCI_INIT_END; 839 840 return 0; 841 } 842 843 void 844 fwohci_timeout(void *arg) 845 { 846 struct fwohci_softc *sc; 847 848 sc = (struct fwohci_softc *)arg; 849 } 850 851 uint32_t 852 fwohci_cyctimer(struct firewire_comm *fc) 853 { 854 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 855 return(OREAD(sc, OHCI_CYCLETIMER)); 856 } 857 858 FWOHCI_DETACH() 859 { 860 int i; 861 862 FWOHCI_DETACH_START; 863 if (sc->sid_buf != NULL) 864 fwdma_free(&sc->fc, &sc->sid_dma); 865 if (sc->fc.config_rom != NULL) 866 fwdma_free(&sc->fc, &sc->crom_dma); 867 868 fwohci_db_free(&sc->arrq); 869 fwohci_db_free(&sc->arrs); 870 871 fwohci_db_free(&sc->atrq); 872 fwohci_db_free(&sc->atrs); 873 874 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 875 fwohci_db_free(&sc->it[i]); 876 fwohci_db_free(&sc->ir[i]); 877 } 878 FWOHCI_DETACH_END; 879 880 return 0; 881 } 882 883 #define LAST_DB(dbtr, db) do { \ 884 struct fwohcidb_tr *_dbtr = (dbtr); \ 885 int _cnt = _dbtr->dbcnt; \ 886 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 887 } while (0) 888 889 static void 890 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 891 { 892 struct fwohcidb_tr *db_tr; 893 struct fwohcidb *db; 894 bus_dma_segment_t *s; 895 int i; 896 897 db_tr = (struct fwohcidb_tr *)arg; 898 db = &db_tr->db[db_tr->dbcnt]; 899 if (error) { 900 if (firewire_debug || error != EFBIG) 901 printf("fwohci_execute_db: error=%d\n", error); 902 return; 903 } 904 for (i = 0; i < nseg; i++) { 905 s = &segs[i]; 906 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 907 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 908 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 909 db++; 910 db_tr->dbcnt++; 911 } 912 } 913 914 static void 915 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 916 bus_size_t size, int error) 917 { 918 fwohci_execute_db(arg, segs, nseg, error); 919 } 920 921 static void 922 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 923 { 924 int i, s; 925 int tcode, hdr_len, pl_off; 926 int fsegment = -1; 927 uint32_t off; 928 struct fw_xfer *xfer; 929 struct fw_pkt *fp; 930 struct fwohci_txpkthdr *ohcifp; 931 struct fwohcidb_tr *db_tr; 932 struct fwohcidb *db; 933 uint32_t *ld; 934 const struct tcode_info *info; 935 static int maxdesc=0; 936 937 if(&sc->atrq == dbch){ 938 off = OHCI_ATQOFF; 939 }else if(&sc->atrs == dbch){ 940 off = OHCI_ATSOFF; 941 }else{ 942 return; 943 } 944 945 if (dbch->flags & FWOHCI_DBCH_FULL) 946 return; 947 948 s = splfw(); 949 fwdma_sync_multiseg_all(dbch->am, 950 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 951 db_tr = dbch->top; 952 txloop: 953 xfer = STAILQ_FIRST(&dbch->xferq.q); 954 if(xfer == NULL){ 955 goto kick; 956 } 957 if(dbch->xferq.queued == 0 ){ 958 device_printf(sc->fc.dev, "TX queue empty\n"); 959 } 960 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 961 db_tr->xfer = xfer; 962 xfer->state = FWXF_START; 963 964 fp = &xfer->send.hdr; 965 tcode = fp->mode.common.tcode; 966 967 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 968 info = &tinfo[tcode]; 969 hdr_len = pl_off = info->hdr_len; 970 971 ld = &ohcifp->mode.ld[0]; 972 ld[0] = ld[1] = ld[2] = ld[3] = 0; 973 for( i = 0 ; i < pl_off ; i+= 4) 974 ld[i/4] = fp->mode.ld[i/4]; 975 976 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 977 if (tcode == FWTCODE_STREAM ){ 978 hdr_len = 8; 979 ohcifp->mode.stream.len = fp->mode.stream.len; 980 } else if (tcode == FWTCODE_PHY) { 981 hdr_len = 12; 982 ld[1] = fp->mode.ld[1]; 983 ld[2] = fp->mode.ld[2]; 984 ohcifp->mode.common.spd = 0; 985 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 986 } else { 987 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 988 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 989 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 990 } 991 db = &db_tr->db[0]; 992 FWOHCI_DMA_WRITE(db->db.desc.cmd, 993 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 994 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 995 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 996 /* Specify bound timer of asy. responce */ 997 if(&sc->atrs == dbch){ 998 FWOHCI_DMA_WRITE(db->db.desc.res, 999 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1000 } 1001 #if BYTE_ORDER == BIG_ENDIAN 1002 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1003 hdr_len = 12; 1004 for (i = 0; i < hdr_len/4; i ++) 1005 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1006 #endif 1007 1008 again: 1009 db_tr->dbcnt = 2; 1010 db = &db_tr->db[db_tr->dbcnt]; 1011 if (xfer->send.pay_len > 0) { 1012 int err; 1013 /* handle payload */ 1014 if (xfer->mbuf == NULL) { 1015 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1016 &xfer->send.payload[0], xfer->send.pay_len, 1017 fwohci_execute_db, db_tr, 1018 BUS_DMA_WAITOK); 1019 } else { 1020 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1021 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1022 db_tr->dma_map, xfer->mbuf, 1023 fwohci_execute_db2, db_tr, 1024 BUS_DMA_WAITOK); 1025 if (err == EFBIG) { 1026 struct mbuf *m0; 1027 1028 if (firewire_debug) 1029 device_printf(sc->fc.dev, "EFBIG.\n"); 1030 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1031 if (m0 != NULL) { 1032 m_copydata(xfer->mbuf, 0, 1033 xfer->mbuf->m_pkthdr.len, 1034 mtod(m0, caddr_t)); 1035 m0->m_len = m0->m_pkthdr.len = 1036 xfer->mbuf->m_pkthdr.len; 1037 m_freem(xfer->mbuf); 1038 xfer->mbuf = m0; 1039 goto again; 1040 } 1041 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1042 } 1043 } 1044 if (err) 1045 printf("dmamap_load: err=%d\n", err); 1046 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1047 BUS_DMASYNC_PREWRITE); 1048 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1049 for (i = 2; i < db_tr->dbcnt; i++) 1050 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1051 OHCI_OUTPUT_MORE); 1052 #endif 1053 } 1054 if (maxdesc < db_tr->dbcnt) { 1055 maxdesc = db_tr->dbcnt; 1056 if (firewire_debug) 1057 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1058 } 1059 /* last db */ 1060 LAST_DB(db_tr, db); 1061 FWOHCI_DMA_SET(db->db.desc.cmd, 1062 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1063 FWOHCI_DMA_WRITE(db->db.desc.depend, 1064 STAILQ_NEXT(db_tr, link)->bus_addr); 1065 1066 if(fsegment == -1 ) 1067 fsegment = db_tr->dbcnt; 1068 if (dbch->pdb_tr != NULL) { 1069 LAST_DB(dbch->pdb_tr, db); 1070 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1071 } 1072 dbch->pdb_tr = db_tr; 1073 db_tr = STAILQ_NEXT(db_tr, link); 1074 if(db_tr != dbch->bottom){ 1075 goto txloop; 1076 } else { 1077 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1078 dbch->flags |= FWOHCI_DBCH_FULL; 1079 } 1080 kick: 1081 /* kick asy q */ 1082 fwdma_sync_multiseg_all(dbch->am, 1083 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1084 1085 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1086 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1087 } else { 1088 if (firewire_debug) 1089 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1090 OREAD(sc, OHCI_DMACTL(off))); 1091 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1092 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1093 dbch->xferq.flag |= FWXFERQ_RUNNING; 1094 } 1095 CTR0(KTR_DEV, "start kick done"); 1096 CTR0(KTR_DEV, "start kick done2"); 1097 1098 dbch->top = db_tr; 1099 splx(s); 1100 return; 1101 } 1102 1103 static void 1104 fwohci_start_atq(struct firewire_comm *fc) 1105 { 1106 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1107 fwohci_start( sc, &(sc->atrq)); 1108 return; 1109 } 1110 1111 static void 1112 fwohci_start_ats(struct firewire_comm *fc) 1113 { 1114 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1115 fwohci_start( sc, &(sc->atrs)); 1116 return; 1117 } 1118 1119 void 1120 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1121 { 1122 int s, ch, err = 0; 1123 struct fwohcidb_tr *tr; 1124 struct fwohcidb *db; 1125 struct fw_xfer *xfer; 1126 uint32_t off; 1127 u_int stat, status; 1128 int packets; 1129 struct firewire_comm *fc = (struct firewire_comm *)sc; 1130 1131 if(&sc->atrq == dbch){ 1132 off = OHCI_ATQOFF; 1133 ch = ATRQ_CH; 1134 }else if(&sc->atrs == dbch){ 1135 off = OHCI_ATSOFF; 1136 ch = ATRS_CH; 1137 }else{ 1138 return; 1139 } 1140 s = splfw(); 1141 tr = dbch->bottom; 1142 packets = 0; 1143 fwdma_sync_multiseg_all(dbch->am, 1144 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1145 while(dbch->xferq.queued > 0){ 1146 LAST_DB(tr, db); 1147 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1148 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1149 if (fc->status != FWBUSRESET) 1150 /* maybe out of order?? */ 1151 goto out; 1152 } 1153 if (tr->xfer->send.pay_len > 0) { 1154 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1155 BUS_DMASYNC_POSTWRITE); 1156 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1157 } 1158 #if 1 1159 if (firewire_debug > 1) 1160 dump_db(sc, ch); 1161 #endif 1162 if(status & OHCI_CNTL_DMA_DEAD) { 1163 /* Stop DMA */ 1164 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1165 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1166 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1167 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1168 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1169 } 1170 stat = status & FWOHCIEV_MASK; 1171 switch(stat){ 1172 case FWOHCIEV_ACKPEND: 1173 CTR0(KTR_DEV, "txd: ack pending"); 1174 /* fall through */ 1175 case FWOHCIEV_ACKCOMPL: 1176 err = 0; 1177 break; 1178 case FWOHCIEV_ACKBSA: 1179 case FWOHCIEV_ACKBSB: 1180 case FWOHCIEV_ACKBSX: 1181 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1182 err = EBUSY; 1183 break; 1184 case FWOHCIEV_FLUSHED: 1185 case FWOHCIEV_ACKTARD: 1186 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1187 err = EAGAIN; 1188 break; 1189 case FWOHCIEV_MISSACK: 1190 case FWOHCIEV_UNDRRUN: 1191 case FWOHCIEV_OVRRUN: 1192 case FWOHCIEV_DESCERR: 1193 case FWOHCIEV_DTRDERR: 1194 case FWOHCIEV_TIMEOUT: 1195 case FWOHCIEV_TCODERR: 1196 case FWOHCIEV_UNKNOWN: 1197 case FWOHCIEV_ACKDERR: 1198 case FWOHCIEV_ACKTERR: 1199 default: 1200 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1201 stat, fwohcicode[stat]); 1202 err = EINVAL; 1203 break; 1204 } 1205 if (tr->xfer != NULL) { 1206 xfer = tr->xfer; 1207 CTR0(KTR_DEV, "txd"); 1208 if (xfer->state == FWXF_RCVD) { 1209 #if 0 1210 if (firewire_debug) 1211 printf("already rcvd\n"); 1212 #endif 1213 fw_xfer_done(xfer); 1214 } else { 1215 xfer->state = FWXF_SENT; 1216 if (err == EBUSY && fc->status != FWBUSRESET) { 1217 xfer->state = FWXF_BUSY; 1218 xfer->resp = err; 1219 xfer->recv.pay_len = 0; 1220 fw_xfer_done(xfer); 1221 } else if (stat != FWOHCIEV_ACKPEND) { 1222 if (stat != FWOHCIEV_ACKCOMPL) 1223 xfer->state = FWXF_SENTERR; 1224 xfer->resp = err; 1225 xfer->recv.pay_len = 0; 1226 fw_xfer_done(xfer); 1227 } 1228 } 1229 /* 1230 * The watchdog timer takes care of split 1231 * transcation timeout for ACKPEND case. 1232 */ 1233 } else { 1234 printf("this shouldn't happen\n"); 1235 } 1236 dbch->xferq.queued --; 1237 tr->xfer = NULL; 1238 1239 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1240 packets ++; 1241 tr = STAILQ_NEXT(tr, link); 1242 dbch->bottom = tr; 1243 if (dbch->bottom == dbch->top) { 1244 /* we reaches the end of context program */ 1245 if (firewire_debug && dbch->xferq.queued > 0) 1246 printf("queued > 0\n"); 1247 break; 1248 } 1249 } 1250 out: 1251 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1252 printf("make free slot\n"); 1253 dbch->flags &= ~FWOHCI_DBCH_FULL; 1254 fwohci_start(sc, dbch); 1255 } 1256 fwdma_sync_multiseg_all( 1257 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1258 splx(s); 1259 } 1260 1261 static void 1262 fwohci_db_free(struct fwohci_dbch *dbch) 1263 { 1264 struct fwohcidb_tr *db_tr; 1265 int idb; 1266 1267 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1268 return; 1269 1270 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1271 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1272 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1273 db_tr->buf != NULL) { 1274 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1275 db_tr->buf, dbch->xferq.psize); 1276 db_tr->buf = NULL; 1277 } else if (db_tr->dma_map != NULL) 1278 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1279 } 1280 dbch->ndb = 0; 1281 db_tr = STAILQ_FIRST(&dbch->db_trq); 1282 fwdma_free_multiseg(dbch->am); 1283 free(db_tr, M_FW); 1284 STAILQ_INIT(&dbch->db_trq); 1285 dbch->flags &= ~FWOHCI_DBCH_INIT; 1286 } 1287 1288 static void 1289 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1290 { 1291 int idb; 1292 struct fwohcidb_tr *db_tr; 1293 1294 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1295 goto out; 1296 1297 /* create dma_tag for buffers */ 1298 #define MAX_REQCOUNT 0xffff 1299 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1300 /*alignment*/ 1, /*boundary*/ 0, 1301 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1302 /*highaddr*/ BUS_SPACE_MAXADDR, 1303 /*filter*/NULL, /*filterarg*/NULL, 1304 /*maxsize*/ dbch->xferq.psize, 1305 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1306 /*maxsegsz*/ MAX_REQCOUNT, 1307 /*flags*/ 0, 1308 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1309 /*lockfunc*/busdma_lock_mutex, 1310 /*lockarg*/&Giant, 1311 #endif 1312 &dbch->dmat)) 1313 return; 1314 1315 /* allocate DB entries and attach one to each DMA channels */ 1316 /* DB entry must start at 16 bytes bounary. */ 1317 STAILQ_INIT(&dbch->db_trq); 1318 db_tr = (struct fwohcidb_tr *) 1319 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1320 M_FW, M_WAITOK | M_ZERO); 1321 if(db_tr == NULL){ 1322 printf("fwohci_db_init: malloc(1) failed\n"); 1323 return; 1324 } 1325 1326 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1327 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1328 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1329 if (dbch->am == NULL) { 1330 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1331 free(db_tr, M_FW); 1332 return; 1333 } 1334 /* Attach DB to DMA ch. */ 1335 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1336 db_tr->dbcnt = 0; 1337 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1338 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1339 /* create dmamap for buffers */ 1340 /* XXX do we need 4bytes alignment tag? */ 1341 /* XXX don't alloc dma_map for AR */ 1342 if (bus_dmamap_create(sc->fc.dmat, dbch->xferq.psize, 1343 dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, MAX_REQCOUNT, 1344 0, BUS_DMA_NOWAIT, &db_tr->dma_map) != 0) { 1345 printf("bus_dmamap_create failed\n"); 1346 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1347 fwohci_db_free(dbch); 1348 return; 1349 } 1350 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1351 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1352 if (idb % dbch->xferq.bnpacket == 0) 1353 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1354 ].start = (caddr_t)db_tr; 1355 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1356 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1357 ].end = (caddr_t)db_tr; 1358 } 1359 db_tr++; 1360 } 1361 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1362 = STAILQ_FIRST(&dbch->db_trq); 1363 out: 1364 dbch->xferq.queued = 0; 1365 dbch->pdb_tr = NULL; 1366 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1367 dbch->bottom = dbch->top; 1368 dbch->flags = FWOHCI_DBCH_INIT; 1369 } 1370 1371 static int 1372 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1373 { 1374 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1375 int sleepch; 1376 1377 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1378 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1379 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1380 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1381 /* XXX we cannot free buffers until the DMA really stops */ 1382 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1383 fwohci_db_free(&sc->it[dmach]); 1384 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1385 return 0; 1386 } 1387 1388 static int 1389 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1390 { 1391 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1392 int sleepch; 1393 1394 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1395 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1396 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1397 /* XXX we cannot free buffers until the DMA really stops */ 1398 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1399 fwohci_db_free(&sc->ir[dmach]); 1400 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1401 return 0; 1402 } 1403 1404 #if BYTE_ORDER == BIG_ENDIAN 1405 static void 1406 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1407 { 1408 qld[0] = FWOHCI_DMA_READ(qld[0]); 1409 return; 1410 } 1411 #endif 1412 1413 static int 1414 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1415 { 1416 int err = 0; 1417 int idb, z, i, dmach = 0, ldesc; 1418 uint32_t off = 0; 1419 struct fwohcidb_tr *db_tr; 1420 struct fwohcidb *db; 1421 1422 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1423 err = EINVAL; 1424 return err; 1425 } 1426 z = dbch->ndesc; 1427 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1428 if( &sc->it[dmach] == dbch){ 1429 off = OHCI_ITOFF(dmach); 1430 break; 1431 } 1432 } 1433 if(off == 0){ 1434 err = EINVAL; 1435 return err; 1436 } 1437 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1438 return err; 1439 dbch->xferq.flag |= FWXFERQ_RUNNING; 1440 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1441 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1442 } 1443 db_tr = dbch->top; 1444 for (idb = 0; idb < dbch->ndb; idb ++) { 1445 fwohci_add_tx_buf(dbch, db_tr, idb); 1446 if(STAILQ_NEXT(db_tr, link) == NULL){ 1447 break; 1448 } 1449 db = db_tr->db; 1450 ldesc = db_tr->dbcnt - 1; 1451 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1452 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1453 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1454 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1455 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1456 FWOHCI_DMA_SET( 1457 db[ldesc].db.desc.cmd, 1458 OHCI_INTERRUPT_ALWAYS); 1459 /* OHCI 1.1 and above */ 1460 FWOHCI_DMA_SET( 1461 db[0].db.desc.cmd, 1462 OHCI_INTERRUPT_ALWAYS); 1463 } 1464 } 1465 db_tr = STAILQ_NEXT(db_tr, link); 1466 } 1467 FWOHCI_DMA_CLEAR( 1468 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1469 return err; 1470 } 1471 1472 static int 1473 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1474 { 1475 int err = 0; 1476 int idb, z, i, dmach = 0, ldesc; 1477 uint32_t off = 0; 1478 struct fwohcidb_tr *db_tr; 1479 struct fwohcidb *db; 1480 1481 z = dbch->ndesc; 1482 if(&sc->arrq == dbch){ 1483 off = OHCI_ARQOFF; 1484 }else if(&sc->arrs == dbch){ 1485 off = OHCI_ARSOFF; 1486 }else{ 1487 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1488 if( &sc->ir[dmach] == dbch){ 1489 off = OHCI_IROFF(dmach); 1490 break; 1491 } 1492 } 1493 } 1494 if(off == 0){ 1495 err = EINVAL; 1496 return err; 1497 } 1498 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1499 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1500 return err; 1501 }else{ 1502 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1503 err = EBUSY; 1504 return err; 1505 } 1506 } 1507 dbch->xferq.flag |= FWXFERQ_RUNNING; 1508 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1509 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1510 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1511 } 1512 db_tr = dbch->top; 1513 for (idb = 0; idb < dbch->ndb; idb ++) { 1514 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1515 if (STAILQ_NEXT(db_tr, link) == NULL) 1516 break; 1517 db = db_tr->db; 1518 ldesc = db_tr->dbcnt - 1; 1519 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1520 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1521 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1522 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1523 FWOHCI_DMA_SET( 1524 db[ldesc].db.desc.cmd, 1525 OHCI_INTERRUPT_ALWAYS); 1526 FWOHCI_DMA_CLEAR( 1527 db[ldesc].db.desc.depend, 1528 0xf); 1529 } 1530 } 1531 db_tr = STAILQ_NEXT(db_tr, link); 1532 } 1533 FWOHCI_DMA_CLEAR( 1534 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1535 dbch->buf_offset = 0; 1536 fwdma_sync_multiseg_all(dbch->am, 1537 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1538 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1539 return err; 1540 }else{ 1541 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1542 } 1543 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1544 return err; 1545 } 1546 1547 static int 1548 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1549 { 1550 int sec, cycle, cycle_match; 1551 1552 cycle = cycle_now & 0x1fff; 1553 sec = cycle_now >> 13; 1554 #define CYCLE_MOD 0x10 1555 #if 1 1556 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1557 #else 1558 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1559 #endif 1560 cycle = cycle + CYCLE_DELAY; 1561 if (cycle >= 8000) { 1562 sec ++; 1563 cycle -= 8000; 1564 } 1565 cycle = roundup2(cycle, CYCLE_MOD); 1566 if (cycle >= 8000) { 1567 sec ++; 1568 if (cycle == 8000) 1569 cycle = 0; 1570 else 1571 cycle = CYCLE_MOD; 1572 } 1573 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1574 1575 return(cycle_match); 1576 } 1577 1578 static int 1579 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1580 { 1581 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1582 int err = 0; 1583 unsigned short tag, ich; 1584 struct fwohci_dbch *dbch; 1585 int cycle_match, cycle_now, s, ldesc; 1586 uint32_t stat; 1587 struct fw_bulkxfer *first, *chunk, *prev; 1588 struct fw_xferq *it; 1589 1590 dbch = &sc->it[dmach]; 1591 it = &dbch->xferq; 1592 1593 tag = (it->flag >> 6) & 3; 1594 ich = it->flag & 0x3f; 1595 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1596 dbch->ndb = it->bnpacket * it->bnchunk; 1597 dbch->ndesc = 3; 1598 fwohci_db_init(sc, dbch); 1599 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1600 return ENOMEM; 1601 err = fwohci_tx_enable(sc, dbch); 1602 } 1603 if(err) 1604 return err; 1605 1606 ldesc = dbch->ndesc - 1; 1607 s = splfw(); 1608 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1609 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1610 struct fwohcidb *db; 1611 1612 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1613 BUS_DMASYNC_PREWRITE); 1614 fwohci_txbufdb(sc, dmach, chunk); 1615 if (prev != NULL) { 1616 db = ((struct fwohcidb_tr *)(prev->end))->db; 1617 #if 0 /* XXX necessary? */ 1618 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1619 OHCI_BRANCH_ALWAYS); 1620 #endif 1621 #if 0 /* if bulkxfer->npacket changes */ 1622 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1623 ((struct fwohcidb_tr *) 1624 (chunk->start))->bus_addr | dbch->ndesc; 1625 #else 1626 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1627 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1628 #endif 1629 } 1630 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1631 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1632 prev = chunk; 1633 } 1634 fwdma_sync_multiseg_all(dbch->am, 1635 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1636 splx(s); 1637 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1638 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1639 printf("stat 0x%x\n", stat); 1640 1641 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1642 return 0; 1643 1644 #if 0 1645 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1646 #endif 1647 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1648 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1649 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1650 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1651 1652 first = STAILQ_FIRST(&it->stdma); 1653 OWRITE(sc, OHCI_ITCMD(dmach), 1654 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1655 if (firewire_debug > 1) { 1656 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1657 #if 1 1658 dump_dma(sc, ITX_CH + dmach); 1659 #endif 1660 } 1661 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1662 #if 1 1663 /* Don't start until all chunks are buffered */ 1664 if (STAILQ_FIRST(&it->stfree) != NULL) 1665 goto out; 1666 #endif 1667 #if 1 1668 /* Clear cycle match counter bits */ 1669 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1670 1671 /* 2bit second + 13bit cycle */ 1672 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1673 cycle_match = fwohci_next_cycle(fc, cycle_now); 1674 1675 OWRITE(sc, OHCI_ITCTL(dmach), 1676 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1677 | OHCI_CNTL_DMA_RUN); 1678 #else 1679 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1680 #endif 1681 if (firewire_debug > 1) { 1682 printf("cycle_match: 0x%04x->0x%04x\n", 1683 cycle_now, cycle_match); 1684 dump_dma(sc, ITX_CH + dmach); 1685 dump_db(sc, ITX_CH + dmach); 1686 } 1687 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1688 device_printf(sc->fc.dev, 1689 "IT DMA underrun (0x%08x)\n", stat); 1690 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1691 } 1692 out: 1693 return err; 1694 } 1695 1696 static int 1697 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1698 { 1699 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1700 int err = 0, s, ldesc; 1701 unsigned short tag, ich; 1702 uint32_t stat; 1703 struct fwohci_dbch *dbch; 1704 struct fwohcidb_tr *db_tr; 1705 struct fw_bulkxfer *first, *prev, *chunk; 1706 struct fw_xferq *ir; 1707 1708 dbch = &sc->ir[dmach]; 1709 ir = &dbch->xferq; 1710 1711 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1712 tag = (ir->flag >> 6) & 3; 1713 ich = ir->flag & 0x3f; 1714 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1715 1716 ir->queued = 0; 1717 dbch->ndb = ir->bnpacket * ir->bnchunk; 1718 dbch->ndesc = 2; 1719 fwohci_db_init(sc, dbch); 1720 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1721 return ENOMEM; 1722 err = fwohci_rx_enable(sc, dbch); 1723 } 1724 if(err) 1725 return err; 1726 1727 first = STAILQ_FIRST(&ir->stfree); 1728 if (first == NULL) { 1729 device_printf(fc->dev, "IR DMA no free chunk\n"); 1730 return 0; 1731 } 1732 1733 ldesc = dbch->ndesc - 1; 1734 s = splfw(); 1735 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1736 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1737 struct fwohcidb *db; 1738 1739 #if 1 /* XXX for if_fwe */ 1740 if (chunk->mbuf != NULL) { 1741 db_tr = (struct fwohcidb_tr *)(chunk->start); 1742 db_tr->dbcnt = 1; 1743 err = fw_bus_dmamap_load_mbuf( 1744 dbch->dmat, db_tr->dma_map, 1745 chunk->mbuf, fwohci_execute_db2, db_tr, 1746 BUS_DMA_WAITOK); 1747 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1748 OHCI_UPDATE | OHCI_INPUT_LAST | 1749 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1750 } 1751 #endif 1752 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1753 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1754 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1755 if (prev != NULL) { 1756 db = ((struct fwohcidb_tr *)(prev->end))->db; 1757 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1758 } 1759 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1760 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1761 prev = chunk; 1762 } 1763 fwdma_sync_multiseg_all(dbch->am, 1764 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1765 splx(s); 1766 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1767 if (stat & OHCI_CNTL_DMA_ACTIVE) 1768 return 0; 1769 if (stat & OHCI_CNTL_DMA_RUN) { 1770 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1771 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1772 } 1773 1774 if (firewire_debug) 1775 printf("start IR DMA 0x%x\n", stat); 1776 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1777 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1778 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1779 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1780 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1781 OWRITE(sc, OHCI_IRCMD(dmach), 1782 ((struct fwohcidb_tr *)(first->start))->bus_addr 1783 | dbch->ndesc); 1784 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1785 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1786 #if 0 1787 dump_db(sc, IRX_CH + dmach); 1788 #endif 1789 return err; 1790 } 1791 1792 FWOHCI_STOP() 1793 { 1794 FWOHCI_STOP_START; 1795 u_int i; 1796 1797 /* Now stopping all DMA channel */ 1798 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1799 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1800 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1801 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1802 1803 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1804 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1805 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1806 } 1807 1808 /* FLUSH FIFO and reset Transmitter/Reciever */ 1809 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1810 1811 /* Stop interrupt */ 1812 OWRITE(sc, FWOHCI_INTMASKCLR, 1813 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1814 | OHCI_INT_PHY_INT 1815 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1816 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1817 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1818 | OHCI_INT_PHY_BUS_R); 1819 1820 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1821 fw_drain_txq(&sc->fc); 1822 1823 /* XXX Link down? Bus reset? */ 1824 FWOHCI_STOP_RETURN(0); 1825 } 1826 1827 #if defined(__NetBSD__) 1828 static void 1829 fwohci_power(int why, void *arg) 1830 { 1831 struct fwohci_softc *sc = arg; 1832 int s; 1833 1834 s = splbio(); 1835 switch (why) { 1836 case PWR_SUSPEND: 1837 case PWR_STANDBY: 1838 fwohci_stop(arg); 1839 break; 1840 case PWR_RESUME: 1841 fwohci_resume(sc, sc->fc.dev); 1842 break; 1843 case PWR_SOFTSUSPEND: 1844 case PWR_SOFTSTANDBY: 1845 case PWR_SOFTRESUME: 1846 break; 1847 } 1848 splx(s); 1849 } 1850 #endif 1851 1852 int 1853 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1854 { 1855 int i; 1856 struct fw_xferq *ir; 1857 struct fw_bulkxfer *chunk; 1858 1859 fwohci_reset(sc, dev); 1860 /* XXX resume isochronous receive automatically. (how about TX?) */ 1861 for(i = 0; i < sc->fc.nisodma; i ++) { 1862 ir = &sc->ir[i].xferq; 1863 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1864 device_printf(sc->fc.dev, 1865 "resume iso receive ch: %d\n", i); 1866 ir->flag &= ~FWXFERQ_RUNNING; 1867 /* requeue stdma to stfree */ 1868 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1869 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1870 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1871 } 1872 sc->fc.irx_enable(&sc->fc, i); 1873 } 1874 } 1875 1876 #if defined(__FreeBSD__) 1877 bus_generic_resume(dev); 1878 #endif 1879 sc->fc.ibr(&sc->fc); 1880 return 0; 1881 } 1882 1883 #define ACK_ALL 1884 static void 1885 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1886 { 1887 uint32_t irstat, itstat; 1888 u_int i; 1889 struct firewire_comm *fc = (struct firewire_comm *)sc; 1890 1891 CTR0(KTR_DEV, "fwohci_intr_body"); 1892 #ifdef OHCI_DEBUG 1893 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1894 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1895 stat & OHCI_INT_EN ? "DMA_EN ":"", 1896 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1897 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1898 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1899 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1900 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1901 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1902 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1903 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1904 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1905 stat & OHCI_INT_PHY_SID ? "SID ":"", 1906 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1907 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1908 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1909 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1910 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1911 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1912 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1913 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1914 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1915 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1916 stat, OREAD(sc, FWOHCI_INTMASK) 1917 ); 1918 #endif 1919 /* Bus reset */ 1920 if(stat & OHCI_INT_PHY_BUS_R ){ 1921 if (fc->status == FWBUSRESET) 1922 goto busresetout; 1923 /* Disable bus reset interrupt until sid recv. */ 1924 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1925 1926 device_printf(fc->dev, "BUS reset\n"); 1927 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1928 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1929 1930 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1931 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1932 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1933 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1934 1935 #ifndef ACK_ALL 1936 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1937 #endif 1938 fw_busreset(fc); 1939 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1940 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1941 } 1942 busresetout: 1943 if((stat & OHCI_INT_DMA_IR )){ 1944 #ifndef ACK_ALL 1945 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1946 #endif 1947 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1948 irstat = sc->irstat; 1949 sc->irstat = 0; 1950 #else 1951 irstat = atomic_readandclear_int(&sc->irstat); 1952 #endif 1953 for(i = 0; i < fc->nisodma ; i++){ 1954 struct fwohci_dbch *dbch; 1955 1956 if((irstat & (1 << i)) != 0){ 1957 dbch = &sc->ir[i]; 1958 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1959 device_printf(sc->fc.dev, 1960 "dma(%d) not active\n", i); 1961 continue; 1962 } 1963 fwohci_rbuf_update(sc, i); 1964 } 1965 } 1966 } 1967 if((stat & OHCI_INT_DMA_IT )){ 1968 #ifndef ACK_ALL 1969 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1970 #endif 1971 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1972 itstat = sc->itstat; 1973 sc->itstat = 0; 1974 #else 1975 itstat = atomic_readandclear_int(&sc->itstat); 1976 #endif 1977 for(i = 0; i < fc->nisodma ; i++){ 1978 if((itstat & (1 << i)) != 0){ 1979 fwohci_tbuf_update(sc, i); 1980 } 1981 } 1982 } 1983 if((stat & OHCI_INT_DMA_PRRS )){ 1984 #ifndef ACK_ALL 1985 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1986 #endif 1987 #if 0 1988 dump_dma(sc, ARRS_CH); 1989 dump_db(sc, ARRS_CH); 1990 #endif 1991 fwohci_arcv(sc, &sc->arrs, count); 1992 } 1993 if((stat & OHCI_INT_DMA_PRRQ )){ 1994 #ifndef ACK_ALL 1995 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1996 #endif 1997 #if 0 1998 dump_dma(sc, ARRQ_CH); 1999 dump_db(sc, ARRQ_CH); 2000 #endif 2001 fwohci_arcv(sc, &sc->arrq, count); 2002 } 2003 if (stat & OHCI_INT_CYC_LOST) { 2004 if (sc->cycle_lost >= 0) 2005 sc->cycle_lost ++; 2006 if (sc->cycle_lost > 10) { 2007 sc->cycle_lost = -1; 2008 #if 0 2009 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2010 #endif 2011 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2012 device_printf(fc->dev, "too many cycle lost, " 2013 "no cycle master presents?\n"); 2014 } 2015 } 2016 if(stat & OHCI_INT_PHY_SID){ 2017 uint32_t *buf, node_id; 2018 int plen; 2019 2020 #ifndef ACK_ALL 2021 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2022 #endif 2023 /* Enable bus reset interrupt */ 2024 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2025 /* Allow async. request to us */ 2026 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2027 /* XXX insecure ?? */ 2028 /* allow from all nodes */ 2029 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2030 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2031 /* 0 to 4GB regison */ 2032 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2033 /* Set ATRetries register */ 2034 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2035 /* 2036 ** Checking whether the node is root or not. If root, turn on 2037 ** cycle master. 2038 */ 2039 node_id = OREAD(sc, FWOHCI_NODEID); 2040 plen = OREAD(sc, OHCI_SID_CNT); 2041 2042 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2043 node_id, (plen >> 16) & 0xff); 2044 if (!(node_id & OHCI_NODE_VALID)) { 2045 printf("Bus reset failure\n"); 2046 goto sidout; 2047 } 2048 2049 /* cycle timer */ 2050 sc->cycle_lost = 0; 2051 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2052 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2053 printf("CYCLEMASTER mode\n"); 2054 OWRITE(sc, OHCI_LNKCTL, 2055 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2056 } else { 2057 printf("non CYCLEMASTER mode\n"); 2058 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2059 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2060 } 2061 2062 fc->nodeid = node_id & 0x3f; 2063 2064 if (plen & OHCI_SID_ERR) { 2065 device_printf(fc->dev, "SID Error\n"); 2066 goto sidout; 2067 } 2068 plen &= OHCI_SID_CNT_MASK; 2069 if (plen < 4 || plen > OHCI_SIDSIZE) { 2070 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2071 goto sidout; 2072 } 2073 plen -= 4; /* chop control info */ 2074 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2075 if (buf == NULL) { 2076 device_printf(fc->dev, "malloc failed\n"); 2077 goto sidout; 2078 } 2079 for (i = 0; i < plen / 4; i ++) 2080 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2081 #if defined(__NetBSD__) && defined(macppc) 2082 /* XXX required as bootdisk for macppc. */ 2083 delay(500000); 2084 #endif 2085 #if 1 /* XXX needed?? */ 2086 /* pending all pre-bus_reset packets */ 2087 fwohci_txd(sc, &sc->atrq); 2088 fwohci_txd(sc, &sc->atrs); 2089 fwohci_arcv(sc, &sc->arrs, -1); 2090 fwohci_arcv(sc, &sc->arrq, -1); 2091 fw_drain_txq(fc); 2092 #endif 2093 fw_sidrcv(fc, buf, plen); 2094 free(buf, M_FW); 2095 } 2096 sidout: 2097 if((stat & OHCI_INT_DMA_ATRQ )){ 2098 #ifndef ACK_ALL 2099 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2100 #endif 2101 fwohci_txd(sc, &(sc->atrq)); 2102 } 2103 if((stat & OHCI_INT_DMA_ATRS )){ 2104 #ifndef ACK_ALL 2105 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2106 #endif 2107 fwohci_txd(sc, &(sc->atrs)); 2108 } 2109 if((stat & OHCI_INT_PW_ERR )){ 2110 #ifndef ACK_ALL 2111 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2112 #endif 2113 device_printf(fc->dev, "posted write error\n"); 2114 } 2115 if((stat & OHCI_INT_ERR )){ 2116 #ifndef ACK_ALL 2117 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2118 #endif 2119 device_printf(fc->dev, "unrecoverable error\n"); 2120 } 2121 if((stat & OHCI_INT_PHY_INT)) { 2122 #ifndef ACK_ALL 2123 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2124 #endif 2125 device_printf(fc->dev, "phy int\n"); 2126 } 2127 2128 CTR0(KTR_DEV, "fwohci_intr_body done"); 2129 return; 2130 } 2131 2132 #if FWOHCI_TASKQUEUE 2133 static void 2134 fwohci_complete(void *arg, int pending) 2135 { 2136 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2137 uint32_t stat; 2138 2139 again: 2140 stat = atomic_readandclear_int(&sc->intstat); 2141 if (stat) { 2142 FW_LOCK; 2143 fwohci_intr_body(sc, stat, -1); 2144 FW_UNLOCK; 2145 } else 2146 return; 2147 goto again; 2148 } 2149 #endif 2150 2151 static uint32_t 2152 fwochi_check_stat(struct fwohci_softc *sc) 2153 { 2154 uint32_t stat, irstat, itstat; 2155 2156 stat = OREAD(sc, FWOHCI_INTSTAT); 2157 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2158 if (stat == 0xffffffff) { 2159 device_printf(sc->fc.dev, 2160 "device physically ejected?\n"); 2161 return(stat); 2162 } 2163 #ifdef ACK_ALL 2164 if (stat) 2165 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2166 #endif 2167 if (stat & OHCI_INT_DMA_IR) { 2168 irstat = OREAD(sc, OHCI_IR_STAT); 2169 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2170 atomic_set_int(&sc->irstat, irstat); 2171 } 2172 if (stat & OHCI_INT_DMA_IT) { 2173 itstat = OREAD(sc, OHCI_IT_STAT); 2174 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2175 atomic_set_int(&sc->itstat, itstat); 2176 } 2177 return(stat); 2178 } 2179 2180 FW_INTR(fwohci) 2181 { 2182 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2183 uint32_t stat; 2184 #if !FWOHCI_TASKQUEUE 2185 uint32_t bus_reset = 0; 2186 #endif 2187 2188 if (!(sc->intmask & OHCI_INT_EN)) { 2189 /* polling mode */ 2190 FW_INTR_RETURN(0); 2191 } 2192 2193 #if !FWOHCI_TASKQUEUE 2194 again: 2195 #endif 2196 CTR0(KTR_DEV, "fwohci_intr"); 2197 stat = fwochi_check_stat(sc); 2198 if (stat == 0 || stat == 0xffffffff) 2199 FW_INTR_RETURN(1); 2200 #if FWOHCI_TASKQUEUE 2201 atomic_set_int(&sc->intstat, stat); 2202 /* XXX mask bus reset intr. during bus reset phase */ 2203 if (stat) 2204 #if 1 2205 taskqueue_enqueue_fast(taskqueue_fast, 2206 &sc->fwohci_task_complete); 2207 #else 2208 taskqueue_enqueue(taskqueue_swi, 2209 &sc->fwohci_task_complete); 2210 #endif 2211 #else 2212 /* We cannot clear bus reset event during bus reset phase */ 2213 if ((stat & ~bus_reset) == 0) 2214 FW_INTR_RETURN(1); 2215 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2216 fwohci_intr_body(sc, stat, -1); 2217 goto again; 2218 #endif 2219 CTR0(KTR_DEV, "fwohci_intr end"); 2220 } 2221 2222 void 2223 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2224 { 2225 int s; 2226 uint32_t stat; 2227 struct fwohci_softc *sc; 2228 2229 2230 sc = (struct fwohci_softc *)fc; 2231 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2232 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2233 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2234 #if 0 2235 if (!quick) { 2236 #else 2237 if (1) { 2238 #endif 2239 stat = fwochi_check_stat(sc); 2240 if (stat == 0 || stat == 0xffffffff) 2241 return; 2242 } 2243 s = splfw(); 2244 fwohci_intr_body(sc, stat, count); 2245 splx(s); 2246 } 2247 2248 static void 2249 fwohci_set_intr(struct firewire_comm *fc, int enable) 2250 { 2251 struct fwohci_softc *sc; 2252 2253 sc = (struct fwohci_softc *)fc; 2254 if (firewire_debug) 2255 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2256 if (enable) { 2257 sc->intmask |= OHCI_INT_EN; 2258 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2259 } else { 2260 sc->intmask &= ~OHCI_INT_EN; 2261 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2262 } 2263 } 2264 2265 static void 2266 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2267 { 2268 struct firewire_comm *fc = &sc->fc; 2269 struct fwohcidb *db; 2270 struct fw_bulkxfer *chunk; 2271 struct fw_xferq *it; 2272 uint32_t stat, count; 2273 int s, w=0, ldesc; 2274 2275 it = fc->it[dmach]; 2276 ldesc = sc->it[dmach].ndesc - 1; 2277 s = splfw(); /* unnecessary ? */ 2278 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2279 if (firewire_debug) 2280 dump_db(sc, ITX_CH + dmach); 2281 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2282 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2283 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2284 >> OHCI_STATUS_SHIFT; 2285 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2286 /* timestamp */ 2287 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2288 & OHCI_COUNT_MASK; 2289 if (stat == 0) 2290 break; 2291 STAILQ_REMOVE_HEAD(&it->stdma, link); 2292 switch (stat & FWOHCIEV_MASK){ 2293 case FWOHCIEV_ACKCOMPL: 2294 #if 0 2295 device_printf(fc->dev, "0x%08x\n", count); 2296 #endif 2297 break; 2298 default: 2299 device_printf(fc->dev, 2300 "Isochronous transmit err %02x(%s)\n", 2301 stat, fwohcicode[stat & 0x1f]); 2302 } 2303 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2304 w++; 2305 } 2306 splx(s); 2307 if (w) 2308 wakeup(it); 2309 } 2310 2311 static void 2312 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2313 { 2314 struct firewire_comm *fc = &sc->fc; 2315 struct fwohcidb_tr *db_tr; 2316 struct fw_bulkxfer *chunk; 2317 struct fw_xferq *ir; 2318 uint32_t stat; 2319 int s, w=0, ldesc; 2320 2321 ir = fc->ir[dmach]; 2322 ldesc = sc->ir[dmach].ndesc - 1; 2323 #if 0 2324 dump_db(sc, dmach); 2325 #endif 2326 s = splfw(); 2327 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2328 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2329 db_tr = (struct fwohcidb_tr *)chunk->end; 2330 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2331 >> OHCI_STATUS_SHIFT; 2332 if (stat == 0) 2333 break; 2334 2335 if (chunk->mbuf != NULL) { 2336 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2337 BUS_DMASYNC_POSTREAD); 2338 fw_bus_dmamap_unload( 2339 sc->ir[dmach].dmat, db_tr->dma_map); 2340 } else if (ir->buf != NULL) { 2341 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2342 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2343 } else { 2344 /* XXX */ 2345 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2346 } 2347 2348 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2349 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2350 switch (stat & FWOHCIEV_MASK) { 2351 case FWOHCIEV_ACKCOMPL: 2352 chunk->resp = 0; 2353 break; 2354 default: 2355 chunk->resp = EINVAL; 2356 device_printf(fc->dev, 2357 "Isochronous receive err %02x(%s)\n", 2358 stat, fwohcicode[stat & 0x1f]); 2359 } 2360 w++; 2361 } 2362 splx(s); 2363 if (w) { 2364 if (ir->flag & FWXFERQ_HANDLER) 2365 ir->hand(ir); 2366 else 2367 wakeup(ir); 2368 } 2369 } 2370 2371 void 2372 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2373 { 2374 uint32_t off, cntl, stat, cmd, match; 2375 2376 if(ch == 0){ 2377 off = OHCI_ATQOFF; 2378 }else if(ch == 1){ 2379 off = OHCI_ATSOFF; 2380 }else if(ch == 2){ 2381 off = OHCI_ARQOFF; 2382 }else if(ch == 3){ 2383 off = OHCI_ARSOFF; 2384 }else if(ch < IRX_CH){ 2385 off = OHCI_ITCTL(ch - ITX_CH); 2386 }else{ 2387 off = OHCI_IRCTL(ch - IRX_CH); 2388 } 2389 cntl = stat = OREAD(sc, off); 2390 cmd = OREAD(sc, off + 0xc); 2391 match = OREAD(sc, off + 0x10); 2392 2393 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2394 ch, 2395 cntl, 2396 cmd, 2397 match); 2398 stat &= 0xffff ; 2399 if (stat) { 2400 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2401 ch, 2402 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2403 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2404 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2405 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2406 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2407 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2408 fwohcicode[stat & 0x1f], 2409 stat & 0x1f 2410 ); 2411 }else{ 2412 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2413 } 2414 } 2415 2416 void 2417 dump_db(struct fwohci_softc *sc, uint32_t ch) 2418 { 2419 struct fwohci_dbch *dbch; 2420 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2421 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2422 int idb, jdb; 2423 uint32_t cmd, off; 2424 if(ch == 0){ 2425 off = OHCI_ATQOFF; 2426 dbch = &sc->atrq; 2427 }else if(ch == 1){ 2428 off = OHCI_ATSOFF; 2429 dbch = &sc->atrs; 2430 }else if(ch == 2){ 2431 off = OHCI_ARQOFF; 2432 dbch = &sc->arrq; 2433 }else if(ch == 3){ 2434 off = OHCI_ARSOFF; 2435 dbch = &sc->arrs; 2436 }else if(ch < IRX_CH){ 2437 off = OHCI_ITCTL(ch - ITX_CH); 2438 dbch = &sc->it[ch - ITX_CH]; 2439 }else { 2440 off = OHCI_IRCTL(ch - IRX_CH); 2441 dbch = &sc->ir[ch - IRX_CH]; 2442 } 2443 cmd = OREAD(sc, off + 0xc); 2444 2445 if( dbch->ndb == 0 ){ 2446 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2447 return; 2448 } 2449 pp = dbch->top; 2450 prev = pp->db; 2451 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2452 cp = STAILQ_NEXT(pp, link); 2453 if(cp == NULL){ 2454 curr = NULL; 2455 goto outdb; 2456 } 2457 np = STAILQ_NEXT(cp, link); 2458 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2459 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2460 curr = cp->db; 2461 if(np != NULL){ 2462 next = np->db; 2463 }else{ 2464 next = NULL; 2465 } 2466 goto outdb; 2467 } 2468 } 2469 pp = STAILQ_NEXT(pp, link); 2470 if(pp == NULL){ 2471 curr = NULL; 2472 goto outdb; 2473 } 2474 prev = pp->db; 2475 } 2476 outdb: 2477 if( curr != NULL){ 2478 #if 0 2479 printf("Prev DB %d\n", ch); 2480 print_db(pp, prev, ch, dbch->ndesc); 2481 #endif 2482 printf("Current DB %d\n", ch); 2483 print_db(cp, curr, ch, dbch->ndesc); 2484 #if 0 2485 printf("Next DB %d\n", ch); 2486 print_db(np, next, ch, dbch->ndesc); 2487 #endif 2488 }else{ 2489 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2490 } 2491 return; 2492 } 2493 2494 void 2495 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2496 uint32_t ch, uint32_t hogemax) 2497 { 2498 fwohcireg_t stat; 2499 int i, key; 2500 uint32_t cmd, res; 2501 2502 if(db == NULL){ 2503 printf("No Descriptor is found\n"); 2504 return; 2505 } 2506 2507 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2508 ch, 2509 "Current", 2510 "OP ", 2511 "KEY", 2512 "INT", 2513 "BR ", 2514 "len", 2515 "Addr", 2516 "Depend", 2517 "Stat", 2518 "Cnt"); 2519 for( i = 0 ; i <= hogemax ; i ++){ 2520 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2521 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2522 key = cmd & OHCI_KEY_MASK; 2523 stat = res >> OHCI_STATUS_SHIFT; 2524 #if defined(__DragonFly__) || \ 2525 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2526 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2527 db_tr->bus_addr, 2528 #else 2529 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2530 (uintmax_t)db_tr->bus_addr, 2531 #endif 2532 dbcode[(cmd >> 28) & 0xf], 2533 dbkey[(cmd >> 24) & 0x7], 2534 dbcond[(cmd >> 20) & 0x3], 2535 dbcond[(cmd >> 18) & 0x3], 2536 cmd & OHCI_COUNT_MASK, 2537 FWOHCI_DMA_READ(db[i].db.desc.addr), 2538 FWOHCI_DMA_READ(db[i].db.desc.depend), 2539 stat, 2540 res & OHCI_COUNT_MASK); 2541 if(stat & 0xff00){ 2542 printf(" %s%s%s%s%s%s %s(%x)\n", 2543 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2544 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2545 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2546 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2547 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2548 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2549 fwohcicode[stat & 0x1f], 2550 stat & 0x1f 2551 ); 2552 }else{ 2553 printf(" Nostat\n"); 2554 } 2555 if(key == OHCI_KEY_ST2 ){ 2556 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2557 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2558 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2559 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2560 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2561 } 2562 if(key == OHCI_KEY_DEVICE){ 2563 return; 2564 } 2565 if((cmd & OHCI_BRANCH_MASK) 2566 == OHCI_BRANCH_ALWAYS){ 2567 return; 2568 } 2569 if((cmd & OHCI_CMD_MASK) 2570 == OHCI_OUTPUT_LAST){ 2571 return; 2572 } 2573 if((cmd & OHCI_CMD_MASK) 2574 == OHCI_INPUT_LAST){ 2575 return; 2576 } 2577 if(key == OHCI_KEY_ST2 ){ 2578 i++; 2579 } 2580 } 2581 return; 2582 } 2583 2584 void 2585 fwohci_ibr(struct firewire_comm *fc) 2586 { 2587 struct fwohci_softc *sc; 2588 uint32_t fun; 2589 2590 device_printf(fc->dev, "Initiate bus reset\n"); 2591 sc = (struct fwohci_softc *)fc; 2592 2593 /* 2594 * Make sure our cached values from the config rom are 2595 * initialised. 2596 */ 2597 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2598 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2599 2600 /* 2601 * Set root hold-off bit so that non cyclemaster capable node 2602 * shouldn't became the root node. 2603 */ 2604 #if 1 2605 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2606 fun |= FW_PHY_IBR | FW_PHY_RHB; 2607 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2608 #else /* Short bus reset */ 2609 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2610 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2611 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2612 #endif 2613 } 2614 2615 void 2616 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2617 { 2618 struct fwohcidb_tr *db_tr, *fdb_tr; 2619 struct fwohci_dbch *dbch; 2620 struct fwohcidb *db; 2621 struct fw_pkt *fp; 2622 struct fwohci_txpkthdr *ohcifp; 2623 unsigned short chtag; 2624 int idb; 2625 2626 dbch = &sc->it[dmach]; 2627 chtag = sc->it[dmach].xferq.flag & 0xff; 2628 2629 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2630 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2631 /* 2632 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2633 */ 2634 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2635 db = db_tr->db; 2636 fp = (struct fw_pkt *)db_tr->buf; 2637 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2638 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2639 ohcifp->mode.common.spd = 0 & 0x7; 2640 ohcifp->mode.stream.len = fp->mode.stream.len; 2641 ohcifp->mode.stream.chtag = chtag; 2642 ohcifp->mode.stream.tcode = 0xa; 2643 #if BYTE_ORDER == BIG_ENDIAN 2644 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2645 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2646 #endif 2647 2648 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2649 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2650 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2651 #if 0 /* if bulkxfer->npackets changes */ 2652 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2653 | OHCI_UPDATE 2654 | OHCI_BRANCH_ALWAYS; 2655 db[0].db.desc.depend = 2656 = db[dbch->ndesc - 1].db.desc.depend 2657 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2658 #else 2659 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2660 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2661 #endif 2662 bulkxfer->end = (caddr_t)db_tr; 2663 db_tr = STAILQ_NEXT(db_tr, link); 2664 } 2665 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2666 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2667 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2668 #if 0 /* if bulkxfer->npackets changes */ 2669 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2670 /* OHCI 1.1 and above */ 2671 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2672 #endif 2673 /* 2674 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2675 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2676 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2677 */ 2678 return; 2679 } 2680 2681 static int 2682 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2683 int poffset) 2684 { 2685 struct fwohcidb *db = db_tr->db; 2686 struct fw_xferq *it; 2687 int err = 0; 2688 2689 it = &dbch->xferq; 2690 if(it->buf == 0){ 2691 err = EINVAL; 2692 return err; 2693 } 2694 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2695 db_tr->dbcnt = 3; 2696 2697 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2698 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2699 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2700 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2701 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2702 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2703 2704 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2705 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2706 #if 1 2707 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2708 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2709 #endif 2710 return 0; 2711 } 2712 2713 int 2714 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2715 int poffset, struct fwdma_alloc *dummy_dma) 2716 { 2717 struct fwohcidb *db = db_tr->db; 2718 struct fw_xferq *ir; 2719 int i, ldesc; 2720 bus_addr_t dbuf[2]; 2721 int dsiz[2]; 2722 2723 ir = &dbch->xferq; 2724 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2725 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2726 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2727 if (db_tr->buf == NULL) 2728 return(ENOMEM); 2729 db_tr->dbcnt = 1; 2730 dsiz[0] = ir->psize; 2731 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2732 BUS_DMASYNC_PREREAD); 2733 } else { 2734 db_tr->dbcnt = 0; 2735 if (dummy_dma != NULL) { 2736 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2737 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2738 } 2739 dsiz[db_tr->dbcnt] = ir->psize; 2740 if (ir->buf != NULL) { 2741 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2742 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2743 } 2744 db_tr->dbcnt++; 2745 } 2746 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2747 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2748 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2749 if (ir->flag & FWXFERQ_STREAM) { 2750 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2751 } 2752 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2753 } 2754 ldesc = db_tr->dbcnt - 1; 2755 if (ir->flag & FWXFERQ_STREAM) { 2756 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2757 } 2758 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2759 return 0; 2760 } 2761 2762 2763 static int 2764 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2765 { 2766 struct fw_pkt *fp0; 2767 uint32_t ld0; 2768 int slen, hlen; 2769 #if BYTE_ORDER == BIG_ENDIAN 2770 int i; 2771 #endif 2772 2773 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2774 #if 0 2775 printf("ld0: x%08x\n", ld0); 2776 #endif 2777 fp0 = (struct fw_pkt *)&ld0; 2778 /* determine length to swap */ 2779 switch (fp0->mode.common.tcode) { 2780 case FWTCODE_WRES: 2781 CTR0(KTR_DEV, "WRES"); 2782 case FWTCODE_RREQQ: 2783 case FWTCODE_WREQQ: 2784 case FWTCODE_RRESQ: 2785 case FWOHCITCODE_PHY: 2786 slen = 12; 2787 break; 2788 case FWTCODE_RREQB: 2789 case FWTCODE_WREQB: 2790 case FWTCODE_LREQ: 2791 case FWTCODE_RRESB: 2792 case FWTCODE_LRES: 2793 slen = 16; 2794 break; 2795 default: 2796 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2797 return(0); 2798 } 2799 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2800 if (hlen > len) { 2801 if (firewire_debug) 2802 printf("splitted header\n"); 2803 return(-hlen); 2804 } 2805 #if BYTE_ORDER == BIG_ENDIAN 2806 for(i = 0; i < slen/4; i ++) 2807 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2808 #endif 2809 return(hlen); 2810 } 2811 2812 static int 2813 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2814 { 2815 const struct tcode_info *info; 2816 int r; 2817 2818 info = &tinfo[fp->mode.common.tcode]; 2819 r = info->hdr_len + sizeof(uint32_t); 2820 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2821 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2822 2823 if (r == sizeof(uint32_t)) { 2824 /* XXX */ 2825 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2826 fp->mode.common.tcode); 2827 return (-1); 2828 } 2829 2830 if (r > dbch->xferq.psize) { 2831 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2832 return (-1); 2833 /* panic ? */ 2834 } 2835 2836 return r; 2837 } 2838 2839 static void 2840 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2841 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2842 { 2843 struct fwohcidb *db = &db_tr->db[0]; 2844 2845 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2846 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2847 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2848 fwdma_sync_multiseg_all(dbch->am, 2849 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2850 dbch->bottom = db_tr; 2851 2852 if (wake) 2853 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2854 } 2855 2856 static void 2857 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2858 { 2859 struct fwohcidb_tr *db_tr; 2860 struct iovec vec[2]; 2861 struct fw_pkt pktbuf; 2862 int nvec; 2863 struct fw_pkt *fp; 2864 uint8_t *ld; 2865 uint32_t stat, off, status, event; 2866 u_int spd; 2867 int len, plen, hlen, pcnt, offset; 2868 int s; 2869 caddr_t buf; 2870 int resCount; 2871 2872 CTR0(KTR_DEV, "fwohci_arv"); 2873 2874 if(&sc->arrq == dbch){ 2875 off = OHCI_ARQOFF; 2876 }else if(&sc->arrs == dbch){ 2877 off = OHCI_ARSOFF; 2878 }else{ 2879 return; 2880 } 2881 2882 s = splfw(); 2883 db_tr = dbch->top; 2884 pcnt = 0; 2885 /* XXX we cannot handle a packet which lies in more than two buf */ 2886 fwdma_sync_multiseg_all(dbch->am, 2887 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2888 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2889 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2890 while (status & OHCI_CNTL_DMA_ACTIVE) { 2891 #if 0 2892 2893 if (off == OHCI_ARQOFF) 2894 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2895 db_tr->bus_addr, status, resCount); 2896 #endif 2897 len = dbch->xferq.psize - resCount; 2898 ld = (uint8_t *)db_tr->buf; 2899 if (dbch->pdb_tr == NULL) { 2900 len -= dbch->buf_offset; 2901 ld += dbch->buf_offset; 2902 } 2903 if (len > 0) 2904 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2905 BUS_DMASYNC_POSTREAD); 2906 while (len > 0 ) { 2907 if (count >= 0 && count-- == 0) 2908 goto out; 2909 if(dbch->pdb_tr != NULL){ 2910 /* we have a fragment in previous buffer */ 2911 int rlen; 2912 2913 offset = dbch->buf_offset; 2914 if (offset < 0) 2915 offset = - offset; 2916 buf = dbch->pdb_tr->buf + offset; 2917 rlen = dbch->xferq.psize - offset; 2918 if (firewire_debug) 2919 printf("rlen=%d, offset=%d\n", 2920 rlen, dbch->buf_offset); 2921 if (dbch->buf_offset < 0) { 2922 /* splitted in header, pull up */ 2923 char *p; 2924 2925 p = (char *)&pktbuf; 2926 bcopy(buf, p, rlen); 2927 p += rlen; 2928 /* this must be too long but harmless */ 2929 rlen = sizeof(pktbuf) - rlen; 2930 if (rlen < 0) 2931 printf("why rlen < 0\n"); 2932 bcopy(db_tr->buf, p, rlen); 2933 ld += rlen; 2934 len -= rlen; 2935 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2936 if (hlen <= 0) { 2937 printf("hlen < 0 shouldn't happen"); 2938 goto err; 2939 } 2940 offset = sizeof(pktbuf); 2941 vec[0].iov_base = (char *)&pktbuf; 2942 vec[0].iov_len = offset; 2943 } else { 2944 /* splitted in payload */ 2945 offset = rlen; 2946 vec[0].iov_base = buf; 2947 vec[0].iov_len = rlen; 2948 } 2949 fp=(struct fw_pkt *)vec[0].iov_base; 2950 nvec = 1; 2951 } else { 2952 /* no fragment in previous buffer */ 2953 fp=(struct fw_pkt *)ld; 2954 hlen = fwohci_arcv_swap(fp, len); 2955 if (hlen == 0) 2956 goto err; 2957 if (hlen < 0) { 2958 dbch->pdb_tr = db_tr; 2959 dbch->buf_offset = - dbch->buf_offset; 2960 /* sanity check */ 2961 if (resCount != 0) { 2962 printf("resCount=%d hlen=%d\n", 2963 resCount, hlen); 2964 goto err; 2965 } 2966 goto out; 2967 } 2968 offset = 0; 2969 nvec = 0; 2970 } 2971 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2972 if (plen < 0) { 2973 /* minimum header size + trailer 2974 = sizeof(fw_pkt) so this shouldn't happens */ 2975 printf("plen(%d) is negative! offset=%d\n", 2976 plen, offset); 2977 goto err; 2978 } 2979 if (plen > 0) { 2980 len -= plen; 2981 if (len < 0) { 2982 dbch->pdb_tr = db_tr; 2983 if (firewire_debug) 2984 printf("splitted payload\n"); 2985 /* sanity check */ 2986 if (resCount != 0) { 2987 printf("resCount=%d plen=%d" 2988 " len=%d\n", 2989 resCount, plen, len); 2990 goto err; 2991 } 2992 goto out; 2993 } 2994 vec[nvec].iov_base = ld; 2995 vec[nvec].iov_len = plen; 2996 nvec ++; 2997 ld += plen; 2998 } 2999 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 3000 if (nvec == 0) 3001 printf("nvec == 0\n"); 3002 3003 /* DMA result-code will be written at the tail of packet */ 3004 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3005 #if 0 3006 printf("plen: %d, stat %x\n", 3007 plen ,stat); 3008 #endif 3009 spd = (stat >> 21) & 0x3; 3010 event = (stat >> 16) & 0x1f; 3011 switch (event) { 3012 case FWOHCIEV_ACKPEND: 3013 #if 0 3014 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3015 #endif 3016 /* fall through */ 3017 case FWOHCIEV_ACKCOMPL: 3018 { 3019 struct fw_rcv_buf rb; 3020 3021 if ((vec[nvec-1].iov_len -= 3022 sizeof(struct fwohci_trailer)) == 0) 3023 nvec--; 3024 rb.fc = &sc->fc; 3025 rb.vec = vec; 3026 rb.nvec = nvec; 3027 rb.spd = spd; 3028 fw_rcv(&rb); 3029 break; 3030 } 3031 case FWOHCIEV_BUSRST: 3032 if (sc->fc.status != FWBUSRESET) 3033 printf("got BUSRST packet!?\n"); 3034 break; 3035 default: 3036 device_printf(sc->fc.dev, 3037 "Async DMA Receive error err=%02x %s" 3038 " plen=%d offset=%d len=%d status=0x%08x" 3039 " tcode=0x%x, stat=0x%08x\n", 3040 event, fwohcicode[event], plen, 3041 dbch->buf_offset, len, 3042 OREAD(sc, OHCI_DMACTL(off)), 3043 fp->mode.common.tcode, stat); 3044 #if 1 /* XXX */ 3045 goto err; 3046 #endif 3047 break; 3048 } 3049 pcnt ++; 3050 if (dbch->pdb_tr != NULL) { 3051 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3052 off, 1); 3053 dbch->pdb_tr = NULL; 3054 } 3055 3056 } 3057 out: 3058 if (resCount == 0) { 3059 /* done on this buffer */ 3060 if (dbch->pdb_tr == NULL) { 3061 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3062 dbch->buf_offset = 0; 3063 } else 3064 if (dbch->pdb_tr != db_tr) 3065 printf("pdb_tr != db_tr\n"); 3066 db_tr = STAILQ_NEXT(db_tr, link); 3067 fwdma_sync_multiseg_all(dbch->am, 3068 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3069 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3070 >> OHCI_STATUS_SHIFT; 3071 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3072 & OHCI_COUNT_MASK; 3073 /* XXX check buffer overrun */ 3074 dbch->top = db_tr; 3075 } else { 3076 dbch->buf_offset = dbch->xferq.psize - resCount; 3077 fw_bus_dmamap_sync( 3078 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3079 break; 3080 } 3081 /* XXX make sure DMA is not dead */ 3082 } 3083 #if 0 3084 if (pcnt < 1) 3085 printf("fwohci_arcv: no packets\n"); 3086 #endif 3087 fwdma_sync_multiseg_all(dbch->am, 3088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3089 splx(s); 3090 return; 3091 3092 err: 3093 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3094 OREAD(sc, OHCI_DMACTL(off))); 3095 dbch->pdb_tr = NULL; 3096 /* skip until resCount != 0 */ 3097 printf(" skip buffer"); 3098 while (resCount == 0) { 3099 printf(" #"); 3100 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3101 db_tr = STAILQ_NEXT(db_tr, link); 3102 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3103 & OHCI_COUNT_MASK; 3104 } 3105 printf(" done\n"); 3106 dbch->top = db_tr; 3107 dbch->buf_offset = dbch->xferq.psize - resCount; 3108 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3109 fwdma_sync_multiseg_all( 3110 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3111 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3112 splx(s); 3113 } 3114 #if defined(__NetBSD__) 3115 3116 int 3117 fwohci_print(void *aux, const char *pnp) 3118 { 3119 char *name = aux; 3120 3121 if (pnp) 3122 aprint_normal("%s at %s", name, pnp); 3123 3124 return UNCONF; 3125 } 3126 #endif 3127
Indexes created Fri Sep 26 20:09:58 GMT 2025