fwohci.c revision 1.91
1 /* $NetBSD: fwohci.c,v 1.91 2005/12/11 12:22:02 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/ktr.h> 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.91 2005/12/11 12:22:02 christos Exp $"); 62 63 #if defined(__DragonFly__) || __FreeBSD_version < 500000 64 #include <machine/clock.h> /* for DELAY() */ 65 #endif 66 67 #ifdef __DragonFly__ 68 #include "fw_port.h" 69 #include "firewire.h" 70 #include "firewirereg.h" 71 #include "fwdma.h" 72 #include "fwohcireg.h" 73 #include "fwohcivar.h" 74 #include "firewire_phy.h" 75 #else 76 #include <dev/firewire/fw_port.h> 77 #include <dev/firewire/firewire.h> 78 #include <dev/firewire/firewirereg.h> 79 #include <dev/firewire/fwdma.h> 80 #include <dev/firewire/fwohcireg.h> 81 #include <dev/firewire/fwohcivar.h> 82 #include <dev/firewire/firewire_phy.h> 83 #endif 84 #elif defined(__NetBSD__) 85 #include <sys/param.h> 86 #include <sys/device.h> 87 #include <sys/errno.h> 88 #include <sys/conf.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/mbuf.h> 92 #include <sys/proc.h> 93 #include <sys/reboot.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <machine/bus.h> 98 99 #include <dev/ieee1394/fw_port.h> 100 #include <dev/ieee1394/firewire.h> 101 #include <dev/ieee1394/firewirereg.h> 102 #include <dev/ieee1394/fwdma.h> 103 #include <dev/ieee1394/fwohcireg.h> 104 #include <dev/ieee1394/fwohcivar.h> 105 #include <dev/ieee1394/firewire_phy.h> 106 #endif 107 108 #undef OHCI_DEBUG 109 110 static int nocyclemaster = 0; 111 #if defined(__FreeBSD__) 112 SYSCTL_DECL(_hw_firewire); 113 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 114 "Do not send cycle start packets"); 115 #elif defined(__NetBSD__) 116 /* 117 * Setup sysctl(3) MIB, hw.fwohci.* 118 * 119 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 120 */ 121 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 122 { 123 int rc; 124 const struct sysctlnode *node; 125 126 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 127 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 128 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 129 goto err; 130 } 131 132 if ((rc = sysctl_createv(clog, 0, NULL, &node, 133 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 134 SYSCTL_DESCR("fwohci controls"), 135 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 136 goto err; 137 } 138 139 /* fwohci no cyclemaster flag */ 140 if ((rc = sysctl_createv(clog, 0, NULL, &node, 141 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 142 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 143 NULL, 0, &nocyclemaster, 144 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 145 goto err; 146 } 147 return; 148 149 err: 150 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 151 } 152 #endif 153 154 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 155 "STOR","LOAD","NOP ","STOP", 156 "", "", "", "", "", "", "", ""}; 157 158 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 159 "UNDEF","REG","SYS","DEV"}; 160 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 161 static const char * const fwohcicode[32] = { 162 "No stat","Undef","long","miss Ack err", 163 "underrun","overrun","desc err", "data read err", 164 "data write err","bus reset","timeout","tcode err", 165 "Undef","Undef","unknown event","flushed", 166 "Undef","ack complete","ack pend","Undef", 167 "ack busy_X","ack busy_A","ack busy_B","Undef", 168 "Undef","Undef","Undef","ack tardy", 169 "Undef","ack data_err","ack type_err",""}; 170 171 #define MAX_SPEED 3 172 extern const char *fw_linkspeed[]; 173 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 174 175 static const struct tcode_info tinfo[] = { 176 /* hdr_len block flag*/ 177 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 178 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 179 /* 2 WRES */ {12, FWTI_RES}, 180 /* 3 XXX */ { 0, 0}, 181 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 182 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 183 /* 6 RRESQ */ {16, FWTI_RES}, 184 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 185 /* 8 CYCS */ { 0, 0}, 186 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 187 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 188 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 189 /* c XXX */ { 0, 0}, 190 /* d XXX */ { 0, 0}, 191 /* e PHY */ {12, FWTI_REQ}, 192 /* f XXX */ { 0, 0} 193 }; 194 195 #define OHCI_WRITE_SIGMASK 0xffff0000 196 #define OHCI_READ_SIGMASK 0xffff0000 197 198 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 199 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 200 201 static void fwohci_ibr (struct firewire_comm *); 202 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 203 static void fwohci_db_free (struct fwohci_dbch *); 204 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 205 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 206 static void fwohci_start_atq (struct firewire_comm *); 207 static void fwohci_start_ats (struct firewire_comm *); 208 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 209 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 210 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 211 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 212 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 213 static int fwohci_irx_enable (struct firewire_comm *, int); 214 static int fwohci_irx_disable (struct firewire_comm *, int); 215 #if BYTE_ORDER == BIG_ENDIAN 216 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 217 #endif 218 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 219 static int fwohci_itx_disable (struct firewire_comm *, int); 220 static void fwohci_timeout (void *); 221 static void fwohci_set_intr (struct firewire_comm *, int); 222 223 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 224 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 225 static void dump_db (struct fwohci_softc *, uint32_t); 226 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 227 static void dump_dma (struct fwohci_softc *, uint32_t); 228 static uint32_t fwohci_cyctimer (struct firewire_comm *); 229 static void fwohci_rbuf_update (struct fwohci_softc *, int); 230 static void fwohci_tbuf_update (struct fwohci_softc *, int); 231 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 232 #if FWOHCI_TASKQUEUE 233 static void fwohci_complete(void *, int); 234 #endif 235 #if defined(__NetBSD__) 236 static void fwohci_power(int, void *); 237 int fwohci_print(void *, const char *); 238 #endif 239 240 /* 241 * memory allocated for DMA programs 242 */ 243 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 244 245 #define NDB FWMAXQUEUE 246 247 #define OHCI_VERSION 0x00 248 #define OHCI_ATRETRY 0x08 249 #define OHCI_CROMHDR 0x18 250 #define OHCI_BUS_OPT 0x20 251 #define OHCI_BUSIRMC (1 << 31) 252 #define OHCI_BUSCMC (1 << 30) 253 #define OHCI_BUSISC (1 << 29) 254 #define OHCI_BUSBMC (1 << 28) 255 #define OHCI_BUSPMC (1 << 27) 256 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 257 OHCI_BUSBMC | OHCI_BUSPMC 258 259 #define OHCI_EUID_HI 0x24 260 #define OHCI_EUID_LO 0x28 261 262 #define OHCI_CROMPTR 0x34 263 #define OHCI_HCCCTL 0x50 264 #define OHCI_HCCCTLCLR 0x54 265 #define OHCI_AREQHI 0x100 266 #define OHCI_AREQHICLR 0x104 267 #define OHCI_AREQLO 0x108 268 #define OHCI_AREQLOCLR 0x10c 269 #define OHCI_PREQHI 0x110 270 #define OHCI_PREQHICLR 0x114 271 #define OHCI_PREQLO 0x118 272 #define OHCI_PREQLOCLR 0x11c 273 #define OHCI_PREQUPPER 0x120 274 275 #define OHCI_SID_BUF 0x64 276 #define OHCI_SID_CNT 0x68 277 #define OHCI_SID_ERR (1 << 31) 278 #define OHCI_SID_CNT_MASK 0xffc 279 280 #define OHCI_IT_STAT 0x90 281 #define OHCI_IT_STATCLR 0x94 282 #define OHCI_IT_MASK 0x98 283 #define OHCI_IT_MASKCLR 0x9c 284 285 #define OHCI_IR_STAT 0xa0 286 #define OHCI_IR_STATCLR 0xa4 287 #define OHCI_IR_MASK 0xa8 288 #define OHCI_IR_MASKCLR 0xac 289 290 #define OHCI_LNKCTL 0xe0 291 #define OHCI_LNKCTLCLR 0xe4 292 293 #define OHCI_PHYACCESS 0xec 294 #define OHCI_CYCLETIMER 0xf0 295 296 #define OHCI_DMACTL(off) (off) 297 #define OHCI_DMACTLCLR(off) (off + 4) 298 #define OHCI_DMACMD(off) (off + 0xc) 299 #define OHCI_DMAMATCH(off) (off + 0x10) 300 301 #define OHCI_ATQOFF 0x180 302 #define OHCI_ATQCTL OHCI_ATQOFF 303 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 304 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 305 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 306 307 #define OHCI_ATSOFF 0x1a0 308 #define OHCI_ATSCTL OHCI_ATSOFF 309 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 310 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 311 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 312 313 #define OHCI_ARQOFF 0x1c0 314 #define OHCI_ARQCTL OHCI_ARQOFF 315 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 316 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 317 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 318 319 #define OHCI_ARSOFF 0x1e0 320 #define OHCI_ARSCTL OHCI_ARSOFF 321 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 322 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 323 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 324 325 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 326 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 327 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 328 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 329 330 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 331 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 332 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 333 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 334 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 335 336 #if defined(__FreeBSD__) 337 d_ioctl_t fwohci_ioctl; 338 #elif defined(__NetBSD__) 339 extern struct cfdriver fwohci_cd; 340 dev_type_ioctl(fwohci_ioctl); 341 #endif 342 343 /* 344 * Communication with PHY device 345 */ 346 static uint32_t 347 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 348 { 349 uint32_t fun; 350 351 addr &= 0xf; 352 data &= 0xff; 353 354 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 355 OWRITE(sc, OHCI_PHYACCESS, fun); 356 DELAY(100); 357 358 return(fwphy_rddata( sc, addr)); 359 } 360 361 static uint32_t 362 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 363 { 364 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 365 int i; 366 uint32_t bm; 367 368 #define OHCI_CSR_DATA 0x0c 369 #define OHCI_CSR_COMP 0x10 370 #define OHCI_CSR_CONT 0x14 371 #define OHCI_BUS_MANAGER_ID 0 372 373 OWRITE(sc, OHCI_CSR_DATA, node); 374 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 375 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 376 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 377 DELAY(10); 378 bm = OREAD(sc, OHCI_CSR_DATA); 379 if((bm & 0x3f) == 0x3f) 380 bm = node; 381 if (firewire_debug) 382 device_printf(sc->fc.dev, 383 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 384 385 return(bm); 386 } 387 388 static uint32_t 389 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 390 { 391 uint32_t fun, stat; 392 u_int i, retry = 0; 393 394 addr &= 0xf; 395 #define MAX_RETRY 100 396 again: 397 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 398 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 399 OWRITE(sc, OHCI_PHYACCESS, fun); 400 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 401 fun = OREAD(sc, OHCI_PHYACCESS); 402 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 403 break; 404 DELAY(100); 405 } 406 if(i >= MAX_RETRY) { 407 if (firewire_debug) 408 device_printf(sc->fc.dev, "phy read failed(1).\n"); 409 if (++retry < MAX_RETRY) { 410 DELAY(100); 411 goto again; 412 } 413 } 414 /* Make sure that SCLK is started */ 415 stat = OREAD(sc, FWOHCI_INTSTAT); 416 if ((stat & OHCI_INT_REG_FAIL) != 0 || 417 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 418 if (firewire_debug) 419 device_printf(sc->fc.dev, "phy read failed(2).\n"); 420 if (++retry < MAX_RETRY) { 421 DELAY(100); 422 goto again; 423 } 424 } 425 if (firewire_debug || retry >= MAX_RETRY) 426 device_printf(sc->fc.dev, 427 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 428 #undef MAX_RETRY 429 return((fun >> PHYDEV_RDDATA )& 0xff); 430 } 431 /* Device specific ioctl. */ 432 FW_IOCTL(fwohci) 433 { 434 FW_IOCTL_START; 435 struct fwohci_softc *fc; 436 int err = 0; 437 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 438 uint32_t *dmach = (uint32_t *) data; 439 440 if(sc == NULL){ 441 return(EINVAL); 442 } 443 fc = (struct fwohci_softc *)sc->fc; 444 445 if (!data) 446 return(EINVAL); 447 448 switch (cmd) { 449 case FWOHCI_WRREG: 450 #define OHCI_MAX_REG 0x800 451 if(reg->addr <= OHCI_MAX_REG){ 452 OWRITE(fc, reg->addr, reg->data); 453 reg->data = OREAD(fc, reg->addr); 454 }else{ 455 err = EINVAL; 456 } 457 break; 458 case FWOHCI_RDREG: 459 if(reg->addr <= OHCI_MAX_REG){ 460 reg->data = OREAD(fc, reg->addr); 461 }else{ 462 err = EINVAL; 463 } 464 break; 465 /* Read DMA descriptors for debug */ 466 case DUMPDMA: 467 if(*dmach <= OHCI_MAX_DMA_CH ){ 468 dump_dma(fc, *dmach); 469 dump_db(fc, *dmach); 470 }else{ 471 err = EINVAL; 472 } 473 break; 474 /* Read/Write Phy registers */ 475 #define OHCI_MAX_PHY_REG 0xf 476 case FWOHCI_RDPHYREG: 477 if (reg->addr <= OHCI_MAX_PHY_REG) 478 reg->data = fwphy_rddata(fc, reg->addr); 479 else 480 err = EINVAL; 481 break; 482 case FWOHCI_WRPHYREG: 483 if (reg->addr <= OHCI_MAX_PHY_REG) 484 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 485 else 486 err = EINVAL; 487 break; 488 default: 489 err = EINVAL; 490 break; 491 } 492 return err; 493 } 494 495 static int 496 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 497 { 498 uint32_t reg, reg2; 499 int e1394a = 1; 500 /* 501 * probe PHY parameters 502 * 0. to prove PHY version, whether compliance of 1394a. 503 * 1. to probe maximum speed supported by the PHY and 504 * number of port supported by core-logic. 505 * It is not actually available port on your PC . 506 */ 507 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 508 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 509 510 if((reg >> 5) != 7 ){ 511 sc->fc.mode &= ~FWPHYASYST; 512 sc->fc.nport = reg & FW_PHY_NP; 513 sc->fc.speed = reg & FW_PHY_SPD >> 6; 514 if (sc->fc.speed > MAX_SPEED) { 515 device_printf(dev, "invalid speed %d (fixed to %d).\n", 516 sc->fc.speed, MAX_SPEED); 517 sc->fc.speed = MAX_SPEED; 518 } 519 device_printf(dev, 520 "Phy 1394 only %s, %d ports.\n", 521 fw_linkspeed[sc->fc.speed], sc->fc.nport); 522 }else{ 523 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 524 sc->fc.mode |= FWPHYASYST; 525 sc->fc.nport = reg & FW_PHY_NP; 526 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 527 if (sc->fc.speed > MAX_SPEED) { 528 device_printf(dev, "invalid speed %d (fixed to %d).\n", 529 sc->fc.speed, MAX_SPEED); 530 sc->fc.speed = MAX_SPEED; 531 } 532 device_printf(dev, 533 "Phy 1394a available %s, %d ports.\n", 534 fw_linkspeed[sc->fc.speed], sc->fc.nport); 535 536 /* check programPhyEnable */ 537 reg2 = fwphy_rddata(sc, 5); 538 #if 0 539 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 540 #else /* XXX force to enable 1394a */ 541 if (e1394a) { 542 #endif 543 if (firewire_debug) 544 device_printf(dev, 545 "Enable 1394a Enhancements\n"); 546 /* enable EAA EMC */ 547 reg2 |= 0x03; 548 /* set aPhyEnhanceEnable */ 549 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 550 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 551 } else { 552 /* for safe */ 553 reg2 &= ~0x83; 554 } 555 reg2 = fwphy_wrdata(sc, 5, reg2); 556 } 557 558 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 559 if((reg >> 5) == 7 ){ 560 reg = fwphy_rddata(sc, 4); 561 reg |= 1 << 6; 562 fwphy_wrdata(sc, 4, reg); 563 reg = fwphy_rddata(sc, 4); 564 } 565 return 0; 566 } 567 568 569 void 570 fwohci_reset(struct fwohci_softc *sc, device_t dev) 571 { 572 int i, max_rec, speed; 573 uint32_t reg, reg2; 574 struct fwohcidb_tr *db_tr; 575 576 /* Disable interrupts */ 577 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 578 579 /* Now stopping all DMA channels */ 580 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 581 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 582 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 583 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 584 585 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 586 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 587 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 588 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 589 } 590 591 /* FLUSH FIFO and reset Transmitter/Reciever */ 592 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 593 if (firewire_debug) 594 device_printf(dev, "resetting OHCI..."); 595 i = 0; 596 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 597 if (i++ > 100) break; 598 DELAY(1000); 599 } 600 if (firewire_debug) 601 printf("done (loop=%d)\n", i); 602 603 /* Probe phy */ 604 fwohci_probe_phy(sc, dev); 605 606 /* Probe link */ 607 reg = OREAD(sc, OHCI_BUS_OPT); 608 reg2 = reg | OHCI_BUSFNC; 609 max_rec = (reg & 0x0000f000) >> 12; 610 speed = (reg & 0x00000007); 611 device_printf(dev, "Link %s, max_rec %d bytes.\n", 612 fw_linkspeed[speed], MAXREC(max_rec)); 613 /* XXX fix max_rec */ 614 sc->fc.maxrec = sc->fc.speed + 8; 615 if (max_rec != sc->fc.maxrec) { 616 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 617 device_printf(dev, "max_rec %d -> %d\n", 618 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 619 } 620 if (firewire_debug) 621 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 622 OWRITE(sc, OHCI_BUS_OPT, reg2); 623 624 /* Initialize registers */ 625 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 626 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 627 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 628 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 629 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 630 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 631 632 /* Enable link */ 633 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 634 635 /* Force to start async RX DMA */ 636 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 637 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 638 fwohci_rx_enable(sc, &sc->arrq); 639 fwohci_rx_enable(sc, &sc->arrs); 640 641 /* Initialize async TX */ 642 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 643 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 644 645 /* AT Retries */ 646 OWRITE(sc, FWOHCI_RETRY, 647 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 648 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 649 650 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 651 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 652 sc->atrq.bottom = sc->atrq.top; 653 sc->atrs.bottom = sc->atrs.top; 654 655 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 656 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 657 db_tr->xfer = NULL; 658 } 659 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 660 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 661 db_tr->xfer = NULL; 662 } 663 664 665 /* Enable interrupts */ 666 OWRITE(sc, FWOHCI_INTMASK, 667 OHCI_INT_ERR | OHCI_INT_PHY_SID 668 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 669 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 670 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 671 fwohci_set_intr(&sc->fc, 1); 672 673 } 674 675 int 676 fwohci_init(struct fwohci_softc *sc, device_t dev) 677 { 678 int i, mver; 679 uint32_t reg; 680 uint8_t ui[8]; 681 682 #if FWOHCI_TASKQUEUE 683 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 684 #endif 685 686 /* OHCI version */ 687 reg = OREAD(sc, OHCI_VERSION); 688 mver = (reg >> 16) & 0xff; 689 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 690 mver, reg & 0xff, (reg>>24) & 1); 691 if (mver < 1 || mver > 9) { 692 device_printf(dev, "invalid OHCI version\n"); 693 return (ENXIO); 694 } 695 696 /* Available Isochronous DMA channel probe */ 697 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 698 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 699 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 700 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 701 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 702 for (i = 0; i < 0x20; i++) 703 if ((reg & (1 << i)) == 0) 704 break; 705 sc->fc.nisodma = i; 706 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 707 if (i == 0) 708 return (ENXIO); 709 710 sc->fc.arq = &sc->arrq.xferq; 711 sc->fc.ars = &sc->arrs.xferq; 712 sc->fc.atq = &sc->atrq.xferq; 713 sc->fc.ats = &sc->atrs.xferq; 714 715 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 716 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 717 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 718 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 719 720 sc->arrq.xferq.start = NULL; 721 sc->arrs.xferq.start = NULL; 722 sc->atrq.xferq.start = fwohci_start_atq; 723 sc->atrs.xferq.start = fwohci_start_ats; 724 725 sc->arrq.xferq.buf = NULL; 726 sc->arrs.xferq.buf = NULL; 727 sc->atrq.xferq.buf = NULL; 728 sc->atrs.xferq.buf = NULL; 729 730 sc->arrq.xferq.dmach = -1; 731 sc->arrs.xferq.dmach = -1; 732 sc->atrq.xferq.dmach = -1; 733 sc->atrs.xferq.dmach = -1; 734 735 sc->arrq.ndesc = 1; 736 sc->arrs.ndesc = 1; 737 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 738 sc->atrs.ndesc = 2; 739 740 sc->arrq.ndb = NDB; 741 sc->arrs.ndb = NDB / 2; 742 sc->atrq.ndb = NDB; 743 sc->atrs.ndb = NDB / 2; 744 745 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 746 sc->fc.it[i] = &sc->it[i].xferq; 747 sc->fc.ir[i] = &sc->ir[i].xferq; 748 sc->it[i].xferq.dmach = i; 749 sc->ir[i].xferq.dmach = i; 750 sc->it[i].ndb = 0; 751 sc->ir[i].ndb = 0; 752 } 753 754 sc->fc.tcode = tinfo; 755 sc->fc.dev = dev; 756 757 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 758 &sc->crom_dma, BUS_DMA_WAITOK); 759 if(sc->fc.config_rom == NULL){ 760 device_printf(dev, "config_rom alloc failed."); 761 return ENOMEM; 762 } 763 764 #if 0 765 bzero(&sc->fc.config_rom[0], CROMSIZE); 766 sc->fc.config_rom[1] = 0x31333934; 767 sc->fc.config_rom[2] = 0xf000a002; 768 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 769 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 770 sc->fc.config_rom[5] = 0; 771 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 772 773 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 774 #endif 775 776 777 /* SID recieve buffer must align 2^11 */ 778 #define OHCI_SIDSIZE (1 << 11) 779 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 780 &sc->sid_dma, BUS_DMA_WAITOK); 781 if (sc->sid_buf == NULL) { 782 device_printf(dev, "sid_buf alloc failed."); 783 return ENOMEM; 784 } 785 786 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 787 &sc->dummy_dma, BUS_DMA_WAITOK); 788 789 if (sc->dummy_dma.v_addr == NULL) { 790 device_printf(dev, "dummy_dma alloc failed."); 791 return ENOMEM; 792 } 793 794 fwohci_db_init(sc, &sc->arrq); 795 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 796 return ENOMEM; 797 798 fwohci_db_init(sc, &sc->arrs); 799 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 800 return ENOMEM; 801 802 fwohci_db_init(sc, &sc->atrq); 803 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 804 return ENOMEM; 805 806 fwohci_db_init(sc, &sc->atrs); 807 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 808 return ENOMEM; 809 810 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 811 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 812 for( i = 0 ; i < 8 ; i ++) 813 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 814 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 815 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 816 817 sc->fc.ioctl = fwohci_ioctl; 818 sc->fc.cyctimer = fwohci_cyctimer; 819 sc->fc.set_bmr = fwohci_set_bus_manager; 820 sc->fc.ibr = fwohci_ibr; 821 sc->fc.irx_enable = fwohci_irx_enable; 822 sc->fc.irx_disable = fwohci_irx_disable; 823 824 sc->fc.itx_enable = fwohci_itxbuf_enable; 825 sc->fc.itx_disable = fwohci_itx_disable; 826 #if BYTE_ORDER == BIG_ENDIAN 827 sc->fc.irx_post = fwohci_irx_post; 828 #else 829 sc->fc.irx_post = NULL; 830 #endif 831 sc->fc.itx_post = NULL; 832 sc->fc.timeout = fwohci_timeout; 833 sc->fc.poll = fwohci_poll; 834 sc->fc.set_intr = fwohci_set_intr; 835 836 sc->intmask = sc->irstat = sc->itstat = 0; 837 838 fw_init(&sc->fc); 839 fwohci_reset(sc, dev); 840 FWOHCI_INIT_END; 841 842 return 0; 843 } 844 845 void 846 fwohci_timeout(void *arg) 847 { 848 struct fwohci_softc *sc; 849 850 sc = (struct fwohci_softc *)arg; 851 } 852 853 uint32_t 854 fwohci_cyctimer(struct firewire_comm *fc) 855 { 856 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 857 return(OREAD(sc, OHCI_CYCLETIMER)); 858 } 859 860 FWOHCI_DETACH() 861 { 862 int i; 863 864 FWOHCI_DETACH_START; 865 if (sc->sid_buf != NULL) 866 fwdma_free(&sc->fc, &sc->sid_dma); 867 if (sc->fc.config_rom != NULL) 868 fwdma_free(&sc->fc, &sc->crom_dma); 869 870 fwohci_db_free(&sc->arrq); 871 fwohci_db_free(&sc->arrs); 872 873 fwohci_db_free(&sc->atrq); 874 fwohci_db_free(&sc->atrs); 875 876 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 877 fwohci_db_free(&sc->it[i]); 878 fwohci_db_free(&sc->ir[i]); 879 } 880 FWOHCI_DETACH_END; 881 882 return 0; 883 } 884 885 #define LAST_DB(dbtr, db) do { \ 886 struct fwohcidb_tr *_dbtr = (dbtr); \ 887 int _cnt = _dbtr->dbcnt; \ 888 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 889 } while (0) 890 891 static void 892 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 893 { 894 struct fwohcidb_tr *db_tr; 895 struct fwohcidb *db; 896 bus_dma_segment_t *s; 897 int i; 898 899 db_tr = (struct fwohcidb_tr *)arg; 900 db = &db_tr->db[db_tr->dbcnt]; 901 if (error) { 902 if (firewire_debug || error != EFBIG) 903 printf("fwohci_execute_db: error=%d\n", error); 904 return; 905 } 906 for (i = 0; i < nseg; i++) { 907 s = &segs[i]; 908 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 909 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 910 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 911 db++; 912 db_tr->dbcnt++; 913 } 914 } 915 916 static void 917 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 918 bus_size_t size, int error) 919 { 920 fwohci_execute_db(arg, segs, nseg, error); 921 } 922 923 static void 924 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 925 { 926 int i, s; 927 int tcode, hdr_len, pl_off; 928 int fsegment = -1; 929 uint32_t off; 930 struct fw_xfer *xfer; 931 struct fw_pkt *fp; 932 struct fwohci_txpkthdr *ohcifp; 933 struct fwohcidb_tr *db_tr; 934 struct fwohcidb *db; 935 uint32_t *ld; 936 const struct tcode_info *info; 937 static int maxdesc=0; 938 939 if(&sc->atrq == dbch){ 940 off = OHCI_ATQOFF; 941 }else if(&sc->atrs == dbch){ 942 off = OHCI_ATSOFF; 943 }else{ 944 return; 945 } 946 947 if (dbch->flags & FWOHCI_DBCH_FULL) 948 return; 949 950 s = splfw(); 951 fwdma_sync_multiseg_all(dbch->am, 952 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 953 db_tr = dbch->top; 954 txloop: 955 xfer = STAILQ_FIRST(&dbch->xferq.q); 956 if(xfer == NULL){ 957 goto kick; 958 } 959 if(dbch->xferq.queued == 0 ){ 960 device_printf(sc->fc.dev, "TX queue empty\n"); 961 } 962 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 963 db_tr->xfer = xfer; 964 xfer->state = FWXF_START; 965 966 fp = &xfer->send.hdr; 967 tcode = fp->mode.common.tcode; 968 969 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 970 info = &tinfo[tcode]; 971 hdr_len = pl_off = info->hdr_len; 972 973 ld = &ohcifp->mode.ld[0]; 974 ld[0] = ld[1] = ld[2] = ld[3] = 0; 975 for( i = 0 ; i < pl_off ; i+= 4) 976 ld[i/4] = fp->mode.ld[i/4]; 977 978 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 979 if (tcode == FWTCODE_STREAM ){ 980 hdr_len = 8; 981 ohcifp->mode.stream.len = fp->mode.stream.len; 982 } else if (tcode == FWTCODE_PHY) { 983 hdr_len = 12; 984 ld[1] = fp->mode.ld[1]; 985 ld[2] = fp->mode.ld[2]; 986 ohcifp->mode.common.spd = 0; 987 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 988 } else { 989 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 990 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 991 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 992 } 993 db = &db_tr->db[0]; 994 FWOHCI_DMA_WRITE(db->db.desc.cmd, 995 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 996 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 997 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 998 /* Specify bound timer of asy. responce */ 999 if(&sc->atrs == dbch){ 1000 FWOHCI_DMA_WRITE(db->db.desc.res, 1001 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1002 } 1003 #if BYTE_ORDER == BIG_ENDIAN 1004 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1005 hdr_len = 12; 1006 for (i = 0; i < hdr_len/4; i ++) 1007 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1008 #endif 1009 1010 again: 1011 db_tr->dbcnt = 2; 1012 db = &db_tr->db[db_tr->dbcnt]; 1013 if (xfer->send.pay_len > 0) { 1014 int err; 1015 /* handle payload */ 1016 if (xfer->mbuf == NULL) { 1017 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1018 &xfer->send.payload[0], xfer->send.pay_len, 1019 fwohci_execute_db, db_tr, 1020 BUS_DMA_WAITOK); 1021 } else { 1022 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1023 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1024 db_tr->dma_map, xfer->mbuf, 1025 fwohci_execute_db2, db_tr, 1026 BUS_DMA_WAITOK); 1027 if (err == EFBIG) { 1028 struct mbuf *m0; 1029 1030 if (firewire_debug) 1031 device_printf(sc->fc.dev, "EFBIG.\n"); 1032 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1033 if (m0 != NULL) { 1034 m_copydata(xfer->mbuf, 0, 1035 xfer->mbuf->m_pkthdr.len, 1036 mtod(m0, caddr_t)); 1037 m0->m_len = m0->m_pkthdr.len = 1038 xfer->mbuf->m_pkthdr.len; 1039 m_freem(xfer->mbuf); 1040 xfer->mbuf = m0; 1041 goto again; 1042 } 1043 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1044 } 1045 } 1046 if (err) 1047 printf("dmamap_load: err=%d\n", err); 1048 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1049 BUS_DMASYNC_PREWRITE); 1050 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1051 for (i = 2; i < db_tr->dbcnt; i++) 1052 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1053 OHCI_OUTPUT_MORE); 1054 #endif 1055 } 1056 if (maxdesc < db_tr->dbcnt) { 1057 maxdesc = db_tr->dbcnt; 1058 if (firewire_debug) 1059 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1060 } 1061 /* last db */ 1062 LAST_DB(db_tr, db); 1063 FWOHCI_DMA_SET(db->db.desc.cmd, 1064 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1065 FWOHCI_DMA_WRITE(db->db.desc.depend, 1066 STAILQ_NEXT(db_tr, link)->bus_addr); 1067 1068 if(fsegment == -1 ) 1069 fsegment = db_tr->dbcnt; 1070 if (dbch->pdb_tr != NULL) { 1071 LAST_DB(dbch->pdb_tr, db); 1072 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1073 } 1074 dbch->pdb_tr = db_tr; 1075 db_tr = STAILQ_NEXT(db_tr, link); 1076 if(db_tr != dbch->bottom){ 1077 goto txloop; 1078 } else { 1079 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1080 dbch->flags |= FWOHCI_DBCH_FULL; 1081 } 1082 kick: 1083 /* kick asy q */ 1084 fwdma_sync_multiseg_all(dbch->am, 1085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1086 1087 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1088 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1089 } else { 1090 if (firewire_debug) 1091 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1092 OREAD(sc, OHCI_DMACTL(off))); 1093 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1094 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1095 dbch->xferq.flag |= FWXFERQ_RUNNING; 1096 } 1097 CTR0(KTR_DEV, "start kick done"); 1098 CTR0(KTR_DEV, "start kick done2"); 1099 1100 dbch->top = db_tr; 1101 splx(s); 1102 return; 1103 } 1104 1105 static void 1106 fwohci_start_atq(struct firewire_comm *fc) 1107 { 1108 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1109 fwohci_start( sc, &(sc->atrq)); 1110 return; 1111 } 1112 1113 static void 1114 fwohci_start_ats(struct firewire_comm *fc) 1115 { 1116 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1117 fwohci_start( sc, &(sc->atrs)); 1118 return; 1119 } 1120 1121 void 1122 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1123 { 1124 int s, ch, err = 0; 1125 struct fwohcidb_tr *tr; 1126 struct fwohcidb *db; 1127 struct fw_xfer *xfer; 1128 uint32_t off; 1129 u_int stat, status; 1130 int packets; 1131 struct firewire_comm *fc = (struct firewire_comm *)sc; 1132 1133 if(&sc->atrq == dbch){ 1134 off = OHCI_ATQOFF; 1135 ch = ATRQ_CH; 1136 }else if(&sc->atrs == dbch){ 1137 off = OHCI_ATSOFF; 1138 ch = ATRS_CH; 1139 }else{ 1140 return; 1141 } 1142 s = splfw(); 1143 tr = dbch->bottom; 1144 packets = 0; 1145 fwdma_sync_multiseg_all(dbch->am, 1146 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1147 while(dbch->xferq.queued > 0){ 1148 LAST_DB(tr, db); 1149 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1150 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1151 if (fc->status != FWBUSRESET) 1152 /* maybe out of order?? */ 1153 goto out; 1154 } 1155 if (tr->xfer->send.pay_len > 0) { 1156 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1157 BUS_DMASYNC_POSTWRITE); 1158 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1159 } 1160 #if 1 1161 if (firewire_debug > 1) 1162 dump_db(sc, ch); 1163 #endif 1164 if(status & OHCI_CNTL_DMA_DEAD) { 1165 /* Stop DMA */ 1166 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1167 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1168 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1169 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1170 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1171 } 1172 stat = status & FWOHCIEV_MASK; 1173 switch(stat){ 1174 case FWOHCIEV_ACKPEND: 1175 CTR0(KTR_DEV, "txd: ack pending"); 1176 /* fall through */ 1177 case FWOHCIEV_ACKCOMPL: 1178 err = 0; 1179 break; 1180 case FWOHCIEV_ACKBSA: 1181 case FWOHCIEV_ACKBSB: 1182 case FWOHCIEV_ACKBSX: 1183 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1184 err = EBUSY; 1185 break; 1186 case FWOHCIEV_FLUSHED: 1187 case FWOHCIEV_ACKTARD: 1188 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1189 err = EAGAIN; 1190 break; 1191 case FWOHCIEV_MISSACK: 1192 case FWOHCIEV_UNDRRUN: 1193 case FWOHCIEV_OVRRUN: 1194 case FWOHCIEV_DESCERR: 1195 case FWOHCIEV_DTRDERR: 1196 case FWOHCIEV_TIMEOUT: 1197 case FWOHCIEV_TCODERR: 1198 case FWOHCIEV_UNKNOWN: 1199 case FWOHCIEV_ACKDERR: 1200 case FWOHCIEV_ACKTERR: 1201 default: 1202 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1203 stat, fwohcicode[stat]); 1204 err = EINVAL; 1205 break; 1206 } 1207 if (tr->xfer != NULL) { 1208 xfer = tr->xfer; 1209 CTR0(KTR_DEV, "txd"); 1210 if (xfer->state == FWXF_RCVD) { 1211 #if 0 1212 if (firewire_debug) 1213 printf("already rcvd\n"); 1214 #endif 1215 fw_xfer_done(xfer); 1216 } else { 1217 xfer->state = FWXF_SENT; 1218 if (err == EBUSY && fc->status != FWBUSRESET) { 1219 xfer->state = FWXF_BUSY; 1220 xfer->resp = err; 1221 xfer->recv.pay_len = 0; 1222 fw_xfer_done(xfer); 1223 } else if (stat != FWOHCIEV_ACKPEND) { 1224 if (stat != FWOHCIEV_ACKCOMPL) 1225 xfer->state = FWXF_SENTERR; 1226 xfer->resp = err; 1227 xfer->recv.pay_len = 0; 1228 fw_xfer_done(xfer); 1229 } 1230 } 1231 /* 1232 * The watchdog timer takes care of split 1233 * transcation timeout for ACKPEND case. 1234 */ 1235 } else { 1236 printf("this shouldn't happen\n"); 1237 } 1238 dbch->xferq.queued --; 1239 tr->xfer = NULL; 1240 1241 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1242 packets ++; 1243 tr = STAILQ_NEXT(tr, link); 1244 dbch->bottom = tr; 1245 if (dbch->bottom == dbch->top) { 1246 /* we reaches the end of context program */ 1247 if (firewire_debug && dbch->xferq.queued > 0) 1248 printf("queued > 0\n"); 1249 break; 1250 } 1251 } 1252 out: 1253 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1254 printf("make free slot\n"); 1255 dbch->flags &= ~FWOHCI_DBCH_FULL; 1256 fwohci_start(sc, dbch); 1257 } 1258 fwdma_sync_multiseg_all( 1259 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1260 splx(s); 1261 } 1262 1263 static void 1264 fwohci_db_free(struct fwohci_dbch *dbch) 1265 { 1266 struct fwohcidb_tr *db_tr; 1267 int idb; 1268 1269 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1270 return; 1271 1272 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1273 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1274 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1275 db_tr->buf != NULL) { 1276 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1277 db_tr->buf, dbch->xferq.psize); 1278 db_tr->buf = NULL; 1279 } else if (db_tr->dma_map != NULL) 1280 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1281 } 1282 dbch->ndb = 0; 1283 db_tr = STAILQ_FIRST(&dbch->db_trq); 1284 fwdma_free_multiseg(dbch->am); 1285 free(db_tr, M_FW); 1286 STAILQ_INIT(&dbch->db_trq); 1287 dbch->flags &= ~FWOHCI_DBCH_INIT; 1288 } 1289 1290 static void 1291 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1292 { 1293 int idb; 1294 struct fwohcidb_tr *db_tr; 1295 1296 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1297 goto out; 1298 1299 /* create dma_tag for buffers */ 1300 #define MAX_REQCOUNT 0xffff 1301 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1302 /*alignment*/ 1, /*boundary*/ 0, 1303 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1304 /*highaddr*/ BUS_SPACE_MAXADDR, 1305 /*filter*/NULL, /*filterarg*/NULL, 1306 /*maxsize*/ dbch->xferq.psize, 1307 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1308 /*maxsegsz*/ MAX_REQCOUNT, 1309 /*flags*/ 0, 1310 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1311 /*lockfunc*/busdma_lock_mutex, 1312 /*lockarg*/&Giant, 1313 #endif 1314 &dbch->dmat)) 1315 return; 1316 1317 /* allocate DB entries and attach one to each DMA channels */ 1318 /* DB entry must start at 16 bytes bounary. */ 1319 STAILQ_INIT(&dbch->db_trq); 1320 db_tr = (struct fwohcidb_tr *) 1321 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1322 M_FW, M_WAITOK | M_ZERO); 1323 if(db_tr == NULL){ 1324 printf("fwohci_db_init: malloc(1) failed\n"); 1325 return; 1326 } 1327 1328 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1329 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1330 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1331 if (dbch->am == NULL) { 1332 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1333 free(db_tr, M_FW); 1334 return; 1335 } 1336 /* Attach DB to DMA ch. */ 1337 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1338 db_tr->dbcnt = 0; 1339 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1340 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1341 /* create dmamap for buffers */ 1342 /* XXX do we need 4bytes alignment tag? */ 1343 /* XXX don't alloc dma_map for AR */ 1344 if (bus_dmamap_create(sc->fc.dmat, dbch->xferq.psize, 1345 dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, MAX_REQCOUNT, 1346 0, BUS_DMA_NOWAIT, &db_tr->dma_map) != 0) { 1347 printf("bus_dmamap_create failed\n"); 1348 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1349 fwohci_db_free(dbch); 1350 return; 1351 } 1352 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1353 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1354 if (idb % dbch->xferq.bnpacket == 0) 1355 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1356 ].start = (caddr_t)db_tr; 1357 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1358 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1359 ].end = (caddr_t)db_tr; 1360 } 1361 db_tr++; 1362 } 1363 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1364 = STAILQ_FIRST(&dbch->db_trq); 1365 out: 1366 dbch->xferq.queued = 0; 1367 dbch->pdb_tr = NULL; 1368 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1369 dbch->bottom = dbch->top; 1370 dbch->flags = FWOHCI_DBCH_INIT; 1371 } 1372 1373 static int 1374 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1375 { 1376 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1377 int sleepch; 1378 1379 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1380 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1381 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1382 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1383 /* XXX we cannot free buffers until the DMA really stops */ 1384 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1385 fwohci_db_free(&sc->it[dmach]); 1386 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1387 return 0; 1388 } 1389 1390 static int 1391 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1392 { 1393 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1394 int sleepch; 1395 1396 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1397 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1398 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1399 /* XXX we cannot free buffers until the DMA really stops */ 1400 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1401 fwohci_db_free(&sc->ir[dmach]); 1402 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1403 return 0; 1404 } 1405 1406 #if BYTE_ORDER == BIG_ENDIAN 1407 static void 1408 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1409 { 1410 qld[0] = FWOHCI_DMA_READ(qld[0]); 1411 return; 1412 } 1413 #endif 1414 1415 static int 1416 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1417 { 1418 int err = 0; 1419 int idb, z, i, dmach = 0, ldesc; 1420 uint32_t off = 0; 1421 struct fwohcidb_tr *db_tr; 1422 struct fwohcidb *db; 1423 1424 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1425 err = EINVAL; 1426 return err; 1427 } 1428 z = dbch->ndesc; 1429 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1430 if( &sc->it[dmach] == dbch){ 1431 off = OHCI_ITOFF(dmach); 1432 break; 1433 } 1434 } 1435 if(off == 0){ 1436 err = EINVAL; 1437 return err; 1438 } 1439 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1440 return err; 1441 dbch->xferq.flag |= FWXFERQ_RUNNING; 1442 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1443 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1444 } 1445 db_tr = dbch->top; 1446 for (idb = 0; idb < dbch->ndb; idb ++) { 1447 fwohci_add_tx_buf(dbch, db_tr, idb); 1448 if(STAILQ_NEXT(db_tr, link) == NULL){ 1449 break; 1450 } 1451 db = db_tr->db; 1452 ldesc = db_tr->dbcnt - 1; 1453 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1454 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1455 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1456 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1457 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1458 FWOHCI_DMA_SET( 1459 db[ldesc].db.desc.cmd, 1460 OHCI_INTERRUPT_ALWAYS); 1461 /* OHCI 1.1 and above */ 1462 FWOHCI_DMA_SET( 1463 db[0].db.desc.cmd, 1464 OHCI_INTERRUPT_ALWAYS); 1465 } 1466 } 1467 db_tr = STAILQ_NEXT(db_tr, link); 1468 } 1469 FWOHCI_DMA_CLEAR( 1470 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1471 return err; 1472 } 1473 1474 static int 1475 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1476 { 1477 int err = 0; 1478 int idb, z, i, dmach = 0, ldesc; 1479 uint32_t off = 0; 1480 struct fwohcidb_tr *db_tr; 1481 struct fwohcidb *db; 1482 1483 z = dbch->ndesc; 1484 if(&sc->arrq == dbch){ 1485 off = OHCI_ARQOFF; 1486 }else if(&sc->arrs == dbch){ 1487 off = OHCI_ARSOFF; 1488 }else{ 1489 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1490 if( &sc->ir[dmach] == dbch){ 1491 off = OHCI_IROFF(dmach); 1492 break; 1493 } 1494 } 1495 } 1496 if(off == 0){ 1497 err = EINVAL; 1498 return err; 1499 } 1500 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1501 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1502 return err; 1503 }else{ 1504 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1505 err = EBUSY; 1506 return err; 1507 } 1508 } 1509 dbch->xferq.flag |= FWXFERQ_RUNNING; 1510 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1511 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1512 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1513 } 1514 db_tr = dbch->top; 1515 for (idb = 0; idb < dbch->ndb; idb ++) { 1516 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1517 if (STAILQ_NEXT(db_tr, link) == NULL) 1518 break; 1519 db = db_tr->db; 1520 ldesc = db_tr->dbcnt - 1; 1521 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1522 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1523 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1524 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1525 FWOHCI_DMA_SET( 1526 db[ldesc].db.desc.cmd, 1527 OHCI_INTERRUPT_ALWAYS); 1528 FWOHCI_DMA_CLEAR( 1529 db[ldesc].db.desc.depend, 1530 0xf); 1531 } 1532 } 1533 db_tr = STAILQ_NEXT(db_tr, link); 1534 } 1535 FWOHCI_DMA_CLEAR( 1536 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1537 dbch->buf_offset = 0; 1538 fwdma_sync_multiseg_all(dbch->am, 1539 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1540 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1541 return err; 1542 }else{ 1543 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1544 } 1545 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1546 return err; 1547 } 1548 1549 static int 1550 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1551 { 1552 int sec, cycle, cycle_match; 1553 1554 cycle = cycle_now & 0x1fff; 1555 sec = cycle_now >> 13; 1556 #define CYCLE_MOD 0x10 1557 #if 1 1558 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1559 #else 1560 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1561 #endif 1562 cycle = cycle + CYCLE_DELAY; 1563 if (cycle >= 8000) { 1564 sec ++; 1565 cycle -= 8000; 1566 } 1567 cycle = roundup2(cycle, CYCLE_MOD); 1568 if (cycle >= 8000) { 1569 sec ++; 1570 if (cycle == 8000) 1571 cycle = 0; 1572 else 1573 cycle = CYCLE_MOD; 1574 } 1575 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1576 1577 return(cycle_match); 1578 } 1579 1580 static int 1581 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1582 { 1583 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1584 int err = 0; 1585 unsigned short tag, ich; 1586 struct fwohci_dbch *dbch; 1587 int cycle_match, cycle_now, s, ldesc; 1588 uint32_t stat; 1589 struct fw_bulkxfer *first, *chunk, *prev; 1590 struct fw_xferq *it; 1591 1592 dbch = &sc->it[dmach]; 1593 it = &dbch->xferq; 1594 1595 tag = (it->flag >> 6) & 3; 1596 ich = it->flag & 0x3f; 1597 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1598 dbch->ndb = it->bnpacket * it->bnchunk; 1599 dbch->ndesc = 3; 1600 fwohci_db_init(sc, dbch); 1601 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1602 return ENOMEM; 1603 err = fwohci_tx_enable(sc, dbch); 1604 } 1605 if(err) 1606 return err; 1607 1608 ldesc = dbch->ndesc - 1; 1609 s = splfw(); 1610 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1611 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1612 struct fwohcidb *db; 1613 1614 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1615 BUS_DMASYNC_PREWRITE); 1616 fwohci_txbufdb(sc, dmach, chunk); 1617 if (prev != NULL) { 1618 db = ((struct fwohcidb_tr *)(prev->end))->db; 1619 #if 0 /* XXX necessary? */ 1620 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1621 OHCI_BRANCH_ALWAYS); 1622 #endif 1623 #if 0 /* if bulkxfer->npacket changes */ 1624 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1625 ((struct fwohcidb_tr *) 1626 (chunk->start))->bus_addr | dbch->ndesc; 1627 #else 1628 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1629 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1630 #endif 1631 } 1632 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1633 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1634 prev = chunk; 1635 } 1636 fwdma_sync_multiseg_all(dbch->am, 1637 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1638 splx(s); 1639 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1640 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1641 printf("stat 0x%x\n", stat); 1642 1643 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1644 return 0; 1645 1646 #if 0 1647 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1648 #endif 1649 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1650 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1651 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1652 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1653 1654 first = STAILQ_FIRST(&it->stdma); 1655 OWRITE(sc, OHCI_ITCMD(dmach), 1656 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1657 if (firewire_debug > 1) { 1658 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1659 #if 1 1660 dump_dma(sc, ITX_CH + dmach); 1661 #endif 1662 } 1663 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1664 #if 1 1665 /* Don't start until all chunks are buffered */ 1666 if (STAILQ_FIRST(&it->stfree) != NULL) 1667 goto out; 1668 #endif 1669 #if 1 1670 /* Clear cycle match counter bits */ 1671 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1672 1673 /* 2bit second + 13bit cycle */ 1674 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1675 cycle_match = fwohci_next_cycle(fc, cycle_now); 1676 1677 OWRITE(sc, OHCI_ITCTL(dmach), 1678 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1679 | OHCI_CNTL_DMA_RUN); 1680 #else 1681 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1682 #endif 1683 if (firewire_debug > 1) { 1684 printf("cycle_match: 0x%04x->0x%04x\n", 1685 cycle_now, cycle_match); 1686 dump_dma(sc, ITX_CH + dmach); 1687 dump_db(sc, ITX_CH + dmach); 1688 } 1689 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1690 device_printf(sc->fc.dev, 1691 "IT DMA underrun (0x%08x)\n", stat); 1692 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1693 } 1694 out: 1695 return err; 1696 } 1697 1698 static int 1699 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1700 { 1701 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1702 int err = 0, s, ldesc; 1703 unsigned short tag, ich; 1704 uint32_t stat; 1705 struct fwohci_dbch *dbch; 1706 struct fwohcidb_tr *db_tr; 1707 struct fw_bulkxfer *first, *prev, *chunk; 1708 struct fw_xferq *ir; 1709 1710 dbch = &sc->ir[dmach]; 1711 ir = &dbch->xferq; 1712 1713 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1714 tag = (ir->flag >> 6) & 3; 1715 ich = ir->flag & 0x3f; 1716 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1717 1718 ir->queued = 0; 1719 dbch->ndb = ir->bnpacket * ir->bnchunk; 1720 dbch->ndesc = 2; 1721 fwohci_db_init(sc, dbch); 1722 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1723 return ENOMEM; 1724 err = fwohci_rx_enable(sc, dbch); 1725 } 1726 if(err) 1727 return err; 1728 1729 first = STAILQ_FIRST(&ir->stfree); 1730 if (first == NULL) { 1731 device_printf(fc->dev, "IR DMA no free chunk\n"); 1732 return 0; 1733 } 1734 1735 ldesc = dbch->ndesc - 1; 1736 s = splfw(); 1737 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1738 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1739 struct fwohcidb *db; 1740 1741 #if 1 /* XXX for if_fwe */ 1742 if (chunk->mbuf != NULL) { 1743 db_tr = (struct fwohcidb_tr *)(chunk->start); 1744 db_tr->dbcnt = 1; 1745 err = fw_bus_dmamap_load_mbuf( 1746 dbch->dmat, db_tr->dma_map, 1747 chunk->mbuf, fwohci_execute_db2, db_tr, 1748 BUS_DMA_WAITOK); 1749 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1750 OHCI_UPDATE | OHCI_INPUT_LAST | 1751 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1752 } 1753 #endif 1754 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1755 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1756 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1757 if (prev != NULL) { 1758 db = ((struct fwohcidb_tr *)(prev->end))->db; 1759 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1760 } 1761 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1762 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1763 prev = chunk; 1764 } 1765 fwdma_sync_multiseg_all(dbch->am, 1766 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1767 splx(s); 1768 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1769 if (stat & OHCI_CNTL_DMA_ACTIVE) 1770 return 0; 1771 if (stat & OHCI_CNTL_DMA_RUN) { 1772 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1773 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1774 } 1775 1776 if (firewire_debug) 1777 printf("start IR DMA 0x%x\n", stat); 1778 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1779 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1780 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1781 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1782 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1783 OWRITE(sc, OHCI_IRCMD(dmach), 1784 ((struct fwohcidb_tr *)(first->start))->bus_addr 1785 | dbch->ndesc); 1786 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1787 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1788 #if 0 1789 dump_db(sc, IRX_CH + dmach); 1790 #endif 1791 return err; 1792 } 1793 1794 FWOHCI_STOP() 1795 { 1796 FWOHCI_STOP_START; 1797 u_int i; 1798 1799 /* Now stopping all DMA channel */ 1800 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1801 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1802 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1803 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1804 1805 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1806 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1807 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1808 } 1809 1810 /* FLUSH FIFO and reset Transmitter/Reciever */ 1811 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1812 1813 /* Stop interrupt */ 1814 OWRITE(sc, FWOHCI_INTMASKCLR, 1815 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1816 | OHCI_INT_PHY_INT 1817 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1818 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1819 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1820 | OHCI_INT_PHY_BUS_R); 1821 1822 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1823 fw_drain_txq(&sc->fc); 1824 1825 /* XXX Link down? Bus reset? */ 1826 FWOHCI_STOP_RETURN(0); 1827 } 1828 1829 #if defined(__NetBSD__) 1830 static void 1831 fwohci_power(int why, void *arg) 1832 { 1833 struct fwohci_softc *sc = arg; 1834 int s; 1835 1836 s = splbio(); 1837 switch (why) { 1838 case PWR_SUSPEND: 1839 case PWR_STANDBY: 1840 fwohci_stop(arg); 1841 break; 1842 case PWR_RESUME: 1843 fwohci_resume(sc, sc->fc.dev); 1844 break; 1845 case PWR_SOFTSUSPEND: 1846 case PWR_SOFTSTANDBY: 1847 case PWR_SOFTRESUME: 1848 break; 1849 } 1850 splx(s); 1851 } 1852 #endif 1853 1854 int 1855 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1856 { 1857 int i; 1858 struct fw_xferq *ir; 1859 struct fw_bulkxfer *chunk; 1860 1861 fwohci_reset(sc, dev); 1862 /* XXX resume isochronous receive automatically. (how about TX?) */ 1863 for(i = 0; i < sc->fc.nisodma; i ++) { 1864 ir = &sc->ir[i].xferq; 1865 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1866 device_printf(sc->fc.dev, 1867 "resume iso receive ch: %d\n", i); 1868 ir->flag &= ~FWXFERQ_RUNNING; 1869 /* requeue stdma to stfree */ 1870 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1871 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1872 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1873 } 1874 sc->fc.irx_enable(&sc->fc, i); 1875 } 1876 } 1877 1878 #if defined(__FreeBSD__) 1879 bus_generic_resume(dev); 1880 #endif 1881 sc->fc.ibr(&sc->fc); 1882 return 0; 1883 } 1884 1885 #define ACK_ALL 1886 static void 1887 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1888 { 1889 uint32_t irstat, itstat; 1890 u_int i; 1891 struct firewire_comm *fc = (struct firewire_comm *)sc; 1892 1893 CTR0(KTR_DEV, "fwohci_intr_body"); 1894 #ifdef OHCI_DEBUG 1895 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1896 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1897 stat & OHCI_INT_EN ? "DMA_EN ":"", 1898 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1899 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1900 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1901 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1902 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1903 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1904 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1905 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1906 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1907 stat & OHCI_INT_PHY_SID ? "SID ":"", 1908 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1909 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1910 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1911 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1912 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1913 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1914 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1915 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1916 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1917 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1918 stat, OREAD(sc, FWOHCI_INTMASK) 1919 ); 1920 #endif 1921 /* Bus reset */ 1922 if(stat & OHCI_INT_PHY_BUS_R ){ 1923 if (fc->status == FWBUSRESET) 1924 goto busresetout; 1925 /* Disable bus reset interrupt until sid recv. */ 1926 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1927 1928 device_printf(fc->dev, "BUS reset\n"); 1929 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1930 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1931 1932 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1933 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1934 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1935 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1936 1937 #ifndef ACK_ALL 1938 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1939 #endif 1940 fw_busreset(fc); 1941 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1942 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1943 } 1944 busresetout: 1945 if((stat & OHCI_INT_DMA_IR )){ 1946 #ifndef ACK_ALL 1947 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1948 #endif 1949 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1950 irstat = sc->irstat; 1951 sc->irstat = 0; 1952 #else 1953 irstat = atomic_readandclear_int(&sc->irstat); 1954 #endif 1955 for(i = 0; i < fc->nisodma ; i++){ 1956 struct fwohci_dbch *dbch; 1957 1958 if((irstat & (1 << i)) != 0){ 1959 dbch = &sc->ir[i]; 1960 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1961 device_printf(sc->fc.dev, 1962 "dma(%d) not active\n", i); 1963 continue; 1964 } 1965 fwohci_rbuf_update(sc, i); 1966 } 1967 } 1968 } 1969 if((stat & OHCI_INT_DMA_IT )){ 1970 #ifndef ACK_ALL 1971 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1972 #endif 1973 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1974 itstat = sc->itstat; 1975 sc->itstat = 0; 1976 #else 1977 itstat = atomic_readandclear_int(&sc->itstat); 1978 #endif 1979 for(i = 0; i < fc->nisodma ; i++){ 1980 if((itstat & (1 << i)) != 0){ 1981 fwohci_tbuf_update(sc, i); 1982 } 1983 } 1984 } 1985 if((stat & OHCI_INT_DMA_PRRS )){ 1986 #ifndef ACK_ALL 1987 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1988 #endif 1989 #if 0 1990 dump_dma(sc, ARRS_CH); 1991 dump_db(sc, ARRS_CH); 1992 #endif 1993 fwohci_arcv(sc, &sc->arrs, count); 1994 } 1995 if((stat & OHCI_INT_DMA_PRRQ )){ 1996 #ifndef ACK_ALL 1997 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1998 #endif 1999 #if 0 2000 dump_dma(sc, ARRQ_CH); 2001 dump_db(sc, ARRQ_CH); 2002 #endif 2003 fwohci_arcv(sc, &sc->arrq, count); 2004 } 2005 if (stat & OHCI_INT_CYC_LOST) { 2006 if (sc->cycle_lost >= 0) 2007 sc->cycle_lost ++; 2008 if (sc->cycle_lost > 10) { 2009 sc->cycle_lost = -1; 2010 #if 0 2011 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2012 #endif 2013 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2014 device_printf(fc->dev, "too many cycle lost, " 2015 "no cycle master presents?\n"); 2016 } 2017 } 2018 if(stat & OHCI_INT_PHY_SID){ 2019 uint32_t *buf, node_id; 2020 int plen; 2021 2022 #ifndef ACK_ALL 2023 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2024 #endif 2025 /* Enable bus reset interrupt */ 2026 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2027 /* Allow async. request to us */ 2028 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2029 /* XXX insecure ?? */ 2030 /* allow from all nodes */ 2031 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2032 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2033 /* 0 to 4GB regison */ 2034 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2035 /* Set ATRetries register */ 2036 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2037 /* 2038 ** Checking whether the node is root or not. If root, turn on 2039 ** cycle master. 2040 */ 2041 node_id = OREAD(sc, FWOHCI_NODEID); 2042 plen = OREAD(sc, OHCI_SID_CNT); 2043 2044 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2045 node_id, (plen >> 16) & 0xff); 2046 if (!(node_id & OHCI_NODE_VALID)) { 2047 printf("Bus reset failure\n"); 2048 goto sidout; 2049 } 2050 2051 /* cycle timer */ 2052 sc->cycle_lost = 0; 2053 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2054 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2055 printf("CYCLEMASTER mode\n"); 2056 OWRITE(sc, OHCI_LNKCTL, 2057 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2058 } else { 2059 printf("non CYCLEMASTER mode\n"); 2060 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2061 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2062 } 2063 2064 fc->nodeid = node_id & 0x3f; 2065 2066 if (plen & OHCI_SID_ERR) { 2067 device_printf(fc->dev, "SID Error\n"); 2068 goto sidout; 2069 } 2070 plen &= OHCI_SID_CNT_MASK; 2071 if (plen < 4 || plen > OHCI_SIDSIZE) { 2072 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2073 goto sidout; 2074 } 2075 plen -= 4; /* chop control info */ 2076 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2077 if (buf == NULL) { 2078 device_printf(fc->dev, "malloc failed\n"); 2079 goto sidout; 2080 } 2081 for (i = 0; i < plen / 4; i ++) 2082 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2083 #if defined(__NetBSD__) && defined(macppc) 2084 /* XXX required as bootdisk for macppc. */ 2085 delay(500000); 2086 #endif 2087 #if 1 /* XXX needed?? */ 2088 /* pending all pre-bus_reset packets */ 2089 fwohci_txd(sc, &sc->atrq); 2090 fwohci_txd(sc, &sc->atrs); 2091 fwohci_arcv(sc, &sc->arrs, -1); 2092 fwohci_arcv(sc, &sc->arrq, -1); 2093 fw_drain_txq(fc); 2094 #endif 2095 fw_sidrcv(fc, buf, plen); 2096 free(buf, M_FW); 2097 } 2098 sidout: 2099 if((stat & OHCI_INT_DMA_ATRQ )){ 2100 #ifndef ACK_ALL 2101 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2102 #endif 2103 fwohci_txd(sc, &(sc->atrq)); 2104 } 2105 if((stat & OHCI_INT_DMA_ATRS )){ 2106 #ifndef ACK_ALL 2107 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2108 #endif 2109 fwohci_txd(sc, &(sc->atrs)); 2110 } 2111 if((stat & OHCI_INT_PW_ERR )){ 2112 #ifndef ACK_ALL 2113 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2114 #endif 2115 device_printf(fc->dev, "posted write error\n"); 2116 } 2117 if((stat & OHCI_INT_ERR )){ 2118 #ifndef ACK_ALL 2119 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2120 #endif 2121 device_printf(fc->dev, "unrecoverable error\n"); 2122 } 2123 if((stat & OHCI_INT_PHY_INT)) { 2124 #ifndef ACK_ALL 2125 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2126 #endif 2127 device_printf(fc->dev, "phy int\n"); 2128 } 2129 2130 CTR0(KTR_DEV, "fwohci_intr_body done"); 2131 return; 2132 } 2133 2134 #if FWOHCI_TASKQUEUE 2135 static void 2136 fwohci_complete(void *arg, int pending) 2137 { 2138 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2139 uint32_t stat; 2140 2141 again: 2142 stat = atomic_readandclear_int(&sc->intstat); 2143 if (stat) { 2144 FW_LOCK; 2145 fwohci_intr_body(sc, stat, -1); 2146 FW_UNLOCK; 2147 } else 2148 return; 2149 goto again; 2150 } 2151 #endif 2152 2153 static uint32_t 2154 fwochi_check_stat(struct fwohci_softc *sc) 2155 { 2156 uint32_t stat, irstat, itstat; 2157 2158 stat = OREAD(sc, FWOHCI_INTSTAT); 2159 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2160 if (stat == 0xffffffff) { 2161 device_printf(sc->fc.dev, 2162 "device physically ejected?\n"); 2163 return(stat); 2164 } 2165 #ifdef ACK_ALL 2166 if (stat) 2167 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2168 #endif 2169 if (stat & OHCI_INT_DMA_IR) { 2170 irstat = OREAD(sc, OHCI_IR_STAT); 2171 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2172 atomic_set_int(&sc->irstat, irstat); 2173 } 2174 if (stat & OHCI_INT_DMA_IT) { 2175 itstat = OREAD(sc, OHCI_IT_STAT); 2176 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2177 atomic_set_int(&sc->itstat, itstat); 2178 } 2179 return(stat); 2180 } 2181 2182 FW_INTR(fwohci) 2183 { 2184 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2185 uint32_t stat; 2186 #if !FWOHCI_TASKQUEUE 2187 uint32_t bus_reset = 0; 2188 #endif 2189 2190 if (!(sc->intmask & OHCI_INT_EN)) { 2191 /* polling mode */ 2192 FW_INTR_RETURN(0); 2193 } 2194 2195 #if !FWOHCI_TASKQUEUE 2196 again: 2197 #endif 2198 CTR0(KTR_DEV, "fwohci_intr"); 2199 stat = fwochi_check_stat(sc); 2200 if (stat == 0 || stat == 0xffffffff) 2201 FW_INTR_RETURN(1); 2202 #if FWOHCI_TASKQUEUE 2203 atomic_set_int(&sc->intstat, stat); 2204 /* XXX mask bus reset intr. during bus reset phase */ 2205 if (stat) 2206 #if 1 2207 taskqueue_enqueue_fast(taskqueue_fast, 2208 &sc->fwohci_task_complete); 2209 #else 2210 taskqueue_enqueue(taskqueue_swi, 2211 &sc->fwohci_task_complete); 2212 #endif 2213 #else 2214 /* We cannot clear bus reset event during bus reset phase */ 2215 if ((stat & ~bus_reset) == 0) 2216 FW_INTR_RETURN(1); 2217 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2218 fwohci_intr_body(sc, stat, -1); 2219 goto again; 2220 #endif 2221 CTR0(KTR_DEV, "fwohci_intr end"); 2222 } 2223 2224 void 2225 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2226 { 2227 int s; 2228 uint32_t stat; 2229 struct fwohci_softc *sc; 2230 2231 2232 sc = (struct fwohci_softc *)fc; 2233 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2234 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2235 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2236 #if 0 2237 if (!quick) { 2238 #else 2239 if (1) { 2240 #endif 2241 stat = fwochi_check_stat(sc); 2242 if (stat == 0 || stat == 0xffffffff) 2243 return; 2244 } 2245 s = splfw(); 2246 fwohci_intr_body(sc, stat, count); 2247 splx(s); 2248 } 2249 2250 static void 2251 fwohci_set_intr(struct firewire_comm *fc, int enable) 2252 { 2253 struct fwohci_softc *sc; 2254 2255 sc = (struct fwohci_softc *)fc; 2256 if (firewire_debug) 2257 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2258 if (enable) { 2259 sc->intmask |= OHCI_INT_EN; 2260 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2261 } else { 2262 sc->intmask &= ~OHCI_INT_EN; 2263 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2264 } 2265 } 2266 2267 static void 2268 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2269 { 2270 struct firewire_comm *fc = &sc->fc; 2271 struct fwohcidb *db; 2272 struct fw_bulkxfer *chunk; 2273 struct fw_xferq *it; 2274 uint32_t stat, count; 2275 int s, w=0, ldesc; 2276 2277 it = fc->it[dmach]; 2278 ldesc = sc->it[dmach].ndesc - 1; 2279 s = splfw(); /* unnecessary ? */ 2280 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2281 if (firewire_debug) 2282 dump_db(sc, ITX_CH + dmach); 2283 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2284 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2285 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2286 >> OHCI_STATUS_SHIFT; 2287 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2288 /* timestamp */ 2289 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2290 & OHCI_COUNT_MASK; 2291 if (stat == 0) 2292 break; 2293 STAILQ_REMOVE_HEAD(&it->stdma, link); 2294 switch (stat & FWOHCIEV_MASK){ 2295 case FWOHCIEV_ACKCOMPL: 2296 #if 0 2297 device_printf(fc->dev, "0x%08x\n", count); 2298 #endif 2299 break; 2300 default: 2301 device_printf(fc->dev, 2302 "Isochronous transmit err %02x(%s)\n", 2303 stat, fwohcicode[stat & 0x1f]); 2304 } 2305 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2306 w++; 2307 } 2308 splx(s); 2309 if (w) 2310 wakeup(it); 2311 } 2312 2313 static void 2314 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2315 { 2316 struct firewire_comm *fc = &sc->fc; 2317 struct fwohcidb_tr *db_tr; 2318 struct fw_bulkxfer *chunk; 2319 struct fw_xferq *ir; 2320 uint32_t stat; 2321 int s, w=0, ldesc; 2322 2323 ir = fc->ir[dmach]; 2324 ldesc = sc->ir[dmach].ndesc - 1; 2325 #if 0 2326 dump_db(sc, dmach); 2327 #endif 2328 s = splfw(); 2329 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2330 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2331 db_tr = (struct fwohcidb_tr *)chunk->end; 2332 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2333 >> OHCI_STATUS_SHIFT; 2334 if (stat == 0) 2335 break; 2336 2337 if (chunk->mbuf != NULL) { 2338 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2339 BUS_DMASYNC_POSTREAD); 2340 fw_bus_dmamap_unload( 2341 sc->ir[dmach].dmat, db_tr->dma_map); 2342 } else if (ir->buf != NULL) { 2343 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2344 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2345 } else { 2346 /* XXX */ 2347 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2348 } 2349 2350 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2351 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2352 switch (stat & FWOHCIEV_MASK) { 2353 case FWOHCIEV_ACKCOMPL: 2354 chunk->resp = 0; 2355 break; 2356 default: 2357 chunk->resp = EINVAL; 2358 device_printf(fc->dev, 2359 "Isochronous receive err %02x(%s)\n", 2360 stat, fwohcicode[stat & 0x1f]); 2361 } 2362 w++; 2363 } 2364 splx(s); 2365 if (w) { 2366 if (ir->flag & FWXFERQ_HANDLER) 2367 ir->hand(ir); 2368 else 2369 wakeup(ir); 2370 } 2371 } 2372 2373 void 2374 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2375 { 2376 uint32_t off, cntl, stat, cmd, match; 2377 2378 if(ch == 0){ 2379 off = OHCI_ATQOFF; 2380 }else if(ch == 1){ 2381 off = OHCI_ATSOFF; 2382 }else if(ch == 2){ 2383 off = OHCI_ARQOFF; 2384 }else if(ch == 3){ 2385 off = OHCI_ARSOFF; 2386 }else if(ch < IRX_CH){ 2387 off = OHCI_ITCTL(ch - ITX_CH); 2388 }else{ 2389 off = OHCI_IRCTL(ch - IRX_CH); 2390 } 2391 cntl = stat = OREAD(sc, off); 2392 cmd = OREAD(sc, off + 0xc); 2393 match = OREAD(sc, off + 0x10); 2394 2395 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2396 ch, 2397 cntl, 2398 cmd, 2399 match); 2400 stat &= 0xffff ; 2401 if (stat) { 2402 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2403 ch, 2404 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2405 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2406 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2407 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2408 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2409 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2410 fwohcicode[stat & 0x1f], 2411 stat & 0x1f 2412 ); 2413 }else{ 2414 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2415 } 2416 } 2417 2418 void 2419 dump_db(struct fwohci_softc *sc, uint32_t ch) 2420 { 2421 struct fwohci_dbch *dbch; 2422 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2423 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2424 int idb, jdb; 2425 uint32_t cmd, off; 2426 if(ch == 0){ 2427 off = OHCI_ATQOFF; 2428 dbch = &sc->atrq; 2429 }else if(ch == 1){ 2430 off = OHCI_ATSOFF; 2431 dbch = &sc->atrs; 2432 }else if(ch == 2){ 2433 off = OHCI_ARQOFF; 2434 dbch = &sc->arrq; 2435 }else if(ch == 3){ 2436 off = OHCI_ARSOFF; 2437 dbch = &sc->arrs; 2438 }else if(ch < IRX_CH){ 2439 off = OHCI_ITCTL(ch - ITX_CH); 2440 dbch = &sc->it[ch - ITX_CH]; 2441 }else { 2442 off = OHCI_IRCTL(ch - IRX_CH); 2443 dbch = &sc->ir[ch - IRX_CH]; 2444 } 2445 cmd = OREAD(sc, off + 0xc); 2446 2447 if( dbch->ndb == 0 ){ 2448 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2449 return; 2450 } 2451 pp = dbch->top; 2452 prev = pp->db; 2453 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2454 cp = STAILQ_NEXT(pp, link); 2455 if(cp == NULL){ 2456 curr = NULL; 2457 goto outdb; 2458 } 2459 np = STAILQ_NEXT(cp, link); 2460 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2461 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2462 curr = cp->db; 2463 if(np != NULL){ 2464 next = np->db; 2465 }else{ 2466 next = NULL; 2467 } 2468 goto outdb; 2469 } 2470 } 2471 pp = STAILQ_NEXT(pp, link); 2472 if(pp == NULL){ 2473 curr = NULL; 2474 goto outdb; 2475 } 2476 prev = pp->db; 2477 } 2478 outdb: 2479 if( curr != NULL){ 2480 #if 0 2481 printf("Prev DB %d\n", ch); 2482 print_db(pp, prev, ch, dbch->ndesc); 2483 #endif 2484 printf("Current DB %d\n", ch); 2485 print_db(cp, curr, ch, dbch->ndesc); 2486 #if 0 2487 printf("Next DB %d\n", ch); 2488 print_db(np, next, ch, dbch->ndesc); 2489 #endif 2490 }else{ 2491 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2492 } 2493 return; 2494 } 2495 2496 void 2497 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2498 uint32_t ch, uint32_t hogemax) 2499 { 2500 fwohcireg_t stat; 2501 int i, key; 2502 uint32_t cmd, res; 2503 2504 if(db == NULL){ 2505 printf("No Descriptor is found\n"); 2506 return; 2507 } 2508 2509 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2510 ch, 2511 "Current", 2512 "OP ", 2513 "KEY", 2514 "INT", 2515 "BR ", 2516 "len", 2517 "Addr", 2518 "Depend", 2519 "Stat", 2520 "Cnt"); 2521 for( i = 0 ; i <= hogemax ; i ++){ 2522 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2523 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2524 key = cmd & OHCI_KEY_MASK; 2525 stat = res >> OHCI_STATUS_SHIFT; 2526 #if defined(__DragonFly__) || \ 2527 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2528 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2529 db_tr->bus_addr, 2530 #else 2531 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2532 (uintmax_t)db_tr->bus_addr, 2533 #endif 2534 dbcode[(cmd >> 28) & 0xf], 2535 dbkey[(cmd >> 24) & 0x7], 2536 dbcond[(cmd >> 20) & 0x3], 2537 dbcond[(cmd >> 18) & 0x3], 2538 cmd & OHCI_COUNT_MASK, 2539 FWOHCI_DMA_READ(db[i].db.desc.addr), 2540 FWOHCI_DMA_READ(db[i].db.desc.depend), 2541 stat, 2542 res & OHCI_COUNT_MASK); 2543 if(stat & 0xff00){ 2544 printf(" %s%s%s%s%s%s %s(%x)\n", 2545 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2546 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2547 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2548 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2549 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2550 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2551 fwohcicode[stat & 0x1f], 2552 stat & 0x1f 2553 ); 2554 }else{ 2555 printf(" Nostat\n"); 2556 } 2557 if(key == OHCI_KEY_ST2 ){ 2558 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2559 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2560 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2561 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2562 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2563 } 2564 if(key == OHCI_KEY_DEVICE){ 2565 return; 2566 } 2567 if((cmd & OHCI_BRANCH_MASK) 2568 == OHCI_BRANCH_ALWAYS){ 2569 return; 2570 } 2571 if((cmd & OHCI_CMD_MASK) 2572 == OHCI_OUTPUT_LAST){ 2573 return; 2574 } 2575 if((cmd & OHCI_CMD_MASK) 2576 == OHCI_INPUT_LAST){ 2577 return; 2578 } 2579 if(key == OHCI_KEY_ST2 ){ 2580 i++; 2581 } 2582 } 2583 return; 2584 } 2585 2586 void 2587 fwohci_ibr(struct firewire_comm *fc) 2588 { 2589 struct fwohci_softc *sc; 2590 uint32_t fun; 2591 2592 device_printf(fc->dev, "Initiate bus reset\n"); 2593 sc = (struct fwohci_softc *)fc; 2594 2595 /* 2596 * Make sure our cached values from the config rom are 2597 * initialised. 2598 */ 2599 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2600 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2601 2602 /* 2603 * Set root hold-off bit so that non cyclemaster capable node 2604 * shouldn't became the root node. 2605 */ 2606 #if 1 2607 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2608 fun |= FW_PHY_IBR | FW_PHY_RHB; 2609 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2610 #else /* Short bus reset */ 2611 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2612 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2613 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2614 #endif 2615 } 2616 2617 void 2618 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2619 { 2620 struct fwohcidb_tr *db_tr, *fdb_tr; 2621 struct fwohci_dbch *dbch; 2622 struct fwohcidb *db; 2623 struct fw_pkt *fp; 2624 struct fwohci_txpkthdr *ohcifp; 2625 unsigned short chtag; 2626 int idb; 2627 2628 dbch = &sc->it[dmach]; 2629 chtag = sc->it[dmach].xferq.flag & 0xff; 2630 2631 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2632 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2633 /* 2634 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2635 */ 2636 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2637 db = db_tr->db; 2638 fp = (struct fw_pkt *)db_tr->buf; 2639 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2640 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2641 ohcifp->mode.common.spd = 0 & 0x7; 2642 ohcifp->mode.stream.len = fp->mode.stream.len; 2643 ohcifp->mode.stream.chtag = chtag; 2644 ohcifp->mode.stream.tcode = 0xa; 2645 #if BYTE_ORDER == BIG_ENDIAN 2646 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2647 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2648 #endif 2649 2650 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2651 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2652 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2653 #if 0 /* if bulkxfer->npackets changes */ 2654 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2655 | OHCI_UPDATE 2656 | OHCI_BRANCH_ALWAYS; 2657 db[0].db.desc.depend = 2658 = db[dbch->ndesc - 1].db.desc.depend 2659 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2660 #else 2661 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2662 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2663 #endif 2664 bulkxfer->end = (caddr_t)db_tr; 2665 db_tr = STAILQ_NEXT(db_tr, link); 2666 } 2667 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2668 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2669 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2670 #if 0 /* if bulkxfer->npackets changes */ 2671 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2672 /* OHCI 1.1 and above */ 2673 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2674 #endif 2675 /* 2676 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2677 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2678 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2679 */ 2680 return; 2681 } 2682 2683 static int 2684 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2685 int poffset) 2686 { 2687 struct fwohcidb *db = db_tr->db; 2688 struct fw_xferq *it; 2689 int err = 0; 2690 2691 it = &dbch->xferq; 2692 if(it->buf == 0){ 2693 err = EINVAL; 2694 return err; 2695 } 2696 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2697 db_tr->dbcnt = 3; 2698 2699 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2700 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2701 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2702 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2703 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2704 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2705 2706 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2707 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2708 #if 1 2709 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2710 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2711 #endif 2712 return 0; 2713 } 2714 2715 int 2716 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2717 int poffset, struct fwdma_alloc *dummy_dma) 2718 { 2719 struct fwohcidb *db = db_tr->db; 2720 struct fw_xferq *ir; 2721 int i, ldesc; 2722 bus_addr_t dbuf[2]; 2723 int dsiz[2]; 2724 2725 ir = &dbch->xferq; 2726 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2727 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2728 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2729 if (db_tr->buf == NULL) 2730 return(ENOMEM); 2731 db_tr->dbcnt = 1; 2732 dsiz[0] = ir->psize; 2733 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2734 BUS_DMASYNC_PREREAD); 2735 } else { 2736 db_tr->dbcnt = 0; 2737 if (dummy_dma != NULL) { 2738 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2739 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2740 } 2741 dsiz[db_tr->dbcnt] = ir->psize; 2742 if (ir->buf != NULL) { 2743 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2744 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2745 } 2746 db_tr->dbcnt++; 2747 } 2748 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2749 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2750 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2751 if (ir->flag & FWXFERQ_STREAM) { 2752 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2753 } 2754 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2755 } 2756 ldesc = db_tr->dbcnt - 1; 2757 if (ir->flag & FWXFERQ_STREAM) { 2758 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2759 } 2760 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2761 return 0; 2762 } 2763 2764 2765 static int 2766 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2767 { 2768 struct fw_pkt *fp0; 2769 uint32_t ld0; 2770 int slen, hlen; 2771 #if BYTE_ORDER == BIG_ENDIAN 2772 int i; 2773 #endif 2774 2775 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2776 #if 0 2777 printf("ld0: x%08x\n", ld0); 2778 #endif 2779 fp0 = (struct fw_pkt *)&ld0; 2780 /* determine length to swap */ 2781 switch (fp0->mode.common.tcode) { 2782 case FWTCODE_WRES: 2783 CTR0(KTR_DEV, "WRES"); 2784 case FWTCODE_RREQQ: 2785 case FWTCODE_WREQQ: 2786 case FWTCODE_RRESQ: 2787 case FWOHCITCODE_PHY: 2788 slen = 12; 2789 break; 2790 case FWTCODE_RREQB: 2791 case FWTCODE_WREQB: 2792 case FWTCODE_LREQ: 2793 case FWTCODE_RRESB: 2794 case FWTCODE_LRES: 2795 slen = 16; 2796 break; 2797 default: 2798 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2799 return(0); 2800 } 2801 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2802 if (hlen > len) { 2803 if (firewire_debug) 2804 printf("splitted header\n"); 2805 return(-hlen); 2806 } 2807 #if BYTE_ORDER == BIG_ENDIAN 2808 for(i = 0; i < slen/4; i ++) 2809 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2810 #endif 2811 return(hlen); 2812 } 2813 2814 static int 2815 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2816 { 2817 const struct tcode_info *info; 2818 int r; 2819 2820 info = &tinfo[fp->mode.common.tcode]; 2821 r = info->hdr_len + sizeof(uint32_t); 2822 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2823 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2824 2825 if (r == sizeof(uint32_t)) { 2826 /* XXX */ 2827 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2828 fp->mode.common.tcode); 2829 return (-1); 2830 } 2831 2832 if (r > dbch->xferq.psize) { 2833 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2834 return (-1); 2835 /* panic ? */ 2836 } 2837 2838 return r; 2839 } 2840 2841 static void 2842 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2843 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2844 { 2845 struct fwohcidb *db = &db_tr->db[0]; 2846 2847 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2848 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2849 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2850 fwdma_sync_multiseg_all(dbch->am, 2851 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2852 dbch->bottom = db_tr; 2853 2854 if (wake) 2855 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2856 } 2857 2858 static void 2859 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2860 { 2861 struct fwohcidb_tr *db_tr; 2862 struct iovec vec[2]; 2863 struct fw_pkt pktbuf; 2864 int nvec; 2865 struct fw_pkt *fp; 2866 uint8_t *ld; 2867 uint32_t stat, off, status, event; 2868 u_int spd; 2869 int len, plen, hlen, pcnt, offset; 2870 int s; 2871 caddr_t buf; 2872 int resCount; 2873 2874 CTR0(KTR_DEV, "fwohci_arv"); 2875 2876 if(&sc->arrq == dbch){ 2877 off = OHCI_ARQOFF; 2878 }else if(&sc->arrs == dbch){ 2879 off = OHCI_ARSOFF; 2880 }else{ 2881 return; 2882 } 2883 2884 s = splfw(); 2885 db_tr = dbch->top; 2886 pcnt = 0; 2887 /* XXX we cannot handle a packet which lies in more than two buf */ 2888 fwdma_sync_multiseg_all(dbch->am, 2889 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2890 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2891 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2892 while (status & OHCI_CNTL_DMA_ACTIVE) { 2893 #if 0 2894 2895 if (off == OHCI_ARQOFF) 2896 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2897 db_tr->bus_addr, status, resCount); 2898 #endif 2899 len = dbch->xferq.psize - resCount; 2900 ld = (uint8_t *)db_tr->buf; 2901 if (dbch->pdb_tr == NULL) { 2902 len -= dbch->buf_offset; 2903 ld += dbch->buf_offset; 2904 } 2905 if (len > 0) 2906 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2907 BUS_DMASYNC_POSTREAD); 2908 while (len > 0 ) { 2909 if (count >= 0 && count-- == 0) 2910 goto out; 2911 if(dbch->pdb_tr != NULL){ 2912 /* we have a fragment in previous buffer */ 2913 int rlen; 2914 2915 offset = dbch->buf_offset; 2916 if (offset < 0) 2917 offset = - offset; 2918 buf = dbch->pdb_tr->buf + offset; 2919 rlen = dbch->xferq.psize - offset; 2920 if (firewire_debug) 2921 printf("rlen=%d, offset=%d\n", 2922 rlen, dbch->buf_offset); 2923 if (dbch->buf_offset < 0) { 2924 /* splitted in header, pull up */ 2925 char *p; 2926 2927 p = (char *)&pktbuf; 2928 bcopy(buf, p, rlen); 2929 p += rlen; 2930 /* this must be too long but harmless */ 2931 rlen = sizeof(pktbuf) - rlen; 2932 if (rlen < 0) 2933 printf("why rlen < 0\n"); 2934 bcopy(db_tr->buf, p, rlen); 2935 ld += rlen; 2936 len -= rlen; 2937 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2938 if (hlen <= 0) { 2939 printf("hlen < 0 shouldn't happen"); 2940 goto err; 2941 } 2942 offset = sizeof(pktbuf); 2943 vec[0].iov_base = (char *)&pktbuf; 2944 vec[0].iov_len = offset; 2945 } else { 2946 /* splitted in payload */ 2947 offset = rlen; 2948 vec[0].iov_base = buf; 2949 vec[0].iov_len = rlen; 2950 } 2951 fp=(struct fw_pkt *)vec[0].iov_base; 2952 nvec = 1; 2953 } else { 2954 /* no fragment in previous buffer */ 2955 fp=(struct fw_pkt *)ld; 2956 hlen = fwohci_arcv_swap(fp, len); 2957 if (hlen == 0) 2958 goto err; 2959 if (hlen < 0) { 2960 dbch->pdb_tr = db_tr; 2961 dbch->buf_offset = - dbch->buf_offset; 2962 /* sanity check */ 2963 if (resCount != 0) { 2964 printf("resCount=%d hlen=%d\n", 2965 resCount, hlen); 2966 goto err; 2967 } 2968 goto out; 2969 } 2970 offset = 0; 2971 nvec = 0; 2972 } 2973 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2974 if (plen < 0) { 2975 /* minimum header size + trailer 2976 = sizeof(fw_pkt) so this shouldn't happens */ 2977 printf("plen(%d) is negative! offset=%d\n", 2978 plen, offset); 2979 goto err; 2980 } 2981 if (plen > 0) { 2982 len -= plen; 2983 if (len < 0) { 2984 dbch->pdb_tr = db_tr; 2985 if (firewire_debug) 2986 printf("splitted payload\n"); 2987 /* sanity check */ 2988 if (resCount != 0) { 2989 printf("resCount=%d plen=%d" 2990 " len=%d\n", 2991 resCount, plen, len); 2992 goto err; 2993 } 2994 goto out; 2995 } 2996 vec[nvec].iov_base = ld; 2997 vec[nvec].iov_len = plen; 2998 nvec ++; 2999 ld += plen; 3000 } 3001 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 3002 if (nvec == 0) 3003 printf("nvec == 0\n"); 3004 3005 /* DMA result-code will be written at the tail of packet */ 3006 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3007 #if 0 3008 printf("plen: %d, stat %x\n", 3009 plen ,stat); 3010 #endif 3011 spd = (stat >> 21) & 0x3; 3012 event = (stat >> 16) & 0x1f; 3013 switch (event) { 3014 case FWOHCIEV_ACKPEND: 3015 #if 0 3016 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3017 #endif 3018 /* fall through */ 3019 case FWOHCIEV_ACKCOMPL: 3020 { 3021 struct fw_rcv_buf rb; 3022 3023 if ((vec[nvec-1].iov_len -= 3024 sizeof(struct fwohci_trailer)) == 0) 3025 nvec--; 3026 rb.fc = &sc->fc; 3027 rb.vec = vec; 3028 rb.nvec = nvec; 3029 rb.spd = spd; 3030 fw_rcv(&rb); 3031 break; 3032 } 3033 case FWOHCIEV_BUSRST: 3034 if (sc->fc.status != FWBUSRESET) 3035 printf("got BUSRST packet!?\n"); 3036 break; 3037 default: 3038 device_printf(sc->fc.dev, 3039 "Async DMA Receive error err=%02x %s" 3040 " plen=%d offset=%d len=%d status=0x%08x" 3041 " tcode=0x%x, stat=0x%08x\n", 3042 event, fwohcicode[event], plen, 3043 dbch->buf_offset, len, 3044 OREAD(sc, OHCI_DMACTL(off)), 3045 fp->mode.common.tcode, stat); 3046 #if 1 /* XXX */ 3047 goto err; 3048 #endif 3049 break; 3050 } 3051 pcnt ++; 3052 if (dbch->pdb_tr != NULL) { 3053 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3054 off, 1); 3055 dbch->pdb_tr = NULL; 3056 } 3057 3058 } 3059 out: 3060 if (resCount == 0) { 3061 /* done on this buffer */ 3062 if (dbch->pdb_tr == NULL) { 3063 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3064 dbch->buf_offset = 0; 3065 } else 3066 if (dbch->pdb_tr != db_tr) 3067 printf("pdb_tr != db_tr\n"); 3068 db_tr = STAILQ_NEXT(db_tr, link); 3069 fwdma_sync_multiseg_all(dbch->am, 3070 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3071 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3072 >> OHCI_STATUS_SHIFT; 3073 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3074 & OHCI_COUNT_MASK; 3075 /* XXX check buffer overrun */ 3076 dbch->top = db_tr; 3077 } else { 3078 dbch->buf_offset = dbch->xferq.psize - resCount; 3079 fw_bus_dmamap_sync( 3080 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3081 break; 3082 } 3083 /* XXX make sure DMA is not dead */ 3084 } 3085 #if 0 3086 if (pcnt < 1) 3087 printf("fwohci_arcv: no packets\n"); 3088 #endif 3089 fwdma_sync_multiseg_all(dbch->am, 3090 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3091 splx(s); 3092 return; 3093 3094 err: 3095 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3096 OREAD(sc, OHCI_DMACTL(off))); 3097 dbch->pdb_tr = NULL; 3098 /* skip until resCount != 0 */ 3099 printf(" skip buffer"); 3100 while (resCount == 0) { 3101 printf(" #"); 3102 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3103 db_tr = STAILQ_NEXT(db_tr, link); 3104 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3105 & OHCI_COUNT_MASK; 3106 } 3107 printf(" done\n"); 3108 dbch->top = db_tr; 3109 dbch->buf_offset = dbch->xferq.psize - resCount; 3110 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3111 fwdma_sync_multiseg_all( 3112 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3113 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3114 splx(s); 3115 } 3116 #if defined(__NetBSD__) 3117 3118 int 3119 fwohci_print(void *aux, const char *pnp) 3120 { 3121 char *name = aux; 3122 3123 if (pnp) 3124 aprint_normal("%s at %s", name, pnp); 3125 3126 return UNCONF; 3127 } 3128 #endif 3129
Indexes created Mon Sep 29 03:10:08 GMT 2025