fwohci.c revision 1.92
1 /* $NetBSD: fwohci.c,v 1.92 2006/04/14 21:42:37 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/ktr.h> 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.92 2006/04/14 21:42:37 christos Exp $"); 62 63 #if defined(__DragonFly__) || __FreeBSD_version < 500000 64 #include <machine/clock.h> /* for DELAY() */ 65 #endif 66 67 #ifdef __DragonFly__ 68 #include "fw_port.h" 69 #include "firewire.h" 70 #include "firewirereg.h" 71 #include "fwdma.h" 72 #include "fwohcireg.h" 73 #include "fwohcivar.h" 74 #include "firewire_phy.h" 75 #else 76 #include <dev/firewire/fw_port.h> 77 #include <dev/firewire/firewire.h> 78 #include <dev/firewire/firewirereg.h> 79 #include <dev/firewire/fwdma.h> 80 #include <dev/firewire/fwohcireg.h> 81 #include <dev/firewire/fwohcivar.h> 82 #include <dev/firewire/firewire_phy.h> 83 #endif 84 #elif defined(__NetBSD__) 85 #include <sys/param.h> 86 #include <sys/device.h> 87 #include <sys/errno.h> 88 #include <sys/conf.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/mbuf.h> 92 #include <sys/proc.h> 93 #include <sys/reboot.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <machine/bus.h> 98 99 #include <dev/ieee1394/fw_port.h> 100 #include <dev/ieee1394/firewire.h> 101 #include <dev/ieee1394/firewirereg.h> 102 #include <dev/ieee1394/fwdma.h> 103 #include <dev/ieee1394/fwohcireg.h> 104 #include <dev/ieee1394/fwohcivar.h> 105 #include <dev/ieee1394/firewire_phy.h> 106 #endif 107 108 #undef OHCI_DEBUG 109 110 static int nocyclemaster = 0; 111 #if defined(__FreeBSD__) 112 SYSCTL_DECL(_hw_firewire); 113 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 114 "Do not send cycle start packets"); 115 #elif defined(__NetBSD__) 116 /* 117 * Setup sysctl(3) MIB, hw.fwohci.* 118 * 119 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 120 */ 121 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 122 { 123 int rc; 124 const struct sysctlnode *node; 125 126 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 127 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 128 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 129 goto err; 130 } 131 132 if ((rc = sysctl_createv(clog, 0, NULL, &node, 133 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 134 SYSCTL_DESCR("fwohci controls"), 135 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 136 goto err; 137 } 138 139 /* fwohci no cyclemaster flag */ 140 if ((rc = sysctl_createv(clog, 0, NULL, &node, 141 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 142 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 143 NULL, 0, &nocyclemaster, 144 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 145 goto err; 146 } 147 return; 148 149 err: 150 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 151 } 152 #endif 153 154 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 155 "STOR","LOAD","NOP ","STOP", 156 "", "", "", "", "", "", "", ""}; 157 158 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 159 "UNDEF","REG","SYS","DEV"}; 160 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 161 static const char * const fwohcicode[32] = { 162 "No stat","Undef","long","miss Ack err", 163 "underrun","overrun","desc err", "data read err", 164 "data write err","bus reset","timeout","tcode err", 165 "Undef","Undef","unknown event","flushed", 166 "Undef","ack complete","ack pend","Undef", 167 "ack busy_X","ack busy_A","ack busy_B","Undef", 168 "Undef","Undef","Undef","ack tardy", 169 "Undef","ack data_err","ack type_err",""}; 170 171 #define MAX_SPEED 3 172 extern const char *fw_linkspeed[]; 173 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 174 175 static const struct tcode_info tinfo[] = { 176 /* hdr_len block flag*/ 177 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 178 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 179 /* 2 WRES */ {12, FWTI_RES}, 180 /* 3 XXX */ { 0, 0}, 181 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 182 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 183 /* 6 RRESQ */ {16, FWTI_RES}, 184 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 185 /* 8 CYCS */ { 0, 0}, 186 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 187 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 188 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 189 /* c XXX */ { 0, 0}, 190 /* d XXX */ { 0, 0}, 191 /* e PHY */ {12, FWTI_REQ}, 192 /* f XXX */ { 0, 0} 193 }; 194 195 #define OHCI_WRITE_SIGMASK 0xffff0000 196 #define OHCI_READ_SIGMASK 0xffff0000 197 198 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 199 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 200 201 static void fwohci_ibr (struct firewire_comm *); 202 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 203 static void fwohci_db_free (struct fwohci_dbch *); 204 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 205 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 206 static void fwohci_start_atq (struct firewire_comm *); 207 static void fwohci_start_ats (struct firewire_comm *); 208 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 209 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 210 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 211 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 212 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 213 static int fwohci_irx_enable (struct firewire_comm *, int); 214 static int fwohci_irx_disable (struct firewire_comm *, int); 215 #if BYTE_ORDER == BIG_ENDIAN 216 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 217 #endif 218 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 219 static int fwohci_itx_disable (struct firewire_comm *, int); 220 static void fwohci_timeout (void *); 221 static void fwohci_set_intr (struct firewire_comm *, int); 222 223 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 224 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 225 static void dump_db (struct fwohci_softc *, uint32_t); 226 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 227 static void dump_dma (struct fwohci_softc *, uint32_t); 228 static uint32_t fwohci_cyctimer (struct firewire_comm *); 229 static void fwohci_rbuf_update (struct fwohci_softc *, int); 230 static void fwohci_tbuf_update (struct fwohci_softc *, int); 231 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 232 #if FWOHCI_TASKQUEUE 233 static void fwohci_complete(void *, int); 234 #endif 235 #if defined(__NetBSD__) 236 static void fwohci_power(int, void *); 237 int fwohci_print(void *, const char *); 238 #endif 239 240 /* 241 * memory allocated for DMA programs 242 */ 243 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 244 245 #define NDB FWMAXQUEUE 246 247 #define OHCI_VERSION 0x00 248 #define OHCI_ATRETRY 0x08 249 #define OHCI_CROMHDR 0x18 250 #define OHCI_BUS_OPT 0x20 251 #define OHCI_BUSIRMC (1 << 31) 252 #define OHCI_BUSCMC (1 << 30) 253 #define OHCI_BUSISC (1 << 29) 254 #define OHCI_BUSBMC (1 << 28) 255 #define OHCI_BUSPMC (1 << 27) 256 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 257 OHCI_BUSBMC | OHCI_BUSPMC 258 259 #define OHCI_EUID_HI 0x24 260 #define OHCI_EUID_LO 0x28 261 262 #define OHCI_CROMPTR 0x34 263 #define OHCI_HCCCTL 0x50 264 #define OHCI_HCCCTLCLR 0x54 265 #define OHCI_AREQHI 0x100 266 #define OHCI_AREQHICLR 0x104 267 #define OHCI_AREQLO 0x108 268 #define OHCI_AREQLOCLR 0x10c 269 #define OHCI_PREQHI 0x110 270 #define OHCI_PREQHICLR 0x114 271 #define OHCI_PREQLO 0x118 272 #define OHCI_PREQLOCLR 0x11c 273 #define OHCI_PREQUPPER 0x120 274 275 #define OHCI_SID_BUF 0x64 276 #define OHCI_SID_CNT 0x68 277 #define OHCI_SID_ERR (1 << 31) 278 #define OHCI_SID_CNT_MASK 0xffc 279 280 #define OHCI_IT_STAT 0x90 281 #define OHCI_IT_STATCLR 0x94 282 #define OHCI_IT_MASK 0x98 283 #define OHCI_IT_MASKCLR 0x9c 284 285 #define OHCI_IR_STAT 0xa0 286 #define OHCI_IR_STATCLR 0xa4 287 #define OHCI_IR_MASK 0xa8 288 #define OHCI_IR_MASKCLR 0xac 289 290 #define OHCI_LNKCTL 0xe0 291 #define OHCI_LNKCTLCLR 0xe4 292 293 #define OHCI_PHYACCESS 0xec 294 #define OHCI_CYCLETIMER 0xf0 295 296 #define OHCI_DMACTL(off) (off) 297 #define OHCI_DMACTLCLR(off) (off + 4) 298 #define OHCI_DMACMD(off) (off + 0xc) 299 #define OHCI_DMAMATCH(off) (off + 0x10) 300 301 #define OHCI_ATQOFF 0x180 302 #define OHCI_ATQCTL OHCI_ATQOFF 303 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 304 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 305 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 306 307 #define OHCI_ATSOFF 0x1a0 308 #define OHCI_ATSCTL OHCI_ATSOFF 309 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 310 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 311 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 312 313 #define OHCI_ARQOFF 0x1c0 314 #define OHCI_ARQCTL OHCI_ARQOFF 315 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 316 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 317 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 318 319 #define OHCI_ARSOFF 0x1e0 320 #define OHCI_ARSCTL OHCI_ARSOFF 321 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 322 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 323 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 324 325 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 326 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 327 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 328 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 329 330 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 331 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 332 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 333 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 334 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 335 336 #if defined(__FreeBSD__) 337 d_ioctl_t fwohci_ioctl; 338 #elif defined(__NetBSD__) 339 extern struct cfdriver fwohci_cd; 340 dev_type_ioctl(fwohci_ioctl); 341 #endif 342 343 /* 344 * Communication with PHY device 345 */ 346 static uint32_t 347 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 348 { 349 uint32_t fun; 350 351 addr &= 0xf; 352 data &= 0xff; 353 354 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 355 OWRITE(sc, OHCI_PHYACCESS, fun); 356 DELAY(100); 357 358 return(fwphy_rddata( sc, addr)); 359 } 360 361 static uint32_t 362 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 363 { 364 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 365 int i; 366 uint32_t bm; 367 368 #define OHCI_CSR_DATA 0x0c 369 #define OHCI_CSR_COMP 0x10 370 #define OHCI_CSR_CONT 0x14 371 #define OHCI_BUS_MANAGER_ID 0 372 373 OWRITE(sc, OHCI_CSR_DATA, node); 374 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 375 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 376 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 377 DELAY(10); 378 bm = OREAD(sc, OHCI_CSR_DATA); 379 if((bm & 0x3f) == 0x3f) 380 bm = node; 381 if (firewire_debug) 382 device_printf(sc->fc.dev, 383 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 384 385 return(bm); 386 } 387 388 static uint32_t 389 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 390 { 391 uint32_t fun, stat; 392 u_int i, retry = 0; 393 394 addr &= 0xf; 395 #define MAX_RETRY 100 396 again: 397 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 398 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 399 OWRITE(sc, OHCI_PHYACCESS, fun); 400 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 401 fun = OREAD(sc, OHCI_PHYACCESS); 402 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 403 break; 404 DELAY(100); 405 } 406 if(i >= MAX_RETRY) { 407 if (firewire_debug) 408 device_printf(sc->fc.dev, "phy read failed(1).\n"); 409 if (++retry < MAX_RETRY) { 410 DELAY(100); 411 goto again; 412 } 413 } 414 /* Make sure that SCLK is started */ 415 stat = OREAD(sc, FWOHCI_INTSTAT); 416 if ((stat & OHCI_INT_REG_FAIL) != 0 || 417 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 418 if (firewire_debug) 419 device_printf(sc->fc.dev, "phy read failed(2).\n"); 420 if (++retry < MAX_RETRY) { 421 DELAY(100); 422 goto again; 423 } 424 } 425 if (firewire_debug || retry >= MAX_RETRY) 426 device_printf(sc->fc.dev, 427 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 428 #undef MAX_RETRY 429 return((fun >> PHYDEV_RDDATA )& 0xff); 430 } 431 /* Device specific ioctl. */ 432 FW_IOCTL(fwohci) 433 { 434 FW_IOCTL_START; 435 struct fwohci_softc *fc; 436 int err = 0; 437 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 438 uint32_t *dmach = (uint32_t *) data; 439 440 if(sc == NULL){ 441 return(EINVAL); 442 } 443 fc = (struct fwohci_softc *)sc->fc; 444 445 if (!data) 446 return(EINVAL); 447 448 switch (cmd) { 449 case FWOHCI_WRREG: 450 #define OHCI_MAX_REG 0x800 451 if(reg->addr <= OHCI_MAX_REG){ 452 OWRITE(fc, reg->addr, reg->data); 453 reg->data = OREAD(fc, reg->addr); 454 }else{ 455 err = EINVAL; 456 } 457 break; 458 case FWOHCI_RDREG: 459 if(reg->addr <= OHCI_MAX_REG){ 460 reg->data = OREAD(fc, reg->addr); 461 }else{ 462 err = EINVAL; 463 } 464 break; 465 /* Read DMA descriptors for debug */ 466 case DUMPDMA: 467 if(*dmach <= OHCI_MAX_DMA_CH ){ 468 dump_dma(fc, *dmach); 469 dump_db(fc, *dmach); 470 }else{ 471 err = EINVAL; 472 } 473 break; 474 /* Read/Write Phy registers */ 475 #define OHCI_MAX_PHY_REG 0xf 476 case FWOHCI_RDPHYREG: 477 if (reg->addr <= OHCI_MAX_PHY_REG) 478 reg->data = fwphy_rddata(fc, reg->addr); 479 else 480 err = EINVAL; 481 break; 482 case FWOHCI_WRPHYREG: 483 if (reg->addr <= OHCI_MAX_PHY_REG) 484 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 485 else 486 err = EINVAL; 487 break; 488 default: 489 err = EINVAL; 490 break; 491 } 492 return err; 493 } 494 495 static int 496 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 497 { 498 uint32_t reg, reg2; 499 int e1394a = 1; 500 /* 501 * probe PHY parameters 502 * 0. to prove PHY version, whether compliance of 1394a. 503 * 1. to probe maximum speed supported by the PHY and 504 * number of port supported by core-logic. 505 * It is not actually available port on your PC . 506 */ 507 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 508 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 509 510 if((reg >> 5) != 7 ){ 511 sc->fc.mode &= ~FWPHYASYST; 512 sc->fc.nport = reg & FW_PHY_NP; 513 sc->fc.speed = reg & FW_PHY_SPD >> 6; 514 if (sc->fc.speed > MAX_SPEED) { 515 device_printf(dev, "invalid speed %d (fixed to %d).\n", 516 sc->fc.speed, MAX_SPEED); 517 sc->fc.speed = MAX_SPEED; 518 } 519 device_printf(dev, 520 "Phy 1394 only %s, %d ports.\n", 521 fw_linkspeed[sc->fc.speed], sc->fc.nport); 522 }else{ 523 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 524 sc->fc.mode |= FWPHYASYST; 525 sc->fc.nport = reg & FW_PHY_NP; 526 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 527 if (sc->fc.speed > MAX_SPEED) { 528 device_printf(dev, "invalid speed %d (fixed to %d).\n", 529 sc->fc.speed, MAX_SPEED); 530 sc->fc.speed = MAX_SPEED; 531 } 532 device_printf(dev, 533 "Phy 1394a available %s, %d ports.\n", 534 fw_linkspeed[sc->fc.speed], sc->fc.nport); 535 536 /* check programPhyEnable */ 537 reg2 = fwphy_rddata(sc, 5); 538 #if 0 539 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 540 #else /* XXX force to enable 1394a */ 541 if (e1394a) { 542 #endif 543 if (firewire_debug) 544 device_printf(dev, 545 "Enable 1394a Enhancements\n"); 546 /* enable EAA EMC */ 547 reg2 |= 0x03; 548 /* set aPhyEnhanceEnable */ 549 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 550 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 551 } 552 #if 0 553 else { 554 /* for safe */ 555 reg2 &= ~0x83; 556 } 557 #endif 558 reg2 = fwphy_wrdata(sc, 5, reg2); 559 } 560 561 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 562 if((reg >> 5) == 7 ){ 563 reg = fwphy_rddata(sc, 4); 564 reg |= 1 << 6; 565 fwphy_wrdata(sc, 4, reg); 566 reg = fwphy_rddata(sc, 4); 567 } 568 return 0; 569 } 570 571 572 void 573 fwohci_reset(struct fwohci_softc *sc, device_t dev) 574 { 575 int i, max_rec, speed; 576 uint32_t reg, reg2; 577 struct fwohcidb_tr *db_tr; 578 579 /* Disable interrupts */ 580 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 581 582 /* Now stopping all DMA channels */ 583 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 584 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 585 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 586 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 587 588 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 589 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 590 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 591 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 592 } 593 594 /* FLUSH FIFO and reset Transmitter/Reciever */ 595 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 596 if (firewire_debug) 597 device_printf(dev, "resetting OHCI..."); 598 i = 0; 599 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 600 if (i++ > 100) break; 601 DELAY(1000); 602 } 603 if (firewire_debug) 604 printf("done (loop=%d)\n", i); 605 606 /* Probe phy */ 607 fwohci_probe_phy(sc, dev); 608 609 /* Probe link */ 610 reg = OREAD(sc, OHCI_BUS_OPT); 611 reg2 = reg | OHCI_BUSFNC; 612 max_rec = (reg & 0x0000f000) >> 12; 613 speed = (reg & 0x00000007); 614 device_printf(dev, "Link %s, max_rec %d bytes.\n", 615 fw_linkspeed[speed], MAXREC(max_rec)); 616 /* XXX fix max_rec */ 617 sc->fc.maxrec = sc->fc.speed + 8; 618 if (max_rec != sc->fc.maxrec) { 619 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 620 device_printf(dev, "max_rec %d -> %d\n", 621 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 622 } 623 if (firewire_debug) 624 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 625 OWRITE(sc, OHCI_BUS_OPT, reg2); 626 627 /* Initialize registers */ 628 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 629 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 630 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 631 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 632 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 633 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 634 635 /* Enable link */ 636 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 637 638 /* Force to start async RX DMA */ 639 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 640 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 641 fwohci_rx_enable(sc, &sc->arrq); 642 fwohci_rx_enable(sc, &sc->arrs); 643 644 /* Initialize async TX */ 645 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 646 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 647 648 /* AT Retries */ 649 OWRITE(sc, FWOHCI_RETRY, 650 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 651 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 652 653 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 654 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 655 sc->atrq.bottom = sc->atrq.top; 656 sc->atrs.bottom = sc->atrs.top; 657 658 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 659 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 660 db_tr->xfer = NULL; 661 } 662 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 663 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 664 db_tr->xfer = NULL; 665 } 666 667 668 /* Enable interrupts */ 669 OWRITE(sc, FWOHCI_INTMASK, 670 OHCI_INT_ERR | OHCI_INT_PHY_SID 671 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 672 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 673 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 674 fwohci_set_intr(&sc->fc, 1); 675 676 } 677 678 int 679 fwohci_init(struct fwohci_softc *sc, device_t dev) 680 { 681 int i, mver; 682 uint32_t reg; 683 uint8_t ui[8]; 684 685 #if FWOHCI_TASKQUEUE 686 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 687 #endif 688 689 /* OHCI version */ 690 reg = OREAD(sc, OHCI_VERSION); 691 mver = (reg >> 16) & 0xff; 692 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 693 mver, reg & 0xff, (reg>>24) & 1); 694 if (mver < 1 || mver > 9) { 695 device_printf(dev, "invalid OHCI version\n"); 696 return (ENXIO); 697 } 698 699 /* Available Isochronous DMA channel probe */ 700 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 701 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 702 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 703 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 704 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 705 for (i = 0; i < 0x20; i++) 706 if ((reg & (1 << i)) == 0) 707 break; 708 sc->fc.nisodma = i; 709 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 710 if (i == 0) 711 return (ENXIO); 712 713 sc->fc.arq = &sc->arrq.xferq; 714 sc->fc.ars = &sc->arrs.xferq; 715 sc->fc.atq = &sc->atrq.xferq; 716 sc->fc.ats = &sc->atrs.xferq; 717 718 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 719 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 720 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 721 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 722 723 sc->arrq.xferq.start = NULL; 724 sc->arrs.xferq.start = NULL; 725 sc->atrq.xferq.start = fwohci_start_atq; 726 sc->atrs.xferq.start = fwohci_start_ats; 727 728 sc->arrq.xferq.buf = NULL; 729 sc->arrs.xferq.buf = NULL; 730 sc->atrq.xferq.buf = NULL; 731 sc->atrs.xferq.buf = NULL; 732 733 sc->arrq.xferq.dmach = -1; 734 sc->arrs.xferq.dmach = -1; 735 sc->atrq.xferq.dmach = -1; 736 sc->atrs.xferq.dmach = -1; 737 738 sc->arrq.ndesc = 1; 739 sc->arrs.ndesc = 1; 740 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 741 sc->atrs.ndesc = 2; 742 743 sc->arrq.ndb = NDB; 744 sc->arrs.ndb = NDB / 2; 745 sc->atrq.ndb = NDB; 746 sc->atrs.ndb = NDB / 2; 747 748 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 749 sc->fc.it[i] = &sc->it[i].xferq; 750 sc->fc.ir[i] = &sc->ir[i].xferq; 751 sc->it[i].xferq.dmach = i; 752 sc->ir[i].xferq.dmach = i; 753 sc->it[i].ndb = 0; 754 sc->ir[i].ndb = 0; 755 } 756 757 sc->fc.tcode = tinfo; 758 sc->fc.dev = dev; 759 760 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 761 &sc->crom_dma, BUS_DMA_WAITOK); 762 if(sc->fc.config_rom == NULL){ 763 device_printf(dev, "config_rom alloc failed."); 764 return ENOMEM; 765 } 766 767 #if 0 768 bzero(&sc->fc.config_rom[0], CROMSIZE); 769 sc->fc.config_rom[1] = 0x31333934; 770 sc->fc.config_rom[2] = 0xf000a002; 771 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 772 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 773 sc->fc.config_rom[5] = 0; 774 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 775 776 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 777 #endif 778 779 780 /* SID recieve buffer must align 2^11 */ 781 #define OHCI_SIDSIZE (1 << 11) 782 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 783 &sc->sid_dma, BUS_DMA_WAITOK); 784 if (sc->sid_buf == NULL) { 785 device_printf(dev, "sid_buf alloc failed."); 786 return ENOMEM; 787 } 788 789 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 790 &sc->dummy_dma, BUS_DMA_WAITOK); 791 792 if (sc->dummy_dma.v_addr == NULL) { 793 device_printf(dev, "dummy_dma alloc failed."); 794 return ENOMEM; 795 } 796 797 fwohci_db_init(sc, &sc->arrq); 798 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 799 return ENOMEM; 800 801 fwohci_db_init(sc, &sc->arrs); 802 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 803 return ENOMEM; 804 805 fwohci_db_init(sc, &sc->atrq); 806 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 807 return ENOMEM; 808 809 fwohci_db_init(sc, &sc->atrs); 810 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 811 return ENOMEM; 812 813 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 814 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 815 for( i = 0 ; i < 8 ; i ++) 816 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 817 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 818 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 819 820 sc->fc.ioctl = fwohci_ioctl; 821 sc->fc.cyctimer = fwohci_cyctimer; 822 sc->fc.set_bmr = fwohci_set_bus_manager; 823 sc->fc.ibr = fwohci_ibr; 824 sc->fc.irx_enable = fwohci_irx_enable; 825 sc->fc.irx_disable = fwohci_irx_disable; 826 827 sc->fc.itx_enable = fwohci_itxbuf_enable; 828 sc->fc.itx_disable = fwohci_itx_disable; 829 #if BYTE_ORDER == BIG_ENDIAN 830 sc->fc.irx_post = fwohci_irx_post; 831 #else 832 sc->fc.irx_post = NULL; 833 #endif 834 sc->fc.itx_post = NULL; 835 sc->fc.timeout = fwohci_timeout; 836 sc->fc.poll = fwohci_poll; 837 sc->fc.set_intr = fwohci_set_intr; 838 839 sc->intmask = sc->irstat = sc->itstat = 0; 840 841 fw_init(&sc->fc); 842 fwohci_reset(sc, dev); 843 FWOHCI_INIT_END; 844 845 return 0; 846 } 847 848 void 849 fwohci_timeout(void *arg) 850 { 851 struct fwohci_softc *sc; 852 853 sc = (struct fwohci_softc *)arg; 854 } 855 856 uint32_t 857 fwohci_cyctimer(struct firewire_comm *fc) 858 { 859 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 860 return(OREAD(sc, OHCI_CYCLETIMER)); 861 } 862 863 FWOHCI_DETACH() 864 { 865 int i; 866 867 FWOHCI_DETACH_START; 868 if (sc->sid_buf != NULL) 869 fwdma_free(&sc->fc, &sc->sid_dma); 870 if (sc->fc.config_rom != NULL) 871 fwdma_free(&sc->fc, &sc->crom_dma); 872 873 fwohci_db_free(&sc->arrq); 874 fwohci_db_free(&sc->arrs); 875 876 fwohci_db_free(&sc->atrq); 877 fwohci_db_free(&sc->atrs); 878 879 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 880 fwohci_db_free(&sc->it[i]); 881 fwohci_db_free(&sc->ir[i]); 882 } 883 FWOHCI_DETACH_END; 884 885 return 0; 886 } 887 888 #define LAST_DB(dbtr, db) do { \ 889 struct fwohcidb_tr *_dbtr = (dbtr); \ 890 int _cnt = _dbtr->dbcnt; \ 891 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 892 } while (0) 893 894 static void 895 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 896 { 897 struct fwohcidb_tr *db_tr; 898 struct fwohcidb *db; 899 bus_dma_segment_t *s; 900 int i; 901 902 db_tr = (struct fwohcidb_tr *)arg; 903 db = &db_tr->db[db_tr->dbcnt]; 904 if (error) { 905 if (firewire_debug || error != EFBIG) 906 printf("fwohci_execute_db: error=%d\n", error); 907 return; 908 } 909 for (i = 0; i < nseg; i++) { 910 s = &segs[i]; 911 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 912 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 913 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 914 db++; 915 db_tr->dbcnt++; 916 } 917 } 918 919 static void 920 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 921 bus_size_t size, int error) 922 { 923 fwohci_execute_db(arg, segs, nseg, error); 924 } 925 926 static void 927 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 928 { 929 int i, s; 930 int tcode, hdr_len, pl_off; 931 int fsegment = -1; 932 uint32_t off; 933 struct fw_xfer *xfer; 934 struct fw_pkt *fp; 935 struct fwohci_txpkthdr *ohcifp; 936 struct fwohcidb_tr *db_tr; 937 struct fwohcidb *db; 938 uint32_t *ld; 939 const struct tcode_info *info; 940 static int maxdesc=0; 941 942 if(&sc->atrq == dbch){ 943 off = OHCI_ATQOFF; 944 }else if(&sc->atrs == dbch){ 945 off = OHCI_ATSOFF; 946 }else{ 947 return; 948 } 949 950 if (dbch->flags & FWOHCI_DBCH_FULL) 951 return; 952 953 s = splfw(); 954 fwdma_sync_multiseg_all(dbch->am, 955 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 956 db_tr = dbch->top; 957 txloop: 958 xfer = STAILQ_FIRST(&dbch->xferq.q); 959 if(xfer == NULL){ 960 goto kick; 961 } 962 if(dbch->xferq.queued == 0 ){ 963 device_printf(sc->fc.dev, "TX queue empty\n"); 964 } 965 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 966 db_tr->xfer = xfer; 967 xfer->state = FWXF_START; 968 969 fp = &xfer->send.hdr; 970 tcode = fp->mode.common.tcode; 971 972 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 973 info = &tinfo[tcode]; 974 hdr_len = pl_off = info->hdr_len; 975 976 ld = &ohcifp->mode.ld[0]; 977 ld[0] = ld[1] = ld[2] = ld[3] = 0; 978 for( i = 0 ; i < pl_off ; i+= 4) 979 ld[i/4] = fp->mode.ld[i/4]; 980 981 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 982 if (tcode == FWTCODE_STREAM ){ 983 hdr_len = 8; 984 ohcifp->mode.stream.len = fp->mode.stream.len; 985 } else if (tcode == FWTCODE_PHY) { 986 hdr_len = 12; 987 ld[1] = fp->mode.ld[1]; 988 ld[2] = fp->mode.ld[2]; 989 ohcifp->mode.common.spd = 0; 990 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 991 } else { 992 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 993 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 994 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 995 } 996 db = &db_tr->db[0]; 997 FWOHCI_DMA_WRITE(db->db.desc.cmd, 998 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 999 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 1000 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 1001 /* Specify bound timer of asy. responce */ 1002 if(&sc->atrs == dbch){ 1003 FWOHCI_DMA_WRITE(db->db.desc.res, 1004 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1005 } 1006 #if BYTE_ORDER == BIG_ENDIAN 1007 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1008 hdr_len = 12; 1009 for (i = 0; i < hdr_len/4; i ++) 1010 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1011 #endif 1012 1013 again: 1014 db_tr->dbcnt = 2; 1015 db = &db_tr->db[db_tr->dbcnt]; 1016 if (xfer->send.pay_len > 0) { 1017 int err; 1018 /* handle payload */ 1019 if (xfer->mbuf == NULL) { 1020 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1021 &xfer->send.payload[0], xfer->send.pay_len, 1022 fwohci_execute_db, db_tr, 1023 BUS_DMA_WAITOK); 1024 } else { 1025 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1026 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1027 db_tr->dma_map, xfer->mbuf, 1028 fwohci_execute_db2, db_tr, 1029 BUS_DMA_WAITOK); 1030 if (err == EFBIG) { 1031 struct mbuf *m0; 1032 1033 if (firewire_debug) 1034 device_printf(sc->fc.dev, "EFBIG.\n"); 1035 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1036 if (m0 != NULL) { 1037 m_copydata(xfer->mbuf, 0, 1038 xfer->mbuf->m_pkthdr.len, 1039 mtod(m0, caddr_t)); 1040 m0->m_len = m0->m_pkthdr.len = 1041 xfer->mbuf->m_pkthdr.len; 1042 m_freem(xfer->mbuf); 1043 xfer->mbuf = m0; 1044 goto again; 1045 } 1046 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1047 } 1048 } 1049 if (err) 1050 printf("dmamap_load: err=%d\n", err); 1051 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1052 BUS_DMASYNC_PREWRITE); 1053 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1054 for (i = 2; i < db_tr->dbcnt; i++) 1055 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1056 OHCI_OUTPUT_MORE); 1057 #endif 1058 } 1059 if (maxdesc < db_tr->dbcnt) { 1060 maxdesc = db_tr->dbcnt; 1061 if (firewire_debug) 1062 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1063 } 1064 /* last db */ 1065 LAST_DB(db_tr, db); 1066 FWOHCI_DMA_SET(db->db.desc.cmd, 1067 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1068 FWOHCI_DMA_WRITE(db->db.desc.depend, 1069 STAILQ_NEXT(db_tr, link)->bus_addr); 1070 1071 if(fsegment == -1 ) 1072 fsegment = db_tr->dbcnt; 1073 if (dbch->pdb_tr != NULL) { 1074 LAST_DB(dbch->pdb_tr, db); 1075 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1076 } 1077 dbch->pdb_tr = db_tr; 1078 db_tr = STAILQ_NEXT(db_tr, link); 1079 if(db_tr != dbch->bottom){ 1080 goto txloop; 1081 } else { 1082 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1083 dbch->flags |= FWOHCI_DBCH_FULL; 1084 } 1085 kick: 1086 /* kick asy q */ 1087 fwdma_sync_multiseg_all(dbch->am, 1088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1089 1090 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1091 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1092 } else { 1093 if (firewire_debug) 1094 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1095 OREAD(sc, OHCI_DMACTL(off))); 1096 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1097 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1098 dbch->xferq.flag |= FWXFERQ_RUNNING; 1099 } 1100 CTR0(KTR_DEV, "start kick done"); 1101 CTR0(KTR_DEV, "start kick done2"); 1102 1103 dbch->top = db_tr; 1104 splx(s); 1105 return; 1106 } 1107 1108 static void 1109 fwohci_start_atq(struct firewire_comm *fc) 1110 { 1111 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1112 fwohci_start( sc, &(sc->atrq)); 1113 return; 1114 } 1115 1116 static void 1117 fwohci_start_ats(struct firewire_comm *fc) 1118 { 1119 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1120 fwohci_start( sc, &(sc->atrs)); 1121 return; 1122 } 1123 1124 void 1125 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1126 { 1127 int s, ch, err = 0; 1128 struct fwohcidb_tr *tr; 1129 struct fwohcidb *db; 1130 struct fw_xfer *xfer; 1131 uint32_t off; 1132 u_int stat, status; 1133 int packets; 1134 struct firewire_comm *fc = (struct firewire_comm *)sc; 1135 1136 if(&sc->atrq == dbch){ 1137 off = OHCI_ATQOFF; 1138 ch = ATRQ_CH; 1139 }else if(&sc->atrs == dbch){ 1140 off = OHCI_ATSOFF; 1141 ch = ATRS_CH; 1142 }else{ 1143 return; 1144 } 1145 s = splfw(); 1146 tr = dbch->bottom; 1147 packets = 0; 1148 fwdma_sync_multiseg_all(dbch->am, 1149 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1150 while(dbch->xferq.queued > 0){ 1151 LAST_DB(tr, db); 1152 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1153 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1154 if (fc->status != FWBUSRESET) 1155 /* maybe out of order?? */ 1156 goto out; 1157 } 1158 if (tr->xfer->send.pay_len > 0) { 1159 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1160 BUS_DMASYNC_POSTWRITE); 1161 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1162 } 1163 #if 1 1164 if (firewire_debug > 1) 1165 dump_db(sc, ch); 1166 #endif 1167 if(status & OHCI_CNTL_DMA_DEAD) { 1168 /* Stop DMA */ 1169 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1170 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1171 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1172 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1173 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1174 } 1175 stat = status & FWOHCIEV_MASK; 1176 switch(stat){ 1177 case FWOHCIEV_ACKPEND: 1178 CTR0(KTR_DEV, "txd: ack pending"); 1179 /* fall through */ 1180 case FWOHCIEV_ACKCOMPL: 1181 err = 0; 1182 break; 1183 case FWOHCIEV_ACKBSA: 1184 case FWOHCIEV_ACKBSB: 1185 case FWOHCIEV_ACKBSX: 1186 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1187 err = EBUSY; 1188 break; 1189 case FWOHCIEV_FLUSHED: 1190 case FWOHCIEV_ACKTARD: 1191 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1192 err = EAGAIN; 1193 break; 1194 case FWOHCIEV_MISSACK: 1195 case FWOHCIEV_UNDRRUN: 1196 case FWOHCIEV_OVRRUN: 1197 case FWOHCIEV_DESCERR: 1198 case FWOHCIEV_DTRDERR: 1199 case FWOHCIEV_TIMEOUT: 1200 case FWOHCIEV_TCODERR: 1201 case FWOHCIEV_UNKNOWN: 1202 case FWOHCIEV_ACKDERR: 1203 case FWOHCIEV_ACKTERR: 1204 default: 1205 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1206 stat, fwohcicode[stat]); 1207 err = EINVAL; 1208 break; 1209 } 1210 if (tr->xfer != NULL) { 1211 xfer = tr->xfer; 1212 CTR0(KTR_DEV, "txd"); 1213 if (xfer->state == FWXF_RCVD) { 1214 #if 0 1215 if (firewire_debug) 1216 printf("already rcvd\n"); 1217 #endif 1218 fw_xfer_done(xfer); 1219 } else { 1220 xfer->state = FWXF_SENT; 1221 if (err == EBUSY && fc->status != FWBUSRESET) { 1222 xfer->state = FWXF_BUSY; 1223 xfer->resp = err; 1224 xfer->recv.pay_len = 0; 1225 fw_xfer_done(xfer); 1226 } else if (stat != FWOHCIEV_ACKPEND) { 1227 if (stat != FWOHCIEV_ACKCOMPL) 1228 xfer->state = FWXF_SENTERR; 1229 xfer->resp = err; 1230 xfer->recv.pay_len = 0; 1231 fw_xfer_done(xfer); 1232 } 1233 } 1234 /* 1235 * The watchdog timer takes care of split 1236 * transcation timeout for ACKPEND case. 1237 */ 1238 } else { 1239 printf("this shouldn't happen\n"); 1240 } 1241 dbch->xferq.queued --; 1242 tr->xfer = NULL; 1243 1244 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); 1245 packets ++; 1246 tr = STAILQ_NEXT(tr, link); 1247 dbch->bottom = tr; 1248 if (dbch->bottom == dbch->top) { 1249 /* we reaches the end of context program */ 1250 if (firewire_debug && dbch->xferq.queued > 0) 1251 printf("queued > 0\n"); 1252 break; 1253 } 1254 } 1255 out: 1256 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1257 printf("make free slot\n"); 1258 dbch->flags &= ~FWOHCI_DBCH_FULL; 1259 fwohci_start(sc, dbch); 1260 } 1261 fwdma_sync_multiseg_all( 1262 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1263 splx(s); 1264 } 1265 1266 static void 1267 fwohci_db_free(struct fwohci_dbch *dbch) 1268 { 1269 struct fwohcidb_tr *db_tr; 1270 int idb; 1271 1272 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1273 return; 1274 1275 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1276 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1277 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1278 db_tr->buf != NULL) { 1279 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1280 db_tr->buf, dbch->xferq.psize); 1281 db_tr->buf = NULL; 1282 } else if (db_tr->dma_map != NULL) 1283 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1284 } 1285 dbch->ndb = 0; 1286 db_tr = STAILQ_FIRST(&dbch->db_trq); 1287 fwdma_free_multiseg(dbch->am); 1288 free(db_tr, M_FW); 1289 STAILQ_INIT(&dbch->db_trq); 1290 dbch->flags &= ~FWOHCI_DBCH_INIT; 1291 } 1292 1293 static void 1294 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1295 { 1296 int idb; 1297 struct fwohcidb_tr *db_tr; 1298 1299 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1300 goto out; 1301 1302 /* create dma_tag for buffers */ 1303 #define MAX_REQCOUNT 0xffff 1304 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1305 /*alignment*/ 1, /*boundary*/ 0, 1306 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1307 /*highaddr*/ BUS_SPACE_MAXADDR, 1308 /*filter*/NULL, /*filterarg*/NULL, 1309 /*maxsize*/ dbch->xferq.psize, 1310 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1311 /*maxsegsz*/ MAX_REQCOUNT, 1312 /*flags*/ 0, 1313 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 1314 /*lockfunc*/busdma_lock_mutex, 1315 /*lockarg*/&Giant, 1316 #endif 1317 &dbch->dmat)) 1318 return; 1319 1320 /* allocate DB entries and attach one to each DMA channels */ 1321 /* DB entry must start at 16 bytes bounary. */ 1322 STAILQ_INIT(&dbch->db_trq); 1323 db_tr = (struct fwohcidb_tr *) 1324 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1325 M_FW, M_WAITOK | M_ZERO); 1326 if(db_tr == NULL){ 1327 printf("fwohci_db_init: malloc(1) failed\n"); 1328 return; 1329 } 1330 1331 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1332 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1333 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1334 if (dbch->am == NULL) { 1335 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1336 free(db_tr, M_FW); 1337 return; 1338 } 1339 /* Attach DB to DMA ch. */ 1340 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1341 db_tr->dbcnt = 0; 1342 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1343 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1344 /* create dmamap for buffers */ 1345 /* XXX do we need 4bytes alignment tag? */ 1346 /* XXX don't alloc dma_map for AR */ 1347 if (bus_dmamap_create(sc->fc.dmat, dbch->xferq.psize, 1348 dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, MAX_REQCOUNT, 1349 0, BUS_DMA_NOWAIT, &db_tr->dma_map) != 0) { 1350 printf("bus_dmamap_create failed\n"); 1351 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1352 fwohci_db_free(dbch); 1353 return; 1354 } 1355 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1356 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1357 if (idb % dbch->xferq.bnpacket == 0) 1358 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1359 ].start = (caddr_t)db_tr; 1360 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1361 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1362 ].end = (caddr_t)db_tr; 1363 } 1364 db_tr++; 1365 } 1366 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1367 = STAILQ_FIRST(&dbch->db_trq); 1368 out: 1369 dbch->xferq.queued = 0; 1370 dbch->pdb_tr = NULL; 1371 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1372 dbch->bottom = dbch->top; 1373 dbch->flags = FWOHCI_DBCH_INIT; 1374 } 1375 1376 static int 1377 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1378 { 1379 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1380 int sleepch; 1381 1382 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1383 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1384 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1385 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1386 /* XXX we cannot free buffers until the DMA really stops */ 1387 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1388 fwohci_db_free(&sc->it[dmach]); 1389 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1390 return 0; 1391 } 1392 1393 static int 1394 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1395 { 1396 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1397 int sleepch; 1398 1399 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1400 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1401 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1402 /* XXX we cannot free buffers until the DMA really stops */ 1403 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1404 fwohci_db_free(&sc->ir[dmach]); 1405 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1406 return 0; 1407 } 1408 1409 #if BYTE_ORDER == BIG_ENDIAN 1410 static void 1411 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1412 { 1413 qld[0] = FWOHCI_DMA_READ(qld[0]); 1414 return; 1415 } 1416 #endif 1417 1418 static int 1419 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1420 { 1421 int err = 0; 1422 int idb, z, i, dmach = 0, ldesc; 1423 uint32_t off = 0; 1424 struct fwohcidb_tr *db_tr; 1425 struct fwohcidb *db; 1426 1427 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1428 err = EINVAL; 1429 return err; 1430 } 1431 z = dbch->ndesc; 1432 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1433 if( &sc->it[dmach] == dbch){ 1434 off = OHCI_ITOFF(dmach); 1435 break; 1436 } 1437 } 1438 if(off == 0){ 1439 err = EINVAL; 1440 return err; 1441 } 1442 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1443 return err; 1444 dbch->xferq.flag |= FWXFERQ_RUNNING; 1445 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1446 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1447 } 1448 db_tr = dbch->top; 1449 for (idb = 0; idb < dbch->ndb; idb ++) { 1450 fwohci_add_tx_buf(dbch, db_tr, idb); 1451 if(STAILQ_NEXT(db_tr, link) == NULL){ 1452 break; 1453 } 1454 db = db_tr->db; 1455 ldesc = db_tr->dbcnt - 1; 1456 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1457 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1458 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1459 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1460 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1461 FWOHCI_DMA_SET( 1462 db[ldesc].db.desc.cmd, 1463 OHCI_INTERRUPT_ALWAYS); 1464 /* OHCI 1.1 and above */ 1465 FWOHCI_DMA_SET( 1466 db[0].db.desc.cmd, 1467 OHCI_INTERRUPT_ALWAYS); 1468 } 1469 } 1470 db_tr = STAILQ_NEXT(db_tr, link); 1471 } 1472 FWOHCI_DMA_CLEAR( 1473 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1474 return err; 1475 } 1476 1477 static int 1478 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1479 { 1480 int err = 0; 1481 int idb, z, i, dmach = 0, ldesc; 1482 uint32_t off = 0; 1483 struct fwohcidb_tr *db_tr; 1484 struct fwohcidb *db; 1485 1486 z = dbch->ndesc; 1487 if(&sc->arrq == dbch){ 1488 off = OHCI_ARQOFF; 1489 }else if(&sc->arrs == dbch){ 1490 off = OHCI_ARSOFF; 1491 }else{ 1492 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1493 if( &sc->ir[dmach] == dbch){ 1494 off = OHCI_IROFF(dmach); 1495 break; 1496 } 1497 } 1498 } 1499 if(off == 0){ 1500 err = EINVAL; 1501 return err; 1502 } 1503 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1504 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1505 return err; 1506 }else{ 1507 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1508 err = EBUSY; 1509 return err; 1510 } 1511 } 1512 dbch->xferq.flag |= FWXFERQ_RUNNING; 1513 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1514 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1515 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1516 } 1517 db_tr = dbch->top; 1518 for (idb = 0; idb < dbch->ndb; idb ++) { 1519 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1520 if (STAILQ_NEXT(db_tr, link) == NULL) 1521 break; 1522 db = db_tr->db; 1523 ldesc = db_tr->dbcnt - 1; 1524 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1525 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1526 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1527 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1528 FWOHCI_DMA_SET( 1529 db[ldesc].db.desc.cmd, 1530 OHCI_INTERRUPT_ALWAYS); 1531 FWOHCI_DMA_CLEAR( 1532 db[ldesc].db.desc.depend, 1533 0xf); 1534 } 1535 } 1536 db_tr = STAILQ_NEXT(db_tr, link); 1537 } 1538 FWOHCI_DMA_CLEAR( 1539 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1540 dbch->buf_offset = 0; 1541 fwdma_sync_multiseg_all(dbch->am, 1542 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1543 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1544 return err; 1545 }else{ 1546 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1547 } 1548 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1549 return err; 1550 } 1551 1552 static int 1553 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1554 { 1555 int sec, cycle, cycle_match; 1556 1557 cycle = cycle_now & 0x1fff; 1558 sec = cycle_now >> 13; 1559 #define CYCLE_MOD 0x10 1560 #if 1 1561 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1562 #else 1563 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1564 #endif 1565 cycle = cycle + CYCLE_DELAY; 1566 if (cycle >= 8000) { 1567 sec ++; 1568 cycle -= 8000; 1569 } 1570 cycle = roundup2(cycle, CYCLE_MOD); 1571 if (cycle >= 8000) { 1572 sec ++; 1573 if (cycle == 8000) 1574 cycle = 0; 1575 else 1576 cycle = CYCLE_MOD; 1577 } 1578 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1579 1580 return(cycle_match); 1581 } 1582 1583 static int 1584 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1585 { 1586 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1587 int err = 0; 1588 unsigned short tag, ich; 1589 struct fwohci_dbch *dbch; 1590 int cycle_match, cycle_now, s, ldesc; 1591 uint32_t stat; 1592 struct fw_bulkxfer *first, *chunk, *prev; 1593 struct fw_xferq *it; 1594 1595 dbch = &sc->it[dmach]; 1596 it = &dbch->xferq; 1597 1598 tag = (it->flag >> 6) & 3; 1599 ich = it->flag & 0x3f; 1600 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1601 dbch->ndb = it->bnpacket * it->bnchunk; 1602 dbch->ndesc = 3; 1603 fwohci_db_init(sc, dbch); 1604 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1605 return ENOMEM; 1606 err = fwohci_tx_enable(sc, dbch); 1607 } 1608 if(err) 1609 return err; 1610 1611 ldesc = dbch->ndesc - 1; 1612 s = splfw(); 1613 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1614 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1615 struct fwohcidb *db; 1616 1617 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1618 BUS_DMASYNC_PREWRITE); 1619 fwohci_txbufdb(sc, dmach, chunk); 1620 if (prev != NULL) { 1621 db = ((struct fwohcidb_tr *)(prev->end))->db; 1622 #if 0 /* XXX necessary? */ 1623 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1624 OHCI_BRANCH_ALWAYS); 1625 #endif 1626 #if 0 /* if bulkxfer->npacket changes */ 1627 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1628 ((struct fwohcidb_tr *) 1629 (chunk->start))->bus_addr | dbch->ndesc; 1630 #else 1631 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1632 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1633 #endif 1634 } 1635 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1636 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1637 prev = chunk; 1638 } 1639 fwdma_sync_multiseg_all(dbch->am, 1640 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1641 splx(s); 1642 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1643 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1644 printf("stat 0x%x\n", stat); 1645 1646 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1647 return 0; 1648 1649 #if 0 1650 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1651 #endif 1652 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1653 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1654 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1655 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1656 1657 first = STAILQ_FIRST(&it->stdma); 1658 OWRITE(sc, OHCI_ITCMD(dmach), 1659 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1660 if (firewire_debug > 1) { 1661 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1662 #if 1 1663 dump_dma(sc, ITX_CH + dmach); 1664 #endif 1665 } 1666 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1667 #if 1 1668 /* Don't start until all chunks are buffered */ 1669 if (STAILQ_FIRST(&it->stfree) != NULL) 1670 goto out; 1671 #endif 1672 #if 1 1673 /* Clear cycle match counter bits */ 1674 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1675 1676 /* 2bit second + 13bit cycle */ 1677 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1678 cycle_match = fwohci_next_cycle(fc, cycle_now); 1679 1680 OWRITE(sc, OHCI_ITCTL(dmach), 1681 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1682 | OHCI_CNTL_DMA_RUN); 1683 #else 1684 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1685 #endif 1686 if (firewire_debug > 1) { 1687 printf("cycle_match: 0x%04x->0x%04x\n", 1688 cycle_now, cycle_match); 1689 dump_dma(sc, ITX_CH + dmach); 1690 dump_db(sc, ITX_CH + dmach); 1691 } 1692 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1693 device_printf(sc->fc.dev, 1694 "IT DMA underrun (0x%08x)\n", stat); 1695 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1696 } 1697 out: 1698 return err; 1699 } 1700 1701 static int 1702 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1703 { 1704 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1705 int err = 0, s, ldesc; 1706 unsigned short tag, ich; 1707 uint32_t stat; 1708 struct fwohci_dbch *dbch; 1709 struct fwohcidb_tr *db_tr; 1710 struct fw_bulkxfer *first, *prev, *chunk; 1711 struct fw_xferq *ir; 1712 1713 dbch = &sc->ir[dmach]; 1714 ir = &dbch->xferq; 1715 1716 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1717 tag = (ir->flag >> 6) & 3; 1718 ich = ir->flag & 0x3f; 1719 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1720 1721 ir->queued = 0; 1722 dbch->ndb = ir->bnpacket * ir->bnchunk; 1723 dbch->ndesc = 2; 1724 fwohci_db_init(sc, dbch); 1725 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1726 return ENOMEM; 1727 err = fwohci_rx_enable(sc, dbch); 1728 } 1729 if(err) 1730 return err; 1731 1732 first = STAILQ_FIRST(&ir->stfree); 1733 if (first == NULL) { 1734 device_printf(fc->dev, "IR DMA no free chunk\n"); 1735 return 0; 1736 } 1737 1738 ldesc = dbch->ndesc - 1; 1739 s = splfw(); 1740 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1741 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1742 struct fwohcidb *db; 1743 1744 #if 1 /* XXX for if_fwe */ 1745 if (chunk->mbuf != NULL) { 1746 db_tr = (struct fwohcidb_tr *)(chunk->start); 1747 db_tr->dbcnt = 1; 1748 err = fw_bus_dmamap_load_mbuf( 1749 dbch->dmat, db_tr->dma_map, 1750 chunk->mbuf, fwohci_execute_db2, db_tr, 1751 BUS_DMA_WAITOK); 1752 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1753 OHCI_UPDATE | OHCI_INPUT_LAST | 1754 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1755 } 1756 #endif 1757 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1758 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1759 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1760 if (prev != NULL) { 1761 db = ((struct fwohcidb_tr *)(prev->end))->db; 1762 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1763 } 1764 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1765 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1766 prev = chunk; 1767 } 1768 fwdma_sync_multiseg_all(dbch->am, 1769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1770 splx(s); 1771 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1772 if (stat & OHCI_CNTL_DMA_ACTIVE) 1773 return 0; 1774 if (stat & OHCI_CNTL_DMA_RUN) { 1775 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1776 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1777 } 1778 1779 if (firewire_debug) 1780 printf("start IR DMA 0x%x\n", stat); 1781 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1782 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1783 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1784 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1785 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1786 OWRITE(sc, OHCI_IRCMD(dmach), 1787 ((struct fwohcidb_tr *)(first->start))->bus_addr 1788 | dbch->ndesc); 1789 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1790 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1791 #if 0 1792 dump_db(sc, IRX_CH + dmach); 1793 #endif 1794 return err; 1795 } 1796 1797 FWOHCI_STOP() 1798 { 1799 FWOHCI_STOP_START; 1800 u_int i; 1801 1802 /* Now stopping all DMA channel */ 1803 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1804 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1805 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1806 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1807 1808 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1809 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1810 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1811 } 1812 1813 /* FLUSH FIFO and reset Transmitter/Reciever */ 1814 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1815 1816 /* Stop interrupt */ 1817 OWRITE(sc, FWOHCI_INTMASKCLR, 1818 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1819 | OHCI_INT_PHY_INT 1820 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1821 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1822 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1823 | OHCI_INT_PHY_BUS_R); 1824 1825 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1826 fw_drain_txq(&sc->fc); 1827 1828 /* XXX Link down? Bus reset? */ 1829 FWOHCI_STOP_RETURN(0); 1830 } 1831 1832 #if defined(__NetBSD__) 1833 static void 1834 fwohci_power(int why, void *arg) 1835 { 1836 struct fwohci_softc *sc = arg; 1837 int s; 1838 1839 s = splbio(); 1840 switch (why) { 1841 case PWR_SUSPEND: 1842 case PWR_STANDBY: 1843 fwohci_stop(arg); 1844 break; 1845 case PWR_RESUME: 1846 fwohci_resume(sc, sc->fc.dev); 1847 break; 1848 case PWR_SOFTSUSPEND: 1849 case PWR_SOFTSTANDBY: 1850 case PWR_SOFTRESUME: 1851 break; 1852 } 1853 splx(s); 1854 } 1855 #endif 1856 1857 int 1858 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1859 { 1860 int i; 1861 struct fw_xferq *ir; 1862 struct fw_bulkxfer *chunk; 1863 1864 fwohci_reset(sc, dev); 1865 /* XXX resume isochronous receive automatically. (how about TX?) */ 1866 for(i = 0; i < sc->fc.nisodma; i ++) { 1867 ir = &sc->ir[i].xferq; 1868 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1869 device_printf(sc->fc.dev, 1870 "resume iso receive ch: %d\n", i); 1871 ir->flag &= ~FWXFERQ_RUNNING; 1872 /* requeue stdma to stfree */ 1873 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1874 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1875 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1876 } 1877 sc->fc.irx_enable(&sc->fc, i); 1878 } 1879 } 1880 1881 #if defined(__FreeBSD__) 1882 bus_generic_resume(dev); 1883 #endif 1884 sc->fc.ibr(&sc->fc); 1885 return 0; 1886 } 1887 1888 #define ACK_ALL 1889 static void 1890 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1891 { 1892 uint32_t irstat, itstat; 1893 u_int i; 1894 struct firewire_comm *fc = (struct firewire_comm *)sc; 1895 1896 CTR0(KTR_DEV, "fwohci_intr_body"); 1897 #ifdef OHCI_DEBUG 1898 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1899 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1900 stat & OHCI_INT_EN ? "DMA_EN ":"", 1901 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1902 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1903 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1904 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1905 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1906 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1907 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1908 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1909 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1910 stat & OHCI_INT_PHY_SID ? "SID ":"", 1911 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1912 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1913 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1914 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1915 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1916 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1917 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1918 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1919 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1920 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1921 stat, OREAD(sc, FWOHCI_INTMASK) 1922 ); 1923 #endif 1924 /* Bus reset */ 1925 if(stat & OHCI_INT_PHY_BUS_R ){ 1926 if (fc->status == FWBUSRESET) 1927 goto busresetout; 1928 /* Disable bus reset interrupt until sid recv. */ 1929 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1930 1931 device_printf(fc->dev, "BUS reset\n"); 1932 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1933 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1934 1935 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1936 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1937 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1938 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1939 1940 #ifndef ACK_ALL 1941 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1942 #endif 1943 fw_busreset(fc); 1944 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1945 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1946 } 1947 busresetout: 1948 if((stat & OHCI_INT_DMA_IR )){ 1949 #ifndef ACK_ALL 1950 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1951 #endif 1952 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1953 irstat = sc->irstat; 1954 sc->irstat = 0; 1955 #else 1956 irstat = atomic_readandclear_int(&sc->irstat); 1957 #endif 1958 for(i = 0; i < fc->nisodma ; i++){ 1959 struct fwohci_dbch *dbch; 1960 1961 if((irstat & (1 << i)) != 0){ 1962 dbch = &sc->ir[i]; 1963 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1964 device_printf(sc->fc.dev, 1965 "dma(%d) not active\n", i); 1966 continue; 1967 } 1968 fwohci_rbuf_update(sc, i); 1969 } 1970 } 1971 } 1972 if((stat & OHCI_INT_DMA_IT )){ 1973 #ifndef ACK_ALL 1974 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1975 #endif 1976 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1977 itstat = sc->itstat; 1978 sc->itstat = 0; 1979 #else 1980 itstat = atomic_readandclear_int(&sc->itstat); 1981 #endif 1982 for(i = 0; i < fc->nisodma ; i++){ 1983 if((itstat & (1 << i)) != 0){ 1984 fwohci_tbuf_update(sc, i); 1985 } 1986 } 1987 } 1988 if((stat & OHCI_INT_DMA_PRRS )){ 1989 #ifndef ACK_ALL 1990 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1991 #endif 1992 #if 0 1993 dump_dma(sc, ARRS_CH); 1994 dump_db(sc, ARRS_CH); 1995 #endif 1996 fwohci_arcv(sc, &sc->arrs, count); 1997 } 1998 if((stat & OHCI_INT_DMA_PRRQ )){ 1999 #ifndef ACK_ALL 2000 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 2001 #endif 2002 #if 0 2003 dump_dma(sc, ARRQ_CH); 2004 dump_db(sc, ARRQ_CH); 2005 #endif 2006 fwohci_arcv(sc, &sc->arrq, count); 2007 } 2008 if (stat & OHCI_INT_CYC_LOST) { 2009 if (sc->cycle_lost >= 0) 2010 sc->cycle_lost ++; 2011 if (sc->cycle_lost > 10) { 2012 sc->cycle_lost = -1; 2013 #if 0 2014 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 2015 #endif 2016 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 2017 device_printf(fc->dev, "too many cycle lost, " 2018 "no cycle master presents?\n"); 2019 } 2020 } 2021 if(stat & OHCI_INT_PHY_SID){ 2022 uint32_t *buf, node_id; 2023 int plen; 2024 2025 #ifndef ACK_ALL 2026 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2027 #endif 2028 /* Enable bus reset interrupt */ 2029 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2030 /* Allow async. request to us */ 2031 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2032 /* XXX insecure ?? */ 2033 /* allow from all nodes */ 2034 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2035 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2036 /* 0 to 4GB regison */ 2037 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2038 /* Set ATRetries register */ 2039 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2040 /* 2041 ** Checking whether the node is root or not. If root, turn on 2042 ** cycle master. 2043 */ 2044 node_id = OREAD(sc, FWOHCI_NODEID); 2045 plen = OREAD(sc, OHCI_SID_CNT); 2046 2047 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2048 node_id, (plen >> 16) & 0xff); 2049 if (!(node_id & OHCI_NODE_VALID)) { 2050 printf("Bus reset failure\n"); 2051 goto sidout; 2052 } 2053 2054 /* cycle timer */ 2055 sc->cycle_lost = 0; 2056 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2057 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2058 printf("CYCLEMASTER mode\n"); 2059 OWRITE(sc, OHCI_LNKCTL, 2060 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2061 } else { 2062 printf("non CYCLEMASTER mode\n"); 2063 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2064 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2065 } 2066 2067 fc->nodeid = node_id & 0x3f; 2068 2069 if (plen & OHCI_SID_ERR) { 2070 device_printf(fc->dev, "SID Error\n"); 2071 goto sidout; 2072 } 2073 plen &= OHCI_SID_CNT_MASK; 2074 if (plen < 4 || plen > OHCI_SIDSIZE) { 2075 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2076 goto sidout; 2077 } 2078 plen -= 4; /* chop control info */ 2079 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2080 if (buf == NULL) { 2081 device_printf(fc->dev, "malloc failed\n"); 2082 goto sidout; 2083 } 2084 for (i = 0; i < plen / 4; i ++) 2085 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2086 #if defined(__NetBSD__) && defined(macppc) 2087 /* XXX required as bootdisk for macppc. */ 2088 delay(500000); 2089 #endif 2090 #if 1 /* XXX needed?? */ 2091 /* pending all pre-bus_reset packets */ 2092 fwohci_txd(sc, &sc->atrq); 2093 fwohci_txd(sc, &sc->atrs); 2094 fwohci_arcv(sc, &sc->arrs, -1); 2095 fwohci_arcv(sc, &sc->arrq, -1); 2096 fw_drain_txq(fc); 2097 #endif 2098 fw_sidrcv(fc, buf, plen); 2099 free(buf, M_FW); 2100 } 2101 sidout: 2102 if((stat & OHCI_INT_DMA_ATRQ )){ 2103 #ifndef ACK_ALL 2104 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2105 #endif 2106 fwohci_txd(sc, &(sc->atrq)); 2107 } 2108 if((stat & OHCI_INT_DMA_ATRS )){ 2109 #ifndef ACK_ALL 2110 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2111 #endif 2112 fwohci_txd(sc, &(sc->atrs)); 2113 } 2114 if((stat & OHCI_INT_PW_ERR )){ 2115 #ifndef ACK_ALL 2116 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2117 #endif 2118 device_printf(fc->dev, "posted write error\n"); 2119 } 2120 if((stat & OHCI_INT_ERR )){ 2121 #ifndef ACK_ALL 2122 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2123 #endif 2124 device_printf(fc->dev, "unrecoverable error\n"); 2125 } 2126 if((stat & OHCI_INT_PHY_INT)) { 2127 #ifndef ACK_ALL 2128 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2129 #endif 2130 device_printf(fc->dev, "phy int\n"); 2131 } 2132 2133 CTR0(KTR_DEV, "fwohci_intr_body done"); 2134 return; 2135 } 2136 2137 #if FWOHCI_TASKQUEUE 2138 static void 2139 fwohci_complete(void *arg, int pending) 2140 { 2141 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2142 uint32_t stat; 2143 2144 again: 2145 stat = atomic_readandclear_int(&sc->intstat); 2146 if (stat) { 2147 FW_LOCK; 2148 fwohci_intr_body(sc, stat, -1); 2149 FW_UNLOCK; 2150 } else 2151 return; 2152 goto again; 2153 } 2154 #endif 2155 2156 static uint32_t 2157 fwochi_check_stat(struct fwohci_softc *sc) 2158 { 2159 uint32_t stat, irstat, itstat; 2160 2161 stat = OREAD(sc, FWOHCI_INTSTAT); 2162 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2163 if (stat == 0xffffffff) { 2164 device_printf(sc->fc.dev, 2165 "device physically ejected?\n"); 2166 return(stat); 2167 } 2168 #ifdef ACK_ALL 2169 if (stat) 2170 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2171 #endif 2172 if (stat & OHCI_INT_DMA_IR) { 2173 irstat = OREAD(sc, OHCI_IR_STAT); 2174 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2175 atomic_set_int(&sc->irstat, irstat); 2176 } 2177 if (stat & OHCI_INT_DMA_IT) { 2178 itstat = OREAD(sc, OHCI_IT_STAT); 2179 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2180 atomic_set_int(&sc->itstat, itstat); 2181 } 2182 return(stat); 2183 } 2184 2185 FW_INTR(fwohci) 2186 { 2187 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2188 uint32_t stat; 2189 #if !FWOHCI_TASKQUEUE 2190 uint32_t bus_reset = 0; 2191 #endif 2192 2193 if (!(sc->intmask & OHCI_INT_EN)) { 2194 /* polling mode */ 2195 FW_INTR_RETURN(0); 2196 } 2197 2198 #if !FWOHCI_TASKQUEUE 2199 again: 2200 #endif 2201 CTR0(KTR_DEV, "fwohci_intr"); 2202 stat = fwochi_check_stat(sc); 2203 if (stat == 0 || stat == 0xffffffff) 2204 FW_INTR_RETURN(1); 2205 #if FWOHCI_TASKQUEUE 2206 atomic_set_int(&sc->intstat, stat); 2207 /* XXX mask bus reset intr. during bus reset phase */ 2208 if (stat) 2209 #if 1 2210 taskqueue_enqueue_fast(taskqueue_fast, 2211 &sc->fwohci_task_complete); 2212 #else 2213 taskqueue_enqueue(taskqueue_swi, 2214 &sc->fwohci_task_complete); 2215 #endif 2216 #else 2217 /* We cannot clear bus reset event during bus reset phase */ 2218 if ((stat & ~bus_reset) == 0) 2219 FW_INTR_RETURN(1); 2220 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2221 fwohci_intr_body(sc, stat, -1); 2222 goto again; 2223 #endif 2224 CTR0(KTR_DEV, "fwohci_intr end"); 2225 } 2226 2227 void 2228 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2229 { 2230 int s; 2231 uint32_t stat; 2232 struct fwohci_softc *sc; 2233 2234 2235 sc = (struct fwohci_softc *)fc; 2236 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2237 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2238 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2239 #if 0 2240 if (!quick) { 2241 #else 2242 if (1) { 2243 #endif 2244 stat = fwochi_check_stat(sc); 2245 if (stat == 0 || stat == 0xffffffff) 2246 return; 2247 } 2248 s = splfw(); 2249 fwohci_intr_body(sc, stat, count); 2250 splx(s); 2251 } 2252 2253 static void 2254 fwohci_set_intr(struct firewire_comm *fc, int enable) 2255 { 2256 struct fwohci_softc *sc; 2257 2258 sc = (struct fwohci_softc *)fc; 2259 if (firewire_debug) 2260 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2261 if (enable) { 2262 sc->intmask |= OHCI_INT_EN; 2263 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2264 } else { 2265 sc->intmask &= ~OHCI_INT_EN; 2266 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2267 } 2268 } 2269 2270 static void 2271 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2272 { 2273 struct firewire_comm *fc = &sc->fc; 2274 struct fwohcidb *db; 2275 struct fw_bulkxfer *chunk; 2276 struct fw_xferq *it; 2277 uint32_t stat, count; 2278 int s, w=0, ldesc; 2279 2280 it = fc->it[dmach]; 2281 ldesc = sc->it[dmach].ndesc - 1; 2282 s = splfw(); /* unnecessary ? */ 2283 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); 2284 if (firewire_debug) 2285 dump_db(sc, ITX_CH + dmach); 2286 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2287 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2288 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2289 >> OHCI_STATUS_SHIFT; 2290 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2291 /* timestamp */ 2292 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2293 & OHCI_COUNT_MASK; 2294 if (stat == 0) 2295 break; 2296 STAILQ_REMOVE_HEAD(&it->stdma, link); 2297 switch (stat & FWOHCIEV_MASK){ 2298 case FWOHCIEV_ACKCOMPL: 2299 #if 0 2300 device_printf(fc->dev, "0x%08x\n", count); 2301 #endif 2302 break; 2303 default: 2304 device_printf(fc->dev, 2305 "Isochronous transmit err %02x(%s)\n", 2306 stat, fwohcicode[stat & 0x1f]); 2307 } 2308 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2309 w++; 2310 } 2311 splx(s); 2312 if (w) 2313 wakeup(it); 2314 } 2315 2316 static void 2317 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2318 { 2319 struct firewire_comm *fc = &sc->fc; 2320 struct fwohcidb_tr *db_tr; 2321 struct fw_bulkxfer *chunk; 2322 struct fw_xferq *ir; 2323 uint32_t stat; 2324 int s, w=0, ldesc; 2325 2326 ir = fc->ir[dmach]; 2327 ldesc = sc->ir[dmach].ndesc - 1; 2328 #if 0 2329 dump_db(sc, dmach); 2330 #endif 2331 s = splfw(); 2332 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); 2333 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2334 db_tr = (struct fwohcidb_tr *)chunk->end; 2335 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2336 >> OHCI_STATUS_SHIFT; 2337 if (stat == 0) 2338 break; 2339 2340 if (chunk->mbuf != NULL) { 2341 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2342 BUS_DMASYNC_POSTREAD); 2343 fw_bus_dmamap_unload( 2344 sc->ir[dmach].dmat, db_tr->dma_map); 2345 } else if (ir->buf != NULL) { 2346 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2347 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2348 } else { 2349 /* XXX */ 2350 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2351 } 2352 2353 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2354 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2355 switch (stat & FWOHCIEV_MASK) { 2356 case FWOHCIEV_ACKCOMPL: 2357 chunk->resp = 0; 2358 break; 2359 default: 2360 chunk->resp = EINVAL; 2361 device_printf(fc->dev, 2362 "Isochronous receive err %02x(%s)\n", 2363 stat, fwohcicode[stat & 0x1f]); 2364 } 2365 w++; 2366 } 2367 splx(s); 2368 if (w) { 2369 if (ir->flag & FWXFERQ_HANDLER) 2370 ir->hand(ir); 2371 else 2372 wakeup(ir); 2373 } 2374 } 2375 2376 void 2377 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2378 { 2379 uint32_t off, cntl, stat, cmd, match; 2380 2381 if(ch == 0){ 2382 off = OHCI_ATQOFF; 2383 }else if(ch == 1){ 2384 off = OHCI_ATSOFF; 2385 }else if(ch == 2){ 2386 off = OHCI_ARQOFF; 2387 }else if(ch == 3){ 2388 off = OHCI_ARSOFF; 2389 }else if(ch < IRX_CH){ 2390 off = OHCI_ITCTL(ch - ITX_CH); 2391 }else{ 2392 off = OHCI_IRCTL(ch - IRX_CH); 2393 } 2394 cntl = stat = OREAD(sc, off); 2395 cmd = OREAD(sc, off + 0xc); 2396 match = OREAD(sc, off + 0x10); 2397 2398 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2399 ch, 2400 cntl, 2401 cmd, 2402 match); 2403 stat &= 0xffff ; 2404 if (stat) { 2405 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2406 ch, 2407 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2408 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2409 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2410 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2411 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2412 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2413 fwohcicode[stat & 0x1f], 2414 stat & 0x1f 2415 ); 2416 }else{ 2417 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2418 } 2419 } 2420 2421 void 2422 dump_db(struct fwohci_softc *sc, uint32_t ch) 2423 { 2424 struct fwohci_dbch *dbch; 2425 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2426 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2427 int idb, jdb; 2428 uint32_t cmd, off; 2429 if(ch == 0){ 2430 off = OHCI_ATQOFF; 2431 dbch = &sc->atrq; 2432 }else if(ch == 1){ 2433 off = OHCI_ATSOFF; 2434 dbch = &sc->atrs; 2435 }else if(ch == 2){ 2436 off = OHCI_ARQOFF; 2437 dbch = &sc->arrq; 2438 }else if(ch == 3){ 2439 off = OHCI_ARSOFF; 2440 dbch = &sc->arrs; 2441 }else if(ch < IRX_CH){ 2442 off = OHCI_ITCTL(ch - ITX_CH); 2443 dbch = &sc->it[ch - ITX_CH]; 2444 }else { 2445 off = OHCI_IRCTL(ch - IRX_CH); 2446 dbch = &sc->ir[ch - IRX_CH]; 2447 } 2448 cmd = OREAD(sc, off + 0xc); 2449 2450 if( dbch->ndb == 0 ){ 2451 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2452 return; 2453 } 2454 pp = dbch->top; 2455 prev = pp->db; 2456 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2457 cp = STAILQ_NEXT(pp, link); 2458 if(cp == NULL){ 2459 curr = NULL; 2460 goto outdb; 2461 } 2462 np = STAILQ_NEXT(cp, link); 2463 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2464 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2465 curr = cp->db; 2466 if(np != NULL){ 2467 next = np->db; 2468 }else{ 2469 next = NULL; 2470 } 2471 goto outdb; 2472 } 2473 } 2474 pp = STAILQ_NEXT(pp, link); 2475 if(pp == NULL){ 2476 curr = NULL; 2477 goto outdb; 2478 } 2479 prev = pp->db; 2480 } 2481 outdb: 2482 if( curr != NULL){ 2483 #if 0 2484 printf("Prev DB %d\n", ch); 2485 print_db(pp, prev, ch, dbch->ndesc); 2486 #endif 2487 printf("Current DB %d\n", ch); 2488 print_db(cp, curr, ch, dbch->ndesc); 2489 #if 0 2490 printf("Next DB %d\n", ch); 2491 print_db(np, next, ch, dbch->ndesc); 2492 #endif 2493 }else{ 2494 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2495 } 2496 return; 2497 } 2498 2499 void 2500 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2501 uint32_t ch, uint32_t hogemax) 2502 { 2503 fwohcireg_t stat; 2504 int i, key; 2505 uint32_t cmd, res; 2506 2507 if(db == NULL){ 2508 printf("No Descriptor is found\n"); 2509 return; 2510 } 2511 2512 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2513 ch, 2514 "Current", 2515 "OP ", 2516 "KEY", 2517 "INT", 2518 "BR ", 2519 "len", 2520 "Addr", 2521 "Depend", 2522 "Stat", 2523 "Cnt"); 2524 for( i = 0 ; i <= hogemax ; i ++){ 2525 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2526 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2527 key = cmd & OHCI_KEY_MASK; 2528 stat = res >> OHCI_STATUS_SHIFT; 2529 #if defined(__DragonFly__) || \ 2530 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2531 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2532 db_tr->bus_addr, 2533 #else 2534 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2535 (uintmax_t)db_tr->bus_addr, 2536 #endif 2537 dbcode[(cmd >> 28) & 0xf], 2538 dbkey[(cmd >> 24) & 0x7], 2539 dbcond[(cmd >> 20) & 0x3], 2540 dbcond[(cmd >> 18) & 0x3], 2541 cmd & OHCI_COUNT_MASK, 2542 FWOHCI_DMA_READ(db[i].db.desc.addr), 2543 FWOHCI_DMA_READ(db[i].db.desc.depend), 2544 stat, 2545 res & OHCI_COUNT_MASK); 2546 if(stat & 0xff00){ 2547 printf(" %s%s%s%s%s%s %s(%x)\n", 2548 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2549 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2550 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2551 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2552 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2553 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2554 fwohcicode[stat & 0x1f], 2555 stat & 0x1f 2556 ); 2557 }else{ 2558 printf(" Nostat\n"); 2559 } 2560 if(key == OHCI_KEY_ST2 ){ 2561 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2562 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2563 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2564 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2565 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2566 } 2567 if(key == OHCI_KEY_DEVICE){ 2568 return; 2569 } 2570 if((cmd & OHCI_BRANCH_MASK) 2571 == OHCI_BRANCH_ALWAYS){ 2572 return; 2573 } 2574 if((cmd & OHCI_CMD_MASK) 2575 == OHCI_OUTPUT_LAST){ 2576 return; 2577 } 2578 if((cmd & OHCI_CMD_MASK) 2579 == OHCI_INPUT_LAST){ 2580 return; 2581 } 2582 if(key == OHCI_KEY_ST2 ){ 2583 i++; 2584 } 2585 } 2586 return; 2587 } 2588 2589 void 2590 fwohci_ibr(struct firewire_comm *fc) 2591 { 2592 struct fwohci_softc *sc; 2593 uint32_t fun; 2594 2595 device_printf(fc->dev, "Initiate bus reset\n"); 2596 sc = (struct fwohci_softc *)fc; 2597 2598 /* 2599 * Make sure our cached values from the config rom are 2600 * initialised. 2601 */ 2602 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2603 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2604 2605 /* 2606 * Set root hold-off bit so that non cyclemaster capable node 2607 * shouldn't became the root node. 2608 */ 2609 #if 1 2610 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2611 fun |= FW_PHY_IBR | FW_PHY_RHB; 2612 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2613 #else /* Short bus reset */ 2614 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2615 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2616 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2617 #endif 2618 } 2619 2620 void 2621 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2622 { 2623 struct fwohcidb_tr *db_tr, *fdb_tr; 2624 struct fwohci_dbch *dbch; 2625 struct fwohcidb *db; 2626 struct fw_pkt *fp; 2627 struct fwohci_txpkthdr *ohcifp; 2628 unsigned short chtag; 2629 int idb; 2630 2631 dbch = &sc->it[dmach]; 2632 chtag = sc->it[dmach].xferq.flag & 0xff; 2633 2634 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2635 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2636 /* 2637 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2638 */ 2639 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2640 db = db_tr->db; 2641 fp = (struct fw_pkt *)db_tr->buf; 2642 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2643 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2644 ohcifp->mode.common.spd = 0 & 0x7; 2645 ohcifp->mode.stream.len = fp->mode.stream.len; 2646 ohcifp->mode.stream.chtag = chtag; 2647 ohcifp->mode.stream.tcode = 0xa; 2648 #if BYTE_ORDER == BIG_ENDIAN 2649 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2650 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2651 #endif 2652 2653 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2654 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2655 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2656 #if 0 /* if bulkxfer->npackets changes */ 2657 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2658 | OHCI_UPDATE 2659 | OHCI_BRANCH_ALWAYS; 2660 db[0].db.desc.depend = 2661 = db[dbch->ndesc - 1].db.desc.depend 2662 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2663 #else 2664 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2665 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2666 #endif 2667 bulkxfer->end = (caddr_t)db_tr; 2668 db_tr = STAILQ_NEXT(db_tr, link); 2669 } 2670 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2671 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2672 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2673 #if 0 /* if bulkxfer->npackets changes */ 2674 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2675 /* OHCI 1.1 and above */ 2676 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2677 #endif 2678 /* 2679 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2680 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2681 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2682 */ 2683 return; 2684 } 2685 2686 static int 2687 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2688 int poffset) 2689 { 2690 struct fwohcidb *db = db_tr->db; 2691 struct fw_xferq *it; 2692 int err = 0; 2693 2694 it = &dbch->xferq; 2695 if(it->buf == 0){ 2696 err = EINVAL; 2697 return err; 2698 } 2699 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2700 db_tr->dbcnt = 3; 2701 2702 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2703 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2704 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2705 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2706 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2707 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2708 2709 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2710 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2711 #if 1 2712 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2713 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2714 #endif 2715 return 0; 2716 } 2717 2718 int 2719 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2720 int poffset, struct fwdma_alloc *dummy_dma) 2721 { 2722 struct fwohcidb *db = db_tr->db; 2723 struct fw_xferq *ir; 2724 int i, ldesc; 2725 bus_addr_t dbuf[2]; 2726 int dsiz[2]; 2727 2728 ir = &dbch->xferq; 2729 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2730 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2731 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2732 if (db_tr->buf == NULL) 2733 return(ENOMEM); 2734 db_tr->dbcnt = 1; 2735 dsiz[0] = ir->psize; 2736 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2737 BUS_DMASYNC_PREREAD); 2738 } else { 2739 db_tr->dbcnt = 0; 2740 if (dummy_dma != NULL) { 2741 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2742 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2743 } 2744 dsiz[db_tr->dbcnt] = ir->psize; 2745 if (ir->buf != NULL) { 2746 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2747 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2748 } 2749 db_tr->dbcnt++; 2750 } 2751 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2752 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2753 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2754 if (ir->flag & FWXFERQ_STREAM) { 2755 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2756 } 2757 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2758 } 2759 ldesc = db_tr->dbcnt - 1; 2760 if (ir->flag & FWXFERQ_STREAM) { 2761 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2762 } 2763 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2764 return 0; 2765 } 2766 2767 2768 static int 2769 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2770 { 2771 struct fw_pkt *fp0; 2772 uint32_t ld0; 2773 int slen, hlen; 2774 #if BYTE_ORDER == BIG_ENDIAN 2775 int i; 2776 #endif 2777 2778 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2779 #if 0 2780 printf("ld0: x%08x\n", ld0); 2781 #endif 2782 fp0 = (struct fw_pkt *)&ld0; 2783 /* determine length to swap */ 2784 switch (fp0->mode.common.tcode) { 2785 case FWTCODE_WRES: 2786 CTR0(KTR_DEV, "WRES"); 2787 case FWTCODE_RREQQ: 2788 case FWTCODE_WREQQ: 2789 case FWTCODE_RRESQ: 2790 case FWOHCITCODE_PHY: 2791 slen = 12; 2792 break; 2793 case FWTCODE_RREQB: 2794 case FWTCODE_WREQB: 2795 case FWTCODE_LREQ: 2796 case FWTCODE_RRESB: 2797 case FWTCODE_LRES: 2798 slen = 16; 2799 break; 2800 default: 2801 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2802 return(0); 2803 } 2804 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2805 if (hlen > len) { 2806 if (firewire_debug) 2807 printf("splitted header\n"); 2808 return(-hlen); 2809 } 2810 #if BYTE_ORDER == BIG_ENDIAN 2811 for(i = 0; i < slen/4; i ++) 2812 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2813 #endif 2814 return(hlen); 2815 } 2816 2817 static int 2818 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2819 { 2820 const struct tcode_info *info; 2821 int r; 2822 2823 info = &tinfo[fp->mode.common.tcode]; 2824 r = info->hdr_len + sizeof(uint32_t); 2825 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2826 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2827 2828 if (r == sizeof(uint32_t)) { 2829 /* XXX */ 2830 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2831 fp->mode.common.tcode); 2832 return (-1); 2833 } 2834 2835 if (r > dbch->xferq.psize) { 2836 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2837 return (-1); 2838 /* panic ? */ 2839 } 2840 2841 return r; 2842 } 2843 2844 static void 2845 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2846 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2847 { 2848 struct fwohcidb *db = &db_tr->db[0]; 2849 2850 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2851 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2852 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2853 fwdma_sync_multiseg_all(dbch->am, 2854 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2855 dbch->bottom = db_tr; 2856 2857 if (wake) 2858 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2859 } 2860 2861 static void 2862 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2863 { 2864 struct fwohcidb_tr *db_tr; 2865 struct iovec vec[2]; 2866 struct fw_pkt pktbuf; 2867 int nvec; 2868 struct fw_pkt *fp; 2869 uint8_t *ld; 2870 uint32_t stat, off, status, event; 2871 u_int spd; 2872 int len, plen, hlen, pcnt, offset; 2873 int s; 2874 caddr_t buf; 2875 int resCount; 2876 2877 CTR0(KTR_DEV, "fwohci_arv"); 2878 2879 if(&sc->arrq == dbch){ 2880 off = OHCI_ARQOFF; 2881 }else if(&sc->arrs == dbch){ 2882 off = OHCI_ARSOFF; 2883 }else{ 2884 return; 2885 } 2886 2887 s = splfw(); 2888 db_tr = dbch->top; 2889 pcnt = 0; 2890 /* XXX we cannot handle a packet which lies in more than two buf */ 2891 fwdma_sync_multiseg_all(dbch->am, 2892 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2893 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2894 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2895 while (status & OHCI_CNTL_DMA_ACTIVE) { 2896 #if 0 2897 2898 if (off == OHCI_ARQOFF) 2899 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2900 db_tr->bus_addr, status, resCount); 2901 #endif 2902 len = dbch->xferq.psize - resCount; 2903 ld = (uint8_t *)db_tr->buf; 2904 if (dbch->pdb_tr == NULL) { 2905 len -= dbch->buf_offset; 2906 ld += dbch->buf_offset; 2907 } 2908 if (len > 0) 2909 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2910 BUS_DMASYNC_POSTREAD); 2911 while (len > 0 ) { 2912 if (count >= 0 && count-- == 0) 2913 goto out; 2914 if(dbch->pdb_tr != NULL){ 2915 /* we have a fragment in previous buffer */ 2916 int rlen; 2917 2918 offset = dbch->buf_offset; 2919 if (offset < 0) 2920 offset = - offset; 2921 buf = dbch->pdb_tr->buf + offset; 2922 rlen = dbch->xferq.psize - offset; 2923 if (firewire_debug) 2924 printf("rlen=%d, offset=%d\n", 2925 rlen, dbch->buf_offset); 2926 if (dbch->buf_offset < 0) { 2927 /* splitted in header, pull up */ 2928 char *p; 2929 2930 p = (char *)&pktbuf; 2931 bcopy(buf, p, rlen); 2932 p += rlen; 2933 /* this must be too long but harmless */ 2934 rlen = sizeof(pktbuf) - rlen; 2935 if (rlen < 0) 2936 printf("why rlen < 0\n"); 2937 bcopy(db_tr->buf, p, rlen); 2938 ld += rlen; 2939 len -= rlen; 2940 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2941 if (hlen <= 0) { 2942 printf("hlen < 0 shouldn't happen"); 2943 goto err; 2944 } 2945 offset = sizeof(pktbuf); 2946 vec[0].iov_base = (char *)&pktbuf; 2947 vec[0].iov_len = offset; 2948 } else { 2949 /* splitted in payload */ 2950 offset = rlen; 2951 vec[0].iov_base = buf; 2952 vec[0].iov_len = rlen; 2953 } 2954 fp=(struct fw_pkt *)vec[0].iov_base; 2955 nvec = 1; 2956 } else { 2957 /* no fragment in previous buffer */ 2958 fp=(struct fw_pkt *)ld; 2959 hlen = fwohci_arcv_swap(fp, len); 2960 if (hlen == 0) 2961 goto err; 2962 if (hlen < 0) { 2963 dbch->pdb_tr = db_tr; 2964 dbch->buf_offset = - dbch->buf_offset; 2965 /* sanity check */ 2966 if (resCount != 0) { 2967 printf("resCount=%d hlen=%d\n", 2968 resCount, hlen); 2969 goto err; 2970 } 2971 goto out; 2972 } 2973 offset = 0; 2974 nvec = 0; 2975 } 2976 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2977 if (plen < 0) { 2978 /* minimum header size + trailer 2979 = sizeof(fw_pkt) so this shouldn't happens */ 2980 printf("plen(%d) is negative! offset=%d\n", 2981 plen, offset); 2982 goto err; 2983 } 2984 if (plen > 0) { 2985 len -= plen; 2986 if (len < 0) { 2987 dbch->pdb_tr = db_tr; 2988 if (firewire_debug) 2989 printf("splitted payload\n"); 2990 /* sanity check */ 2991 if (resCount != 0) { 2992 printf("resCount=%d plen=%d" 2993 " len=%d\n", 2994 resCount, plen, len); 2995 goto err; 2996 } 2997 goto out; 2998 } 2999 vec[nvec].iov_base = ld; 3000 vec[nvec].iov_len = plen; 3001 nvec ++; 3002 ld += plen; 3003 } 3004 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 3005 if (nvec == 0) 3006 printf("nvec == 0\n"); 3007 3008 /* DMA result-code will be written at the tail of packet */ 3009 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 3010 #if 0 3011 printf("plen: %d, stat %x\n", 3012 plen ,stat); 3013 #endif 3014 spd = (stat >> 21) & 0x3; 3015 event = (stat >> 16) & 0x1f; 3016 switch (event) { 3017 case FWOHCIEV_ACKPEND: 3018 #if 0 3019 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 3020 #endif 3021 /* fall through */ 3022 case FWOHCIEV_ACKCOMPL: 3023 { 3024 struct fw_rcv_buf rb; 3025 3026 if ((vec[nvec-1].iov_len -= 3027 sizeof(struct fwohci_trailer)) == 0) 3028 nvec--; 3029 rb.fc = &sc->fc; 3030 rb.vec = vec; 3031 rb.nvec = nvec; 3032 rb.spd = spd; 3033 fw_rcv(&rb); 3034 break; 3035 } 3036 case FWOHCIEV_BUSRST: 3037 if (sc->fc.status != FWBUSRESET) 3038 printf("got BUSRST packet!?\n"); 3039 break; 3040 default: 3041 device_printf(sc->fc.dev, 3042 "Async DMA Receive error err=%02x %s" 3043 " plen=%d offset=%d len=%d status=0x%08x" 3044 " tcode=0x%x, stat=0x%08x\n", 3045 event, fwohcicode[event], plen, 3046 dbch->buf_offset, len, 3047 OREAD(sc, OHCI_DMACTL(off)), 3048 fp->mode.common.tcode, stat); 3049 #if 1 /* XXX */ 3050 goto err; 3051 #endif 3052 break; 3053 } 3054 pcnt ++; 3055 if (dbch->pdb_tr != NULL) { 3056 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3057 off, 1); 3058 dbch->pdb_tr = NULL; 3059 } 3060 3061 } 3062 out: 3063 if (resCount == 0) { 3064 /* done on this buffer */ 3065 if (dbch->pdb_tr == NULL) { 3066 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3067 dbch->buf_offset = 0; 3068 } else 3069 if (dbch->pdb_tr != db_tr) 3070 printf("pdb_tr != db_tr\n"); 3071 db_tr = STAILQ_NEXT(db_tr, link); 3072 fwdma_sync_multiseg_all(dbch->am, 3073 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3074 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3075 >> OHCI_STATUS_SHIFT; 3076 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3077 & OHCI_COUNT_MASK; 3078 /* XXX check buffer overrun */ 3079 dbch->top = db_tr; 3080 } else { 3081 dbch->buf_offset = dbch->xferq.psize - resCount; 3082 fw_bus_dmamap_sync( 3083 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3084 break; 3085 } 3086 /* XXX make sure DMA is not dead */ 3087 } 3088 #if 0 3089 if (pcnt < 1) 3090 printf("fwohci_arcv: no packets\n"); 3091 #endif 3092 fwdma_sync_multiseg_all(dbch->am, 3093 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3094 splx(s); 3095 return; 3096 3097 err: 3098 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3099 OREAD(sc, OHCI_DMACTL(off))); 3100 dbch->pdb_tr = NULL; 3101 /* skip until resCount != 0 */ 3102 printf(" skip buffer"); 3103 while (resCount == 0) { 3104 printf(" #"); 3105 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3106 db_tr = STAILQ_NEXT(db_tr, link); 3107 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3108 & OHCI_COUNT_MASK; 3109 } 3110 printf(" done\n"); 3111 dbch->top = db_tr; 3112 dbch->buf_offset = dbch->xferq.psize - resCount; 3113 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3114 fwdma_sync_multiseg_all( 3115 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3116 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3117 splx(s); 3118 } 3119 #if defined(__NetBSD__) 3120 3121 int 3122 fwohci_print(void *aux, const char *pnp) 3123 { 3124 char *name = aux; 3125 3126 if (pnp) 3127 aprint_normal("%s at %s", name, pnp); 3128 3129 return UNCONF; 3130 } 3131 #endif 3132
Indexes created Fri Sep 26 20:09:58 GMT 2025