fwohci.c revision 1.95
1 /* $NetBSD: fwohci.c,v 1.95 2006/04/30 13:54:18 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/ktr.h> 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.95 2006/04/30 13:54:18 kiyohara Exp $"); 62 63 #if defined(__DragonFly__) || __FreeBSD_version < 500000 64 #include <machine/clock.h> /* for DELAY() */ 65 #endif 66 67 #ifdef __DragonFly__ 68 #include "fw_port.h" 69 #include "firewire.h" 70 #include "firewirereg.h" 71 #include "fwdma.h" 72 #include "fwohcireg.h" 73 #include "fwohcivar.h" 74 #include "firewire_phy.h" 75 #else 76 #include <dev/firewire/fw_port.h> 77 #include <dev/firewire/firewire.h> 78 #include <dev/firewire/firewirereg.h> 79 #include <dev/firewire/fwdma.h> 80 #include <dev/firewire/fwohcireg.h> 81 #include <dev/firewire/fwohcivar.h> 82 #include <dev/firewire/firewire_phy.h> 83 #endif 84 #elif defined(__NetBSD__) 85 #include <sys/param.h> 86 #include <sys/device.h> 87 #include <sys/errno.h> 88 #include <sys/conf.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/mbuf.h> 92 #include <sys/proc.h> 93 #include <sys/reboot.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <machine/bus.h> 98 99 #include <dev/ieee1394/fw_port.h> 100 #include <dev/ieee1394/firewire.h> 101 #include <dev/ieee1394/firewirereg.h> 102 #include <dev/ieee1394/fwdma.h> 103 #include <dev/ieee1394/fwohcireg.h> 104 #include <dev/ieee1394/fwohcivar.h> 105 #include <dev/ieee1394/firewire_phy.h> 106 #endif 107 108 #undef OHCI_DEBUG 109 110 static int nocyclemaster = 0; 111 #if defined(__FreeBSD__) 112 SYSCTL_DECL(_hw_firewire); 113 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 114 "Do not send cycle start packets"); 115 #elif defined(__NetBSD__) 116 /* 117 * Setup sysctl(3) MIB, hw.fwohci.* 118 * 119 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 120 */ 121 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 122 { 123 int rc; 124 const struct sysctlnode *node; 125 126 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 127 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 128 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 129 goto err; 130 } 131 132 if ((rc = sysctl_createv(clog, 0, NULL, &node, 133 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 134 SYSCTL_DESCR("fwohci controls"), 135 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 136 goto err; 137 } 138 139 /* fwohci no cyclemaster flag */ 140 if ((rc = sysctl_createv(clog, 0, NULL, &node, 141 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 142 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 143 NULL, 0, &nocyclemaster, 144 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 145 goto err; 146 } 147 return; 148 149 err: 150 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 151 } 152 #endif 153 154 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 155 "STOR","LOAD","NOP ","STOP", 156 "", "", "", "", "", "", "", ""}; 157 158 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 159 "UNDEF","REG","SYS","DEV"}; 160 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 161 static const char * const fwohcicode[32] = { 162 "No stat","Undef","long","miss Ack err", 163 "underrun","overrun","desc err", "data read err", 164 "data write err","bus reset","timeout","tcode err", 165 "Undef","Undef","unknown event","flushed", 166 "Undef","ack complete","ack pend","Undef", 167 "ack busy_X","ack busy_A","ack busy_B","Undef", 168 "Undef","Undef","Undef","ack tardy", 169 "Undef","ack data_err","ack type_err",""}; 170 171 #define MAX_SPEED 3 172 extern const char *fw_linkspeed[]; 173 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 174 175 static const struct tcode_info tinfo[] = { 176 /* hdr_len block flag*/ 177 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 178 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 179 /* 2 WRES */ {12, FWTI_RES}, 180 /* 3 XXX */ { 0, 0}, 181 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 182 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 183 /* 6 RRESQ */ {16, FWTI_RES}, 184 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 185 /* 8 CYCS */ { 0, 0}, 186 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 187 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 188 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 189 /* c XXX */ { 0, 0}, 190 /* d XXX */ { 0, 0}, 191 /* e PHY */ {12, FWTI_REQ}, 192 /* f XXX */ { 0, 0} 193 }; 194 195 #define OHCI_WRITE_SIGMASK 0xffff0000 196 #define OHCI_READ_SIGMASK 0xffff0000 197 198 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 199 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 200 201 static void fwohci_ibr (struct firewire_comm *); 202 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 203 static void fwohci_db_free (struct fwohci_dbch *); 204 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 205 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 206 static void fwohci_start_atq (struct firewire_comm *); 207 static void fwohci_start_ats (struct firewire_comm *); 208 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 209 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 210 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 211 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 212 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 213 static int fwohci_irx_enable (struct firewire_comm *, int); 214 static int fwohci_irx_disable (struct firewire_comm *, int); 215 #if BYTE_ORDER == BIG_ENDIAN 216 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 217 #endif 218 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 219 static int fwohci_itx_disable (struct firewire_comm *, int); 220 static void fwohci_timeout (void *); 221 static void fwohci_set_intr (struct firewire_comm *, int); 222 223 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 224 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 225 static void dump_db (struct fwohci_softc *, uint32_t); 226 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 227 static void dump_dma (struct fwohci_softc *, uint32_t); 228 static uint32_t fwohci_cyctimer (struct firewire_comm *); 229 static void fwohci_rbuf_update (struct fwohci_softc *, int); 230 static void fwohci_tbuf_update (struct fwohci_softc *, int); 231 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 232 #if FWOHCI_TASKQUEUE 233 static void fwohci_complete(void *, int); 234 #endif 235 #if defined(__NetBSD__) 236 static void fwohci_power(int, void *); 237 int fwohci_print(void *, const char *); 238 #endif 239 240 /* 241 * memory allocated for DMA programs 242 */ 243 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 244 245 #define NDB FWMAXQUEUE 246 247 #define OHCI_VERSION 0x00 248 #define OHCI_ATRETRY 0x08 249 #define OHCI_CROMHDR 0x18 250 #define OHCI_BUS_OPT 0x20 251 #define OHCI_BUSIRMC (1 << 31) 252 #define OHCI_BUSCMC (1 << 30) 253 #define OHCI_BUSISC (1 << 29) 254 #define OHCI_BUSBMC (1 << 28) 255 #define OHCI_BUSPMC (1 << 27) 256 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 257 OHCI_BUSBMC | OHCI_BUSPMC 258 259 #define OHCI_EUID_HI 0x24 260 #define OHCI_EUID_LO 0x28 261 262 #define OHCI_CROMPTR 0x34 263 #define OHCI_HCCCTL 0x50 264 #define OHCI_HCCCTLCLR 0x54 265 #define OHCI_AREQHI 0x100 266 #define OHCI_AREQHICLR 0x104 267 #define OHCI_AREQLO 0x108 268 #define OHCI_AREQLOCLR 0x10c 269 #define OHCI_PREQHI 0x110 270 #define OHCI_PREQHICLR 0x114 271 #define OHCI_PREQLO 0x118 272 #define OHCI_PREQLOCLR 0x11c 273 #define OHCI_PREQUPPER 0x120 274 275 #define OHCI_SID_BUF 0x64 276 #define OHCI_SID_CNT 0x68 277 #define OHCI_SID_ERR (1 << 31) 278 #define OHCI_SID_CNT_MASK 0xffc 279 280 #define OHCI_IT_STAT 0x90 281 #define OHCI_IT_STATCLR 0x94 282 #define OHCI_IT_MASK 0x98 283 #define OHCI_IT_MASKCLR 0x9c 284 285 #define OHCI_IR_STAT 0xa0 286 #define OHCI_IR_STATCLR 0xa4 287 #define OHCI_IR_MASK 0xa8 288 #define OHCI_IR_MASKCLR 0xac 289 290 #define OHCI_LNKCTL 0xe0 291 #define OHCI_LNKCTLCLR 0xe4 292 293 #define OHCI_PHYACCESS 0xec 294 #define OHCI_CYCLETIMER 0xf0 295 296 #define OHCI_DMACTL(off) (off) 297 #define OHCI_DMACTLCLR(off) (off + 4) 298 #define OHCI_DMACMD(off) (off + 0xc) 299 #define OHCI_DMAMATCH(off) (off + 0x10) 300 301 #define OHCI_ATQOFF 0x180 302 #define OHCI_ATQCTL OHCI_ATQOFF 303 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 304 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 305 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 306 307 #define OHCI_ATSOFF 0x1a0 308 #define OHCI_ATSCTL OHCI_ATSOFF 309 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 310 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 311 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 312 313 #define OHCI_ARQOFF 0x1c0 314 #define OHCI_ARQCTL OHCI_ARQOFF 315 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 316 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 317 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 318 319 #define OHCI_ARSOFF 0x1e0 320 #define OHCI_ARSCTL OHCI_ARSOFF 321 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 322 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 323 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 324 325 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 326 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 327 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 328 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 329 330 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 331 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 332 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 333 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 334 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 335 336 #if defined(__FreeBSD__) 337 d_ioctl_t fwohci_ioctl; 338 #elif defined(__NetBSD__) 339 extern struct cfdriver fwohci_cd; 340 dev_type_ioctl(fwohci_ioctl); 341 #endif 342 343 /* 344 * Communication with PHY device 345 */ 346 static uint32_t 347 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 348 { 349 uint32_t fun; 350 351 addr &= 0xf; 352 data &= 0xff; 353 354 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 355 OWRITE(sc, OHCI_PHYACCESS, fun); 356 DELAY(100); 357 358 return(fwphy_rddata( sc, addr)); 359 } 360 361 static uint32_t 362 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 363 { 364 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 365 int i; 366 uint32_t bm; 367 368 #define OHCI_CSR_DATA 0x0c 369 #define OHCI_CSR_COMP 0x10 370 #define OHCI_CSR_CONT 0x14 371 #define OHCI_BUS_MANAGER_ID 0 372 373 OWRITE(sc, OHCI_CSR_DATA, node); 374 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 375 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 376 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 377 DELAY(10); 378 bm = OREAD(sc, OHCI_CSR_DATA); 379 if((bm & 0x3f) == 0x3f) 380 bm = node; 381 if (firewire_debug) 382 device_printf(sc->fc.dev, 383 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 384 385 return(bm); 386 } 387 388 static uint32_t 389 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 390 { 391 uint32_t fun, stat; 392 u_int i, retry = 0; 393 394 addr &= 0xf; 395 #define MAX_RETRY 100 396 again: 397 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 398 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 399 OWRITE(sc, OHCI_PHYACCESS, fun); 400 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 401 fun = OREAD(sc, OHCI_PHYACCESS); 402 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 403 break; 404 DELAY(100); 405 } 406 if(i >= MAX_RETRY) { 407 if (firewire_debug) 408 device_printf(sc->fc.dev, "phy read failed(1).\n"); 409 if (++retry < MAX_RETRY) { 410 DELAY(100); 411 goto again; 412 } 413 } 414 /* Make sure that SCLK is started */ 415 stat = OREAD(sc, FWOHCI_INTSTAT); 416 if ((stat & OHCI_INT_REG_FAIL) != 0 || 417 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 418 if (firewire_debug) 419 device_printf(sc->fc.dev, "phy read failed(2).\n"); 420 if (++retry < MAX_RETRY) { 421 DELAY(100); 422 goto again; 423 } 424 } 425 if (firewire_debug || retry >= MAX_RETRY) 426 device_printf(sc->fc.dev, 427 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 428 #undef MAX_RETRY 429 return((fun >> PHYDEV_RDDATA )& 0xff); 430 } 431 /* Device specific ioctl. */ 432 FW_IOCTL(fwohci) 433 { 434 FW_IOCTL_START; 435 struct fwohci_softc *fc; 436 int err = 0; 437 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 438 uint32_t *dmach = (uint32_t *) data; 439 440 if(sc == NULL){ 441 return(EINVAL); 442 } 443 fc = (struct fwohci_softc *)sc->fc; 444 445 if (!data) 446 return(EINVAL); 447 448 switch (cmd) { 449 case FWOHCI_WRREG: 450 #define OHCI_MAX_REG 0x800 451 if(reg->addr <= OHCI_MAX_REG){ 452 OWRITE(fc, reg->addr, reg->data); 453 reg->data = OREAD(fc, reg->addr); 454 }else{ 455 err = EINVAL; 456 } 457 break; 458 case FWOHCI_RDREG: 459 if(reg->addr <= OHCI_MAX_REG){ 460 reg->data = OREAD(fc, reg->addr); 461 }else{ 462 err = EINVAL; 463 } 464 break; 465 /* Read DMA descriptors for debug */ 466 case DUMPDMA: 467 if(*dmach <= OHCI_MAX_DMA_CH ){ 468 dump_dma(fc, *dmach); 469 dump_db(fc, *dmach); 470 }else{ 471 err = EINVAL; 472 } 473 break; 474 /* Read/Write Phy registers */ 475 #define OHCI_MAX_PHY_REG 0xf 476 case FWOHCI_RDPHYREG: 477 if (reg->addr <= OHCI_MAX_PHY_REG) 478 reg->data = fwphy_rddata(fc, reg->addr); 479 else 480 err = EINVAL; 481 break; 482 case FWOHCI_WRPHYREG: 483 if (reg->addr <= OHCI_MAX_PHY_REG) 484 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 485 else 486 err = EINVAL; 487 break; 488 default: 489 err = EINVAL; 490 break; 491 } 492 return err; 493 } 494 495 static int 496 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 497 { 498 uint32_t reg, reg2; 499 int e1394a = 1; 500 /* 501 * probe PHY parameters 502 * 0. to prove PHY version, whether compliance of 1394a. 503 * 1. to probe maximum speed supported by the PHY and 504 * number of port supported by core-logic. 505 * It is not actually available port on your PC . 506 */ 507 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 508 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 509 510 if((reg >> 5) != 7 ){ 511 sc->fc.mode &= ~FWPHYASYST; 512 sc->fc.nport = reg & FW_PHY_NP; 513 sc->fc.speed = reg & FW_PHY_SPD >> 6; 514 if (sc->fc.speed > MAX_SPEED) { 515 device_printf(dev, "invalid speed %d (fixed to %d).\n", 516 sc->fc.speed, MAX_SPEED); 517 sc->fc.speed = MAX_SPEED; 518 } 519 device_printf(dev, 520 "Phy 1394 only %s, %d ports.\n", 521 fw_linkspeed[sc->fc.speed], sc->fc.nport); 522 }else{ 523 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 524 sc->fc.mode |= FWPHYASYST; 525 sc->fc.nport = reg & FW_PHY_NP; 526 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 527 if (sc->fc.speed > MAX_SPEED) { 528 device_printf(dev, "invalid speed %d (fixed to %d).\n", 529 sc->fc.speed, MAX_SPEED); 530 sc->fc.speed = MAX_SPEED; 531 } 532 device_printf(dev, 533 "Phy 1394a available %s, %d ports.\n", 534 fw_linkspeed[sc->fc.speed], sc->fc.nport); 535 536 /* check programPhyEnable */ 537 reg2 = fwphy_rddata(sc, 5); 538 #if 0 539 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 540 #else /* XXX force to enable 1394a */ 541 if (e1394a) { 542 #endif 543 if (firewire_debug) 544 device_printf(dev, 545 "Enable 1394a Enhancements\n"); 546 /* enable EAA EMC */ 547 reg2 |= 0x03; 548 /* set aPhyEnhanceEnable */ 549 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 550 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 551 } 552 #if 0 553 else { 554 /* for safe */ 555 reg2 &= ~0x83; 556 } 557 #endif 558 reg2 = fwphy_wrdata(sc, 5, reg2); 559 } 560 561 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 562 if((reg >> 5) == 7 ){ 563 reg = fwphy_rddata(sc, 4); 564 reg |= 1 << 6; 565 fwphy_wrdata(sc, 4, reg); 566 reg = fwphy_rddata(sc, 4); 567 } 568 return 0; 569 } 570 571 572 void 573 fwohci_reset(struct fwohci_softc *sc, device_t dev) 574 { 575 int i, max_rec, speed; 576 uint32_t reg, reg2; 577 struct fwohcidb_tr *db_tr; 578 579 /* Disable interrupts */ 580 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 581 582 /* Now stopping all DMA channels */ 583 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 584 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 585 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 586 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 587 588 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 589 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 590 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 591 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 592 } 593 594 /* FLUSH FIFO and reset Transmitter/Reciever */ 595 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 596 if (firewire_debug) 597 device_printf(dev, "resetting OHCI..."); 598 i = 0; 599 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 600 if (i++ > 100) break; 601 DELAY(1000); 602 } 603 if (firewire_debug) 604 printf("done (loop=%d)\n", i); 605 606 /* Probe phy */ 607 fwohci_probe_phy(sc, dev); 608 609 /* Probe link */ 610 reg = OREAD(sc, OHCI_BUS_OPT); 611 reg2 = reg | OHCI_BUSFNC; 612 max_rec = (reg & 0x0000f000) >> 12; 613 speed = (reg & 0x00000007); 614 device_printf(dev, "Link %s, max_rec %d bytes.\n", 615 fw_linkspeed[speed], MAXREC(max_rec)); 616 /* XXX fix max_rec */ 617 sc->fc.maxrec = sc->fc.speed + 8; 618 if (max_rec != sc->fc.maxrec) { 619 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 620 device_printf(dev, "max_rec %d -> %d\n", 621 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 622 } 623 if (firewire_debug) 624 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 625 OWRITE(sc, OHCI_BUS_OPT, reg2); 626 627 /* Initialize registers */ 628 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 629 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 630 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 631 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 632 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 633 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 634 635 /* Enable link */ 636 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 637 638 /* Force to start async RX DMA */ 639 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 640 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 641 fwohci_rx_enable(sc, &sc->arrq); 642 fwohci_rx_enable(sc, &sc->arrs); 643 644 /* Initialize async TX */ 645 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 646 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 647 648 /* AT Retries */ 649 OWRITE(sc, FWOHCI_RETRY, 650 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 651 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 652 653 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 654 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 655 sc->atrq.bottom = sc->atrq.top; 656 sc->atrs.bottom = sc->atrs.top; 657 658 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 659 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 660 db_tr->xfer = NULL; 661 } 662 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 663 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 664 db_tr->xfer = NULL; 665 } 666 667 668 /* Enable interrupts */ 669 OWRITE(sc, FWOHCI_INTMASK, 670 OHCI_INT_ERR | OHCI_INT_PHY_SID 671 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 672 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 673 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 674 fwohci_set_intr(&sc->fc, 1); 675 676 } 677 678 int 679 fwohci_init(struct fwohci_softc *sc, device_t dev) 680 { 681 int i, mver; 682 uint32_t reg; 683 uint8_t ui[8]; 684 685 #if FWOHCI_TASKQUEUE 686 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 687 #endif 688 689 /* OHCI version */ 690 reg = OREAD(sc, OHCI_VERSION); 691 mver = (reg >> 16) & 0xff; 692 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 693 mver, reg & 0xff, (reg>>24) & 1); 694 if (mver < 1 || mver > 9) { 695 device_printf(dev, "invalid OHCI version\n"); 696 return (ENXIO); 697 } 698 699 /* Available Isochronous DMA channel probe */ 700 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 701 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 702 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 703 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 704 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 705 for (i = 0; i < 0x20; i++) 706 if ((reg & (1 << i)) == 0) 707 break; 708 sc->fc.nisodma = i; 709 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 710 if (i == 0) 711 return (ENXIO); 712 713 sc->fc.arq = &sc->arrq.xferq; 714 sc->fc.ars = &sc->arrs.xferq; 715 sc->fc.atq = &sc->atrq.xferq; 716 sc->fc.ats = &sc->atrs.xferq; 717 718 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 719 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 720 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 721 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 722 723 sc->arrq.xferq.start = NULL; 724 sc->arrs.xferq.start = NULL; 725 sc->atrq.xferq.start = fwohci_start_atq; 726 sc->atrs.xferq.start = fwohci_start_ats; 727 728 sc->arrq.xferq.buf = NULL; 729 sc->arrs.xferq.buf = NULL; 730 sc->atrq.xferq.buf = NULL; 731 sc->atrs.xferq.buf = NULL; 732 733 sc->arrq.xferq.dmach = -1; 734 sc->arrs.xferq.dmach = -1; 735 sc->atrq.xferq.dmach = -1; 736 sc->atrs.xferq.dmach = -1; 737 738 sc->arrq.ndesc = 1; 739 sc->arrs.ndesc = 1; 740 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 741 sc->atrs.ndesc = 2; 742 743 sc->arrq.ndb = NDB; 744 sc->arrs.ndb = NDB / 2; 745 sc->atrq.ndb = NDB; 746 sc->atrs.ndb = NDB / 2; 747 748 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 749 sc->fc.it[i] = &sc->it[i].xferq; 750 sc->fc.ir[i] = &sc->ir[i].xferq; 751 sc->it[i].xferq.dmach = i; 752 sc->ir[i].xferq.dmach = i; 753 sc->it[i].ndb = 0; 754 sc->ir[i].ndb = 0; 755 } 756 757 sc->fc.tcode = tinfo; 758 sc->fc.dev = dev; 759 760 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 761 &sc->crom_dma, BUS_DMA_WAITOK); 762 if(sc->fc.config_rom == NULL){ 763 device_printf(dev, "config_rom alloc failed."); 764 return ENOMEM; 765 } 766 767 #if 0 768 bzero(&sc->fc.config_rom[0], CROMSIZE); 769 sc->fc.config_rom[1] = 0x31333934; 770 sc->fc.config_rom[2] = 0xf000a002; 771 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 772 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 773 sc->fc.config_rom[5] = 0; 774 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 775 776 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 777 #endif 778 779 780 /* SID recieve buffer must align 2^11 */ 781 #define OHCI_SIDSIZE (1 << 11) 782 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 783 &sc->sid_dma, BUS_DMA_WAITOK); 784 if (sc->sid_buf == NULL) { 785 device_printf(dev, "sid_buf alloc failed."); 786 return ENOMEM; 787 } 788 789 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 790 &sc->dummy_dma, BUS_DMA_WAITOK); 791 792 if (sc->dummy_dma.v_addr == NULL) { 793 device_printf(dev, "dummy_dma alloc failed."); 794 return ENOMEM; 795 } 796 797 fwohci_db_init(sc, &sc->arrq); 798 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 799 return ENOMEM; 800 801 fwohci_db_init(sc, &sc->arrs); 802 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 803 return ENOMEM; 804 805 fwohci_db_init(sc, &sc->atrq); 806 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 807 return ENOMEM; 808 809 fwohci_db_init(sc, &sc->atrs); 810 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 811 return ENOMEM; 812 813 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 814 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 815 for( i = 0 ; i < 8 ; i ++) 816 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 817 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 818 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 819 820 sc->fc.ioctl = fwohci_ioctl; 821 sc->fc.cyctimer = fwohci_cyctimer; 822 sc->fc.set_bmr = fwohci_set_bus_manager; 823 sc->fc.ibr = fwohci_ibr; 824 sc->fc.irx_enable = fwohci_irx_enable; 825 sc->fc.irx_disable = fwohci_irx_disable; 826 827 sc->fc.itx_enable = fwohci_itxbuf_enable; 828 sc->fc.itx_disable = fwohci_itx_disable; 829 #if BYTE_ORDER == BIG_ENDIAN 830 sc->fc.irx_post = fwohci_irx_post; 831 #else 832 sc->fc.irx_post = NULL; 833 #endif 834 sc->fc.itx_post = NULL; 835 sc->fc.timeout = fwohci_timeout; 836 sc->fc.poll = fwohci_poll; 837 sc->fc.set_intr = fwohci_set_intr; 838 839 sc->intmask = sc->irstat = sc->itstat = 0; 840 841 fw_init(&sc->fc); 842 fwohci_reset(sc, dev); 843 FWOHCI_INIT_END; 844 845 return 0; 846 } 847 848 void 849 fwohci_timeout(void *arg) 850 { 851 struct fwohci_softc *sc; 852 853 sc = (struct fwohci_softc *)arg; 854 } 855 856 uint32_t 857 fwohci_cyctimer(struct firewire_comm *fc) 858 { 859 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 860 return(OREAD(sc, OHCI_CYCLETIMER)); 861 } 862 863 FWOHCI_DETACH() 864 { 865 int i; 866 867 FWOHCI_DETACH_START; 868 if (sc->sid_buf != NULL) 869 fwdma_free(&sc->fc, &sc->sid_dma); 870 if (sc->fc.config_rom != NULL) 871 fwdma_free(&sc->fc, &sc->crom_dma); 872 873 fwohci_db_free(&sc->arrq); 874 fwohci_db_free(&sc->arrs); 875 876 fwohci_db_free(&sc->atrq); 877 fwohci_db_free(&sc->atrs); 878 879 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 880 fwohci_db_free(&sc->it[i]); 881 fwohci_db_free(&sc->ir[i]); 882 } 883 FWOHCI_DETACH_END; 884 885 return 0; 886 } 887 888 #define LAST_DB(dbtr, db) do { \ 889 struct fwohcidb_tr *_dbtr = (dbtr); \ 890 int _cnt = _dbtr->dbcnt; \ 891 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 892 } while (0) 893 894 static void 895 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 896 { 897 struct fwohcidb_tr *db_tr; 898 struct fwohcidb *db; 899 bus_dma_segment_t *s; 900 int i; 901 902 db_tr = (struct fwohcidb_tr *)arg; 903 db = &db_tr->db[db_tr->dbcnt]; 904 if (error) { 905 if (firewire_debug || error != EFBIG) 906 printf("fwohci_execute_db: error=%d\n", error); 907 return; 908 } 909 for (i = 0; i < nseg; i++) { 910 s = &segs[i]; 911 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 912 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 913 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 914 db++; 915 db_tr->dbcnt++; 916 } 917 } 918 919 static void 920 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 921 bus_size_t size, int error) 922 { 923 fwohci_execute_db(arg, segs, nseg, error); 924 } 925 926 static void 927 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 928 { 929 int i, s; 930 int tcode, hdr_len, pl_off; 931 int fsegment = -1; 932 uint32_t off; 933 struct fw_xfer *xfer; 934 struct fw_pkt *fp; 935 struct fwohci_txpkthdr *ohcifp; 936 struct fwohcidb_tr *db_tr; 937 struct fwohcidb *db; 938 uint32_t *ld; 939 const struct tcode_info *info; 940 static int maxdesc=0; 941 942 if(&sc->atrq == dbch){ 943 off = OHCI_ATQOFF; 944 }else if(&sc->atrs == dbch){ 945 off = OHCI_ATSOFF; 946 }else{ 947 return; 948 } 949 950 if (dbch->flags & FWOHCI_DBCH_FULL) 951 return; 952 953 s = splfw(); 954 db_tr = dbch->top; 955 txloop: 956 xfer = STAILQ_FIRST(&dbch->xferq.q); 957 if(xfer == NULL){ 958 goto kick; 959 } 960 if(dbch->xferq.queued == 0 ){ 961 device_printf(sc->fc.dev, "TX queue empty\n"); 962 } 963 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 964 db_tr->xfer = xfer; 965 xfer->state = FWXF_START; 966 967 fp = &xfer->send.hdr; 968 tcode = fp->mode.common.tcode; 969 970 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 971 info = &tinfo[tcode]; 972 hdr_len = pl_off = info->hdr_len; 973 974 ld = &ohcifp->mode.ld[0]; 975 ld[0] = ld[1] = ld[2] = ld[3] = 0; 976 for( i = 0 ; i < pl_off ; i+= 4) 977 ld[i/4] = fp->mode.ld[i/4]; 978 979 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 980 if (tcode == FWTCODE_STREAM ){ 981 hdr_len = 8; 982 ohcifp->mode.stream.len = fp->mode.stream.len; 983 } else if (tcode == FWTCODE_PHY) { 984 hdr_len = 12; 985 ld[1] = fp->mode.ld[1]; 986 ld[2] = fp->mode.ld[2]; 987 ohcifp->mode.common.spd = 0; 988 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 989 } else { 990 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 991 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 992 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 993 } 994 db = &db_tr->db[0]; 995 FWOHCI_DMA_WRITE(db->db.desc.cmd, 996 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 997 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 998 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 999 /* Specify bound timer of asy. responce */ 1000 if(&sc->atrs == dbch){ 1001 FWOHCI_DMA_WRITE(db->db.desc.res, 1002 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1003 } 1004 #if BYTE_ORDER == BIG_ENDIAN 1005 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1006 hdr_len = 12; 1007 for (i = 0; i < hdr_len/4; i ++) 1008 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1009 #endif 1010 1011 again: 1012 db_tr->dbcnt = 2; 1013 db = &db_tr->db[db_tr->dbcnt]; 1014 if (xfer->send.pay_len > 0) { 1015 int err; 1016 /* handle payload */ 1017 if (xfer->mbuf == NULL) { 1018 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1019 &xfer->send.payload[0], xfer->send.pay_len, 1020 fwohci_execute_db, db_tr, 1021 BUS_DMA_WAITOK); 1022 } else { 1023 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1024 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1025 db_tr->dma_map, xfer->mbuf, 1026 fwohci_execute_db2, db_tr, 1027 BUS_DMA_WAITOK); 1028 if (err == EFBIG) { 1029 struct mbuf *m0; 1030 1031 if (firewire_debug) 1032 device_printf(sc->fc.dev, "EFBIG.\n"); 1033 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1034 if (m0 != NULL) { 1035 m_copydata(xfer->mbuf, 0, 1036 xfer->mbuf->m_pkthdr.len, 1037 mtod(m0, caddr_t)); 1038 m0->m_len = m0->m_pkthdr.len = 1039 xfer->mbuf->m_pkthdr.len; 1040 m_freem(xfer->mbuf); 1041 xfer->mbuf = m0; 1042 goto again; 1043 } 1044 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1045 } 1046 } 1047 if (err) 1048 printf("dmamap_load: err=%d\n", err); 1049 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1050 BUS_DMASYNC_PREWRITE); 1051 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1052 for (i = 2; i < db_tr->dbcnt; i++) 1053 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1054 OHCI_OUTPUT_MORE); 1055 #endif 1056 } 1057 if (maxdesc < db_tr->dbcnt) { 1058 maxdesc = db_tr->dbcnt; 1059 if (firewire_debug) 1060 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1061 } 1062 /* last db */ 1063 LAST_DB(db_tr, db); 1064 FWOHCI_DMA_SET(db->db.desc.cmd, 1065 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1066 FWOHCI_DMA_WRITE(db->db.desc.depend, 1067 STAILQ_NEXT(db_tr, link)->bus_addr); 1068 1069 if(fsegment == -1 ) 1070 fsegment = db_tr->dbcnt; 1071 if (dbch->pdb_tr != NULL) { 1072 LAST_DB(dbch->pdb_tr, db); 1073 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1074 } 1075 dbch->pdb_tr = db_tr; 1076 db_tr = STAILQ_NEXT(db_tr, link); 1077 if(db_tr != dbch->bottom){ 1078 goto txloop; 1079 } else { 1080 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1081 dbch->flags |= FWOHCI_DBCH_FULL; 1082 } 1083 kick: 1084 /* kick asy q */ 1085 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1086 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1087 } else { 1088 if (firewire_debug) 1089 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1090 OREAD(sc, OHCI_DMACTL(off))); 1091 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1092 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1093 dbch->xferq.flag |= FWXFERQ_RUNNING; 1094 } 1095 CTR0(KTR_DEV, "start kick done"); 1096 CTR0(KTR_DEV, "start kick done2"); 1097 1098 dbch->top = db_tr; 1099 splx(s); 1100 return; 1101 } 1102 1103 static void 1104 fwohci_start_atq(struct firewire_comm *fc) 1105 { 1106 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1107 fwohci_start( sc, &(sc->atrq)); 1108 return; 1109 } 1110 1111 static void 1112 fwohci_start_ats(struct firewire_comm *fc) 1113 { 1114 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1115 fwohci_start( sc, &(sc->atrs)); 1116 return; 1117 } 1118 1119 void 1120 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1121 { 1122 int s, ch, err = 0; 1123 struct fwohcidb_tr *tr; 1124 struct fwohcidb *db; 1125 struct fw_xfer *xfer; 1126 uint32_t off; 1127 u_int stat, status; 1128 int packets; 1129 struct firewire_comm *fc = (struct firewire_comm *)sc; 1130 1131 if(&sc->atrq == dbch){ 1132 off = OHCI_ATQOFF; 1133 ch = ATRQ_CH; 1134 }else if(&sc->atrs == dbch){ 1135 off = OHCI_ATSOFF; 1136 ch = ATRS_CH; 1137 }else{ 1138 return; 1139 } 1140 s = splfw(); 1141 tr = dbch->bottom; 1142 packets = 0; 1143 while(dbch->xferq.queued > 0){ 1144 LAST_DB(tr, db); 1145 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1146 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1147 if (fc->status != FWBUSRESET) 1148 /* maybe out of order?? */ 1149 goto out; 1150 } 1151 if (tr->xfer->send.pay_len > 0) { 1152 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1153 BUS_DMASYNC_POSTWRITE); 1154 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1155 } 1156 #if 1 1157 if (firewire_debug > 1) 1158 dump_db(sc, ch); 1159 #endif 1160 if(status & OHCI_CNTL_DMA_DEAD) { 1161 /* Stop DMA */ 1162 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1163 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1164 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1165 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1166 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1167 } 1168 stat = status & FWOHCIEV_MASK; 1169 switch(stat){ 1170 case FWOHCIEV_ACKPEND: 1171 CTR0(KTR_DEV, "txd: ack pending"); 1172 /* fall through */ 1173 case FWOHCIEV_ACKCOMPL: 1174 err = 0; 1175 break; 1176 case FWOHCIEV_ACKBSA: 1177 case FWOHCIEV_ACKBSB: 1178 case FWOHCIEV_ACKBSX: 1179 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1180 err = EBUSY; 1181 break; 1182 case FWOHCIEV_FLUSHED: 1183 case FWOHCIEV_ACKTARD: 1184 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1185 err = EAGAIN; 1186 break; 1187 case FWOHCIEV_MISSACK: 1188 case FWOHCIEV_UNDRRUN: 1189 case FWOHCIEV_OVRRUN: 1190 case FWOHCIEV_DESCERR: 1191 case FWOHCIEV_DTRDERR: 1192 case FWOHCIEV_TIMEOUT: 1193 case FWOHCIEV_TCODERR: 1194 case FWOHCIEV_UNKNOWN: 1195 case FWOHCIEV_ACKDERR: 1196 case FWOHCIEV_ACKTERR: 1197 default: 1198 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1199 stat, fwohcicode[stat]); 1200 err = EINVAL; 1201 break; 1202 } 1203 if (tr->xfer != NULL) { 1204 xfer = tr->xfer; 1205 CTR0(KTR_DEV, "txd"); 1206 if (xfer->state == FWXF_RCVD) { 1207 #if 0 1208 if (firewire_debug) 1209 printf("already rcvd\n"); 1210 #endif 1211 fw_xfer_done(xfer); 1212 } else { 1213 xfer->state = FWXF_SENT; 1214 if (err == EBUSY && fc->status != FWBUSRESET) { 1215 xfer->state = FWXF_BUSY; 1216 xfer->resp = err; 1217 xfer->recv.pay_len = 0; 1218 fw_xfer_done(xfer); 1219 } else if (stat != FWOHCIEV_ACKPEND) { 1220 if (stat != FWOHCIEV_ACKCOMPL) 1221 xfer->state = FWXF_SENTERR; 1222 xfer->resp = err; 1223 xfer->recv.pay_len = 0; 1224 fw_xfer_done(xfer); 1225 } 1226 } 1227 /* 1228 * The watchdog timer takes care of split 1229 * transcation timeout for ACKPEND case. 1230 */ 1231 } else { 1232 printf("this shouldn't happen\n"); 1233 } 1234 dbch->xferq.queued --; 1235 tr->xfer = NULL; 1236 1237 packets ++; 1238 tr = STAILQ_NEXT(tr, link); 1239 dbch->bottom = tr; 1240 if (dbch->bottom == dbch->top) { 1241 /* we reaches the end of context program */ 1242 if (firewire_debug && dbch->xferq.queued > 0) 1243 printf("queued > 0\n"); 1244 break; 1245 } 1246 } 1247 out: 1248 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1249 printf("make free slot\n"); 1250 dbch->flags &= ~FWOHCI_DBCH_FULL; 1251 fwohci_start(sc, dbch); 1252 } 1253 splx(s); 1254 } 1255 1256 static void 1257 fwohci_db_free(struct fwohci_dbch *dbch) 1258 { 1259 struct fwohcidb_tr *db_tr; 1260 int idb; 1261 1262 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1263 return; 1264 1265 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1266 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1267 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1268 db_tr->buf != NULL) { 1269 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1270 db_tr->buf, dbch->xferq.psize); 1271 db_tr->buf = NULL; 1272 } else if (db_tr->dma_map != NULL) 1273 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1274 } 1275 dbch->ndb = 0; 1276 db_tr = STAILQ_FIRST(&dbch->db_trq); 1277 fwdma_free_multiseg(dbch->am); 1278 free(db_tr, M_FW); 1279 STAILQ_INIT(&dbch->db_trq); 1280 dbch->flags &= ~FWOHCI_DBCH_INIT; 1281 } 1282 1283 static void 1284 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1285 { 1286 int idb; 1287 struct fwohcidb_tr *db_tr; 1288 1289 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1290 goto out; 1291 1292 /* create dma_tag for buffers */ 1293 #define MAX_REQCOUNT 0xffff 1294 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1295 /*alignment*/ 1, /*boundary*/ 0, 1296 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1297 /*highaddr*/ BUS_SPACE_MAXADDR, 1298 /*filter*/NULL, /*filterarg*/NULL, 1299 /*maxsize*/ dbch->xferq.psize, 1300 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1301 /*maxsegsz*/ MAX_REQCOUNT, 1302 /*flags*/ 0, 1303 /*lockfunc*/busdma_lock_mutex, 1304 /*lockarg*/&Giant, 1305 &dbch->dmat)) 1306 return; 1307 1308 /* allocate DB entries and attach one to each DMA channels */ 1309 /* DB entry must start at 16 bytes bounary. */ 1310 STAILQ_INIT(&dbch->db_trq); 1311 db_tr = (struct fwohcidb_tr *) 1312 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1313 M_FW, M_WAITOK | M_ZERO); 1314 if(db_tr == NULL){ 1315 printf("fwohci_db_init: malloc(1) failed\n"); 1316 return; 1317 } 1318 1319 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1320 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1321 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); 1322 if (dbch->am == NULL) { 1323 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1324 free(db_tr, M_FW); 1325 return; 1326 } 1327 /* Attach DB to DMA ch. */ 1328 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1329 db_tr->dbcnt = 0; 1330 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1331 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1332 /* create dmamap for buffers */ 1333 /* XXX do we need 4bytes alignment tag? */ 1334 /* XXX don't alloc dma_map for AR */ 1335 if (bus_dmamap_create(sc->fc.dmat, dbch->xferq.psize, 1336 dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, MAX_REQCOUNT, 1337 0, BUS_DMA_NOWAIT, &db_tr->dma_map) != 0) { 1338 printf("bus_dmamap_create failed\n"); 1339 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1340 fwohci_db_free(dbch); 1341 return; 1342 } 1343 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1344 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1345 if (idb % dbch->xferq.bnpacket == 0) 1346 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1347 ].start = (caddr_t)db_tr; 1348 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1349 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1350 ].end = (caddr_t)db_tr; 1351 } 1352 db_tr++; 1353 } 1354 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1355 = STAILQ_FIRST(&dbch->db_trq); 1356 out: 1357 dbch->xferq.queued = 0; 1358 dbch->pdb_tr = NULL; 1359 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1360 dbch->bottom = dbch->top; 1361 dbch->flags = FWOHCI_DBCH_INIT; 1362 } 1363 1364 static int 1365 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1366 { 1367 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1368 int sleepch; 1369 1370 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1371 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1372 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1373 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1374 /* XXX we cannot free buffers until the DMA really stops */ 1375 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1376 fwohci_db_free(&sc->it[dmach]); 1377 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1378 return 0; 1379 } 1380 1381 static int 1382 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1383 { 1384 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1385 int sleepch; 1386 1387 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1388 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1389 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1390 /* XXX we cannot free buffers until the DMA really stops */ 1391 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1392 fwohci_db_free(&sc->ir[dmach]); 1393 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1394 return 0; 1395 } 1396 1397 #if BYTE_ORDER == BIG_ENDIAN 1398 static void 1399 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1400 { 1401 qld[0] = FWOHCI_DMA_READ(qld[0]); 1402 return; 1403 } 1404 #endif 1405 1406 static int 1407 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1408 { 1409 int err = 0; 1410 int idb, z, i, dmach = 0, ldesc; 1411 uint32_t off = 0; 1412 struct fwohcidb_tr *db_tr; 1413 struct fwohcidb *db; 1414 1415 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1416 err = EINVAL; 1417 return err; 1418 } 1419 z = dbch->ndesc; 1420 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1421 if( &sc->it[dmach] == dbch){ 1422 off = OHCI_ITOFF(dmach); 1423 break; 1424 } 1425 } 1426 if(off == 0){ 1427 err = EINVAL; 1428 return err; 1429 } 1430 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1431 return err; 1432 dbch->xferq.flag |= FWXFERQ_RUNNING; 1433 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1434 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1435 } 1436 db_tr = dbch->top; 1437 for (idb = 0; idb < dbch->ndb; idb ++) { 1438 fwohci_add_tx_buf(dbch, db_tr, idb); 1439 if(STAILQ_NEXT(db_tr, link) == NULL){ 1440 break; 1441 } 1442 db = db_tr->db; 1443 ldesc = db_tr->dbcnt - 1; 1444 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1445 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1446 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1447 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1448 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1449 FWOHCI_DMA_SET( 1450 db[ldesc].db.desc.cmd, 1451 OHCI_INTERRUPT_ALWAYS); 1452 /* OHCI 1.1 and above */ 1453 FWOHCI_DMA_SET( 1454 db[0].db.desc.cmd, 1455 OHCI_INTERRUPT_ALWAYS); 1456 } 1457 } 1458 db_tr = STAILQ_NEXT(db_tr, link); 1459 } 1460 FWOHCI_DMA_CLEAR( 1461 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1462 return err; 1463 } 1464 1465 static int 1466 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1467 { 1468 int err = 0; 1469 int idb, z, i, dmach = 0, ldesc; 1470 uint32_t off = 0; 1471 struct fwohcidb_tr *db_tr; 1472 struct fwohcidb *db; 1473 1474 z = dbch->ndesc; 1475 if(&sc->arrq == dbch){ 1476 off = OHCI_ARQOFF; 1477 }else if(&sc->arrs == dbch){ 1478 off = OHCI_ARSOFF; 1479 }else{ 1480 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1481 if( &sc->ir[dmach] == dbch){ 1482 off = OHCI_IROFF(dmach); 1483 break; 1484 } 1485 } 1486 } 1487 if(off == 0){ 1488 err = EINVAL; 1489 return err; 1490 } 1491 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1492 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1493 return err; 1494 }else{ 1495 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1496 err = EBUSY; 1497 return err; 1498 } 1499 } 1500 dbch->xferq.flag |= FWXFERQ_RUNNING; 1501 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1502 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1503 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1504 } 1505 db_tr = dbch->top; 1506 for (idb = 0; idb < dbch->ndb; idb ++) { 1507 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1508 if (STAILQ_NEXT(db_tr, link) == NULL) 1509 break; 1510 db = db_tr->db; 1511 ldesc = db_tr->dbcnt - 1; 1512 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1513 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1514 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1515 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1516 FWOHCI_DMA_SET( 1517 db[ldesc].db.desc.cmd, 1518 OHCI_INTERRUPT_ALWAYS); 1519 FWOHCI_DMA_CLEAR( 1520 db[ldesc].db.desc.depend, 1521 0xf); 1522 } 1523 } 1524 db_tr = STAILQ_NEXT(db_tr, link); 1525 } 1526 FWOHCI_DMA_CLEAR( 1527 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1528 dbch->buf_offset = 0; 1529 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1530 return err; 1531 }else{ 1532 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1533 } 1534 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1535 return err; 1536 } 1537 1538 static int 1539 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1540 { 1541 int sec, cycle, cycle_match; 1542 1543 cycle = cycle_now & 0x1fff; 1544 sec = cycle_now >> 13; 1545 #define CYCLE_MOD 0x10 1546 #if 1 1547 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1548 #else 1549 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1550 #endif 1551 cycle = cycle + CYCLE_DELAY; 1552 if (cycle >= 8000) { 1553 sec ++; 1554 cycle -= 8000; 1555 } 1556 cycle = roundup2(cycle, CYCLE_MOD); 1557 if (cycle >= 8000) { 1558 sec ++; 1559 if (cycle == 8000) 1560 cycle = 0; 1561 else 1562 cycle = CYCLE_MOD; 1563 } 1564 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1565 1566 return(cycle_match); 1567 } 1568 1569 static int 1570 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1571 { 1572 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1573 int err = 0; 1574 unsigned short tag, ich; 1575 struct fwohci_dbch *dbch; 1576 int cycle_match, cycle_now, s, ldesc; 1577 uint32_t stat; 1578 struct fw_bulkxfer *first, *chunk, *prev; 1579 struct fw_xferq *it; 1580 1581 dbch = &sc->it[dmach]; 1582 it = &dbch->xferq; 1583 1584 tag = (it->flag >> 6) & 3; 1585 ich = it->flag & 0x3f; 1586 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1587 dbch->ndb = it->bnpacket * it->bnchunk; 1588 dbch->ndesc = 3; 1589 fwohci_db_init(sc, dbch); 1590 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1591 return ENOMEM; 1592 err = fwohci_tx_enable(sc, dbch); 1593 } 1594 if(err) 1595 return err; 1596 1597 ldesc = dbch->ndesc - 1; 1598 s = splfw(); 1599 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1600 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1601 struct fwohcidb *db; 1602 1603 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1604 BUS_DMASYNC_PREWRITE); 1605 fwohci_txbufdb(sc, dmach, chunk); 1606 if (prev != NULL) { 1607 db = ((struct fwohcidb_tr *)(prev->end))->db; 1608 #if 0 /* XXX necessary? */ 1609 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1610 OHCI_BRANCH_ALWAYS); 1611 #endif 1612 #if 0 /* if bulkxfer->npacket changes */ 1613 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1614 ((struct fwohcidb_tr *) 1615 (chunk->start))->bus_addr | dbch->ndesc; 1616 #else 1617 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1618 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1619 #endif 1620 } 1621 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1622 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1623 prev = chunk; 1624 } 1625 splx(s); 1626 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1627 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1628 printf("stat 0x%x\n", stat); 1629 1630 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1631 return 0; 1632 1633 #if 0 1634 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1635 #endif 1636 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1637 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1638 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1639 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1640 1641 first = STAILQ_FIRST(&it->stdma); 1642 OWRITE(sc, OHCI_ITCMD(dmach), 1643 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1644 if (firewire_debug > 1) { 1645 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1646 #if 1 1647 dump_dma(sc, ITX_CH + dmach); 1648 #endif 1649 } 1650 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1651 #if 1 1652 /* Don't start until all chunks are buffered */ 1653 if (STAILQ_FIRST(&it->stfree) != NULL) 1654 goto out; 1655 #endif 1656 #if 1 1657 /* Clear cycle match counter bits */ 1658 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1659 1660 /* 2bit second + 13bit cycle */ 1661 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1662 cycle_match = fwohci_next_cycle(fc, cycle_now); 1663 1664 OWRITE(sc, OHCI_ITCTL(dmach), 1665 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1666 | OHCI_CNTL_DMA_RUN); 1667 #else 1668 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1669 #endif 1670 if (firewire_debug > 1) { 1671 printf("cycle_match: 0x%04x->0x%04x\n", 1672 cycle_now, cycle_match); 1673 dump_dma(sc, ITX_CH + dmach); 1674 dump_db(sc, ITX_CH + dmach); 1675 } 1676 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1677 device_printf(sc->fc.dev, 1678 "IT DMA underrun (0x%08x)\n", stat); 1679 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1680 } 1681 out: 1682 return err; 1683 } 1684 1685 static int 1686 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1687 { 1688 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1689 int err = 0, s, ldesc; 1690 unsigned short tag, ich; 1691 uint32_t stat; 1692 struct fwohci_dbch *dbch; 1693 struct fwohcidb_tr *db_tr; 1694 struct fw_bulkxfer *first, *prev, *chunk; 1695 struct fw_xferq *ir; 1696 1697 dbch = &sc->ir[dmach]; 1698 ir = &dbch->xferq; 1699 1700 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1701 tag = (ir->flag >> 6) & 3; 1702 ich = ir->flag & 0x3f; 1703 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1704 1705 ir->queued = 0; 1706 dbch->ndb = ir->bnpacket * ir->bnchunk; 1707 dbch->ndesc = 2; 1708 fwohci_db_init(sc, dbch); 1709 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1710 return ENOMEM; 1711 err = fwohci_rx_enable(sc, dbch); 1712 } 1713 if(err) 1714 return err; 1715 1716 first = STAILQ_FIRST(&ir->stfree); 1717 if (first == NULL) { 1718 device_printf(fc->dev, "IR DMA no free chunk\n"); 1719 return 0; 1720 } 1721 1722 ldesc = dbch->ndesc - 1; 1723 s = splfw(); 1724 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1725 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1726 struct fwohcidb *db; 1727 1728 #if 1 /* XXX for if_fwe */ 1729 if (chunk->mbuf != NULL) { 1730 db_tr = (struct fwohcidb_tr *)(chunk->start); 1731 db_tr->dbcnt = 1; 1732 err = fw_bus_dmamap_load_mbuf( 1733 dbch->dmat, db_tr->dma_map, 1734 chunk->mbuf, fwohci_execute_db2, db_tr, 1735 BUS_DMA_WAITOK); 1736 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1737 OHCI_UPDATE | OHCI_INPUT_LAST | 1738 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1739 } 1740 #endif 1741 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1742 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1743 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1744 if (prev != NULL) { 1745 db = ((struct fwohcidb_tr *)(prev->end))->db; 1746 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1747 } 1748 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1749 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1750 prev = chunk; 1751 } 1752 splx(s); 1753 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1754 if (stat & OHCI_CNTL_DMA_ACTIVE) 1755 return 0; 1756 if (stat & OHCI_CNTL_DMA_RUN) { 1757 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1758 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1759 } 1760 1761 if (firewire_debug) 1762 printf("start IR DMA 0x%x\n", stat); 1763 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1764 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1765 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1766 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1767 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1768 OWRITE(sc, OHCI_IRCMD(dmach), 1769 ((struct fwohcidb_tr *)(first->start))->bus_addr 1770 | dbch->ndesc); 1771 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1772 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1773 #if 0 1774 dump_db(sc, IRX_CH + dmach); 1775 #endif 1776 return err; 1777 } 1778 1779 FWOHCI_STOP() 1780 { 1781 FWOHCI_STOP_START; 1782 u_int i; 1783 1784 /* Now stopping all DMA channel */ 1785 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1786 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1787 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1788 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1789 1790 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1791 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1792 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1793 } 1794 1795 /* FLUSH FIFO and reset Transmitter/Reciever */ 1796 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1797 1798 /* Stop interrupt */ 1799 OWRITE(sc, FWOHCI_INTMASKCLR, 1800 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1801 | OHCI_INT_PHY_INT 1802 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1803 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1804 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1805 | OHCI_INT_PHY_BUS_R); 1806 1807 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1808 fw_drain_txq(&sc->fc); 1809 1810 /* XXX Link down? Bus reset? */ 1811 FWOHCI_STOP_RETURN(0); 1812 } 1813 1814 #if defined(__NetBSD__) 1815 static void 1816 fwohci_power(int why, void *arg) 1817 { 1818 struct fwohci_softc *sc = arg; 1819 int s; 1820 1821 s = splbio(); 1822 switch (why) { 1823 case PWR_SUSPEND: 1824 case PWR_STANDBY: 1825 fwohci_stop(arg); 1826 break; 1827 case PWR_RESUME: 1828 fwohci_resume(sc, sc->fc.dev); 1829 break; 1830 case PWR_SOFTSUSPEND: 1831 case PWR_SOFTSTANDBY: 1832 case PWR_SOFTRESUME: 1833 break; 1834 } 1835 splx(s); 1836 } 1837 #endif 1838 1839 int 1840 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1841 { 1842 int i; 1843 struct fw_xferq *ir; 1844 struct fw_bulkxfer *chunk; 1845 1846 fwohci_reset(sc, dev); 1847 /* XXX resume isochronous receive automatically. (how about TX?) */ 1848 for(i = 0; i < sc->fc.nisodma; i ++) { 1849 ir = &sc->ir[i].xferq; 1850 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1851 device_printf(sc->fc.dev, 1852 "resume iso receive ch: %d\n", i); 1853 ir->flag &= ~FWXFERQ_RUNNING; 1854 /* requeue stdma to stfree */ 1855 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1856 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1857 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1858 } 1859 sc->fc.irx_enable(&sc->fc, i); 1860 } 1861 } 1862 1863 #if defined(__FreeBSD__) 1864 bus_generic_resume(dev); 1865 #endif 1866 sc->fc.ibr(&sc->fc); 1867 return 0; 1868 } 1869 1870 #define ACK_ALL 1871 static void 1872 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1873 { 1874 uint32_t irstat, itstat; 1875 u_int i; 1876 struct firewire_comm *fc = (struct firewire_comm *)sc; 1877 1878 CTR0(KTR_DEV, "fwohci_intr_body"); 1879 #ifdef OHCI_DEBUG 1880 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1881 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1882 stat & OHCI_INT_EN ? "DMA_EN ":"", 1883 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1884 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1885 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1886 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1887 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1888 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1889 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1890 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1891 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1892 stat & OHCI_INT_PHY_SID ? "SID ":"", 1893 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1894 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1895 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1896 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1897 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1898 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1899 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1900 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1901 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1902 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1903 stat, OREAD(sc, FWOHCI_INTMASK) 1904 ); 1905 #endif 1906 /* Bus reset */ 1907 if(stat & OHCI_INT_PHY_BUS_R ){ 1908 if (fc->status == FWBUSRESET) 1909 goto busresetout; 1910 /* Disable bus reset interrupt until sid recv. */ 1911 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1912 1913 device_printf(fc->dev, "BUS reset\n"); 1914 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1915 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1916 1917 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1918 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1919 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1920 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1921 1922 #ifndef ACK_ALL 1923 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1924 #endif 1925 fw_busreset(fc); 1926 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1927 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1928 } 1929 busresetout: 1930 if((stat & OHCI_INT_DMA_IR )){ 1931 #ifndef ACK_ALL 1932 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1933 #endif 1934 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1935 irstat = sc->irstat; 1936 sc->irstat = 0; 1937 #else 1938 irstat = atomic_readandclear_int(&sc->irstat); 1939 #endif 1940 for(i = 0; i < fc->nisodma ; i++){ 1941 struct fwohci_dbch *dbch; 1942 1943 if((irstat & (1 << i)) != 0){ 1944 dbch = &sc->ir[i]; 1945 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1946 device_printf(sc->fc.dev, 1947 "dma(%d) not active\n", i); 1948 continue; 1949 } 1950 fwohci_rbuf_update(sc, i); 1951 } 1952 } 1953 } 1954 if((stat & OHCI_INT_DMA_IT )){ 1955 #ifndef ACK_ALL 1956 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1957 #endif 1958 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1959 itstat = sc->itstat; 1960 sc->itstat = 0; 1961 #else 1962 itstat = atomic_readandclear_int(&sc->itstat); 1963 #endif 1964 for(i = 0; i < fc->nisodma ; i++){ 1965 if((itstat & (1 << i)) != 0){ 1966 fwohci_tbuf_update(sc, i); 1967 } 1968 } 1969 } 1970 if((stat & OHCI_INT_DMA_PRRS )){ 1971 #ifndef ACK_ALL 1972 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1973 #endif 1974 #if 0 1975 dump_dma(sc, ARRS_CH); 1976 dump_db(sc, ARRS_CH); 1977 #endif 1978 fwohci_arcv(sc, &sc->arrs, count); 1979 } 1980 if((stat & OHCI_INT_DMA_PRRQ )){ 1981 #ifndef ACK_ALL 1982 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1983 #endif 1984 #if 0 1985 dump_dma(sc, ARRQ_CH); 1986 dump_db(sc, ARRQ_CH); 1987 #endif 1988 fwohci_arcv(sc, &sc->arrq, count); 1989 } 1990 if (stat & OHCI_INT_CYC_LOST) { 1991 if (sc->cycle_lost >= 0) 1992 sc->cycle_lost ++; 1993 if (sc->cycle_lost > 10) { 1994 sc->cycle_lost = -1; 1995 #if 0 1996 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1997 #endif 1998 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1999 device_printf(fc->dev, "too many cycle lost, " 2000 "no cycle master presents?\n"); 2001 } 2002 } 2003 if(stat & OHCI_INT_PHY_SID){ 2004 uint32_t *buf, node_id; 2005 int plen; 2006 2007 #ifndef ACK_ALL 2008 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2009 #endif 2010 /* Enable bus reset interrupt */ 2011 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2012 /* Allow async. request to us */ 2013 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2014 /* XXX insecure ?? */ 2015 /* allow from all nodes */ 2016 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2017 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2018 /* 0 to 4GB regison */ 2019 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2020 /* Set ATRetries register */ 2021 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2022 /* 2023 ** Checking whether the node is root or not. If root, turn on 2024 ** cycle master. 2025 */ 2026 node_id = OREAD(sc, FWOHCI_NODEID); 2027 plen = OREAD(sc, OHCI_SID_CNT); 2028 2029 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2030 node_id, (plen >> 16) & 0xff); 2031 if (!(node_id & OHCI_NODE_VALID)) { 2032 printf("Bus reset failure\n"); 2033 goto sidout; 2034 } 2035 2036 /* cycle timer */ 2037 sc->cycle_lost = 0; 2038 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2039 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2040 printf("CYCLEMASTER mode\n"); 2041 OWRITE(sc, OHCI_LNKCTL, 2042 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2043 } else { 2044 printf("non CYCLEMASTER mode\n"); 2045 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2046 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2047 } 2048 2049 fc->nodeid = node_id & 0x3f; 2050 2051 if (plen & OHCI_SID_ERR) { 2052 device_printf(fc->dev, "SID Error\n"); 2053 goto sidout; 2054 } 2055 plen &= OHCI_SID_CNT_MASK; 2056 if (plen < 4 || plen > OHCI_SIDSIZE) { 2057 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2058 goto sidout; 2059 } 2060 plen -= 4; /* chop control info */ 2061 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2062 if (buf == NULL) { 2063 device_printf(fc->dev, "malloc failed\n"); 2064 goto sidout; 2065 } 2066 for (i = 0; i < plen / 4; i ++) 2067 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2068 #if defined(__NetBSD__) && defined(macppc) 2069 /* XXX required as bootdisk for macppc. */ 2070 delay(500000); 2071 #endif 2072 #if 1 /* XXX needed?? */ 2073 /* pending all pre-bus_reset packets */ 2074 fwohci_txd(sc, &sc->atrq); 2075 fwohci_txd(sc, &sc->atrs); 2076 fwohci_arcv(sc, &sc->arrs, -1); 2077 fwohci_arcv(sc, &sc->arrq, -1); 2078 fw_drain_txq(fc); 2079 #endif 2080 fw_sidrcv(fc, buf, plen); 2081 free(buf, M_FW); 2082 } 2083 sidout: 2084 if((stat & OHCI_INT_DMA_ATRQ )){ 2085 #ifndef ACK_ALL 2086 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2087 #endif 2088 fwohci_txd(sc, &(sc->atrq)); 2089 } 2090 if((stat & OHCI_INT_DMA_ATRS )){ 2091 #ifndef ACK_ALL 2092 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2093 #endif 2094 fwohci_txd(sc, &(sc->atrs)); 2095 } 2096 if((stat & OHCI_INT_PW_ERR )){ 2097 #ifndef ACK_ALL 2098 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2099 #endif 2100 device_printf(fc->dev, "posted write error\n"); 2101 } 2102 if((stat & OHCI_INT_ERR )){ 2103 #ifndef ACK_ALL 2104 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2105 #endif 2106 device_printf(fc->dev, "unrecoverable error\n"); 2107 } 2108 if((stat & OHCI_INT_PHY_INT)) { 2109 #ifndef ACK_ALL 2110 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2111 #endif 2112 device_printf(fc->dev, "phy int\n"); 2113 } 2114 2115 CTR0(KTR_DEV, "fwohci_intr_body done"); 2116 return; 2117 } 2118 2119 #if FWOHCI_TASKQUEUE 2120 static void 2121 fwohci_complete(void *arg, int pending) 2122 { 2123 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2124 uint32_t stat; 2125 2126 again: 2127 stat = atomic_readandclear_int(&sc->intstat); 2128 if (stat) { 2129 FW_LOCK; 2130 fwohci_intr_body(sc, stat, -1); 2131 FW_UNLOCK; 2132 } else 2133 return; 2134 goto again; 2135 } 2136 #endif 2137 2138 static uint32_t 2139 fwochi_check_stat(struct fwohci_softc *sc) 2140 { 2141 uint32_t stat, irstat, itstat; 2142 2143 stat = OREAD(sc, FWOHCI_INTSTAT); 2144 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2145 if (stat == 0xffffffff) { 2146 device_printf(sc->fc.dev, 2147 "device physically ejected?\n"); 2148 return(stat); 2149 } 2150 #ifdef ACK_ALL 2151 if (stat) 2152 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2153 #endif 2154 if (stat & OHCI_INT_DMA_IR) { 2155 irstat = OREAD(sc, OHCI_IR_STAT); 2156 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2157 atomic_set_int(&sc->irstat, irstat); 2158 } 2159 if (stat & OHCI_INT_DMA_IT) { 2160 itstat = OREAD(sc, OHCI_IT_STAT); 2161 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2162 atomic_set_int(&sc->itstat, itstat); 2163 } 2164 return(stat); 2165 } 2166 2167 FW_INTR(fwohci) 2168 { 2169 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2170 uint32_t stat; 2171 #if !FWOHCI_TASKQUEUE 2172 uint32_t bus_reset = 0; 2173 #endif 2174 2175 if (!(sc->intmask & OHCI_INT_EN)) { 2176 /* polling mode */ 2177 FW_INTR_RETURN(0); 2178 } 2179 2180 #if !FWOHCI_TASKQUEUE 2181 again: 2182 #endif 2183 CTR0(KTR_DEV, "fwohci_intr"); 2184 stat = fwochi_check_stat(sc); 2185 if (stat == 0 || stat == 0xffffffff) 2186 FW_INTR_RETURN(1); 2187 #if FWOHCI_TASKQUEUE 2188 atomic_set_int(&sc->intstat, stat); 2189 /* XXX mask bus reset intr. during bus reset phase */ 2190 if (stat) 2191 #if 1 2192 taskqueue_enqueue_fast(taskqueue_fast, 2193 &sc->fwohci_task_complete); 2194 #else 2195 taskqueue_enqueue(taskqueue_swi, 2196 &sc->fwohci_task_complete); 2197 #endif 2198 #else 2199 /* We cannot clear bus reset event during bus reset phase */ 2200 if ((stat & ~bus_reset) == 0) 2201 FW_INTR_RETURN(1); 2202 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2203 fwohci_intr_body(sc, stat, -1); 2204 goto again; 2205 #endif 2206 CTR0(KTR_DEV, "fwohci_intr end"); 2207 } 2208 2209 void 2210 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2211 { 2212 int s; 2213 uint32_t stat; 2214 struct fwohci_softc *sc; 2215 2216 2217 sc = (struct fwohci_softc *)fc; 2218 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2219 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2220 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2221 #if 0 2222 if (!quick) { 2223 #else 2224 if (1) { 2225 #endif 2226 stat = fwochi_check_stat(sc); 2227 if (stat == 0 || stat == 0xffffffff) 2228 return; 2229 } 2230 s = splfw(); 2231 fwohci_intr_body(sc, stat, count); 2232 splx(s); 2233 } 2234 2235 static void 2236 fwohci_set_intr(struct firewire_comm *fc, int enable) 2237 { 2238 struct fwohci_softc *sc; 2239 2240 sc = (struct fwohci_softc *)fc; 2241 if (firewire_debug) 2242 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2243 if (enable) { 2244 sc->intmask |= OHCI_INT_EN; 2245 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2246 } else { 2247 sc->intmask &= ~OHCI_INT_EN; 2248 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2249 } 2250 } 2251 2252 static void 2253 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2254 { 2255 struct firewire_comm *fc = &sc->fc; 2256 struct fwohcidb *db; 2257 struct fw_bulkxfer *chunk; 2258 struct fw_xferq *it; 2259 uint32_t stat, count; 2260 int s, w=0, ldesc; 2261 2262 it = fc->it[dmach]; 2263 ldesc = sc->it[dmach].ndesc - 1; 2264 s = splfw(); /* unnecessary ? */ 2265 if (firewire_debug) 2266 dump_db(sc, ITX_CH + dmach); 2267 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2268 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2269 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2270 >> OHCI_STATUS_SHIFT; 2271 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2272 /* timestamp */ 2273 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2274 & OHCI_COUNT_MASK; 2275 if (stat == 0) 2276 break; 2277 STAILQ_REMOVE_HEAD(&it->stdma, link); 2278 switch (stat & FWOHCIEV_MASK){ 2279 case FWOHCIEV_ACKCOMPL: 2280 #if 0 2281 device_printf(fc->dev, "0x%08x\n", count); 2282 #endif 2283 break; 2284 default: 2285 device_printf(fc->dev, 2286 "Isochronous transmit err %02x(%s)\n", 2287 stat, fwohcicode[stat & 0x1f]); 2288 } 2289 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2290 w++; 2291 } 2292 splx(s); 2293 if (w) 2294 wakeup(it); 2295 } 2296 2297 static void 2298 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2299 { 2300 struct firewire_comm *fc = &sc->fc; 2301 struct fwohcidb_tr *db_tr; 2302 struct fw_bulkxfer *chunk; 2303 struct fw_xferq *ir; 2304 uint32_t stat; 2305 int s, w=0, ldesc; 2306 2307 ir = fc->ir[dmach]; 2308 ldesc = sc->ir[dmach].ndesc - 1; 2309 #if 0 2310 dump_db(sc, dmach); 2311 #endif 2312 s = splfw(); 2313 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2314 db_tr = (struct fwohcidb_tr *)chunk->end; 2315 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2316 >> OHCI_STATUS_SHIFT; 2317 if (stat == 0) 2318 break; 2319 2320 if (chunk->mbuf != NULL) { 2321 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2322 BUS_DMASYNC_POSTREAD); 2323 fw_bus_dmamap_unload( 2324 sc->ir[dmach].dmat, db_tr->dma_map); 2325 } else if (ir->buf != NULL) { 2326 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2327 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2328 } else { 2329 /* XXX */ 2330 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2331 } 2332 2333 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2334 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2335 switch (stat & FWOHCIEV_MASK) { 2336 case FWOHCIEV_ACKCOMPL: 2337 chunk->resp = 0; 2338 break; 2339 default: 2340 chunk->resp = EINVAL; 2341 device_printf(fc->dev, 2342 "Isochronous receive err %02x(%s)\n", 2343 stat, fwohcicode[stat & 0x1f]); 2344 } 2345 w++; 2346 } 2347 splx(s); 2348 if (w) { 2349 if (ir->flag & FWXFERQ_HANDLER) 2350 ir->hand(ir); 2351 else 2352 wakeup(ir); 2353 } 2354 } 2355 2356 void 2357 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2358 { 2359 uint32_t off, cntl, stat, cmd, match; 2360 2361 if(ch == 0){ 2362 off = OHCI_ATQOFF; 2363 }else if(ch == 1){ 2364 off = OHCI_ATSOFF; 2365 }else if(ch == 2){ 2366 off = OHCI_ARQOFF; 2367 }else if(ch == 3){ 2368 off = OHCI_ARSOFF; 2369 }else if(ch < IRX_CH){ 2370 off = OHCI_ITCTL(ch - ITX_CH); 2371 }else{ 2372 off = OHCI_IRCTL(ch - IRX_CH); 2373 } 2374 cntl = stat = OREAD(sc, off); 2375 cmd = OREAD(sc, off + 0xc); 2376 match = OREAD(sc, off + 0x10); 2377 2378 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2379 ch, 2380 cntl, 2381 cmd, 2382 match); 2383 stat &= 0xffff ; 2384 if (stat) { 2385 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2386 ch, 2387 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2388 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2389 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2390 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2391 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2392 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2393 fwohcicode[stat & 0x1f], 2394 stat & 0x1f 2395 ); 2396 }else{ 2397 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2398 } 2399 } 2400 2401 void 2402 dump_db(struct fwohci_softc *sc, uint32_t ch) 2403 { 2404 struct fwohci_dbch *dbch; 2405 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2406 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2407 int idb, jdb; 2408 uint32_t cmd, off; 2409 if(ch == 0){ 2410 off = OHCI_ATQOFF; 2411 dbch = &sc->atrq; 2412 }else if(ch == 1){ 2413 off = OHCI_ATSOFF; 2414 dbch = &sc->atrs; 2415 }else if(ch == 2){ 2416 off = OHCI_ARQOFF; 2417 dbch = &sc->arrq; 2418 }else if(ch == 3){ 2419 off = OHCI_ARSOFF; 2420 dbch = &sc->arrs; 2421 }else if(ch < IRX_CH){ 2422 off = OHCI_ITCTL(ch - ITX_CH); 2423 dbch = &sc->it[ch - ITX_CH]; 2424 }else { 2425 off = OHCI_IRCTL(ch - IRX_CH); 2426 dbch = &sc->ir[ch - IRX_CH]; 2427 } 2428 cmd = OREAD(sc, off + 0xc); 2429 2430 if( dbch->ndb == 0 ){ 2431 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2432 return; 2433 } 2434 pp = dbch->top; 2435 prev = pp->db; 2436 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2437 cp = STAILQ_NEXT(pp, link); 2438 if(cp == NULL){ 2439 curr = NULL; 2440 goto outdb; 2441 } 2442 np = STAILQ_NEXT(cp, link); 2443 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2444 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2445 curr = cp->db; 2446 if(np != NULL){ 2447 next = np->db; 2448 }else{ 2449 next = NULL; 2450 } 2451 goto outdb; 2452 } 2453 } 2454 pp = STAILQ_NEXT(pp, link); 2455 if(pp == NULL){ 2456 curr = NULL; 2457 goto outdb; 2458 } 2459 prev = pp->db; 2460 } 2461 outdb: 2462 if( curr != NULL){ 2463 #if 0 2464 printf("Prev DB %d\n", ch); 2465 print_db(pp, prev, ch, dbch->ndesc); 2466 #endif 2467 printf("Current DB %d\n", ch); 2468 print_db(cp, curr, ch, dbch->ndesc); 2469 #if 0 2470 printf("Next DB %d\n", ch); 2471 print_db(np, next, ch, dbch->ndesc); 2472 #endif 2473 }else{ 2474 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2475 } 2476 return; 2477 } 2478 2479 void 2480 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2481 uint32_t ch, uint32_t hogemax) 2482 { 2483 fwohcireg_t stat; 2484 int i, key; 2485 uint32_t cmd, res; 2486 2487 if(db == NULL){ 2488 printf("No Descriptor is found\n"); 2489 return; 2490 } 2491 2492 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2493 ch, 2494 "Current", 2495 "OP ", 2496 "KEY", 2497 "INT", 2498 "BR ", 2499 "len", 2500 "Addr", 2501 "Depend", 2502 "Stat", 2503 "Cnt"); 2504 for( i = 0 ; i <= hogemax ; i ++){ 2505 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2506 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2507 key = cmd & OHCI_KEY_MASK; 2508 stat = res >> OHCI_STATUS_SHIFT; 2509 #if defined(__DragonFly__) || \ 2510 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2511 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2512 db_tr->bus_addr, 2513 #else 2514 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2515 (uintmax_t)db_tr->bus_addr, 2516 #endif 2517 dbcode[(cmd >> 28) & 0xf], 2518 dbkey[(cmd >> 24) & 0x7], 2519 dbcond[(cmd >> 20) & 0x3], 2520 dbcond[(cmd >> 18) & 0x3], 2521 cmd & OHCI_COUNT_MASK, 2522 FWOHCI_DMA_READ(db[i].db.desc.addr), 2523 FWOHCI_DMA_READ(db[i].db.desc.depend), 2524 stat, 2525 res & OHCI_COUNT_MASK); 2526 if(stat & 0xff00){ 2527 printf(" %s%s%s%s%s%s %s(%x)\n", 2528 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2529 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2530 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2531 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2532 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2533 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2534 fwohcicode[stat & 0x1f], 2535 stat & 0x1f 2536 ); 2537 }else{ 2538 printf(" Nostat\n"); 2539 } 2540 if(key == OHCI_KEY_ST2 ){ 2541 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2542 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2543 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2544 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2545 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2546 } 2547 if(key == OHCI_KEY_DEVICE){ 2548 return; 2549 } 2550 if((cmd & OHCI_BRANCH_MASK) 2551 == OHCI_BRANCH_ALWAYS){ 2552 return; 2553 } 2554 if((cmd & OHCI_CMD_MASK) 2555 == OHCI_OUTPUT_LAST){ 2556 return; 2557 } 2558 if((cmd & OHCI_CMD_MASK) 2559 == OHCI_INPUT_LAST){ 2560 return; 2561 } 2562 if(key == OHCI_KEY_ST2 ){ 2563 i++; 2564 } 2565 } 2566 return; 2567 } 2568 2569 void 2570 fwohci_ibr(struct firewire_comm *fc) 2571 { 2572 struct fwohci_softc *sc; 2573 uint32_t fun; 2574 2575 device_printf(fc->dev, "Initiate bus reset\n"); 2576 sc = (struct fwohci_softc *)fc; 2577 2578 /* 2579 * Make sure our cached values from the config rom are 2580 * initialised. 2581 */ 2582 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2583 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2584 2585 /* 2586 * Set root hold-off bit so that non cyclemaster capable node 2587 * shouldn't became the root node. 2588 */ 2589 #if 1 2590 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2591 fun |= FW_PHY_IBR | FW_PHY_RHB; 2592 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2593 #else /* Short bus reset */ 2594 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2595 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2596 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2597 #endif 2598 } 2599 2600 void 2601 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2602 { 2603 struct fwohcidb_tr *db_tr, *fdb_tr; 2604 struct fwohci_dbch *dbch; 2605 struct fwohcidb *db; 2606 struct fw_pkt *fp; 2607 struct fwohci_txpkthdr *ohcifp; 2608 unsigned short chtag; 2609 int idb; 2610 2611 dbch = &sc->it[dmach]; 2612 chtag = sc->it[dmach].xferq.flag & 0xff; 2613 2614 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2615 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2616 /* 2617 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2618 */ 2619 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2620 db = db_tr->db; 2621 fp = (struct fw_pkt *)db_tr->buf; 2622 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2623 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2624 ohcifp->mode.common.spd = 0 & 0x7; 2625 ohcifp->mode.stream.len = fp->mode.stream.len; 2626 ohcifp->mode.stream.chtag = chtag; 2627 ohcifp->mode.stream.tcode = 0xa; 2628 #if BYTE_ORDER == BIG_ENDIAN 2629 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2630 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2631 #endif 2632 2633 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2634 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2635 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2636 #if 0 /* if bulkxfer->npackets changes */ 2637 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2638 | OHCI_UPDATE 2639 | OHCI_BRANCH_ALWAYS; 2640 db[0].db.desc.depend = 2641 = db[dbch->ndesc - 1].db.desc.depend 2642 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2643 #else 2644 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2645 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2646 #endif 2647 bulkxfer->end = (caddr_t)db_tr; 2648 db_tr = STAILQ_NEXT(db_tr, link); 2649 } 2650 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2651 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2652 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2653 #if 0 /* if bulkxfer->npackets changes */ 2654 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2655 /* OHCI 1.1 and above */ 2656 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2657 #endif 2658 /* 2659 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2660 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2661 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2662 */ 2663 return; 2664 } 2665 2666 static int 2667 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2668 int poffset) 2669 { 2670 struct fwohcidb *db = db_tr->db; 2671 struct fw_xferq *it; 2672 int err = 0; 2673 2674 it = &dbch->xferq; 2675 if(it->buf == 0){ 2676 err = EINVAL; 2677 return err; 2678 } 2679 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2680 db_tr->dbcnt = 3; 2681 2682 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2683 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2684 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2685 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2686 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2687 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2688 2689 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2690 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2691 #if 1 2692 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2693 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2694 #endif 2695 return 0; 2696 } 2697 2698 int 2699 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2700 int poffset, struct fwdma_alloc *dummy_dma) 2701 { 2702 struct fwohcidb *db = db_tr->db; 2703 struct fw_xferq *ir; 2704 int i, ldesc; 2705 bus_addr_t dbuf[2]; 2706 int dsiz[2]; 2707 2708 ir = &dbch->xferq; 2709 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2710 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2711 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2712 if (db_tr->buf == NULL) 2713 return(ENOMEM); 2714 db_tr->dbcnt = 1; 2715 dsiz[0] = ir->psize; 2716 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2717 BUS_DMASYNC_PREREAD); 2718 } else { 2719 db_tr->dbcnt = 0; 2720 if (dummy_dma != NULL) { 2721 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2722 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2723 } 2724 dsiz[db_tr->dbcnt] = ir->psize; 2725 if (ir->buf != NULL) { 2726 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2727 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2728 } 2729 db_tr->dbcnt++; 2730 } 2731 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2732 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2733 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2734 if (ir->flag & FWXFERQ_STREAM) { 2735 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2736 } 2737 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2738 } 2739 ldesc = db_tr->dbcnt - 1; 2740 if (ir->flag & FWXFERQ_STREAM) { 2741 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2742 } 2743 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2744 return 0; 2745 } 2746 2747 2748 static int 2749 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2750 { 2751 struct fw_pkt *fp0; 2752 uint32_t ld0; 2753 int slen, hlen; 2754 #if BYTE_ORDER == BIG_ENDIAN 2755 int i; 2756 #endif 2757 2758 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2759 #if 0 2760 printf("ld0: x%08x\n", ld0); 2761 #endif 2762 fp0 = (struct fw_pkt *)&ld0; 2763 /* determine length to swap */ 2764 switch (fp0->mode.common.tcode) { 2765 case FWTCODE_WRES: 2766 CTR0(KTR_DEV, "WRES"); 2767 case FWTCODE_RREQQ: 2768 case FWTCODE_WREQQ: 2769 case FWTCODE_RRESQ: 2770 case FWOHCITCODE_PHY: 2771 slen = 12; 2772 break; 2773 case FWTCODE_RREQB: 2774 case FWTCODE_WREQB: 2775 case FWTCODE_LREQ: 2776 case FWTCODE_RRESB: 2777 case FWTCODE_LRES: 2778 slen = 16; 2779 break; 2780 default: 2781 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2782 return(0); 2783 } 2784 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2785 if (hlen > len) { 2786 if (firewire_debug) 2787 printf("splitted header\n"); 2788 return(-hlen); 2789 } 2790 #if BYTE_ORDER == BIG_ENDIAN 2791 for(i = 0; i < slen/4; i ++) 2792 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2793 #endif 2794 return(hlen); 2795 } 2796 2797 static int 2798 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2799 { 2800 const struct tcode_info *info; 2801 int r; 2802 2803 info = &tinfo[fp->mode.common.tcode]; 2804 r = info->hdr_len + sizeof(uint32_t); 2805 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2806 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2807 2808 if (r == sizeof(uint32_t)) { 2809 /* XXX */ 2810 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2811 fp->mode.common.tcode); 2812 return (-1); 2813 } 2814 2815 if (r > dbch->xferq.psize) { 2816 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2817 return (-1); 2818 /* panic ? */ 2819 } 2820 2821 return r; 2822 } 2823 2824 static void 2825 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2826 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2827 { 2828 struct fwohcidb *db = &db_tr->db[0]; 2829 2830 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2831 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2832 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2833 dbch->bottom = db_tr; 2834 2835 if (wake) 2836 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2837 } 2838 2839 static void 2840 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2841 { 2842 struct fwohcidb_tr *db_tr; 2843 struct iovec vec[2]; 2844 struct fw_pkt pktbuf; 2845 int nvec; 2846 struct fw_pkt *fp; 2847 uint8_t *ld; 2848 uint32_t stat, off, status, event; 2849 u_int spd; 2850 int len, plen, hlen, pcnt, offset; 2851 int s; 2852 caddr_t buf; 2853 int resCount; 2854 2855 CTR0(KTR_DEV, "fwohci_arv"); 2856 2857 if(&sc->arrq == dbch){ 2858 off = OHCI_ARQOFF; 2859 }else if(&sc->arrs == dbch){ 2860 off = OHCI_ARSOFF; 2861 }else{ 2862 return; 2863 } 2864 2865 s = splfw(); 2866 db_tr = dbch->top; 2867 pcnt = 0; 2868 /* XXX we cannot handle a packet which lies in more than two buf */ 2869 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2870 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2871 while (status & OHCI_CNTL_DMA_ACTIVE) { 2872 #if 0 2873 2874 if (off == OHCI_ARQOFF) 2875 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2876 db_tr->bus_addr, status, resCount); 2877 #endif 2878 len = dbch->xferq.psize - resCount; 2879 ld = (uint8_t *)db_tr->buf; 2880 if (dbch->pdb_tr == NULL) { 2881 len -= dbch->buf_offset; 2882 ld += dbch->buf_offset; 2883 } 2884 if (len > 0) 2885 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2886 BUS_DMASYNC_POSTREAD); 2887 while (len > 0 ) { 2888 if (count >= 0 && count-- == 0) 2889 goto out; 2890 if(dbch->pdb_tr != NULL){ 2891 /* we have a fragment in previous buffer */ 2892 int rlen; 2893 2894 offset = dbch->buf_offset; 2895 if (offset < 0) 2896 offset = - offset; 2897 buf = dbch->pdb_tr->buf + offset; 2898 rlen = dbch->xferq.psize - offset; 2899 if (firewire_debug) 2900 printf("rlen=%d, offset=%d\n", 2901 rlen, dbch->buf_offset); 2902 if (dbch->buf_offset < 0) { 2903 /* splitted in header, pull up */ 2904 char *p; 2905 2906 p = (char *)&pktbuf; 2907 bcopy(buf, p, rlen); 2908 p += rlen; 2909 /* this must be too long but harmless */ 2910 rlen = sizeof(pktbuf) - rlen; 2911 if (rlen < 0) 2912 printf("why rlen < 0\n"); 2913 bcopy(db_tr->buf, p, rlen); 2914 ld += rlen; 2915 len -= rlen; 2916 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2917 if (hlen <= 0) { 2918 printf("hlen < 0 shouldn't happen"); 2919 goto err; 2920 } 2921 offset = sizeof(pktbuf); 2922 vec[0].iov_base = (char *)&pktbuf; 2923 vec[0].iov_len = offset; 2924 } else { 2925 /* splitted in payload */ 2926 offset = rlen; 2927 vec[0].iov_base = buf; 2928 vec[0].iov_len = rlen; 2929 } 2930 fp=(struct fw_pkt *)vec[0].iov_base; 2931 nvec = 1; 2932 } else { 2933 /* no fragment in previous buffer */ 2934 fp=(struct fw_pkt *)ld; 2935 hlen = fwohci_arcv_swap(fp, len); 2936 if (hlen == 0) 2937 goto err; 2938 if (hlen < 0) { 2939 dbch->pdb_tr = db_tr; 2940 dbch->buf_offset = - dbch->buf_offset; 2941 /* sanity check */ 2942 if (resCount != 0) { 2943 printf("resCount=%d hlen=%d\n", 2944 resCount, hlen); 2945 goto err; 2946 } 2947 goto out; 2948 } 2949 offset = 0; 2950 nvec = 0; 2951 } 2952 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2953 if (plen < 0) { 2954 /* minimum header size + trailer 2955 = sizeof(fw_pkt) so this shouldn't happens */ 2956 printf("plen(%d) is negative! offset=%d\n", 2957 plen, offset); 2958 goto err; 2959 } 2960 if (plen > 0) { 2961 len -= plen; 2962 if (len < 0) { 2963 dbch->pdb_tr = db_tr; 2964 if (firewire_debug) 2965 printf("splitted payload\n"); 2966 /* sanity check */ 2967 if (resCount != 0) { 2968 printf("resCount=%d plen=%d" 2969 " len=%d\n", 2970 resCount, plen, len); 2971 goto err; 2972 } 2973 goto out; 2974 } 2975 vec[nvec].iov_base = ld; 2976 vec[nvec].iov_len = plen; 2977 nvec ++; 2978 ld += plen; 2979 } 2980 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2981 if (nvec == 0) 2982 printf("nvec == 0\n"); 2983 2984 /* DMA result-code will be written at the tail of packet */ 2985 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 2986 #if 0 2987 printf("plen: %d, stat %x\n", 2988 plen ,stat); 2989 #endif 2990 spd = (stat >> 21) & 0x3; 2991 event = (stat >> 16) & 0x1f; 2992 switch (event) { 2993 case FWOHCIEV_ACKPEND: 2994 #if 0 2995 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2996 #endif 2997 /* fall through */ 2998 case FWOHCIEV_ACKCOMPL: 2999 { 3000 struct fw_rcv_buf rb; 3001 3002 if ((vec[nvec-1].iov_len -= 3003 sizeof(struct fwohci_trailer)) == 0) 3004 nvec--; 3005 rb.fc = &sc->fc; 3006 rb.vec = vec; 3007 rb.nvec = nvec; 3008 rb.spd = spd; 3009 fw_rcv(&rb); 3010 break; 3011 } 3012 case FWOHCIEV_BUSRST: 3013 if (sc->fc.status != FWBUSRESET) 3014 printf("got BUSRST packet!?\n"); 3015 break; 3016 default: 3017 device_printf(sc->fc.dev, 3018 "Async DMA Receive error err=%02x %s" 3019 " plen=%d offset=%d len=%d status=0x%08x" 3020 " tcode=0x%x, stat=0x%08x\n", 3021 event, fwohcicode[event], plen, 3022 dbch->buf_offset, len, 3023 OREAD(sc, OHCI_DMACTL(off)), 3024 fp->mode.common.tcode, stat); 3025 #if 1 /* XXX */ 3026 goto err; 3027 #endif 3028 break; 3029 } 3030 pcnt ++; 3031 if (dbch->pdb_tr != NULL) { 3032 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3033 off, 1); 3034 dbch->pdb_tr = NULL; 3035 } 3036 3037 } 3038 out: 3039 if (resCount == 0) { 3040 /* done on this buffer */ 3041 if (dbch->pdb_tr == NULL) { 3042 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3043 dbch->buf_offset = 0; 3044 } else 3045 if (dbch->pdb_tr != db_tr) 3046 printf("pdb_tr != db_tr\n"); 3047 db_tr = STAILQ_NEXT(db_tr, link); 3048 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3049 >> OHCI_STATUS_SHIFT; 3050 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3051 & OHCI_COUNT_MASK; 3052 /* XXX check buffer overrun */ 3053 dbch->top = db_tr; 3054 } else { 3055 dbch->buf_offset = dbch->xferq.psize - resCount; 3056 fw_bus_dmamap_sync( 3057 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3058 break; 3059 } 3060 /* XXX make sure DMA is not dead */ 3061 } 3062 #if 0 3063 if (pcnt < 1) 3064 printf("fwohci_arcv: no packets\n"); 3065 #endif 3066 splx(s); 3067 return; 3068 3069 err: 3070 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3071 OREAD(sc, OHCI_DMACTL(off))); 3072 dbch->pdb_tr = NULL; 3073 /* skip until resCount != 0 */ 3074 printf(" skip buffer"); 3075 while (resCount == 0) { 3076 printf(" #"); 3077 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3078 db_tr = STAILQ_NEXT(db_tr, link); 3079 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3080 & OHCI_COUNT_MASK; 3081 } 3082 printf(" done\n"); 3083 dbch->top = db_tr; 3084 dbch->buf_offset = dbch->xferq.psize - resCount; 3085 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3086 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3087 splx(s); 3088 } 3089 #if defined(__NetBSD__) 3090 3091 int 3092 fwohci_print(void *aux, const char *pnp) 3093 { 3094 char *name = aux; 3095 3096 if (pnp) 3097 aprint_normal("%s at %s", name, pnp); 3098 3099 return UNCONF; 3100 } 3101 #endif 3102
Indexes created Thu Sep 25 16:09:42 GMT 2025