fwohci.c revision 1.97
1 /* $NetBSD: fwohci.c,v 1.97 2006/04/30 14:14:06 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Hidetoshi Shimokawa 5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the acknowledgement as bellow: 18 * 19 * This product includes software developed by K. Kobayashi and H. Shimokawa 20 * 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $ 37 * 38 */ 39 40 #define ATRQ_CH 0 41 #define ATRS_CH 1 42 #define ARRQ_CH 2 43 #define ARRS_CH 3 44 #define ITX_CH 4 45 #define IRX_CH 0x24 46 47 #if defined(__FreeBSD__) 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/conf.h> 57 #include <sys/endian.h> 58 #include <sys/ktr.h> 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.97 2006/04/30 14:14:06 kiyohara Exp $"); 62 63 #if defined(__DragonFly__) || __FreeBSD_version < 500000 64 #include <machine/clock.h> /* for DELAY() */ 65 #endif 66 67 #ifdef __DragonFly__ 68 #include "fw_port.h" 69 #include "firewire.h" 70 #include "firewirereg.h" 71 #include "fwdma.h" 72 #include "fwohcireg.h" 73 #include "fwohcivar.h" 74 #include "firewire_phy.h" 75 #else 76 #include <dev/firewire/fw_port.h> 77 #include <dev/firewire/firewire.h> 78 #include <dev/firewire/firewirereg.h> 79 #include <dev/firewire/fwdma.h> 80 #include <dev/firewire/fwohcireg.h> 81 #include <dev/firewire/fwohcivar.h> 82 #include <dev/firewire/firewire_phy.h> 83 #endif 84 #elif defined(__NetBSD__) 85 #include <sys/param.h> 86 #include <sys/device.h> 87 #include <sys/errno.h> 88 #include <sys/conf.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/mbuf.h> 92 #include <sys/proc.h> 93 #include <sys/reboot.h> 94 #include <sys/sysctl.h> 95 #include <sys/systm.h> 96 97 #include <machine/bus.h> 98 99 #include <dev/ieee1394/fw_port.h> 100 #include <dev/ieee1394/firewire.h> 101 #include <dev/ieee1394/firewirereg.h> 102 #include <dev/ieee1394/fwdma.h> 103 #include <dev/ieee1394/fwohcireg.h> 104 #include <dev/ieee1394/fwohcivar.h> 105 #include <dev/ieee1394/firewire_phy.h> 106 #endif 107 108 #undef OHCI_DEBUG 109 110 static int nocyclemaster = 0; 111 #if defined(__FreeBSD__) 112 SYSCTL_DECL(_hw_firewire); 113 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 114 "Do not send cycle start packets"); 115 #elif defined(__NetBSD__) 116 /* 117 * Setup sysctl(3) MIB, hw.fwohci.* 118 * 119 * TBD condition CTLFLAG_PERMANENT on being an LKM or not 120 */ 121 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup") 122 { 123 int rc; 124 const struct sysctlnode *node; 125 126 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 127 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 128 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 129 goto err; 130 } 131 132 if ((rc = sysctl_createv(clog, 0, NULL, &node, 133 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci", 134 SYSCTL_DESCR("fwohci controls"), 135 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 136 goto err; 137 } 138 139 /* fwohci no cyclemaster flag */ 140 if ((rc = sysctl_createv(clog, 0, NULL, &node, 141 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 142 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"), 143 NULL, 0, &nocyclemaster, 144 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) { 145 goto err; 146 } 147 return; 148 149 err: 150 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 151 } 152 #endif 153 154 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL", 155 "STOR","LOAD","NOP ","STOP", 156 "", "", "", "", "", "", "", ""}; 157 158 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3", 159 "UNDEF","REG","SYS","DEV"}; 160 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"}; 161 static const char * const fwohcicode[32] = { 162 "No stat","Undef","long","miss Ack err", 163 "underrun","overrun","desc err", "data read err", 164 "data write err","bus reset","timeout","tcode err", 165 "Undef","Undef","unknown event","flushed", 166 "Undef","ack complete","ack pend","Undef", 167 "ack busy_X","ack busy_A","ack busy_B","Undef", 168 "Undef","Undef","Undef","ack tardy", 169 "Undef","ack data_err","ack type_err",""}; 170 171 #define MAX_SPEED 3 172 extern const char *fw_linkspeed[]; 173 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 174 175 static const struct tcode_info tinfo[] = { 176 /* hdr_len block flag*/ 177 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 178 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 179 /* 2 WRES */ {12, FWTI_RES}, 180 /* 3 XXX */ { 0, 0}, 181 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 182 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 183 /* 6 RRESQ */ {16, FWTI_RES}, 184 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 185 /* 8 CYCS */ { 0, 0}, 186 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 187 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 188 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 189 /* c XXX */ { 0, 0}, 190 /* d XXX */ { 0, 0}, 191 /* e PHY */ {12, FWTI_REQ}, 192 /* f XXX */ { 0, 0} 193 }; 194 195 #define OHCI_WRITE_SIGMASK 0xffff0000 196 #define OHCI_READ_SIGMASK 0xffff0000 197 198 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 199 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 200 201 static void fwohci_ibr (struct firewire_comm *); 202 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); 203 static void fwohci_db_free (struct fwohci_dbch *); 204 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); 205 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); 206 static void fwohci_start_atq (struct firewire_comm *); 207 static void fwohci_start_ats (struct firewire_comm *); 208 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); 209 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 210 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 211 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); 212 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); 213 static int fwohci_irx_enable (struct firewire_comm *, int); 214 static int fwohci_irx_disable (struct firewire_comm *, int); 215 #if BYTE_ORDER == BIG_ENDIAN 216 static void fwohci_irx_post (struct firewire_comm *, uint32_t *); 217 #endif 218 static int fwohci_itxbuf_enable (struct firewire_comm *, int); 219 static int fwohci_itx_disable (struct firewire_comm *, int); 220 static void fwohci_timeout (void *); 221 static void fwohci_set_intr (struct firewire_comm *, int); 222 223 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); 224 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); 225 static void dump_db (struct fwohci_softc *, uint32_t); 226 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t); 227 static void dump_dma (struct fwohci_softc *, uint32_t); 228 static uint32_t fwohci_cyctimer (struct firewire_comm *); 229 static void fwohci_rbuf_update (struct fwohci_softc *, int); 230 static void fwohci_tbuf_update (struct fwohci_softc *, int); 231 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); 232 #if FWOHCI_TASKQUEUE 233 static void fwohci_complete(void *, int); 234 #endif 235 #if defined(__NetBSD__) 236 static void fwohci_power(int, void *); 237 int fwohci_print(void *, const char *); 238 #endif 239 240 /* 241 * memory allocated for DMA programs 242 */ 243 #define DMA_PROG_ALLOC (8 * PAGE_SIZE) 244 245 #define NDB FWMAXQUEUE 246 247 #define OHCI_VERSION 0x00 248 #define OHCI_ATRETRY 0x08 249 #define OHCI_CROMHDR 0x18 250 #define OHCI_BUS_OPT 0x20 251 #define OHCI_BUSIRMC (1 << 31) 252 #define OHCI_BUSCMC (1 << 30) 253 #define OHCI_BUSISC (1 << 29) 254 #define OHCI_BUSBMC (1 << 28) 255 #define OHCI_BUSPMC (1 << 27) 256 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 257 OHCI_BUSBMC | OHCI_BUSPMC 258 259 #define OHCI_EUID_HI 0x24 260 #define OHCI_EUID_LO 0x28 261 262 #define OHCI_CROMPTR 0x34 263 #define OHCI_HCCCTL 0x50 264 #define OHCI_HCCCTLCLR 0x54 265 #define OHCI_AREQHI 0x100 266 #define OHCI_AREQHICLR 0x104 267 #define OHCI_AREQLO 0x108 268 #define OHCI_AREQLOCLR 0x10c 269 #define OHCI_PREQHI 0x110 270 #define OHCI_PREQHICLR 0x114 271 #define OHCI_PREQLO 0x118 272 #define OHCI_PREQLOCLR 0x11c 273 #define OHCI_PREQUPPER 0x120 274 275 #define OHCI_SID_BUF 0x64 276 #define OHCI_SID_CNT 0x68 277 #define OHCI_SID_ERR (1 << 31) 278 #define OHCI_SID_CNT_MASK 0xffc 279 280 #define OHCI_IT_STAT 0x90 281 #define OHCI_IT_STATCLR 0x94 282 #define OHCI_IT_MASK 0x98 283 #define OHCI_IT_MASKCLR 0x9c 284 285 #define OHCI_IR_STAT 0xa0 286 #define OHCI_IR_STATCLR 0xa4 287 #define OHCI_IR_MASK 0xa8 288 #define OHCI_IR_MASKCLR 0xac 289 290 #define OHCI_LNKCTL 0xe0 291 #define OHCI_LNKCTLCLR 0xe4 292 293 #define OHCI_PHYACCESS 0xec 294 #define OHCI_CYCLETIMER 0xf0 295 296 #define OHCI_DMACTL(off) (off) 297 #define OHCI_DMACTLCLR(off) (off + 4) 298 #define OHCI_DMACMD(off) (off + 0xc) 299 #define OHCI_DMAMATCH(off) (off + 0x10) 300 301 #define OHCI_ATQOFF 0x180 302 #define OHCI_ATQCTL OHCI_ATQOFF 303 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 304 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 305 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 306 307 #define OHCI_ATSOFF 0x1a0 308 #define OHCI_ATSCTL OHCI_ATSOFF 309 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 310 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 311 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 312 313 #define OHCI_ARQOFF 0x1c0 314 #define OHCI_ARQCTL OHCI_ARQOFF 315 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 316 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 317 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 318 319 #define OHCI_ARSOFF 0x1e0 320 #define OHCI_ARSCTL OHCI_ARSOFF 321 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 322 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 323 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 324 325 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 326 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 327 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 328 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 329 330 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 331 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 332 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 333 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 334 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 335 336 #if defined(__FreeBSD__) 337 d_ioctl_t fwohci_ioctl; 338 #elif defined(__NetBSD__) 339 extern struct cfdriver fwohci_cd; 340 dev_type_ioctl(fwohci_ioctl); 341 #endif 342 343 /* 344 * Communication with PHY device 345 */ 346 static uint32_t 347 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 348 { 349 uint32_t fun; 350 351 addr &= 0xf; 352 data &= 0xff; 353 354 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 355 OWRITE(sc, OHCI_PHYACCESS, fun); 356 DELAY(100); 357 358 return(fwphy_rddata( sc, addr)); 359 } 360 361 static uint32_t 362 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 363 { 364 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 365 int i; 366 uint32_t bm; 367 368 #define OHCI_CSR_DATA 0x0c 369 #define OHCI_CSR_COMP 0x10 370 #define OHCI_CSR_CONT 0x14 371 #define OHCI_BUS_MANAGER_ID 0 372 373 OWRITE(sc, OHCI_CSR_DATA, node); 374 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 375 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 376 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 377 DELAY(10); 378 bm = OREAD(sc, OHCI_CSR_DATA); 379 if((bm & 0x3f) == 0x3f) 380 bm = node; 381 if (firewire_debug) 382 device_printf(sc->fc.dev, 383 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 384 385 return(bm); 386 } 387 388 static uint32_t 389 fwphy_rddata(struct fwohci_softc *sc, u_int addr) 390 { 391 uint32_t fun, stat; 392 u_int i, retry = 0; 393 394 addr &= 0xf; 395 #define MAX_RETRY 100 396 again: 397 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 398 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 399 OWRITE(sc, OHCI_PHYACCESS, fun); 400 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 401 fun = OREAD(sc, OHCI_PHYACCESS); 402 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 403 break; 404 DELAY(100); 405 } 406 if(i >= MAX_RETRY) { 407 if (firewire_debug) 408 device_printf(sc->fc.dev, "phy read failed(1).\n"); 409 if (++retry < MAX_RETRY) { 410 DELAY(100); 411 goto again; 412 } 413 } 414 /* Make sure that SCLK is started */ 415 stat = OREAD(sc, FWOHCI_INTSTAT); 416 if ((stat & OHCI_INT_REG_FAIL) != 0 || 417 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 418 if (firewire_debug) 419 device_printf(sc->fc.dev, "phy read failed(2).\n"); 420 if (++retry < MAX_RETRY) { 421 DELAY(100); 422 goto again; 423 } 424 } 425 if (firewire_debug || retry >= MAX_RETRY) 426 device_printf(sc->fc.dev, 427 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 428 #undef MAX_RETRY 429 return((fun >> PHYDEV_RDDATA )& 0xff); 430 } 431 /* Device specific ioctl. */ 432 FW_IOCTL(fwohci) 433 { 434 FW_IOCTL_START; 435 struct fwohci_softc *fc; 436 int err = 0; 437 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 438 uint32_t *dmach = (uint32_t *) data; 439 440 if(sc == NULL){ 441 return(EINVAL); 442 } 443 fc = (struct fwohci_softc *)sc->fc; 444 445 if (!data) 446 return(EINVAL); 447 448 switch (cmd) { 449 case FWOHCI_WRREG: 450 #define OHCI_MAX_REG 0x800 451 if(reg->addr <= OHCI_MAX_REG){ 452 OWRITE(fc, reg->addr, reg->data); 453 reg->data = OREAD(fc, reg->addr); 454 }else{ 455 err = EINVAL; 456 } 457 break; 458 case FWOHCI_RDREG: 459 if(reg->addr <= OHCI_MAX_REG){ 460 reg->data = OREAD(fc, reg->addr); 461 }else{ 462 err = EINVAL; 463 } 464 break; 465 /* Read DMA descriptors for debug */ 466 case DUMPDMA: 467 if(*dmach <= OHCI_MAX_DMA_CH ){ 468 dump_dma(fc, *dmach); 469 dump_db(fc, *dmach); 470 }else{ 471 err = EINVAL; 472 } 473 break; 474 /* Read/Write Phy registers */ 475 #define OHCI_MAX_PHY_REG 0xf 476 case FWOHCI_RDPHYREG: 477 if (reg->addr <= OHCI_MAX_PHY_REG) 478 reg->data = fwphy_rddata(fc, reg->addr); 479 else 480 err = EINVAL; 481 break; 482 case FWOHCI_WRPHYREG: 483 if (reg->addr <= OHCI_MAX_PHY_REG) 484 reg->data = fwphy_wrdata(fc, reg->addr, reg->data); 485 else 486 err = EINVAL; 487 break; 488 default: 489 err = EINVAL; 490 break; 491 } 492 return err; 493 } 494 495 static int 496 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 497 { 498 uint32_t reg, reg2; 499 int e1394a = 1; 500 /* 501 * probe PHY parameters 502 * 0. to prove PHY version, whether compliance of 1394a. 503 * 1. to probe maximum speed supported by the PHY and 504 * number of port supported by core-logic. 505 * It is not actually available port on your PC . 506 */ 507 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 508 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 509 510 if((reg >> 5) != 7 ){ 511 sc->fc.mode &= ~FWPHYASYST; 512 sc->fc.nport = reg & FW_PHY_NP; 513 sc->fc.speed = reg & FW_PHY_SPD >> 6; 514 if (sc->fc.speed > MAX_SPEED) { 515 device_printf(dev, "invalid speed %d (fixed to %d).\n", 516 sc->fc.speed, MAX_SPEED); 517 sc->fc.speed = MAX_SPEED; 518 } 519 device_printf(dev, 520 "Phy 1394 only %s, %d ports.\n", 521 fw_linkspeed[sc->fc.speed], sc->fc.nport); 522 }else{ 523 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 524 sc->fc.mode |= FWPHYASYST; 525 sc->fc.nport = reg & FW_PHY_NP; 526 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 527 if (sc->fc.speed > MAX_SPEED) { 528 device_printf(dev, "invalid speed %d (fixed to %d).\n", 529 sc->fc.speed, MAX_SPEED); 530 sc->fc.speed = MAX_SPEED; 531 } 532 device_printf(dev, 533 "Phy 1394a available %s, %d ports.\n", 534 fw_linkspeed[sc->fc.speed], sc->fc.nport); 535 536 /* check programPhyEnable */ 537 reg2 = fwphy_rddata(sc, 5); 538 #if 0 539 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 540 #else /* XXX force to enable 1394a */ 541 if (e1394a) { 542 #endif 543 if (firewire_debug) 544 device_printf(dev, 545 "Enable 1394a Enhancements\n"); 546 /* enable EAA EMC */ 547 reg2 |= 0x03; 548 /* set aPhyEnhanceEnable */ 549 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 550 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 551 } 552 #if 0 553 else { 554 /* for safe */ 555 reg2 &= ~0x83; 556 } 557 #endif 558 reg2 = fwphy_wrdata(sc, 5, reg2); 559 } 560 561 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 562 if((reg >> 5) == 7 ){ 563 reg = fwphy_rddata(sc, 4); 564 reg |= 1 << 6; 565 fwphy_wrdata(sc, 4, reg); 566 reg = fwphy_rddata(sc, 4); 567 } 568 return 0; 569 } 570 571 572 void 573 fwohci_reset(struct fwohci_softc *sc, device_t dev) 574 { 575 int i, max_rec, speed; 576 uint32_t reg, reg2; 577 struct fwohcidb_tr *db_tr; 578 579 /* Disable interrupts */ 580 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 581 582 /* Now stopping all DMA channels */ 583 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 584 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 585 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 586 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 587 588 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 589 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 590 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 591 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 592 } 593 594 /* FLUSH FIFO and reset Transmitter/Reciever */ 595 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 596 if (firewire_debug) 597 device_printf(dev, "resetting OHCI..."); 598 i = 0; 599 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 600 if (i++ > 100) break; 601 DELAY(1000); 602 } 603 if (firewire_debug) 604 printf("done (loop=%d)\n", i); 605 606 /* Probe phy */ 607 fwohci_probe_phy(sc, dev); 608 609 /* Probe link */ 610 reg = OREAD(sc, OHCI_BUS_OPT); 611 reg2 = reg | OHCI_BUSFNC; 612 max_rec = (reg & 0x0000f000) >> 12; 613 speed = (reg & 0x00000007); 614 device_printf(dev, "Link %s, max_rec %d bytes.\n", 615 fw_linkspeed[speed], MAXREC(max_rec)); 616 /* XXX fix max_rec */ 617 sc->fc.maxrec = sc->fc.speed + 8; 618 if (max_rec != sc->fc.maxrec) { 619 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 620 device_printf(dev, "max_rec %d -> %d\n", 621 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 622 } 623 if (firewire_debug) 624 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 625 OWRITE(sc, OHCI_BUS_OPT, reg2); 626 627 /* Initialize registers */ 628 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 629 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); 630 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 631 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 632 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 633 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 634 635 /* Enable link */ 636 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 637 638 /* Force to start async RX DMA */ 639 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 640 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 641 fwohci_rx_enable(sc, &sc->arrq); 642 fwohci_rx_enable(sc, &sc->arrs); 643 644 /* Initialize async TX */ 645 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 646 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 647 648 /* AT Retries */ 649 OWRITE(sc, FWOHCI_RETRY, 650 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 651 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 652 653 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); 654 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); 655 sc->atrq.bottom = sc->atrq.top; 656 sc->atrs.bottom = sc->atrs.top; 657 658 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 659 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 660 db_tr->xfer = NULL; 661 } 662 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 663 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 664 db_tr->xfer = NULL; 665 } 666 667 668 /* Enable interrupts */ 669 OWRITE(sc, FWOHCI_INTMASK, 670 OHCI_INT_ERR | OHCI_INT_PHY_SID 671 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 672 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 673 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 674 fwohci_set_intr(&sc->fc, 1); 675 676 } 677 678 int 679 fwohci_init(struct fwohci_softc *sc, device_t dev) 680 { 681 int i, mver; 682 uint32_t reg; 683 uint8_t ui[8]; 684 685 #if FWOHCI_TASKQUEUE 686 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); 687 #endif 688 689 /* OHCI version */ 690 reg = OREAD(sc, OHCI_VERSION); 691 mver = (reg >> 16) & 0xff; 692 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 693 mver, reg & 0xff, (reg>>24) & 1); 694 if (mver < 1 || mver > 9) { 695 device_printf(dev, "invalid OHCI version\n"); 696 return (ENXIO); 697 } 698 699 /* Available Isochronous DMA channel probe */ 700 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 701 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 702 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 703 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 704 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 705 for (i = 0; i < 0x20; i++) 706 if ((reg & (1 << i)) == 0) 707 break; 708 sc->fc.nisodma = i; 709 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 710 if (i == 0) 711 return (ENXIO); 712 713 sc->fc.arq = &sc->arrq.xferq; 714 sc->fc.ars = &sc->arrs.xferq; 715 sc->fc.atq = &sc->atrq.xferq; 716 sc->fc.ats = &sc->atrs.xferq; 717 718 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 719 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 720 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 721 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); 722 723 sc->arrq.xferq.start = NULL; 724 sc->arrs.xferq.start = NULL; 725 sc->atrq.xferq.start = fwohci_start_atq; 726 sc->atrs.xferq.start = fwohci_start_ats; 727 728 sc->arrq.xferq.buf = NULL; 729 sc->arrs.xferq.buf = NULL; 730 sc->atrq.xferq.buf = NULL; 731 sc->atrs.xferq.buf = NULL; 732 733 sc->arrq.xferq.dmach = -1; 734 sc->arrs.xferq.dmach = -1; 735 sc->atrq.xferq.dmach = -1; 736 sc->atrs.xferq.dmach = -1; 737 738 sc->arrq.ndesc = 1; 739 sc->arrs.ndesc = 1; 740 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 741 sc->atrs.ndesc = 2; 742 743 sc->arrq.ndb = NDB; 744 sc->arrs.ndb = NDB / 2; 745 sc->atrq.ndb = NDB; 746 sc->atrs.ndb = NDB / 2; 747 748 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 749 sc->fc.it[i] = &sc->it[i].xferq; 750 sc->fc.ir[i] = &sc->ir[i].xferq; 751 sc->it[i].xferq.dmach = i; 752 sc->ir[i].xferq.dmach = i; 753 sc->it[i].ndb = 0; 754 sc->ir[i].ndb = 0; 755 } 756 757 sc->fc.tcode = tinfo; 758 sc->fc.dev = dev; 759 760 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, 761 &sc->crom_dma, BUS_DMA_WAITOK); 762 if(sc->fc.config_rom == NULL){ 763 device_printf(dev, "config_rom alloc failed."); 764 return ENOMEM; 765 } 766 767 #if 0 768 bzero(&sc->fc.config_rom[0], CROMSIZE); 769 sc->fc.config_rom[1] = 0x31333934; 770 sc->fc.config_rom[2] = 0xf000a002; 771 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 772 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 773 sc->fc.config_rom[5] = 0; 774 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 775 776 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 777 #endif 778 779 780 /* SID recieve buffer must align 2^11 */ 781 #define OHCI_SIDSIZE (1 << 11) 782 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 783 &sc->sid_dma, BUS_DMA_WAITOK); 784 if (sc->sid_buf == NULL) { 785 device_printf(dev, "sid_buf alloc failed."); 786 return ENOMEM; 787 } 788 789 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t), 790 &sc->dummy_dma, BUS_DMA_WAITOK); 791 792 if (sc->dummy_dma.v_addr == NULL) { 793 device_printf(dev, "dummy_dma alloc failed."); 794 return ENOMEM; 795 } 796 797 fwohci_db_init(sc, &sc->arrq); 798 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 799 return ENOMEM; 800 801 fwohci_db_init(sc, &sc->arrs); 802 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 803 return ENOMEM; 804 805 fwohci_db_init(sc, &sc->atrq); 806 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 807 return ENOMEM; 808 809 fwohci_db_init(sc, &sc->atrs); 810 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 811 return ENOMEM; 812 813 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 814 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 815 for( i = 0 ; i < 8 ; i ++) 816 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 817 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 818 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 819 820 sc->fc.ioctl = fwohci_ioctl; 821 sc->fc.cyctimer = fwohci_cyctimer; 822 sc->fc.set_bmr = fwohci_set_bus_manager; 823 sc->fc.ibr = fwohci_ibr; 824 sc->fc.irx_enable = fwohci_irx_enable; 825 sc->fc.irx_disable = fwohci_irx_disable; 826 827 sc->fc.itx_enable = fwohci_itxbuf_enable; 828 sc->fc.itx_disable = fwohci_itx_disable; 829 #if BYTE_ORDER == BIG_ENDIAN 830 sc->fc.irx_post = fwohci_irx_post; 831 #else 832 sc->fc.irx_post = NULL; 833 #endif 834 sc->fc.itx_post = NULL; 835 sc->fc.timeout = fwohci_timeout; 836 sc->fc.poll = fwohci_poll; 837 sc->fc.set_intr = fwohci_set_intr; 838 839 sc->intmask = sc->irstat = sc->itstat = 0; 840 841 fw_init(&sc->fc); 842 fwohci_reset(sc, dev); 843 FWOHCI_INIT_END; 844 845 return 0; 846 } 847 848 void 849 fwohci_timeout(void *arg) 850 { 851 struct fwohci_softc *sc; 852 853 sc = (struct fwohci_softc *)arg; 854 } 855 856 uint32_t 857 fwohci_cyctimer(struct firewire_comm *fc) 858 { 859 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 860 return(OREAD(sc, OHCI_CYCLETIMER)); 861 } 862 863 FWOHCI_DETACH() 864 { 865 int i; 866 867 FWOHCI_DETACH_START; 868 if (sc->sid_buf != NULL) 869 fwdma_free(&sc->fc, &sc->sid_dma); 870 if (sc->fc.config_rom != NULL) 871 fwdma_free(&sc->fc, &sc->crom_dma); 872 873 fwohci_db_free(&sc->arrq); 874 fwohci_db_free(&sc->arrs); 875 876 fwohci_db_free(&sc->atrq); 877 fwohci_db_free(&sc->atrs); 878 879 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 880 fwohci_db_free(&sc->it[i]); 881 fwohci_db_free(&sc->ir[i]); 882 } 883 FWOHCI_DETACH_END; 884 885 return 0; 886 } 887 888 #define LAST_DB(dbtr, db) do { \ 889 struct fwohcidb_tr *_dbtr = (dbtr); \ 890 int _cnt = _dbtr->dbcnt; \ 891 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 892 } while (0) 893 894 static void 895 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) 896 { 897 struct fwohcidb_tr *db_tr; 898 struct fwohcidb *db; 899 bus_dma_segment_t *s; 900 int i; 901 902 db_tr = (struct fwohcidb_tr *)arg; 903 db = &db_tr->db[db_tr->dbcnt]; 904 if (error) { 905 if (firewire_debug || error != EFBIG) 906 printf("fwohci_execute_db: error=%d\n", error); 907 return; 908 } 909 for (i = 0; i < nseg; i++) { 910 s = &segs[i]; 911 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); 912 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); 913 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 914 db++; 915 db_tr->dbcnt++; 916 } 917 } 918 919 static void 920 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, 921 bus_size_t size, int error) 922 { 923 fwohci_execute_db(arg, segs, nseg, error); 924 } 925 926 static void 927 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 928 { 929 int i, s; 930 int tcode, hdr_len, pl_off; 931 int fsegment = -1; 932 uint32_t off; 933 struct fw_xfer *xfer; 934 struct fw_pkt *fp; 935 struct fwohci_txpkthdr *ohcifp; 936 struct fwohcidb_tr *db_tr; 937 struct fwohcidb *db; 938 uint32_t *ld; 939 const struct tcode_info *info; 940 static int maxdesc=0; 941 942 if(&sc->atrq == dbch){ 943 off = OHCI_ATQOFF; 944 }else if(&sc->atrs == dbch){ 945 off = OHCI_ATSOFF; 946 }else{ 947 return; 948 } 949 950 if (dbch->flags & FWOHCI_DBCH_FULL) 951 return; 952 953 s = splfw(); 954 db_tr = dbch->top; 955 txloop: 956 xfer = STAILQ_FIRST(&dbch->xferq.q); 957 if(xfer == NULL){ 958 goto kick; 959 } 960 if(dbch->xferq.queued == 0 ){ 961 device_printf(sc->fc.dev, "TX queue empty\n"); 962 } 963 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 964 db_tr->xfer = xfer; 965 xfer->state = FWXF_START; 966 967 fp = &xfer->send.hdr; 968 tcode = fp->mode.common.tcode; 969 970 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 971 info = &tinfo[tcode]; 972 hdr_len = pl_off = info->hdr_len; 973 974 ld = &ohcifp->mode.ld[0]; 975 ld[0] = ld[1] = ld[2] = ld[3] = 0; 976 for( i = 0 ; i < pl_off ; i+= 4) 977 ld[i/4] = fp->mode.ld[i/4]; 978 979 ohcifp->mode.common.spd = xfer->send.spd & 0x7; 980 if (tcode == FWTCODE_STREAM ){ 981 hdr_len = 8; 982 ohcifp->mode.stream.len = fp->mode.stream.len; 983 } else if (tcode == FWTCODE_PHY) { 984 hdr_len = 12; 985 ld[1] = fp->mode.ld[1]; 986 ld[2] = fp->mode.ld[2]; 987 ohcifp->mode.common.spd = 0; 988 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 989 } else { 990 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; 991 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 992 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 993 } 994 db = &db_tr->db[0]; 995 FWOHCI_DMA_WRITE(db->db.desc.cmd, 996 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); 997 FWOHCI_DMA_WRITE(db->db.desc.addr, 0); 998 FWOHCI_DMA_WRITE(db->db.desc.res, 0); 999 /* Specify bound timer of asy. responce */ 1000 if(&sc->atrs == dbch){ 1001 FWOHCI_DMA_WRITE(db->db.desc.res, 1002 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); 1003 } 1004 #if BYTE_ORDER == BIG_ENDIAN 1005 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) 1006 hdr_len = 12; 1007 for (i = 0; i < hdr_len/4; i ++) 1008 FWOHCI_DMA_WRITE(ld[i], ld[i]); 1009 #endif 1010 1011 again: 1012 db_tr->dbcnt = 2; 1013 db = &db_tr->db[db_tr->dbcnt]; 1014 if (xfer->send.pay_len > 0) { 1015 int err; 1016 /* handle payload */ 1017 if (xfer->mbuf == NULL) { 1018 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map, 1019 &xfer->send.payload[0], xfer->send.pay_len, 1020 fwohci_execute_db, db_tr, 1021 BUS_DMA_WAITOK); 1022 } else { 1023 /* XXX we can handle only 6 (=8-2) mbuf chains */ 1024 err = fw_bus_dmamap_load_mbuf(dbch->dmat, 1025 db_tr->dma_map, xfer->mbuf, 1026 fwohci_execute_db2, db_tr, 1027 BUS_DMA_WAITOK); 1028 if (err == EFBIG) { 1029 struct mbuf *m0; 1030 1031 if (firewire_debug) 1032 device_printf(sc->fc.dev, "EFBIG.\n"); 1033 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1034 if (m0 != NULL) { 1035 m_copydata(xfer->mbuf, 0, 1036 xfer->mbuf->m_pkthdr.len, 1037 mtod(m0, caddr_t)); 1038 m0->m_len = m0->m_pkthdr.len = 1039 xfer->mbuf->m_pkthdr.len; 1040 m_freem(xfer->mbuf); 1041 xfer->mbuf = m0; 1042 goto again; 1043 } 1044 device_printf(sc->fc.dev, "m_getcl failed.\n"); 1045 } 1046 } 1047 if (err) 1048 printf("dmamap_load: err=%d\n", err); 1049 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 1050 BUS_DMASYNC_PREWRITE); 1051 #if 0 /* OHCI_OUTPUT_MODE == 0 */ 1052 for (i = 2; i < db_tr->dbcnt; i++) 1053 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, 1054 OHCI_OUTPUT_MORE); 1055 #endif 1056 } 1057 if (maxdesc < db_tr->dbcnt) { 1058 maxdesc = db_tr->dbcnt; 1059 if (firewire_debug) 1060 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 1061 } 1062 /* last db */ 1063 LAST_DB(db_tr, db); 1064 FWOHCI_DMA_SET(db->db.desc.cmd, 1065 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1066 FWOHCI_DMA_WRITE(db->db.desc.depend, 1067 STAILQ_NEXT(db_tr, link)->bus_addr); 1068 1069 if(fsegment == -1 ) 1070 fsegment = db_tr->dbcnt; 1071 if (dbch->pdb_tr != NULL) { 1072 LAST_DB(dbch->pdb_tr, db); 1073 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); 1074 } 1075 dbch->pdb_tr = db_tr; 1076 db_tr = STAILQ_NEXT(db_tr, link); 1077 if(db_tr != dbch->bottom){ 1078 goto txloop; 1079 } else { 1080 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 1081 dbch->flags |= FWOHCI_DBCH_FULL; 1082 } 1083 kick: 1084 /* kick asy q */ 1085 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 1086 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 1087 } else { 1088 if (firewire_debug) 1089 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 1090 OREAD(sc, OHCI_DMACTL(off))); 1091 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); 1092 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1093 dbch->xferq.flag |= FWXFERQ_RUNNING; 1094 } 1095 CTR0(KTR_DEV, "start kick done"); 1096 CTR0(KTR_DEV, "start kick done2"); 1097 1098 dbch->top = db_tr; 1099 splx(s); 1100 return; 1101 } 1102 1103 static void 1104 fwohci_start_atq(struct firewire_comm *fc) 1105 { 1106 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1107 fwohci_start( sc, &(sc->atrq)); 1108 return; 1109 } 1110 1111 static void 1112 fwohci_start_ats(struct firewire_comm *fc) 1113 { 1114 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1115 fwohci_start( sc, &(sc->atrs)); 1116 return; 1117 } 1118 1119 void 1120 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1121 { 1122 int s, ch, err = 0; 1123 struct fwohcidb_tr *tr; 1124 struct fwohcidb *db; 1125 struct fw_xfer *xfer; 1126 uint32_t off; 1127 u_int stat, status; 1128 int packets; 1129 struct firewire_comm *fc = (struct firewire_comm *)sc; 1130 1131 if(&sc->atrq == dbch){ 1132 off = OHCI_ATQOFF; 1133 ch = ATRQ_CH; 1134 }else if(&sc->atrs == dbch){ 1135 off = OHCI_ATSOFF; 1136 ch = ATRS_CH; 1137 }else{ 1138 return; 1139 } 1140 s = splfw(); 1141 tr = dbch->bottom; 1142 packets = 0; 1143 while(dbch->xferq.queued > 0){ 1144 LAST_DB(tr, db); 1145 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; 1146 if(!(status & OHCI_CNTL_DMA_ACTIVE)){ 1147 if (fc->status != FWBUSRESET) 1148 /* maybe out of order?? */ 1149 goto out; 1150 } 1151 if (tr->xfer->send.pay_len > 0) { 1152 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map, 1153 BUS_DMASYNC_POSTWRITE); 1154 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map); 1155 } 1156 #if 1 1157 if (firewire_debug > 1) 1158 dump_db(sc, ch); 1159 #endif 1160 if(status & OHCI_CNTL_DMA_DEAD) { 1161 /* Stop DMA */ 1162 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1163 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1164 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1165 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1166 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1167 } 1168 stat = status & FWOHCIEV_MASK; 1169 switch(stat){ 1170 case FWOHCIEV_ACKPEND: 1171 CTR0(KTR_DEV, "txd: ack pending"); 1172 /* fall through */ 1173 case FWOHCIEV_ACKCOMPL: 1174 err = 0; 1175 break; 1176 case FWOHCIEV_ACKBSA: 1177 case FWOHCIEV_ACKBSB: 1178 case FWOHCIEV_ACKBSX: 1179 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1180 err = EBUSY; 1181 break; 1182 case FWOHCIEV_FLUSHED: 1183 case FWOHCIEV_ACKTARD: 1184 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1185 err = EAGAIN; 1186 break; 1187 case FWOHCIEV_MISSACK: 1188 case FWOHCIEV_UNDRRUN: 1189 case FWOHCIEV_OVRRUN: 1190 case FWOHCIEV_DESCERR: 1191 case FWOHCIEV_DTRDERR: 1192 case FWOHCIEV_TIMEOUT: 1193 case FWOHCIEV_TCODERR: 1194 case FWOHCIEV_UNKNOWN: 1195 case FWOHCIEV_ACKDERR: 1196 case FWOHCIEV_ACKTERR: 1197 default: 1198 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1199 stat, fwohcicode[stat]); 1200 err = EINVAL; 1201 break; 1202 } 1203 if (tr->xfer != NULL) { 1204 xfer = tr->xfer; 1205 CTR0(KTR_DEV, "txd"); 1206 if (xfer->state == FWXF_RCVD) { 1207 #if 0 1208 if (firewire_debug) 1209 printf("already rcvd\n"); 1210 #endif 1211 fw_xfer_done(xfer); 1212 } else { 1213 xfer->state = FWXF_SENT; 1214 if (err == EBUSY && fc->status != FWBUSRESET) { 1215 xfer->state = FWXF_BUSY; 1216 xfer->resp = err; 1217 xfer->recv.pay_len = 0; 1218 fw_xfer_done(xfer); 1219 } else if (stat != FWOHCIEV_ACKPEND) { 1220 if (stat != FWOHCIEV_ACKCOMPL) 1221 xfer->state = FWXF_SENTERR; 1222 xfer->resp = err; 1223 xfer->recv.pay_len = 0; 1224 fw_xfer_done(xfer); 1225 } 1226 } 1227 /* 1228 * The watchdog timer takes care of split 1229 * transcation timeout for ACKPEND case. 1230 */ 1231 } else { 1232 printf("this shouldn't happen\n"); 1233 } 1234 dbch->xferq.queued --; 1235 tr->xfer = NULL; 1236 1237 packets ++; 1238 tr = STAILQ_NEXT(tr, link); 1239 dbch->bottom = tr; 1240 if (dbch->bottom == dbch->top) { 1241 /* we reaches the end of context program */ 1242 if (firewire_debug && dbch->xferq.queued > 0) 1243 printf("queued > 0\n"); 1244 break; 1245 } 1246 } 1247 out: 1248 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1249 printf("make free slot\n"); 1250 dbch->flags &= ~FWOHCI_DBCH_FULL; 1251 fwohci_start(sc, dbch); 1252 } 1253 splx(s); 1254 } 1255 1256 static void 1257 fwohci_db_free(struct fwohci_dbch *dbch) 1258 { 1259 struct fwohcidb_tr *db_tr; 1260 int idb; 1261 1262 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1263 return; 1264 1265 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; 1266 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1267 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && 1268 db_tr->buf != NULL) { 1269 fwdma_free_size(dbch->dmat, db_tr->dma_map, 1270 db_tr->buf, dbch->xferq.psize); 1271 db_tr->buf = NULL; 1272 } else if (db_tr->dma_map != NULL) 1273 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); 1274 } 1275 dbch->ndb = 0; 1276 db_tr = STAILQ_FIRST(&dbch->db_trq); 1277 fwdma_free_multiseg(dbch->am); 1278 free(db_tr, M_FW); 1279 STAILQ_INIT(&dbch->db_trq); 1280 dbch->flags &= ~FWOHCI_DBCH_INIT; 1281 } 1282 1283 static void 1284 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1285 { 1286 int idb; 1287 struct fwohcidb_tr *db_tr; 1288 1289 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1290 goto out; 1291 1292 /* create dma_tag for buffers */ 1293 #define MAX_REQCOUNT 0xffff 1294 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat, 1295 /*alignment*/ 1, /*boundary*/ 0, 1296 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 1297 /*highaddr*/ BUS_SPACE_MAXADDR, 1298 /*filter*/NULL, /*filterarg*/NULL, 1299 /*maxsize*/ dbch->xferq.psize, 1300 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, 1301 /*maxsegsz*/ MAX_REQCOUNT, 1302 /*flags*/ 0, 1303 /*lockfunc*/busdma_lock_mutex, 1304 /*lockarg*/&Giant, 1305 &dbch->dmat)) 1306 return; 1307 1308 /* allocate DB entries and attach one to each DMA channels */ 1309 /* DB entry must start at 16 bytes bounary. */ 1310 STAILQ_INIT(&dbch->db_trq); 1311 db_tr = (struct fwohcidb_tr *) 1312 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1313 M_FW, M_WAITOK | M_ZERO); 1314 if(db_tr == NULL){ 1315 printf("fwohci_db_init: malloc(1) failed\n"); 1316 return; 1317 } 1318 1319 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) 1320 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), 1321 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1322 if (dbch->am == NULL) { 1323 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); 1324 free(db_tr, M_FW); 1325 return; 1326 } 1327 /* Attach DB to DMA ch. */ 1328 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1329 db_tr->dbcnt = 0; 1330 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); 1331 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); 1332 /* create dmamap for buffers */ 1333 /* XXX do we need 4bytes alignment tag? */ 1334 /* XXX don't alloc dma_map for AR */ 1335 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { 1336 printf("fw_bus_dmamap_create failed\n"); 1337 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ 1338 fwohci_db_free(dbch); 1339 return; 1340 } 1341 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1342 if (dbch->xferq.flag & FWXFERQ_EXTBUF) { 1343 if (idb % dbch->xferq.bnpacket == 0) 1344 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1345 ].start = (caddr_t)db_tr; 1346 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1347 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1348 ].end = (caddr_t)db_tr; 1349 } 1350 db_tr++; 1351 } 1352 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1353 = STAILQ_FIRST(&dbch->db_trq); 1354 out: 1355 dbch->xferq.queued = 0; 1356 dbch->pdb_tr = NULL; 1357 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1358 dbch->bottom = dbch->top; 1359 dbch->flags = FWOHCI_DBCH_INIT; 1360 } 1361 1362 static int 1363 fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1364 { 1365 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1366 int sleepch; 1367 1368 OWRITE(sc, OHCI_ITCTLCLR(dmach), 1369 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); 1370 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1371 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1372 /* XXX we cannot free buffers until the DMA really stops */ 1373 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); 1374 fwohci_db_free(&sc->it[dmach]); 1375 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1376 return 0; 1377 } 1378 1379 static int 1380 fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1381 { 1382 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1383 int sleepch; 1384 1385 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1386 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1387 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1388 /* XXX we cannot free buffers until the DMA really stops */ 1389 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); 1390 fwohci_db_free(&sc->ir[dmach]); 1391 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1392 return 0; 1393 } 1394 1395 #if BYTE_ORDER == BIG_ENDIAN 1396 static void 1397 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld) 1398 { 1399 qld[0] = FWOHCI_DMA_READ(qld[0]); 1400 return; 1401 } 1402 #endif 1403 1404 static int 1405 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1406 { 1407 int err = 0; 1408 int idb, z, i, dmach = 0, ldesc; 1409 uint32_t off = 0; 1410 struct fwohcidb_tr *db_tr; 1411 struct fwohcidb *db; 1412 1413 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1414 err = EINVAL; 1415 return err; 1416 } 1417 z = dbch->ndesc; 1418 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1419 if( &sc->it[dmach] == dbch){ 1420 off = OHCI_ITOFF(dmach); 1421 break; 1422 } 1423 } 1424 if(off == 0){ 1425 err = EINVAL; 1426 return err; 1427 } 1428 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1429 return err; 1430 dbch->xferq.flag |= FWXFERQ_RUNNING; 1431 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1432 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1433 } 1434 db_tr = dbch->top; 1435 for (idb = 0; idb < dbch->ndb; idb ++) { 1436 fwohci_add_tx_buf(dbch, db_tr, idb); 1437 if(STAILQ_NEXT(db_tr, link) == NULL){ 1438 break; 1439 } 1440 db = db_tr->db; 1441 ldesc = db_tr->dbcnt - 1; 1442 FWOHCI_DMA_WRITE(db[0].db.desc.depend, 1443 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1444 db[ldesc].db.desc.depend = db[0].db.desc.depend; 1445 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1446 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1447 FWOHCI_DMA_SET( 1448 db[ldesc].db.desc.cmd, 1449 OHCI_INTERRUPT_ALWAYS); 1450 /* OHCI 1.1 and above */ 1451 FWOHCI_DMA_SET( 1452 db[0].db.desc.cmd, 1453 OHCI_INTERRUPT_ALWAYS); 1454 } 1455 } 1456 db_tr = STAILQ_NEXT(db_tr, link); 1457 } 1458 FWOHCI_DMA_CLEAR( 1459 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); 1460 return err; 1461 } 1462 1463 static int 1464 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1465 { 1466 int err = 0; 1467 int idb, z, i, dmach = 0, ldesc; 1468 uint32_t off = 0; 1469 struct fwohcidb_tr *db_tr; 1470 struct fwohcidb *db; 1471 1472 z = dbch->ndesc; 1473 if(&sc->arrq == dbch){ 1474 off = OHCI_ARQOFF; 1475 }else if(&sc->arrs == dbch){ 1476 off = OHCI_ARSOFF; 1477 }else{ 1478 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1479 if( &sc->ir[dmach] == dbch){ 1480 off = OHCI_IROFF(dmach); 1481 break; 1482 } 1483 } 1484 } 1485 if(off == 0){ 1486 err = EINVAL; 1487 return err; 1488 } 1489 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1490 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1491 return err; 1492 }else{ 1493 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1494 err = EBUSY; 1495 return err; 1496 } 1497 } 1498 dbch->xferq.flag |= FWXFERQ_RUNNING; 1499 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1500 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1501 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1502 } 1503 db_tr = dbch->top; 1504 for (idb = 0; idb < dbch->ndb; idb ++) { 1505 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); 1506 if (STAILQ_NEXT(db_tr, link) == NULL) 1507 break; 1508 db = db_tr->db; 1509 ldesc = db_tr->dbcnt - 1; 1510 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, 1511 STAILQ_NEXT(db_tr, link)->bus_addr | z); 1512 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1513 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1514 FWOHCI_DMA_SET( 1515 db[ldesc].db.desc.cmd, 1516 OHCI_INTERRUPT_ALWAYS); 1517 FWOHCI_DMA_CLEAR( 1518 db[ldesc].db.desc.depend, 1519 0xf); 1520 } 1521 } 1522 db_tr = STAILQ_NEXT(db_tr, link); 1523 } 1524 FWOHCI_DMA_CLEAR( 1525 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); 1526 dbch->buf_offset = 0; 1527 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1528 return err; 1529 }else{ 1530 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); 1531 } 1532 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1533 return err; 1534 } 1535 1536 static int 1537 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) 1538 { 1539 int sec, cycle, cycle_match; 1540 1541 cycle = cycle_now & 0x1fff; 1542 sec = cycle_now >> 13; 1543 #define CYCLE_MOD 0x10 1544 #if 1 1545 #define CYCLE_DELAY 8 /* min delay to start DMA */ 1546 #else 1547 #define CYCLE_DELAY 7000 /* min delay to start DMA */ 1548 #endif 1549 cycle = cycle + CYCLE_DELAY; 1550 if (cycle >= 8000) { 1551 sec ++; 1552 cycle -= 8000; 1553 } 1554 cycle = roundup2(cycle, CYCLE_MOD); 1555 if (cycle >= 8000) { 1556 sec ++; 1557 if (cycle == 8000) 1558 cycle = 0; 1559 else 1560 cycle = CYCLE_MOD; 1561 } 1562 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1563 1564 return(cycle_match); 1565 } 1566 1567 static int 1568 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1569 { 1570 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1571 int err = 0; 1572 unsigned short tag, ich; 1573 struct fwohci_dbch *dbch; 1574 int cycle_match, cycle_now, s, ldesc; 1575 uint32_t stat; 1576 struct fw_bulkxfer *first, *chunk, *prev; 1577 struct fw_xferq *it; 1578 1579 dbch = &sc->it[dmach]; 1580 it = &dbch->xferq; 1581 1582 tag = (it->flag >> 6) & 3; 1583 ich = it->flag & 0x3f; 1584 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1585 dbch->ndb = it->bnpacket * it->bnchunk; 1586 dbch->ndesc = 3; 1587 fwohci_db_init(sc, dbch); 1588 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1589 return ENOMEM; 1590 err = fwohci_tx_enable(sc, dbch); 1591 } 1592 if(err) 1593 return err; 1594 1595 ldesc = dbch->ndesc - 1; 1596 s = splfw(); 1597 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1598 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1599 struct fwohcidb *db; 1600 1601 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, 1602 BUS_DMASYNC_PREWRITE); 1603 fwohci_txbufdb(sc, dmach, chunk); 1604 if (prev != NULL) { 1605 db = ((struct fwohcidb_tr *)(prev->end))->db; 1606 #if 0 /* XXX necessary? */ 1607 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, 1608 OHCI_BRANCH_ALWAYS); 1609 #endif 1610 #if 0 /* if bulkxfer->npacket changes */ 1611 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1612 ((struct fwohcidb_tr *) 1613 (chunk->start))->bus_addr | dbch->ndesc; 1614 #else 1615 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 1616 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1617 #endif 1618 } 1619 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1620 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1621 prev = chunk; 1622 } 1623 splx(s); 1624 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1625 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) 1626 printf("stat 0x%x\n", stat); 1627 1628 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1629 return 0; 1630 1631 #if 0 1632 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1633 #endif 1634 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1635 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1636 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1637 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1638 1639 first = STAILQ_FIRST(&it->stdma); 1640 OWRITE(sc, OHCI_ITCMD(dmach), 1641 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); 1642 if (firewire_debug > 1) { 1643 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1644 #if 1 1645 dump_dma(sc, ITX_CH + dmach); 1646 #endif 1647 } 1648 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1649 #if 1 1650 /* Don't start until all chunks are buffered */ 1651 if (STAILQ_FIRST(&it->stfree) != NULL) 1652 goto out; 1653 #endif 1654 #if 1 1655 /* Clear cycle match counter bits */ 1656 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1657 1658 /* 2bit second + 13bit cycle */ 1659 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1660 cycle_match = fwohci_next_cycle(fc, cycle_now); 1661 1662 OWRITE(sc, OHCI_ITCTL(dmach), 1663 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1664 | OHCI_CNTL_DMA_RUN); 1665 #else 1666 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1667 #endif 1668 if (firewire_debug > 1) { 1669 printf("cycle_match: 0x%04x->0x%04x\n", 1670 cycle_now, cycle_match); 1671 dump_dma(sc, ITX_CH + dmach); 1672 dump_db(sc, ITX_CH + dmach); 1673 } 1674 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1675 device_printf(sc->fc.dev, 1676 "IT DMA underrun (0x%08x)\n", stat); 1677 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1678 } 1679 out: 1680 return err; 1681 } 1682 1683 static int 1684 fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1685 { 1686 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1687 int err = 0, s, ldesc; 1688 unsigned short tag, ich; 1689 uint32_t stat; 1690 struct fwohci_dbch *dbch; 1691 struct fwohcidb_tr *db_tr; 1692 struct fw_bulkxfer *first, *prev, *chunk; 1693 struct fw_xferq *ir; 1694 1695 dbch = &sc->ir[dmach]; 1696 ir = &dbch->xferq; 1697 1698 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1699 tag = (ir->flag >> 6) & 3; 1700 ich = ir->flag & 0x3f; 1701 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1702 1703 ir->queued = 0; 1704 dbch->ndb = ir->bnpacket * ir->bnchunk; 1705 dbch->ndesc = 2; 1706 fwohci_db_init(sc, dbch); 1707 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1708 return ENOMEM; 1709 err = fwohci_rx_enable(sc, dbch); 1710 } 1711 if(err) 1712 return err; 1713 1714 first = STAILQ_FIRST(&ir->stfree); 1715 if (first == NULL) { 1716 device_printf(fc->dev, "IR DMA no free chunk\n"); 1717 return 0; 1718 } 1719 1720 ldesc = dbch->ndesc - 1; 1721 s = splfw(); 1722 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1723 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1724 struct fwohcidb *db; 1725 1726 #if 1 /* XXX for if_fwe */ 1727 if (chunk->mbuf != NULL) { 1728 db_tr = (struct fwohcidb_tr *)(chunk->start); 1729 db_tr->dbcnt = 1; 1730 err = fw_bus_dmamap_load_mbuf( 1731 dbch->dmat, db_tr->dma_map, 1732 chunk->mbuf, fwohci_execute_db2, db_tr, 1733 BUS_DMA_WAITOK); 1734 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, 1735 OHCI_UPDATE | OHCI_INPUT_LAST | 1736 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); 1737 } 1738 #endif 1739 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1740 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); 1741 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); 1742 if (prev != NULL) { 1743 db = ((struct fwohcidb_tr *)(prev->end))->db; 1744 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); 1745 } 1746 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1747 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1748 prev = chunk; 1749 } 1750 splx(s); 1751 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1752 if (stat & OHCI_CNTL_DMA_ACTIVE) 1753 return 0; 1754 if (stat & OHCI_CNTL_DMA_RUN) { 1755 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1756 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1757 } 1758 1759 if (firewire_debug) 1760 printf("start IR DMA 0x%x\n", stat); 1761 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1762 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1763 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1764 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1765 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1766 OWRITE(sc, OHCI_IRCMD(dmach), 1767 ((struct fwohcidb_tr *)(first->start))->bus_addr 1768 | dbch->ndesc); 1769 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1770 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1771 #if 0 1772 dump_db(sc, IRX_CH + dmach); 1773 #endif 1774 return err; 1775 } 1776 1777 FWOHCI_STOP() 1778 { 1779 FWOHCI_STOP_START; 1780 u_int i; 1781 1782 /* Now stopping all DMA channel */ 1783 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1784 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1785 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1786 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1787 1788 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1789 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1790 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1791 } 1792 1793 /* FLUSH FIFO and reset Transmitter/Reciever */ 1794 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1795 1796 /* Stop interrupt */ 1797 OWRITE(sc, FWOHCI_INTMASKCLR, 1798 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1799 | OHCI_INT_PHY_INT 1800 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1801 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1802 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1803 | OHCI_INT_PHY_BUS_R); 1804 1805 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) 1806 fw_drain_txq(&sc->fc); 1807 1808 /* XXX Link down? Bus reset? */ 1809 FWOHCI_STOP_RETURN(0); 1810 } 1811 1812 #if defined(__NetBSD__) 1813 static void 1814 fwohci_power(int why, void *arg) 1815 { 1816 struct fwohci_softc *sc = arg; 1817 int s; 1818 1819 s = splbio(); 1820 switch (why) { 1821 case PWR_SUSPEND: 1822 case PWR_STANDBY: 1823 fwohci_stop(arg); 1824 break; 1825 case PWR_RESUME: 1826 fwohci_resume(sc, sc->fc.dev); 1827 break; 1828 case PWR_SOFTSUSPEND: 1829 case PWR_SOFTSTANDBY: 1830 case PWR_SOFTRESUME: 1831 break; 1832 } 1833 splx(s); 1834 } 1835 #endif 1836 1837 int 1838 fwohci_resume(struct fwohci_softc *sc, device_t dev) 1839 { 1840 int i; 1841 struct fw_xferq *ir; 1842 struct fw_bulkxfer *chunk; 1843 1844 fwohci_reset(sc, dev); 1845 /* XXX resume isochronous receive automatically. (how about TX?) */ 1846 for(i = 0; i < sc->fc.nisodma; i ++) { 1847 ir = &sc->ir[i].xferq; 1848 if((ir->flag & FWXFERQ_RUNNING) != 0) { 1849 device_printf(sc->fc.dev, 1850 "resume iso receive ch: %d\n", i); 1851 ir->flag &= ~FWXFERQ_RUNNING; 1852 /* requeue stdma to stfree */ 1853 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 1854 STAILQ_REMOVE_HEAD(&ir->stdma, link); 1855 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); 1856 } 1857 sc->fc.irx_enable(&sc->fc, i); 1858 } 1859 } 1860 1861 #if defined(__FreeBSD__) 1862 bus_generic_resume(dev); 1863 #endif 1864 sc->fc.ibr(&sc->fc); 1865 return 0; 1866 } 1867 1868 #define ACK_ALL 1869 static void 1870 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 1871 { 1872 uint32_t irstat, itstat; 1873 u_int i; 1874 struct firewire_comm *fc = (struct firewire_comm *)sc; 1875 1876 CTR0(KTR_DEV, "fwohci_intr_body"); 1877 #ifdef OHCI_DEBUG 1878 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1879 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1880 stat & OHCI_INT_EN ? "DMA_EN ":"", 1881 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1882 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1883 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1884 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1885 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1886 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1887 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1888 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1889 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1890 stat & OHCI_INT_PHY_SID ? "SID ":"", 1891 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1892 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1893 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1894 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1895 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1896 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1897 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1898 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1899 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1900 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1901 stat, OREAD(sc, FWOHCI_INTMASK) 1902 ); 1903 #endif 1904 /* Bus reset */ 1905 if(stat & OHCI_INT_PHY_BUS_R ){ 1906 if (fc->status == FWBUSRESET) 1907 goto busresetout; 1908 /* Disable bus reset interrupt until sid recv. */ 1909 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1910 1911 device_printf(fc->dev, "BUS reset\n"); 1912 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1913 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1914 1915 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1916 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1917 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1918 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1919 1920 #ifndef ACK_ALL 1921 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1922 #endif 1923 fw_busreset(fc); 1924 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 1925 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 1926 } 1927 busresetout: 1928 if((stat & OHCI_INT_DMA_IR )){ 1929 #ifndef ACK_ALL 1930 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1931 #endif 1932 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1933 irstat = sc->irstat; 1934 sc->irstat = 0; 1935 #else 1936 irstat = atomic_readandclear_int(&sc->irstat); 1937 #endif 1938 for(i = 0; i < fc->nisodma ; i++){ 1939 struct fwohci_dbch *dbch; 1940 1941 if((irstat & (1 << i)) != 0){ 1942 dbch = &sc->ir[i]; 1943 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1944 device_printf(sc->fc.dev, 1945 "dma(%d) not active\n", i); 1946 continue; 1947 } 1948 fwohci_rbuf_update(sc, i); 1949 } 1950 } 1951 } 1952 if((stat & OHCI_INT_DMA_IT )){ 1953 #ifndef ACK_ALL 1954 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1955 #endif 1956 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__) 1957 itstat = sc->itstat; 1958 sc->itstat = 0; 1959 #else 1960 itstat = atomic_readandclear_int(&sc->itstat); 1961 #endif 1962 for(i = 0; i < fc->nisodma ; i++){ 1963 if((itstat & (1 << i)) != 0){ 1964 fwohci_tbuf_update(sc, i); 1965 } 1966 } 1967 } 1968 if((stat & OHCI_INT_DMA_PRRS )){ 1969 #ifndef ACK_ALL 1970 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1971 #endif 1972 #if 0 1973 dump_dma(sc, ARRS_CH); 1974 dump_db(sc, ARRS_CH); 1975 #endif 1976 fwohci_arcv(sc, &sc->arrs, count); 1977 } 1978 if((stat & OHCI_INT_DMA_PRRQ )){ 1979 #ifndef ACK_ALL 1980 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1981 #endif 1982 #if 0 1983 dump_dma(sc, ARRQ_CH); 1984 dump_db(sc, ARRQ_CH); 1985 #endif 1986 fwohci_arcv(sc, &sc->arrq, count); 1987 } 1988 if (stat & OHCI_INT_CYC_LOST) { 1989 if (sc->cycle_lost >= 0) 1990 sc->cycle_lost ++; 1991 if (sc->cycle_lost > 10) { 1992 sc->cycle_lost = -1; 1993 #if 0 1994 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER); 1995 #endif 1996 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1997 device_printf(fc->dev, "too many cycle lost, " 1998 "no cycle master presents?\n"); 1999 } 2000 } 2001 if(stat & OHCI_INT_PHY_SID){ 2002 uint32_t *buf, node_id; 2003 int plen; 2004 2005 #ifndef ACK_ALL 2006 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 2007 #endif 2008 /* Enable bus reset interrupt */ 2009 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 2010 /* Allow async. request to us */ 2011 OWRITE(sc, OHCI_AREQHI, 1 << 31); 2012 /* XXX insecure ?? */ 2013 /* allow from all nodes */ 2014 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 2015 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 2016 /* 0 to 4GB regison */ 2017 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 2018 /* Set ATRetries register */ 2019 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 2020 /* 2021 ** Checking whether the node is root or not. If root, turn on 2022 ** cycle master. 2023 */ 2024 node_id = OREAD(sc, FWOHCI_NODEID); 2025 plen = OREAD(sc, OHCI_SID_CNT); 2026 2027 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 2028 node_id, (plen >> 16) & 0xff); 2029 if (!(node_id & OHCI_NODE_VALID)) { 2030 printf("Bus reset failure\n"); 2031 goto sidout; 2032 } 2033 2034 /* cycle timer */ 2035 sc->cycle_lost = 0; 2036 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST); 2037 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) { 2038 printf("CYCLEMASTER mode\n"); 2039 OWRITE(sc, OHCI_LNKCTL, 2040 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 2041 } else { 2042 printf("non CYCLEMASTER mode\n"); 2043 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 2044 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 2045 } 2046 2047 fc->nodeid = node_id & 0x3f; 2048 2049 if (plen & OHCI_SID_ERR) { 2050 device_printf(fc->dev, "SID Error\n"); 2051 goto sidout; 2052 } 2053 plen &= OHCI_SID_CNT_MASK; 2054 if (plen < 4 || plen > OHCI_SIDSIZE) { 2055 device_printf(fc->dev, "invalid SID len = %d\n", plen); 2056 goto sidout; 2057 } 2058 plen -= 4; /* chop control info */ 2059 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 2060 if (buf == NULL) { 2061 device_printf(fc->dev, "malloc failed\n"); 2062 goto sidout; 2063 } 2064 for (i = 0; i < plen / 4; i ++) 2065 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); 2066 #if defined(__NetBSD__) && defined(macppc) 2067 /* XXX required as bootdisk for macppc. */ 2068 delay(500000); 2069 #endif 2070 #if 1 /* XXX needed?? */ 2071 /* pending all pre-bus_reset packets */ 2072 fwohci_txd(sc, &sc->atrq); 2073 fwohci_txd(sc, &sc->atrs); 2074 fwohci_arcv(sc, &sc->arrs, -1); 2075 fwohci_arcv(sc, &sc->arrq, -1); 2076 fw_drain_txq(fc); 2077 #endif 2078 fw_sidrcv(fc, buf, plen); 2079 free(buf, M_FW); 2080 } 2081 sidout: 2082 if((stat & OHCI_INT_DMA_ATRQ )){ 2083 #ifndef ACK_ALL 2084 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 2085 #endif 2086 fwohci_txd(sc, &(sc->atrq)); 2087 } 2088 if((stat & OHCI_INT_DMA_ATRS )){ 2089 #ifndef ACK_ALL 2090 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 2091 #endif 2092 fwohci_txd(sc, &(sc->atrs)); 2093 } 2094 if((stat & OHCI_INT_PW_ERR )){ 2095 #ifndef ACK_ALL 2096 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 2097 #endif 2098 device_printf(fc->dev, "posted write error\n"); 2099 } 2100 if((stat & OHCI_INT_ERR )){ 2101 #ifndef ACK_ALL 2102 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 2103 #endif 2104 device_printf(fc->dev, "unrecoverable error\n"); 2105 } 2106 if((stat & OHCI_INT_PHY_INT)) { 2107 #ifndef ACK_ALL 2108 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 2109 #endif 2110 device_printf(fc->dev, "phy int\n"); 2111 } 2112 2113 CTR0(KTR_DEV, "fwohci_intr_body done"); 2114 return; 2115 } 2116 2117 #if FWOHCI_TASKQUEUE 2118 static void 2119 fwohci_complete(void *arg, int pending) 2120 { 2121 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2122 uint32_t stat; 2123 2124 again: 2125 stat = atomic_readandclear_int(&sc->intstat); 2126 if (stat) { 2127 FW_LOCK; 2128 fwohci_intr_body(sc, stat, -1); 2129 FW_UNLOCK; 2130 } else 2131 return; 2132 goto again; 2133 } 2134 #endif 2135 2136 static uint32_t 2137 fwochi_check_stat(struct fwohci_softc *sc) 2138 { 2139 uint32_t stat, irstat, itstat; 2140 2141 stat = OREAD(sc, FWOHCI_INTSTAT); 2142 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat); 2143 if (stat == 0xffffffff) { 2144 device_printf(sc->fc.dev, 2145 "device physically ejected?\n"); 2146 return(stat); 2147 } 2148 #ifdef ACK_ALL 2149 if (stat) 2150 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2151 #endif 2152 if (stat & OHCI_INT_DMA_IR) { 2153 irstat = OREAD(sc, OHCI_IR_STAT); 2154 OWRITE(sc, OHCI_IR_STATCLR, irstat); 2155 atomic_set_int(&sc->irstat, irstat); 2156 } 2157 if (stat & OHCI_INT_DMA_IT) { 2158 itstat = OREAD(sc, OHCI_IT_STAT); 2159 OWRITE(sc, OHCI_IT_STATCLR, itstat); 2160 atomic_set_int(&sc->itstat, itstat); 2161 } 2162 return(stat); 2163 } 2164 2165 FW_INTR(fwohci) 2166 { 2167 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 2168 uint32_t stat; 2169 #if !FWOHCI_TASKQUEUE 2170 uint32_t bus_reset = 0; 2171 #endif 2172 2173 if (!(sc->intmask & OHCI_INT_EN)) { 2174 /* polling mode */ 2175 FW_INTR_RETURN(0); 2176 } 2177 2178 #if !FWOHCI_TASKQUEUE 2179 again: 2180 #endif 2181 CTR0(KTR_DEV, "fwohci_intr"); 2182 stat = fwochi_check_stat(sc); 2183 if (stat == 0 || stat == 0xffffffff) 2184 FW_INTR_RETURN(1); 2185 #if FWOHCI_TASKQUEUE 2186 atomic_set_int(&sc->intstat, stat); 2187 /* XXX mask bus reset intr. during bus reset phase */ 2188 if (stat) 2189 #if 1 2190 taskqueue_enqueue_fast(taskqueue_fast, 2191 &sc->fwohci_task_complete); 2192 #else 2193 taskqueue_enqueue(taskqueue_swi, 2194 &sc->fwohci_task_complete); 2195 #endif 2196 #else 2197 /* We cannot clear bus reset event during bus reset phase */ 2198 if ((stat & ~bus_reset) == 0) 2199 FW_INTR_RETURN(1); 2200 bus_reset = stat & OHCI_INT_PHY_BUS_R; 2201 fwohci_intr_body(sc, stat, -1); 2202 goto again; 2203 #endif 2204 CTR0(KTR_DEV, "fwohci_intr end"); 2205 } 2206 2207 void 2208 fwohci_poll(struct firewire_comm *fc, int quick, int count) 2209 { 2210 int s; 2211 uint32_t stat; 2212 struct fwohci_softc *sc; 2213 2214 2215 sc = (struct fwohci_softc *)fc; 2216 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 2217 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 2218 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 2219 #if 0 2220 if (!quick) { 2221 #else 2222 if (1) { 2223 #endif 2224 stat = fwochi_check_stat(sc); 2225 if (stat == 0 || stat == 0xffffffff) 2226 return; 2227 } 2228 s = splfw(); 2229 fwohci_intr_body(sc, stat, count); 2230 splx(s); 2231 } 2232 2233 static void 2234 fwohci_set_intr(struct firewire_comm *fc, int enable) 2235 { 2236 struct fwohci_softc *sc; 2237 2238 sc = (struct fwohci_softc *)fc; 2239 if (firewire_debug) 2240 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2241 if (enable) { 2242 sc->intmask |= OHCI_INT_EN; 2243 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2244 } else { 2245 sc->intmask &= ~OHCI_INT_EN; 2246 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2247 } 2248 } 2249 2250 static void 2251 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2252 { 2253 struct firewire_comm *fc = &sc->fc; 2254 struct fwohcidb *db; 2255 struct fw_bulkxfer *chunk; 2256 struct fw_xferq *it; 2257 uint32_t stat, count; 2258 int s, w=0, ldesc; 2259 2260 it = fc->it[dmach]; 2261 ldesc = sc->it[dmach].ndesc - 1; 2262 s = splfw(); /* unnecessary ? */ 2263 if (firewire_debug) 2264 dump_db(sc, ITX_CH + dmach); 2265 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2266 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2267 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2268 >> OHCI_STATUS_SHIFT; 2269 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2270 /* timestamp */ 2271 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) 2272 & OHCI_COUNT_MASK; 2273 if (stat == 0) 2274 break; 2275 STAILQ_REMOVE_HEAD(&it->stdma, link); 2276 switch (stat & FWOHCIEV_MASK){ 2277 case FWOHCIEV_ACKCOMPL: 2278 #if 0 2279 device_printf(fc->dev, "0x%08x\n", count); 2280 #endif 2281 break; 2282 default: 2283 device_printf(fc->dev, 2284 "Isochronous transmit err %02x(%s)\n", 2285 stat, fwohcicode[stat & 0x1f]); 2286 } 2287 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2288 w++; 2289 } 2290 splx(s); 2291 if (w) 2292 wakeup(it); 2293 } 2294 2295 static void 2296 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2297 { 2298 struct firewire_comm *fc = &sc->fc; 2299 struct fwohcidb_tr *db_tr; 2300 struct fw_bulkxfer *chunk; 2301 struct fw_xferq *ir; 2302 uint32_t stat; 2303 int s, w=0, ldesc; 2304 2305 ir = fc->ir[dmach]; 2306 ldesc = sc->ir[dmach].ndesc - 1; 2307 #if 0 2308 dump_db(sc, dmach); 2309 #endif 2310 s = splfw(); 2311 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2312 db_tr = (struct fwohcidb_tr *)chunk->end; 2313 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) 2314 >> OHCI_STATUS_SHIFT; 2315 if (stat == 0) 2316 break; 2317 2318 if (chunk->mbuf != NULL) { 2319 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, 2320 BUS_DMASYNC_POSTREAD); 2321 fw_bus_dmamap_unload( 2322 sc->ir[dmach].dmat, db_tr->dma_map); 2323 } else if (ir->buf != NULL) { 2324 fwdma_sync_multiseg(ir->buf, chunk->poffset, 2325 ir->bnpacket, BUS_DMASYNC_POSTREAD); 2326 } else { 2327 /* XXX */ 2328 printf("fwohci_rbuf_update: this shouldn't happend\n"); 2329 } 2330 2331 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2332 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2333 switch (stat & FWOHCIEV_MASK) { 2334 case FWOHCIEV_ACKCOMPL: 2335 chunk->resp = 0; 2336 break; 2337 default: 2338 chunk->resp = EINVAL; 2339 device_printf(fc->dev, 2340 "Isochronous receive err %02x(%s)\n", 2341 stat, fwohcicode[stat & 0x1f]); 2342 } 2343 w++; 2344 } 2345 splx(s); 2346 if (w) { 2347 if (ir->flag & FWXFERQ_HANDLER) 2348 ir->hand(ir); 2349 else 2350 wakeup(ir); 2351 } 2352 } 2353 2354 void 2355 dump_dma(struct fwohci_softc *sc, uint32_t ch) 2356 { 2357 uint32_t off, cntl, stat, cmd, match; 2358 2359 if(ch == 0){ 2360 off = OHCI_ATQOFF; 2361 }else if(ch == 1){ 2362 off = OHCI_ATSOFF; 2363 }else if(ch == 2){ 2364 off = OHCI_ARQOFF; 2365 }else if(ch == 3){ 2366 off = OHCI_ARSOFF; 2367 }else if(ch < IRX_CH){ 2368 off = OHCI_ITCTL(ch - ITX_CH); 2369 }else{ 2370 off = OHCI_IRCTL(ch - IRX_CH); 2371 } 2372 cntl = stat = OREAD(sc, off); 2373 cmd = OREAD(sc, off + 0xc); 2374 match = OREAD(sc, off + 0x10); 2375 2376 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", 2377 ch, 2378 cntl, 2379 cmd, 2380 match); 2381 stat &= 0xffff ; 2382 if (stat) { 2383 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2384 ch, 2385 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2386 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2387 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2388 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2389 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2390 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2391 fwohcicode[stat & 0x1f], 2392 stat & 0x1f 2393 ); 2394 }else{ 2395 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2396 } 2397 } 2398 2399 void 2400 dump_db(struct fwohci_softc *sc, uint32_t ch) 2401 { 2402 struct fwohci_dbch *dbch; 2403 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; 2404 struct fwohcidb *curr = NULL, *prev, *next = NULL; 2405 int idb, jdb; 2406 uint32_t cmd, off; 2407 if(ch == 0){ 2408 off = OHCI_ATQOFF; 2409 dbch = &sc->atrq; 2410 }else if(ch == 1){ 2411 off = OHCI_ATSOFF; 2412 dbch = &sc->atrs; 2413 }else if(ch == 2){ 2414 off = OHCI_ARQOFF; 2415 dbch = &sc->arrq; 2416 }else if(ch == 3){ 2417 off = OHCI_ARSOFF; 2418 dbch = &sc->arrs; 2419 }else if(ch < IRX_CH){ 2420 off = OHCI_ITCTL(ch - ITX_CH); 2421 dbch = &sc->it[ch - ITX_CH]; 2422 }else { 2423 off = OHCI_IRCTL(ch - IRX_CH); 2424 dbch = &sc->ir[ch - IRX_CH]; 2425 } 2426 cmd = OREAD(sc, off + 0xc); 2427 2428 if( dbch->ndb == 0 ){ 2429 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2430 return; 2431 } 2432 pp = dbch->top; 2433 prev = pp->db; 2434 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2435 cp = STAILQ_NEXT(pp, link); 2436 if(cp == NULL){ 2437 curr = NULL; 2438 goto outdb; 2439 } 2440 np = STAILQ_NEXT(cp, link); 2441 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2442 if ((cmd & 0xfffffff0) == cp->bus_addr) { 2443 curr = cp->db; 2444 if(np != NULL){ 2445 next = np->db; 2446 }else{ 2447 next = NULL; 2448 } 2449 goto outdb; 2450 } 2451 } 2452 pp = STAILQ_NEXT(pp, link); 2453 if(pp == NULL){ 2454 curr = NULL; 2455 goto outdb; 2456 } 2457 prev = pp->db; 2458 } 2459 outdb: 2460 if( curr != NULL){ 2461 #if 0 2462 printf("Prev DB %d\n", ch); 2463 print_db(pp, prev, ch, dbch->ndesc); 2464 #endif 2465 printf("Current DB %d\n", ch); 2466 print_db(cp, curr, ch, dbch->ndesc); 2467 #if 0 2468 printf("Next DB %d\n", ch); 2469 print_db(np, next, ch, dbch->ndesc); 2470 #endif 2471 }else{ 2472 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2473 } 2474 return; 2475 } 2476 2477 void 2478 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, 2479 uint32_t ch, uint32_t hogemax) 2480 { 2481 fwohcireg_t stat; 2482 int i, key; 2483 uint32_t cmd, res; 2484 2485 if(db == NULL){ 2486 printf("No Descriptor is found\n"); 2487 return; 2488 } 2489 2490 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2491 ch, 2492 "Current", 2493 "OP ", 2494 "KEY", 2495 "INT", 2496 "BR ", 2497 "len", 2498 "Addr", 2499 "Depend", 2500 "Stat", 2501 "Cnt"); 2502 for( i = 0 ; i <= hogemax ; i ++){ 2503 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); 2504 res = FWOHCI_DMA_READ(db[i].db.desc.res); 2505 key = cmd & OHCI_KEY_MASK; 2506 stat = res >> OHCI_STATUS_SHIFT; 2507 #if defined(__DragonFly__) || \ 2508 (defined(__FreeBSD__) && __FreeBSD_version < 500000) 2509 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2510 db_tr->bus_addr, 2511 #else 2512 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", 2513 (uintmax_t)db_tr->bus_addr, 2514 #endif 2515 dbcode[(cmd >> 28) & 0xf], 2516 dbkey[(cmd >> 24) & 0x7], 2517 dbcond[(cmd >> 20) & 0x3], 2518 dbcond[(cmd >> 18) & 0x3], 2519 cmd & OHCI_COUNT_MASK, 2520 FWOHCI_DMA_READ(db[i].db.desc.addr), 2521 FWOHCI_DMA_READ(db[i].db.desc.depend), 2522 stat, 2523 res & OHCI_COUNT_MASK); 2524 if(stat & 0xff00){ 2525 printf(" %s%s%s%s%s%s %s(%x)\n", 2526 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2527 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2528 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2529 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2530 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2531 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2532 fwohcicode[stat & 0x1f], 2533 stat & 0x1f 2534 ); 2535 }else{ 2536 printf(" Nostat\n"); 2537 } 2538 if(key == OHCI_KEY_ST2 ){ 2539 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2540 FWOHCI_DMA_READ(db[i+1].db.immed[0]), 2541 FWOHCI_DMA_READ(db[i+1].db.immed[1]), 2542 FWOHCI_DMA_READ(db[i+1].db.immed[2]), 2543 FWOHCI_DMA_READ(db[i+1].db.immed[3])); 2544 } 2545 if(key == OHCI_KEY_DEVICE){ 2546 return; 2547 } 2548 if((cmd & OHCI_BRANCH_MASK) 2549 == OHCI_BRANCH_ALWAYS){ 2550 return; 2551 } 2552 if((cmd & OHCI_CMD_MASK) 2553 == OHCI_OUTPUT_LAST){ 2554 return; 2555 } 2556 if((cmd & OHCI_CMD_MASK) 2557 == OHCI_INPUT_LAST){ 2558 return; 2559 } 2560 if(key == OHCI_KEY_ST2 ){ 2561 i++; 2562 } 2563 } 2564 return; 2565 } 2566 2567 void 2568 fwohci_ibr(struct firewire_comm *fc) 2569 { 2570 struct fwohci_softc *sc; 2571 uint32_t fun; 2572 2573 device_printf(fc->dev, "Initiate bus reset\n"); 2574 sc = (struct fwohci_softc *)fc; 2575 2576 /* 2577 * Make sure our cached values from the config rom are 2578 * initialised. 2579 */ 2580 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); 2581 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); 2582 2583 /* 2584 * Set root hold-off bit so that non cyclemaster capable node 2585 * shouldn't became the root node. 2586 */ 2587 #if 1 2588 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2589 fun |= FW_PHY_IBR | FW_PHY_RHB; 2590 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2591 #else /* Short bus reset */ 2592 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2593 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2594 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2595 #endif 2596 } 2597 2598 void 2599 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2600 { 2601 struct fwohcidb_tr *db_tr, *fdb_tr; 2602 struct fwohci_dbch *dbch; 2603 struct fwohcidb *db; 2604 struct fw_pkt *fp; 2605 struct fwohci_txpkthdr *ohcifp; 2606 unsigned short chtag; 2607 int idb; 2608 2609 dbch = &sc->it[dmach]; 2610 chtag = sc->it[dmach].xferq.flag & 0xff; 2611 2612 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2613 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2614 /* 2615 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); 2616 */ 2617 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { 2618 db = db_tr->db; 2619 fp = (struct fw_pkt *)db_tr->buf; 2620 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; 2621 ohcifp->mode.ld[0] = fp->mode.ld[0]; 2622 ohcifp->mode.common.spd = 0 & 0x7; 2623 ohcifp->mode.stream.len = fp->mode.stream.len; 2624 ohcifp->mode.stream.chtag = chtag; 2625 ohcifp->mode.stream.tcode = 0xa; 2626 #if BYTE_ORDER == BIG_ENDIAN 2627 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); 2628 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); 2629 #endif 2630 2631 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); 2632 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); 2633 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2634 #if 0 /* if bulkxfer->npackets changes */ 2635 db[2].db.desc.cmd = OHCI_OUTPUT_LAST 2636 | OHCI_UPDATE 2637 | OHCI_BRANCH_ALWAYS; 2638 db[0].db.desc.depend = 2639 = db[dbch->ndesc - 1].db.desc.depend 2640 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; 2641 #else 2642 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); 2643 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); 2644 #endif 2645 bulkxfer->end = (caddr_t)db_tr; 2646 db_tr = STAILQ_NEXT(db_tr, link); 2647 } 2648 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2649 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); 2650 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); 2651 #if 0 /* if bulkxfer->npackets changes */ 2652 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2653 /* OHCI 1.1 and above */ 2654 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2655 #endif 2656 /* 2657 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2658 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2659 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); 2660 */ 2661 return; 2662 } 2663 2664 static int 2665 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2666 int poffset) 2667 { 2668 struct fwohcidb *db = db_tr->db; 2669 struct fw_xferq *it; 2670 int err = 0; 2671 2672 it = &dbch->xferq; 2673 if(it->buf == 0){ 2674 err = EINVAL; 2675 return err; 2676 } 2677 db_tr->buf = fwdma_v_addr(it->buf, poffset); 2678 db_tr->dbcnt = 3; 2679 2680 FWOHCI_DMA_WRITE(db[0].db.desc.cmd, 2681 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); 2682 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); 2683 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); 2684 FWOHCI_DMA_WRITE(db[2].db.desc.addr, 2685 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t)); 2686 2687 FWOHCI_DMA_WRITE(db[2].db.desc.cmd, 2688 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); 2689 #if 1 2690 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); 2691 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); 2692 #endif 2693 return 0; 2694 } 2695 2696 int 2697 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, 2698 int poffset, struct fwdma_alloc *dummy_dma) 2699 { 2700 struct fwohcidb *db = db_tr->db; 2701 struct fw_xferq *ir; 2702 int i, ldesc; 2703 bus_addr_t dbuf[2]; 2704 int dsiz[2]; 2705 2706 ir = &dbch->xferq; 2707 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { 2708 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, 2709 ir->psize, &dbuf[0], BUS_DMA_NOWAIT); 2710 if (db_tr->buf == NULL) 2711 return(ENOMEM); 2712 db_tr->dbcnt = 1; 2713 dsiz[0] = ir->psize; 2714 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2715 BUS_DMASYNC_PREREAD); 2716 } else { 2717 db_tr->dbcnt = 0; 2718 if (dummy_dma != NULL) { 2719 dsiz[db_tr->dbcnt] = sizeof(uint32_t); 2720 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; 2721 } 2722 dsiz[db_tr->dbcnt] = ir->psize; 2723 if (ir->buf != NULL) { 2724 db_tr->buf = fwdma_v_addr(ir->buf, poffset); 2725 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); 2726 } 2727 db_tr->dbcnt++; 2728 } 2729 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2730 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); 2731 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); 2732 if (ir->flag & FWXFERQ_STREAM) { 2733 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); 2734 } 2735 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); 2736 } 2737 ldesc = db_tr->dbcnt - 1; 2738 if (ir->flag & FWXFERQ_STREAM) { 2739 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); 2740 } 2741 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); 2742 return 0; 2743 } 2744 2745 2746 static int 2747 fwohci_arcv_swap(struct fw_pkt *fp, int len) 2748 { 2749 struct fw_pkt *fp0; 2750 uint32_t ld0; 2751 int slen, hlen; 2752 #if BYTE_ORDER == BIG_ENDIAN 2753 int i; 2754 #endif 2755 2756 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); 2757 #if 0 2758 printf("ld0: x%08x\n", ld0); 2759 #endif 2760 fp0 = (struct fw_pkt *)&ld0; 2761 /* determine length to swap */ 2762 switch (fp0->mode.common.tcode) { 2763 case FWTCODE_WRES: 2764 CTR0(KTR_DEV, "WRES"); 2765 case FWTCODE_RREQQ: 2766 case FWTCODE_WREQQ: 2767 case FWTCODE_RRESQ: 2768 case FWOHCITCODE_PHY: 2769 slen = 12; 2770 break; 2771 case FWTCODE_RREQB: 2772 case FWTCODE_WREQB: 2773 case FWTCODE_LREQ: 2774 case FWTCODE_RRESB: 2775 case FWTCODE_LRES: 2776 slen = 16; 2777 break; 2778 default: 2779 printf("Unknown tcode %d\n", fp0->mode.common.tcode); 2780 return(0); 2781 } 2782 hlen = tinfo[fp0->mode.common.tcode].hdr_len; 2783 if (hlen > len) { 2784 if (firewire_debug) 2785 printf("splitted header\n"); 2786 return(-hlen); 2787 } 2788 #if BYTE_ORDER == BIG_ENDIAN 2789 for(i = 0; i < slen/4; i ++) 2790 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); 2791 #endif 2792 return(hlen); 2793 } 2794 2795 static int 2796 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) 2797 { 2798 const struct tcode_info *info; 2799 int r; 2800 2801 info = &tinfo[fp->mode.common.tcode]; 2802 r = info->hdr_len + sizeof(uint32_t); 2803 if ((info->flag & FWTI_BLOCK_ASY) != 0) 2804 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t)); 2805 2806 if (r == sizeof(uint32_t)) { 2807 /* XXX */ 2808 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2809 fp->mode.common.tcode); 2810 return (-1); 2811 } 2812 2813 if (r > dbch->xferq.psize) { 2814 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2815 return (-1); 2816 /* panic ? */ 2817 } 2818 2819 return r; 2820 } 2821 2822 static void 2823 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch, 2824 struct fwohcidb_tr *db_tr, uint32_t off, int wake) 2825 { 2826 struct fwohcidb *db = &db_tr->db[0]; 2827 2828 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); 2829 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); 2830 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); 2831 dbch->bottom = db_tr; 2832 2833 if (wake) 2834 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 2835 } 2836 2837 static void 2838 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2839 { 2840 struct fwohcidb_tr *db_tr; 2841 struct iovec vec[2]; 2842 struct fw_pkt pktbuf; 2843 int nvec; 2844 struct fw_pkt *fp; 2845 uint8_t *ld; 2846 uint32_t stat, off, status, event; 2847 u_int spd; 2848 int len, plen, hlen, pcnt, offset; 2849 int s; 2850 caddr_t buf; 2851 int resCount; 2852 2853 CTR0(KTR_DEV, "fwohci_arv"); 2854 2855 if(&sc->arrq == dbch){ 2856 off = OHCI_ARQOFF; 2857 }else if(&sc->arrs == dbch){ 2858 off = OHCI_ARSOFF; 2859 }else{ 2860 return; 2861 } 2862 2863 s = splfw(); 2864 db_tr = dbch->top; 2865 pcnt = 0; 2866 /* XXX we cannot handle a packet which lies in more than two buf */ 2867 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; 2868 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; 2869 while (status & OHCI_CNTL_DMA_ACTIVE) { 2870 #if 0 2871 2872 if (off == OHCI_ARQOFF) 2873 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n", 2874 db_tr->bus_addr, status, resCount); 2875 #endif 2876 len = dbch->xferq.psize - resCount; 2877 ld = (uint8_t *)db_tr->buf; 2878 if (dbch->pdb_tr == NULL) { 2879 len -= dbch->buf_offset; 2880 ld += dbch->buf_offset; 2881 } 2882 if (len > 0) 2883 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, 2884 BUS_DMASYNC_POSTREAD); 2885 while (len > 0 ) { 2886 if (count >= 0 && count-- == 0) 2887 goto out; 2888 if(dbch->pdb_tr != NULL){ 2889 /* we have a fragment in previous buffer */ 2890 int rlen; 2891 2892 offset = dbch->buf_offset; 2893 if (offset < 0) 2894 offset = - offset; 2895 buf = dbch->pdb_tr->buf + offset; 2896 rlen = dbch->xferq.psize - offset; 2897 if (firewire_debug) 2898 printf("rlen=%d, offset=%d\n", 2899 rlen, dbch->buf_offset); 2900 if (dbch->buf_offset < 0) { 2901 /* splitted in header, pull up */ 2902 char *p; 2903 2904 p = (char *)&pktbuf; 2905 bcopy(buf, p, rlen); 2906 p += rlen; 2907 /* this must be too long but harmless */ 2908 rlen = sizeof(pktbuf) - rlen; 2909 if (rlen < 0) 2910 printf("why rlen < 0\n"); 2911 bcopy(db_tr->buf, p, rlen); 2912 ld += rlen; 2913 len -= rlen; 2914 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); 2915 if (hlen <= 0) { 2916 printf("hlen < 0 shouldn't happen"); 2917 goto err; 2918 } 2919 offset = sizeof(pktbuf); 2920 vec[0].iov_base = (char *)&pktbuf; 2921 vec[0].iov_len = offset; 2922 } else { 2923 /* splitted in payload */ 2924 offset = rlen; 2925 vec[0].iov_base = buf; 2926 vec[0].iov_len = rlen; 2927 } 2928 fp=(struct fw_pkt *)vec[0].iov_base; 2929 nvec = 1; 2930 } else { 2931 /* no fragment in previous buffer */ 2932 fp=(struct fw_pkt *)ld; 2933 hlen = fwohci_arcv_swap(fp, len); 2934 if (hlen == 0) 2935 goto err; 2936 if (hlen < 0) { 2937 dbch->pdb_tr = db_tr; 2938 dbch->buf_offset = - dbch->buf_offset; 2939 /* sanity check */ 2940 if (resCount != 0) { 2941 printf("resCount=%d hlen=%d\n", 2942 resCount, hlen); 2943 goto err; 2944 } 2945 goto out; 2946 } 2947 offset = 0; 2948 nvec = 0; 2949 } 2950 plen = fwohci_get_plen(sc, dbch, fp) - offset; 2951 if (plen < 0) { 2952 /* minimum header size + trailer 2953 = sizeof(fw_pkt) so this shouldn't happens */ 2954 printf("plen(%d) is negative! offset=%d\n", 2955 plen, offset); 2956 goto err; 2957 } 2958 if (plen > 0) { 2959 len -= plen; 2960 if (len < 0) { 2961 dbch->pdb_tr = db_tr; 2962 if (firewire_debug) 2963 printf("splitted payload\n"); 2964 /* sanity check */ 2965 if (resCount != 0) { 2966 printf("resCount=%d plen=%d" 2967 " len=%d\n", 2968 resCount, plen, len); 2969 goto err; 2970 } 2971 goto out; 2972 } 2973 vec[nvec].iov_base = ld; 2974 vec[nvec].iov_len = plen; 2975 nvec ++; 2976 ld += plen; 2977 } 2978 dbch->buf_offset = ld - (uint8_t *)db_tr->buf; 2979 if (nvec == 0) 2980 printf("nvec == 0\n"); 2981 2982 /* DMA result-code will be written at the tail of packet */ 2983 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer))); 2984 #if 0 2985 printf("plen: %d, stat %x\n", 2986 plen ,stat); 2987 #endif 2988 spd = (stat >> 21) & 0x3; 2989 event = (stat >> 16) & 0x1f; 2990 switch (event) { 2991 case FWOHCIEV_ACKPEND: 2992 #if 0 2993 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); 2994 #endif 2995 /* fall through */ 2996 case FWOHCIEV_ACKCOMPL: 2997 { 2998 struct fw_rcv_buf rb; 2999 3000 if ((vec[nvec-1].iov_len -= 3001 sizeof(struct fwohci_trailer)) == 0) 3002 nvec--; 3003 rb.fc = &sc->fc; 3004 rb.vec = vec; 3005 rb.nvec = nvec; 3006 rb.spd = spd; 3007 fw_rcv(&rb); 3008 break; 3009 } 3010 case FWOHCIEV_BUSRST: 3011 if (sc->fc.status != FWBUSRESET) 3012 printf("got BUSRST packet!?\n"); 3013 break; 3014 default: 3015 device_printf(sc->fc.dev, 3016 "Async DMA Receive error err=%02x %s" 3017 " plen=%d offset=%d len=%d status=0x%08x" 3018 " tcode=0x%x, stat=0x%08x\n", 3019 event, fwohcicode[event], plen, 3020 dbch->buf_offset, len, 3021 OREAD(sc, OHCI_DMACTL(off)), 3022 fp->mode.common.tcode, stat); 3023 #if 1 /* XXX */ 3024 goto err; 3025 #endif 3026 break; 3027 } 3028 pcnt ++; 3029 if (dbch->pdb_tr != NULL) { 3030 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 3031 off, 1); 3032 dbch->pdb_tr = NULL; 3033 } 3034 3035 } 3036 out: 3037 if (resCount == 0) { 3038 /* done on this buffer */ 3039 if (dbch->pdb_tr == NULL) { 3040 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1); 3041 dbch->buf_offset = 0; 3042 } else 3043 if (dbch->pdb_tr != db_tr) 3044 printf("pdb_tr != db_tr\n"); 3045 db_tr = STAILQ_NEXT(db_tr, link); 3046 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3047 >> OHCI_STATUS_SHIFT; 3048 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3049 & OHCI_COUNT_MASK; 3050 /* XXX check buffer overrun */ 3051 dbch->top = db_tr; 3052 } else { 3053 dbch->buf_offset = dbch->xferq.psize - resCount; 3054 fw_bus_dmamap_sync( 3055 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3056 break; 3057 } 3058 /* XXX make sure DMA is not dead */ 3059 } 3060 #if 0 3061 if (pcnt < 1) 3062 printf("fwohci_arcv: no packets\n"); 3063 #endif 3064 splx(s); 3065 return; 3066 3067 err: 3068 device_printf(sc->fc.dev, "AR DMA status=%x, ", 3069 OREAD(sc, OHCI_DMACTL(off))); 3070 dbch->pdb_tr = NULL; 3071 /* skip until resCount != 0 */ 3072 printf(" skip buffer"); 3073 while (resCount == 0) { 3074 printf(" #"); 3075 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0); 3076 db_tr = STAILQ_NEXT(db_tr, link); 3077 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) 3078 & OHCI_COUNT_MASK; 3079 } 3080 printf(" done\n"); 3081 dbch->top = db_tr; 3082 dbch->buf_offset = dbch->xferq.psize - resCount; 3083 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 3084 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); 3085 splx(s); 3086 } 3087 #if defined(__NetBSD__) 3088 3089 int 3090 fwohci_print(void *aux, const char *pnp) 3091 { 3092 char *name = aux; 3093 3094 if (pnp) 3095 aprint_normal("%s at %s", name, pnp); 3096 3097 return UNCONF; 3098 } 3099 #endif 3100
Indexes created Fri Sep 26 08:10:20 GMT 2025