fwohcireg.h revision 1.2
1 /*- 2 * Copyright (c) 2000 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _DEV_IEEE1394_FWOHCIREG_H_ 38 #define _DEV_IEEE1394_FWOHCIREG_H_ 39 40 /* PCI/CardBus-Specific definitions 41 */ 42 43 /* In the PCI Class Code Register ... 44 */ 45 #define PCI_INTERFACE_OHCI 0x10 46 47 /* The OHCI Regisers are in PCI BAR0. 48 */ 49 #define PCI_OHCI_MAP_REGISTER 0x10 50 51 /* HCI Control Register (in PCI config space) 52 */ 53 #define PCI_OHCI_CONTROL_REGISTER 0x40 54 55 /* If the following bit, all OHCI register access 56 * and DMA transactions are byte swapped. 57 */ 58 #define PCI_GLOBAL_SWAP_BE 0x00000001 59 60 /* Bus Independent Definitions */ 61 62 /* OHCI Registers 63 * OHCI Registers are divided into four spaces: 64 * 1) 0x000 .. 0x17C = Control register space 65 * 2) 0x180 .. 0x1FC = Asynchronous DMA context register space 66 * (4 contexts) 67 * 3) 0x200 .. 0x3FC = Isochronous Transmit DMA context register space 68 * (32 contexts) 69 * 4) 0x400 .. 0x7FC = Isochronous Receive DMA context register space 70 * (32 contexts) 71 */ 72 #define OHCI_REG_Version 0x000 73 #define OHCI_REG_Guid_Rom 0x004 74 #define OHCI_REG_ATRetries 0x008 75 #define OHCI_REG_CsrReadData 0x00c 76 #define OHCI_REG_CsrCompareData 0x010 77 #define OHCI_REG_CsrControl 0x014 78 #define OHCI_REG_ConfigROMhdr 0x018 79 #define OHCI_REG_BusId 0x01c 80 #define OHCI_REG_BusOptions 0x020 81 #define OHCI_REG_GUIDHi 0x024 82 #define OHCI_REG_GUIDLo 0x028 83 #define OHCI_REG_reserved_02c 0x02c 84 #define OHCI_REG_reserved_030 0x030 85 #define OHCI_REG_ConfigROMmap 0x034 86 #define OHCI_REG_PostedWriteAddressLo 0x038 87 #define OHCI_REG_PostedWriteAddressHi 0x03c 88 #define OHCI_REG_VendorId 0x040 89 #define OHCI_REG_reserved_044 0x044 90 #define OHCI_REG_reserved_048 0x048 91 #define OHCI_REG_reserved_04c 0x04c 92 #define OHCI_REG_HCControlSet 0x050 93 #define OHCI_REG_HCControlClear 0x054 94 #define OHCI_REG_reserved_058 0x058 95 #define OHCI_REG_reserved_05c 0x05c 96 #define OHCI_REG_reserved_060 0x060 97 #define OHCI_REG_SelfIDBuffer 0x064 98 #define OHCI_REG_SelfIDCount 0x068 99 #define OHCI_REG_reserved_06c 0x06c 100 #define OHCI_REG_IRMultiChanMaskHiSet 0x070 101 #define OHCI_REG_IRMultiChanMaskHiClear 0x074 102 #define OHCI_REG_IRMultiChanMaskLoSet 0x078 103 #define OHCI_REG_IRMultiChanMaskLoClear 0x07c 104 #define OHCI_REG_IntEventSet 0x080 105 #define OHCI_REG_IntEventClear 0x084 106 #define OHCI_REG_IntMaskSet 0x088 107 #define OHCI_REG_IntMaskClear 0x08c 108 #define OHCI_REG_IsoXmitIntEventSet 0x090 109 #define OHCI_REG_IsoXmitIntEventClear 0x094 110 #define OHCI_REG_IsoXmitIntMaskSet 0x098 111 #define OHCI_REG_IsoXmitIntMaskClear 0x09c 112 #define OHCI_REG_IsoRecvIntEventSet 0x0a0 113 #define OHCI_REG_IsoRecvIntEventClear 0x0a4 114 #define OHCI_REG_IsoRecvIntMaskSet 0x0a8 115 #define OHCI_REG_IsoRecvIntMaskClear 0x0ac 116 #define OHCI_REG_InitialBandwidthAvailable 0x0b0 117 #define OHCI_REG_InitialChannelsAvailableHi 0x0b4 118 #define OHCI_REG_InitialChannelsAvailableLo 0x0b8 119 #define OHCI_REG_reserved_0bc 0x0bc 120 #define OHCI_REG_reserved_0c0 0x0c0 121 #define OHCI_REG_reserved_0c4 0x0c4 122 #define OHCI_REG_reserved_0c8 0x0c8 123 #define OHCI_REG_reserved_0cc 0x0cc 124 #define OHCI_REG_reserved_0d0 0x0d0 125 #define OHCI_REG_reserved_0d4 0x0d4 126 #define OHCI_REG_reserved_0d8 0x0d8 127 #define OHCI_REG_FairnessConctrol 0x0dc 128 #define OHCI_REG_LinkControlSet 0x0e0 129 #define OHCI_REG_LinkControlClear 0x0e4 130 #define OHCI_REG_NodeId 0x0e8 131 #define OHCI_REG_PhyControl 0x0ec 132 #define OHCI_REG_IsochronousCycleTimer 0x0f0 133 #define OHCI_REG_reserved_0f0 0x0f4 134 #define OHCI_REG_reserved_0f8 0x0f8 135 #define OHCI_REG_reserved_0fc 0x0fc 136 #define OHCI_REG_AsynchronousRequestFilterHiSet 0x100 137 #define OHCI_REG_AsynchronousRequestFilterHiClear 0x104 138 #define OHCI_REG_AsynchronousRequestFilterLoSet 0x108 139 #define OHCI_REG_AsynchronousRequestFilterLoClear 0x10c 140 #define OHCI_REG_PhysicalRequestFilterHiSet 0x110 141 #define OHCI_REG_PhysicalRequestFilterHiClear 0x114 142 #define OHCI_REG_PhysicalRequestFilterLoSet 0x118 143 #define OHCI_REG_PhysicalRequestFilterLoCLear 0x11c 144 #define OHCI_REG_PhysicalUpperBound 0x120 145 #define OHCI_REG_reserved_124 0x124 146 #define OHCI_REG_reserved_128 0x128 147 #define OHCI_REG_reserved_12c 0x12c 148 #define OHCI_REG_reserved_130 0x130 149 #define OHCI_REG_reserved_134 0x134 150 #define OHCI_REG_reserved_138 0x138 151 #define OHCI_REG_reserved_13c 0x13c 152 #define OHCI_REG_reserved_140 0x140 153 #define OHCI_REG_reserved_144 0x144 154 #define OHCI_REG_reserved_148 0x148 155 #define OHCI_REG_reserved_14c 0x14c 156 #define OHCI_REG_reserved_150 0x150 157 #define OHCI_REG_reserved_154 0x154 158 #define OHCI_REG_reserved_158 0x158 159 #define OHCI_REG_reserved_15c 0x15c 160 #define OHCI_REG_reserved_160 0x160 161 #define OHCI_REG_reserved_164 0x164 162 #define OHCI_REG_reserved_168 0x168 163 #define OHCI_REG_reserved_16c 0x16c 164 #define OHCI_REG_reserved_170 0x170 165 #define OHCI_REG_reserved_174 0x174 166 #define OHCI_REG_reserved_178 0x178 167 #define OHCI_REG_reserved_17c 0x17c 168 169 170 #define OHCI_REG_ASYNC_DMA_BASE 0x180 171 #define OHCI_CTX_ASYNC_TX_REQUEST 0 172 #define OHCI_CTX_ASYNC_TX_RESPONSE 1 173 #define OHCI_CTX_ASYNC_RX_REQUEST 2 174 #define OHCI_CTX_ASYNC_RX_RESPONSE 3 175 #define OHCI_SUBREG_ContextControlSet 0x000 176 #define OHCI_SUBREG_ContextControlClear 0x004 177 #define OHCI_SUBREG_reserved_008 0x008 178 #define OHCI_SUBREG_CommandPtr 0x00c 179 #define OHCI_SUBREG_ContextMatch 0x010 180 #define OHCI_SUBREG_reserved_014 0x014 181 #define OHCI_SUBREG_reserved_018 0x018 182 #define OHCI_SUBREG_reserved_01c 0x01c 183 #define OHCI_ASYNC_DMA_WRITE(sc, ctx, reg, val) \ 184 OHCI_CSR_WRITE(sc, OHCI_REG_ASYNC_DMA_BASE + 32*(ctx) + (reg), val) 185 #define OHCI_ASYNC_DMA_READ(sc, ctx, reg) \ 186 OHCI_CSR_READ(sc, OHCI_REG_ASYNC_DMA_BASE + 32*(ctx) + (reg)) 187 188 #define OHCI_REG_SYNC_TX_DMA_BASE 0x200 189 #define OHCI_SYNC_TX_DMA_WRITE(sc, ctx, reg, val) \ 190 OHCI_CSR_WRITE(sc, OHCI_REG_SYNC_TX_DMA_BASE + 16*(ctx) + (reg), val) 191 #define OHCI_SYNC_TX_DMA_READ(sc, ctx, reg) \ 192 OHCI_CSR_READ(sc, OHCI_REG_SYNC_TX_DMA_BASE + 16*(ctx) + (reg)) 193 194 #define OHCI_REG_SYNC_RX_DMA_BASE 0x400 195 #define OHCI_SYNC_RX_DMA_WRITE(sc, ctx, reg, val) \ 196 OHCI_CSR_WRITE(sc, OHCI_REG_SYNC_RX_DMA_BASE + 32*(ctx) + (reg), val) 197 #define OHCI_SYNC_RX_DMA_READ(sc, ctx, reg) \ 198 OHCI_CSR_READ(sc, OHCI_REG_SYNC_RX_DMA_BASE + 32*(ctx) + (reg)) 199 200 /* OHCI_REG_Version 201 */ 202 #define OHCI_Version_GUID_ROM 0x01000000 203 #define OHCI_Version_GET_Version(x) ((((x) >> 16) & 0xf) + (((x) >> 20) & 0xf) * 10) 204 #define OHCI_Version_GET_Revision(x) ((((x) >> 4) & 0xf) + ((x) & 0xf) * 10) 205 206 /* OHCI_REG_GUIDxx 207 */ 208 209 /* OHCI_REG_CsrControl 210 */ 211 #define OHCI_CsrControl_Done 0x80000000 212 #define OHCI_CsrControl_SelMASK 0x00000003 213 #define OHCI_CsrControl_BusManId 0 214 #define OHCI_CsrControl_BWAvail 1 215 #define OHCI_CsrControl_ChanAvailHi 2 216 #define OHCI_CsrControl_ChanAvailLo 3 217 218 /* OHCI_REG_BusOptions 219 */ 220 #define OHCI_BusOptions_LinkSpd_MASK 0x00000007 221 #define OHCI_BusOptions_LinkSpd_BITPOS 0 222 #define OHCI_BusOptions_G_MASK 0x000000c0 223 #define OHCI_BusOptions_G_BITPOS 6 224 #define OHCI_BusOptions_MaxRec_MASK 0x0000f000 225 #define OHCI_BusOptions_MaxRec_BITPOS 12 226 #define OHCI_BusOptions_CycClkAcc_MASK 0x00ff0000 227 #define OHCI_BusOptions_CycClkAcc_BITPOS 16 228 #define OHCI_BusOptions_PMC 0x08000000 229 #define OHCI_BusOptions_BMC 0x10000000 230 #define OHCI_BusOptions_ISC 0x20000000 231 #define OHCI_BusOptions_CMC 0x40000000 232 #define OHCI_BusOptions_IRMC 0x80000000 233 #define OHCI_BusOptions_reserved 0x07000f38 234 235 /* OHCI_REG_HCControl 236 */ 237 238 #define OHCI_HCControl_SoftReset 0x00010000 239 #define OHCI_HCControl_LinkEnable 0x00020000 240 #define OHCI_HCControl_PostedWriteEnable 0x00040000 241 #define OHCI_HCControl_LPS 0x00080000 242 #define OHCI_HCControl_APhyEnhanceEnable 0x00400000 243 #define OHCI_HCControl_ProgramPhyEnable 0x00800000 244 #define OHCI_HCControl_NoByteSwapData 0x40000000 245 #define OHCI_HCControl_BIBImageValid 0x80000000 246 247 /* OHCI_REG_SelfID 248 */ 249 #define OHCI_SelfID_Error 0x80000000 250 #define OHCI_SelfID_Gen_MASK 0x00ff0000 251 #define OHCI_SelfID_Gen_BITPOS 16 252 #define OHCI_SelfID_Size_MASK 0x000007fc 253 #define OHCI_SelfID_Size_BITPOS 2 254 255 /* OCHI_REG_Int{Event|Mask}* 256 */ 257 #define OHCI_Int_MasterEnable 0x80000000 258 #define OHCI_Int_VendorSpecific 0x40000000 259 #define OHCI_Int_SoftInterrupt 0x20000000 260 #define OHCI_Int_Ack_Tardy 0x08000000 261 #define OHCI_Int_PhyRegRcvd 0x04000000 262 #define OHCI_Int_CycleTooLong 0x02000000 263 #define OHCI_Int_UnrecoverableError 0x01000000 264 #define OHCI_Int_CycleInconsistent 0x00800000 265 #define OHCI_Int_CycleLost 0x00400000 266 #define OHCI_Int_Cycle64Seconds 0x00200000 267 #define OHCI_Int_CycleSynch 0x00100000 268 #define OHCI_Int_Phy 0x00080000 269 #define OHCI_Int_RegAccessFail 0x00040000 270 #define OHCI_Int_BusReset 0x00020000 271 #define OHCI_Int_SelfIDComplete 0x00010000 272 #define OHCI_Int_SelfIDCOmplete2 0x00008000 273 #define OHCI_Int_LockRespErr 0x00000200 274 #define OHCI_Int_PostedWriteErr 0x00000100 275 #define OHCI_Int_IsochRx 0x00000080 276 #define OHCI_Int_IsochTx 0x00000040 277 #define OHCI_Int_RSPkt 0x00000020 278 #define OHCI_Int_RQPkt 0x00000010 279 #define OHCI_Int_ARRS 0x00000008 280 #define OHCI_Int_ARRQ 0x00000004 281 #define OHCI_Int_RespTxComplete 0x00000002 282 #define OHCI_Int_ReqTxComplete 0x00000001 283 284 /* OHCI_REG_LinkControl 285 */ 286 #define OHCI_LinkControl_CycleSource 0x00400000 287 #define OHCI_LinkControl_CycleMaster 0x00200000 288 #define OHCI_LinkControl_CycleTimerEnable 0x00100000 289 #define OHCI_LinkControl_RcvPhyPkt 0x00000400 290 #define OHCI_LinkControl_RcvSelfID 0x00000200 291 #define OHCI_LinkControl_Tag1SyncFilterLock 0x00000040 292 293 /* OHCI_REG_NodeId 294 */ 295 #define OHCI_NodeId_IDValid 0x80000000 296 #define OHCI_NodeId_ROOT 0x40000000 297 #define OHCI_NodeId_CPS 0x08000000 298 #define OHCI_NodeId_BusNumber 0x0000ffc0 299 #define OHCI_NodeId_NodeNumber 0x0000003f 300 301 /* OHCI_REG_PhyControl 302 */ 303 #define OHCI_PhyControl_RdDone 0x80000000 304 #define OHCI_PhyControl_RdAddr 0x0f000000 305 #define OHCI_PhyControl_RdAddr_BITPOS 24 306 #define OHCI_PhyControl_RdData 0x00ff0000 307 #define OHCI_PhyControl_RdData_BITPOS 16 308 #define OHCI_PhyControl_RdReg 0x00008000 309 #define OHCI_PhyControl_WrReg 0x00004000 310 #define OHCI_PhyControl_RegAddr 0x00000f00 311 #define OHCI_PhyControl_RegAddr_BITPOS 8 312 #define OHCI_PhyControl_WrData 0x000000ff 313 #define OHCI_PhyControl_WrData_BITPOS 0 314 315 /* 316 * Section 3.1.1: ContextControl register 317 * 318 * 319 */ 320 #define OHCI_CTXCTL_RUN 0x00008000 321 #define OHCI_CTXCTL_WAKE 0x00001000 322 #define OHCI_CTXCTL_DEAD 0x00000800 323 #define OHCI_CTXCTL_ACTIVE 0x00000400 324 325 #define OHCI_CTXCTL_SPD_BITLEN 3 326 #define OHCI_CTXCTL_SPD_BITPOS 5 327 328 #define OHCI_CTXCTL_SPD_100 0 329 #define OHCI_CTXCTL_SPD_200 1 330 #define OHCI_CTXCTL_SPD_400 2 331 332 #define OHCI_CTXCTL_EVENT_BITLEN 5 333 #define OHCI_CTXCTL_EVENT_BITPOS 0 334 335 /* Events from 0 to 15 are generated by the OpenHCI controller. 336 * Events from 16 to 31 are four-bit IEEE 1394 ack codes or'ed with bit 4 set. 337 */ 338 #define OHCI_CTXCTL_EVENT_NO_STATUS 0 339 #define OHCI_CTXCTL_EVENT_RESERVED1 1 340 341 /* The received data length was greater than the buffer's data_length. 342 */ 343 #define OHCI_CTXCTL_EVENT_LONG_PACKET 2 344 345 /* A subaction gap was detected before an ack arrived or the received 346 * ack had a parity error. 347 */ 348 #define OHCI_CTXCTL_EVENT_MISSING_ACK 3 349 350 /* Underrun on the corresponding FIFO. The packet was truncated. 351 */ 352 #define OHCI_CTXCTL_EVENT_UNDERRUN 4 353 354 /* A receive FIFO overflowed during the reception of an isochronous packet. 355 */ 356 #define OHCI_CTXCTL_EVENT_OVERRUN 5 357 358 /* An unrecoverable error occurred while the Host Controller was reading 359 * a descriptor block. 360 */ 361 #define OHCI_CTXCTL_EVENT_DESCRIPTOR_READ 6 362 363 /* An error occurred while the Host Controller was attempting to read 364 * from host memory in the data stage of descriptor processing. 365 */ 366 #define OHCI_CTXCTL_EVENT_DATA_READ 7 367 368 /* An error occurred while the Host Controller was attempting to write 369 * to host memory either in the data stage of descriptor processing 370 * (AR, IR), or when processing a single 16-bit host * memory write (IT). 371 */ 372 #define OHCI_CTXCTL_EVENT_DATA_WRITE 8 373 374 /* Identifies a PHY packet in the receive buffer as being the synthesized 375 * bus reset packet. (See section 8.4.2.3). 376 */ 377 #define OHCI_CTXCTL_EVENT_BUS_RESET 9 378 379 /* Indicates that the asynchronous transmit response packet expired and 380 * was not transmitted, or that an IT DMA context experienced a skip 381 * processing overflow (See section 9.3.3). 382 */ 383 #define OHCI_CTXCTL_EVENT_TIMEOUT 10 384 385 /* A bad tCode is associated with this packet. The packet was flushed. 386 */ 387 #define OHCI_CTXCTL_EVENT_TCODE_ERR 11 388 #define OHCI_CTXCTL_EVENT_RESERVED12 12 389 #define OHCI_CTXCTL_EVENT_RESERVED13 13 390 391 /* An error condition has occurred that cannot be represented 392 * by any other event codes defined herein. 393 */ 394 #define OHCI_CTXCTL_EVENT_UNKNOWN 14 395 396 /* Sent by the link side of the output FIFO when asynchronous 397 * packets are being flushed due to a bus reset. 398 */ 399 #define OHCI_CTXCTL_EVENT_FLUSHED 15 400 401 /* IEEE1394 derived ACK codes follow 402 */ 403 #define OHCI_CTXCTL_EVENT_RESERVED16 16 404 405 /* For asynchronous request and response packets, this event 406 * indicates the destination node has successfully accepted 407 * the packet. If the packet was a request subaction, the 408 * destination node has successfully completed the transaction 409 * and no response subaction shall follow. The event code for 410 * transmitted PHY, isochronous, asynchronous stream and broadcast 411 * packets, none of which yields a 1394 ack code, shall be set 412 * by hardware to ack_complete unless an event occurs. 413 */ 414 #define OHCI_CTXCTL_EVENT_ACK_COMPLETE 17 415 416 /* The destination node has successfully accepted the packet. 417 * If the packet was a request subaction, a response subaction 418 * should follow at a later time. This code is not returned for 419 * a response subaction. 420 */ 421 #define OHCI_CTXCTL_EVENT_ACK_PENDING 18 422 #define OHCI_CTXCTL_EVENT_RESERVED19 19 423 424 /* The packet could not be accepted after max ATRetries (see 425 * section 5.4) attempts, and the last ack received was ack_busy_X. 426 */ 427 #define OHCI_CTXCTL_EVENT_ACK_BUSY_X 20 428 429 /* The packet could not be accepted after max ATRetries (see 430 * section 5.4) attempts, and the last ack received was ack_busy_A. 431 */ 432 #define OHCI_CTXCTL_EVENT_ACK_BUSY_A 21 433 434 /* The packet could not be accepted after max AT Retries (see 435 * section 5.4) attempts, and the last ack received was ack_busy_B. 436 */ 437 #define OHCI_CTXCTL_EVENT_ACK_BUSY_B 22 438 #define OHCI_CTXCTL_EVENT_RESERVED23 23 439 #define OHCI_CTXCTL_EVENT_RESERVED24 24 440 #define OHCI_CTXCTL_EVENT_RESERVED25 25 441 #define OHCI_CTXCTL_EVENT_RESERVED26 26 442 443 /* The destination node could not accept the packet because 444 * the link and higher layers are in a suspended state. 445 */ 446 #define OHCI_CTXCTL_EVENT_ACK_TARDY 27 447 #define OHCI_CTXCTL_EVENT_RESERVED28 28 448 449 /* An AT context received an ack_data_error, or an IR context 450 * in packet-per-buffer mode detected a data field CRC or 451 * data_length error. 452 */ 453 #define OHCI_CTXCTL_EVENT_ACK_DATA_ERROR 29 454 455 /* A field in the request packet header was set to an unsupported or 456 * incorrect value, or an invalid transaction was attempted (e.g., a 457 * write to a read-only address). 458 */ 459 #define OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR 30 460 #define OHCI_CTXCTL_EVENT_RESERVED31 31 461 462 /* Context Control for isochronous transmit context 463 */ 464 #define OHCI_CTXCTL_TX_CYCLE_MATCH_ENABLE 0x80000000 465 #define OHCI_CTXCTL_TX_CYCLE_MATCH_BITLEN 0x7fff0000 466 #define OHCI_CTXCTL_TX_CYCLE_MATCH_BITPOS 16 467 468 #define OHCI_CTXCTL_RX_BUFFER_FILL 0x80000000 469 #define OHCI_CTXCTL_RX_ISOCH_HEADER 0x40000000 470 #define OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE 0x20000000 471 #define OHCI_CTXCTL_RX_MULTI_CHAN_MODE 0x10000000 472 #define OHCI_CTXCTL_RX_DUAL_BUFFER_MODE 0x08000000 473 474 /* Context Match registers 475 */ 476 #define OHCI_CTXMATCH_TAG3 0x80000000 477 #define OHCI_CTXMATCH_TAG2 0x40000000 478 #define OHCI_CTXMATCH_TAG1 0x20000000 479 #define OHCI_CTXMATCH_TAG0 0x10000000 480 #define OHCI_CTXMATCH_CYCLE_MATCH_MASK 0x07fff000 481 #define OHCI_CTXMATCH_CYCLE_MATCH_BITPOS 12 482 #define OHCI_CTXMATCH_SYNC_MASK 0x00000f00 483 #define OHCI_CTXMATCH_SYNC_BITPOS 8 484 #define OHCI_CTXMATCH_TAG1_SYNC_FILTER 0x00000040 485 #define OHCI_CTXMATCH_CHANNEL_NUMBER_MASK 0x0000003f 486 #define OHCI_CTXMATCH_CHANNEL_NUMBER_BITPOS 0 487 488 /* 489 * Miscellaneous definitions. 490 */ 491 492 #define OHCI_TCODE_PHY 0xe 493 494 #if BYTE_ORDER == BIG_ENDIAN 495 struct fwohci_desc { 496 u_int16_t fd_flags; 497 u_int16_t fd_reqcount; 498 u_int32_t fd_data; 499 u_int32_t fd_branch; 500 u_int16_t fd_status; 501 u_int16_t fd_rescount; 502 }; 503 #endif 504 #if BYTE_ORDER == LITTLE_ENDIAN 505 struct fwohci_desc { 506 u_int16_t fd_reqcount; 507 u_int16_t fd_flags; 508 u_int32_t fd_data; 509 u_int32_t fd_branch; 510 u_int16_t fd_rescount; 511 u_int16_t fd_status; 512 }; 513 #endif 514 #define fd_timestamp fd_rescount 515 516 #define OHCI_DESC_INPUT 0x2000 517 #define OHCI_DESC_LAST 0x1000 518 #define OHCI_DESC_STATUS 0x0800 519 #define OHCI_DESC_IMMED 0x0200 520 #define OHCI_DESC_PING 0x0080 521 #define OHCI_DESC_INTR_ALWAYS 0x0030 522 #define OHCI_DESC_INTR_ERR 0x0010 523 #define OHCI_DESC_BRANCH 0x000c 524 #define OHCI_DESC_WAIT 0x0003 525 526 #endif /* _DEV_IEEE1394_FWOHCIREG_ */ 527
Indexes created Mon Sep 29 21:09:56 GMT 2025