fwohcireg.h revision 1.3
1 /*- 2 * Copyright (c) 2000 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _DEV_IEEE1394_FWOHCIREG_H_ 38 #define _DEV_IEEE1394_FWOHCIREG_H_ 39 40 /* PCI/CardBus-Specific definitions 41 */ 42 43 /* In the PCI Class Code Register ... 44 */ 45 #define PCI_INTERFACE_OHCI 0x10 46 47 /* The OHCI Regisers are in PCI BAR0. 48 */ 49 #define PCI_OHCI_MAP_REGISTER 0x10 50 51 /* HCI Control Register (in PCI config space) 52 */ 53 #define PCI_OHCI_CONTROL_REGISTER 0x40 54 55 /* If the following bit, all OHCI register access 56 * and DMA transactions are byte swapped. 57 */ 58 #define PCI_GLOBAL_SWAP_BE 0x00000001 59 60 /* Bus Independent Definitions */ 61 62 #define OHCI_CONFIG_SIZE 1024 63 #define OHCI_CONFIG_ALIGNMENT 1024 64 65 /* OHCI Registers 66 * OHCI Registers are divided into four spaces: 67 * 1) 0x000 .. 0x17C = Control register space 68 * 2) 0x180 .. 0x1FC = Asynchronous DMA context register space 69 * (4 contexts) 70 * 3) 0x200 .. 0x3FC = Isochronous Transmit DMA context register space 71 * (32 contexts) 72 * 4) 0x400 .. 0x7FC = Isochronous Receive DMA context register space 73 * (32 contexts) 74 */ 75 #define OHCI_REG_Version 0x000 76 #define OHCI_REG_Guid_Rom 0x004 77 #define OHCI_REG_ATRetries 0x008 78 #define OHCI_REG_CsrReadData 0x00c 79 #define OHCI_REG_CsrCompareData 0x010 80 #define OHCI_REG_CsrControl 0x014 81 #define OHCI_REG_ConfigROMhdr 0x018 82 #define OHCI_REG_BusId 0x01c 83 #define OHCI_REG_BusOptions 0x020 84 #define OHCI_REG_GUIDHi 0x024 85 #define OHCI_REG_GUIDLo 0x028 86 #define OHCI_REG_reserved_02c 0x02c 87 #define OHCI_REG_reserved_030 0x030 88 #define OHCI_REG_ConfigROMmap 0x034 89 #define OHCI_REG_PostedWriteAddressLo 0x038 90 #define OHCI_REG_PostedWriteAddressHi 0x03c 91 #define OHCI_REG_VendorId 0x040 92 #define OHCI_REG_reserved_044 0x044 93 #define OHCI_REG_reserved_048 0x048 94 #define OHCI_REG_reserved_04c 0x04c 95 #define OHCI_REG_HCControlSet 0x050 96 #define OHCI_REG_HCControlClear 0x054 97 #define OHCI_REG_reserved_058 0x058 98 #define OHCI_REG_reserved_05c 0x05c 99 #define OHCI_REG_reserved_060 0x060 100 #define OHCI_REG_SelfIDBuffer 0x064 101 #define OHCI_REG_SelfIDCount 0x068 102 #define OHCI_REG_reserved_06c 0x06c 103 #define OHCI_REG_IRMultiChanMaskHiSet 0x070 104 #define OHCI_REG_IRMultiChanMaskHiClear 0x074 105 #define OHCI_REG_IRMultiChanMaskLoSet 0x078 106 #define OHCI_REG_IRMultiChanMaskLoClear 0x07c 107 #define OHCI_REG_IntEventSet 0x080 108 #define OHCI_REG_IntEventClear 0x084 109 #define OHCI_REG_IntMaskSet 0x088 110 #define OHCI_REG_IntMaskClear 0x08c 111 #define OHCI_REG_IsoXmitIntEventSet 0x090 112 #define OHCI_REG_IsoXmitIntEventClear 0x094 113 #define OHCI_REG_IsoXmitIntMaskSet 0x098 114 #define OHCI_REG_IsoXmitIntMaskClear 0x09c 115 #define OHCI_REG_IsoRecvIntEventSet 0x0a0 116 #define OHCI_REG_IsoRecvIntEventClear 0x0a4 117 #define OHCI_REG_IsoRecvIntMaskSet 0x0a8 118 #define OHCI_REG_IsoRecvIntMaskClear 0x0ac 119 #define OHCI_REG_InitialBandwidthAvailable 0x0b0 120 #define OHCI_REG_InitialChannelsAvailableHi 0x0b4 121 #define OHCI_REG_InitialChannelsAvailableLo 0x0b8 122 #define OHCI_REG_reserved_0bc 0x0bc 123 #define OHCI_REG_reserved_0c0 0x0c0 124 #define OHCI_REG_reserved_0c4 0x0c4 125 #define OHCI_REG_reserved_0c8 0x0c8 126 #define OHCI_REG_reserved_0cc 0x0cc 127 #define OHCI_REG_reserved_0d0 0x0d0 128 #define OHCI_REG_reserved_0d4 0x0d4 129 #define OHCI_REG_reserved_0d8 0x0d8 130 #define OHCI_REG_FairnessConctrol 0x0dc 131 #define OHCI_REG_LinkControlSet 0x0e0 132 #define OHCI_REG_LinkControlClear 0x0e4 133 #define OHCI_REG_NodeId 0x0e8 134 #define OHCI_REG_PhyControl 0x0ec 135 #define OHCI_REG_IsochronousCycleTimer 0x0f0 136 #define OHCI_REG_reserved_0f0 0x0f4 137 #define OHCI_REG_reserved_0f8 0x0f8 138 #define OHCI_REG_reserved_0fc 0x0fc 139 #define OHCI_REG_AsynchronousRequestFilterHiSet 0x100 140 #define OHCI_REG_AsynchronousRequestFilterHiClear 0x104 141 #define OHCI_REG_AsynchronousRequestFilterLoSet 0x108 142 #define OHCI_REG_AsynchronousRequestFilterLoClear 0x10c 143 #define OHCI_REG_PhysicalRequestFilterHiSet 0x110 144 #define OHCI_REG_PhysicalRequestFilterHiClear 0x114 145 #define OHCI_REG_PhysicalRequestFilterLoSet 0x118 146 #define OHCI_REG_PhysicalRequestFilterLoCLear 0x11c 147 #define OHCI_REG_PhysicalUpperBound 0x120 148 #define OHCI_REG_reserved_124 0x124 149 #define OHCI_REG_reserved_128 0x128 150 #define OHCI_REG_reserved_12c 0x12c 151 #define OHCI_REG_reserved_130 0x130 152 #define OHCI_REG_reserved_134 0x134 153 #define OHCI_REG_reserved_138 0x138 154 #define OHCI_REG_reserved_13c 0x13c 155 #define OHCI_REG_reserved_140 0x140 156 #define OHCI_REG_reserved_144 0x144 157 #define OHCI_REG_reserved_148 0x148 158 #define OHCI_REG_reserved_14c 0x14c 159 #define OHCI_REG_reserved_150 0x150 160 #define OHCI_REG_reserved_154 0x154 161 #define OHCI_REG_reserved_158 0x158 162 #define OHCI_REG_reserved_15c 0x15c 163 #define OHCI_REG_reserved_160 0x160 164 #define OHCI_REG_reserved_164 0x164 165 #define OHCI_REG_reserved_168 0x168 166 #define OHCI_REG_reserved_16c 0x16c 167 #define OHCI_REG_reserved_170 0x170 168 #define OHCI_REG_reserved_174 0x174 169 #define OHCI_REG_reserved_178 0x178 170 #define OHCI_REG_reserved_17c 0x17c 171 172 173 #define OHCI_REG_ASYNC_DMA_BASE 0x180 174 #define OHCI_CTX_ASYNC_TX_REQUEST 0 175 #define OHCI_CTX_ASYNC_TX_RESPONSE 1 176 #define OHCI_CTX_ASYNC_RX_REQUEST 2 177 #define OHCI_CTX_ASYNC_RX_RESPONSE 3 178 #define OHCI_SUBREG_ContextControlSet 0x000 179 #define OHCI_SUBREG_ContextControlClear 0x004 180 #define OHCI_SUBREG_reserved_008 0x008 181 #define OHCI_SUBREG_CommandPtr 0x00c 182 #define OHCI_SUBREG_ContextMatch 0x010 183 #define OHCI_SUBREG_reserved_014 0x014 184 #define OHCI_SUBREG_reserved_018 0x018 185 #define OHCI_SUBREG_reserved_01c 0x01c 186 #define OHCI_ASYNC_DMA_WRITE(sc, ctx, reg, val) \ 187 OHCI_CSR_WRITE(sc, OHCI_REG_ASYNC_DMA_BASE + 32*(ctx) + (reg), val) 188 #define OHCI_ASYNC_DMA_READ(sc, ctx, reg) \ 189 OHCI_CSR_READ(sc, OHCI_REG_ASYNC_DMA_BASE + 32*(ctx) + (reg)) 190 191 #define OHCI_REG_SYNC_TX_DMA_BASE 0x200 192 #define OHCI_SYNC_TX_DMA_WRITE(sc, ctx, reg, val) \ 193 OHCI_CSR_WRITE(sc, OHCI_REG_SYNC_TX_DMA_BASE + 16*(ctx) + (reg), val) 194 #define OHCI_SYNC_TX_DMA_READ(sc, ctx, reg) \ 195 OHCI_CSR_READ(sc, OHCI_REG_SYNC_TX_DMA_BASE + 16*(ctx) + (reg)) 196 197 #define OHCI_REG_SYNC_RX_DMA_BASE 0x400 198 #define OHCI_SYNC_RX_DMA_WRITE(sc, ctx, reg, val) \ 199 OHCI_CSR_WRITE(sc, OHCI_REG_SYNC_RX_DMA_BASE + 32*(ctx) + (reg), val) 200 #define OHCI_SYNC_RX_DMA_READ(sc, ctx, reg) \ 201 OHCI_CSR_READ(sc, OHCI_REG_SYNC_RX_DMA_BASE + 32*(ctx) + (reg)) 202 203 /* OHCI_REG_Version 204 */ 205 #define OHCI_Version_GUID_ROM 0x01000000 206 #define OHCI_Version_GET_Version(x) ((((x) >> 16) & 0xf) + (((x) >> 20) & 0xf) * 10) 207 #define OHCI_Version_GET_Revision(x) ((((x) >> 4) & 0xf) + ((x) & 0xf) * 10) 208 209 /* OHCI_REG_GUIDxx 210 */ 211 212 /* OHCI_REG_CsrControl 213 */ 214 #define OHCI_CsrControl_Done 0x80000000 215 #define OHCI_CsrControl_SelMASK 0x00000003 216 #define OHCI_CsrControl_BusManId 0 217 #define OHCI_CsrControl_BWAvail 1 218 #define OHCI_CsrControl_ChanAvailHi 2 219 #define OHCI_CsrControl_ChanAvailLo 3 220 221 /* OHCI_REG_BusOptions 222 */ 223 #define OHCI_BusOptions_LinkSpd_MASK 0x00000007 224 #define OHCI_BusOptions_LinkSpd_BITPOS 0 225 #define OHCI_BusOptions_G_MASK 0x000000c0 226 #define OHCI_BusOptions_G_BITPOS 6 227 #define OHCI_BusOptions_MaxRec_MASK 0x0000f000 228 #define OHCI_BusOptions_MaxRec_BITPOS 12 229 #define OHCI_BusOptions_CycClkAcc_MASK 0x00ff0000 230 #define OHCI_BusOptions_CycClkAcc_BITPOS 16 231 #define OHCI_BusOptions_PMC 0x08000000 232 #define OHCI_BusOptions_BMC 0x10000000 233 #define OHCI_BusOptions_ISC 0x20000000 234 #define OHCI_BusOptions_CMC 0x40000000 235 #define OHCI_BusOptions_IRMC 0x80000000 236 #define OHCI_BusOptions_reserved 0x07000f38 237 238 /* OHCI_REG_HCControl 239 */ 240 241 #define OHCI_HCControl_SoftReset 0x00010000 242 #define OHCI_HCControl_LinkEnable 0x00020000 243 #define OHCI_HCControl_PostedWriteEnable 0x00040000 244 #define OHCI_HCControl_LPS 0x00080000 245 #define OHCI_HCControl_APhyEnhanceEnable 0x00400000 246 #define OHCI_HCControl_ProgramPhyEnable 0x00800000 247 #define OHCI_HCControl_NoByteSwapData 0x40000000 248 #define OHCI_HCControl_BIBImageValid 0x80000000 249 250 /* OHCI_REG_SelfID 251 */ 252 #define OHCI_SelfID_Error 0x80000000 253 #define OHCI_SelfID_Gen_MASK 0x00ff0000 254 #define OHCI_SelfID_Gen_BITPOS 16 255 #define OHCI_SelfID_Size_MASK 0x000007fc 256 #define OHCI_SelfID_Size_BITPOS 2 257 258 /* OCHI_REG_Int{Event|Mask}* 259 */ 260 #define OHCI_Int_MasterEnable 0x80000000 261 #define OHCI_Int_VendorSpecific 0x40000000 262 #define OHCI_Int_SoftInterrupt 0x20000000 263 #define OHCI_Int_Ack_Tardy 0x08000000 264 #define OHCI_Int_PhyRegRcvd 0x04000000 265 #define OHCI_Int_CycleTooLong 0x02000000 266 #define OHCI_Int_UnrecoverableError 0x01000000 267 #define OHCI_Int_CycleInconsistent 0x00800000 268 #define OHCI_Int_CycleLost 0x00400000 269 #define OHCI_Int_Cycle64Seconds 0x00200000 270 #define OHCI_Int_CycleSynch 0x00100000 271 #define OHCI_Int_Phy 0x00080000 272 #define OHCI_Int_RegAccessFail 0x00040000 273 #define OHCI_Int_BusReset 0x00020000 274 #define OHCI_Int_SelfIDComplete 0x00010000 275 #define OHCI_Int_SelfIDCOmplete2 0x00008000 276 #define OHCI_Int_LockRespErr 0x00000200 277 #define OHCI_Int_PostedWriteErr 0x00000100 278 #define OHCI_Int_IsochRx 0x00000080 279 #define OHCI_Int_IsochTx 0x00000040 280 #define OHCI_Int_RSPkt 0x00000020 281 #define OHCI_Int_RQPkt 0x00000010 282 #define OHCI_Int_ARRS 0x00000008 283 #define OHCI_Int_ARRQ 0x00000004 284 #define OHCI_Int_RespTxComplete 0x00000002 285 #define OHCI_Int_ReqTxComplete 0x00000001 286 287 /* OHCI_REG_LinkControl 288 */ 289 #define OHCI_LinkControl_CycleSource 0x00400000 290 #define OHCI_LinkControl_CycleMaster 0x00200000 291 #define OHCI_LinkControl_CycleTimerEnable 0x00100000 292 #define OHCI_LinkControl_RcvPhyPkt 0x00000400 293 #define OHCI_LinkControl_RcvSelfID 0x00000200 294 #define OHCI_LinkControl_Tag1SyncFilterLock 0x00000040 295 296 /* OHCI_REG_NodeId 297 */ 298 #define OHCI_NodeId_IDValid 0x80000000 299 #define OHCI_NodeId_ROOT 0x40000000 300 #define OHCI_NodeId_CPS 0x08000000 301 #define OHCI_NodeId_BusNumber 0x0000ffc0 302 #define OHCI_NodeId_NodeNumber 0x0000003f 303 304 /* OHCI_REG_PhyControl 305 */ 306 #define OHCI_PhyControl_RdDone 0x80000000 307 #define OHCI_PhyControl_RdAddr 0x0f000000 308 #define OHCI_PhyControl_RdAddr_BITPOS 24 309 #define OHCI_PhyControl_RdData 0x00ff0000 310 #define OHCI_PhyControl_RdData_BITPOS 16 311 #define OHCI_PhyControl_RdReg 0x00008000 312 #define OHCI_PhyControl_WrReg 0x00004000 313 #define OHCI_PhyControl_RegAddr 0x00000f00 314 #define OHCI_PhyControl_RegAddr_BITPOS 8 315 #define OHCI_PhyControl_WrData 0x000000ff 316 #define OHCI_PhyControl_WrData_BITPOS 0 317 318 /* 319 * Section 3.1.1: ContextControl register 320 * 321 * 322 */ 323 #define OHCI_CTXCTL_RUN 0x00008000 324 #define OHCI_CTXCTL_WAKE 0x00001000 325 #define OHCI_CTXCTL_DEAD 0x00000800 326 #define OHCI_CTXCTL_ACTIVE 0x00000400 327 328 #define OHCI_CTXCTL_SPD_BITLEN 3 329 #define OHCI_CTXCTL_SPD_BITPOS 5 330 331 #define OHCI_CTXCTL_SPD_100 0 332 #define OHCI_CTXCTL_SPD_200 1 333 #define OHCI_CTXCTL_SPD_400 2 334 335 #define OHCI_CTXCTL_EVENT_BITLEN 5 336 #define OHCI_CTXCTL_EVENT_BITPOS 0 337 338 /* Events from 0 to 15 are generated by the OpenHCI controller. 339 * Events from 16 to 31 are four-bit IEEE 1394 ack codes or'ed with bit 4 set. 340 */ 341 #define OHCI_CTXCTL_EVENT_NO_STATUS 0 342 #define OHCI_CTXCTL_EVENT_RESERVED1 1 343 344 /* The received data length was greater than the buffer's data_length. 345 */ 346 #define OHCI_CTXCTL_EVENT_LONG_PACKET 2 347 348 /* A subaction gap was detected before an ack arrived or the received 349 * ack had a parity error. 350 */ 351 #define OHCI_CTXCTL_EVENT_MISSING_ACK 3 352 353 /* Underrun on the corresponding FIFO. The packet was truncated. 354 */ 355 #define OHCI_CTXCTL_EVENT_UNDERRUN 4 356 357 /* A receive FIFO overflowed during the reception of an isochronous packet. 358 */ 359 #define OHCI_CTXCTL_EVENT_OVERRUN 5 360 361 /* An unrecoverable error occurred while the Host Controller was reading 362 * a descriptor block. 363 */ 364 #define OHCI_CTXCTL_EVENT_DESCRIPTOR_READ 6 365 366 /* An error occurred while the Host Controller was attempting to read 367 * from host memory in the data stage of descriptor processing. 368 */ 369 #define OHCI_CTXCTL_EVENT_DATA_READ 7 370 371 /* An error occurred while the Host Controller was attempting to write 372 * to host memory either in the data stage of descriptor processing 373 * (AR, IR), or when processing a single 16-bit host * memory write (IT). 374 */ 375 #define OHCI_CTXCTL_EVENT_DATA_WRITE 8 376 377 /* Identifies a PHY packet in the receive buffer as being the synthesized 378 * bus reset packet. (See section 8.4.2.3). 379 */ 380 #define OHCI_CTXCTL_EVENT_BUS_RESET 9 381 382 /* Indicates that the asynchronous transmit response packet expired and 383 * was not transmitted, or that an IT DMA context experienced a skip 384 * processing overflow (See section 9.3.3). 385 */ 386 #define OHCI_CTXCTL_EVENT_TIMEOUT 10 387 388 /* A bad tCode is associated with this packet. The packet was flushed. 389 */ 390 #define OHCI_CTXCTL_EVENT_TCODE_ERR 11 391 #define OHCI_CTXCTL_EVENT_RESERVED12 12 392 #define OHCI_CTXCTL_EVENT_RESERVED13 13 393 394 /* An error condition has occurred that cannot be represented 395 * by any other event codes defined herein. 396 */ 397 #define OHCI_CTXCTL_EVENT_UNKNOWN 14 398 399 /* Sent by the link side of the output FIFO when asynchronous 400 * packets are being flushed due to a bus reset. 401 */ 402 #define OHCI_CTXCTL_EVENT_FLUSHED 15 403 404 /* IEEE1394 derived ACK codes follow 405 */ 406 #define OHCI_CTXCTL_EVENT_RESERVED16 16 407 408 /* For asynchronous request and response packets, this event 409 * indicates the destination node has successfully accepted 410 * the packet. If the packet was a request subaction, the 411 * destination node has successfully completed the transaction 412 * and no response subaction shall follow. The event code for 413 * transmitted PHY, isochronous, asynchronous stream and broadcast 414 * packets, none of which yields a 1394 ack code, shall be set 415 * by hardware to ack_complete unless an event occurs. 416 */ 417 #define OHCI_CTXCTL_EVENT_ACK_COMPLETE 17 418 419 /* The destination node has successfully accepted the packet. 420 * If the packet was a request subaction, a response subaction 421 * should follow at a later time. This code is not returned for 422 * a response subaction. 423 */ 424 #define OHCI_CTXCTL_EVENT_ACK_PENDING 18 425 #define OHCI_CTXCTL_EVENT_RESERVED19 19 426 427 /* The packet could not be accepted after max ATRetries (see 428 * section 5.4) attempts, and the last ack received was ack_busy_X. 429 */ 430 #define OHCI_CTXCTL_EVENT_ACK_BUSY_X 20 431 432 /* The packet could not be accepted after max ATRetries (see 433 * section 5.4) attempts, and the last ack received was ack_busy_A. 434 */ 435 #define OHCI_CTXCTL_EVENT_ACK_BUSY_A 21 436 437 /* The packet could not be accepted after max AT Retries (see 438 * section 5.4) attempts, and the last ack received was ack_busy_B. 439 */ 440 #define OHCI_CTXCTL_EVENT_ACK_BUSY_B 22 441 #define OHCI_CTXCTL_EVENT_RESERVED23 23 442 #define OHCI_CTXCTL_EVENT_RESERVED24 24 443 #define OHCI_CTXCTL_EVENT_RESERVED25 25 444 #define OHCI_CTXCTL_EVENT_RESERVED26 26 445 446 /* The destination node could not accept the packet because 447 * the link and higher layers are in a suspended state. 448 */ 449 #define OHCI_CTXCTL_EVENT_ACK_TARDY 27 450 #define OHCI_CTXCTL_EVENT_RESERVED28 28 451 452 /* An AT context received an ack_data_error, or an IR context 453 * in packet-per-buffer mode detected a data field CRC or 454 * data_length error. 455 */ 456 #define OHCI_CTXCTL_EVENT_ACK_DATA_ERROR 29 457 458 /* A field in the request packet header was set to an unsupported or 459 * incorrect value, or an invalid transaction was attempted (e.g., a 460 * write to a read-only address). 461 */ 462 #define OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR 30 463 #define OHCI_CTXCTL_EVENT_RESERVED31 31 464 465 /* Context Control for isochronous transmit context 466 */ 467 #define OHCI_CTXCTL_TX_CYCLE_MATCH_ENABLE 0x80000000 468 #define OHCI_CTXCTL_TX_CYCLE_MATCH_BITLEN 0x7fff0000 469 #define OHCI_CTXCTL_TX_CYCLE_MATCH_BITPOS 16 470 471 #define OHCI_CTXCTL_RX_BUFFER_FILL 0x80000000 472 #define OHCI_CTXCTL_RX_ISOCH_HEADER 0x40000000 473 #define OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE 0x20000000 474 #define OHCI_CTXCTL_RX_MULTI_CHAN_MODE 0x10000000 475 #define OHCI_CTXCTL_RX_DUAL_BUFFER_MODE 0x08000000 476 477 /* Context Match registers 478 */ 479 #define OHCI_CTXMATCH_TAG3 0x80000000 480 #define OHCI_CTXMATCH_TAG2 0x40000000 481 #define OHCI_CTXMATCH_TAG1 0x20000000 482 #define OHCI_CTXMATCH_TAG0 0x10000000 483 #define OHCI_CTXMATCH_CYCLE_MATCH_MASK 0x07fff000 484 #define OHCI_CTXMATCH_CYCLE_MATCH_BITPOS 12 485 #define OHCI_CTXMATCH_SYNC_MASK 0x00000f00 486 #define OHCI_CTXMATCH_SYNC_BITPOS 8 487 #define OHCI_CTXMATCH_TAG1_SYNC_FILTER 0x00000040 488 #define OHCI_CTXMATCH_CHANNEL_NUMBER_MASK 0x0000003f 489 #define OHCI_CTXMATCH_CHANNEL_NUMBER_BITPOS 0 490 491 /* 492 * Miscellaneous definitions. 493 */ 494 495 #define OHCI_TCODE_PHY 0xe 496 497 #if BYTE_ORDER == BIG_ENDIAN 498 struct fwohci_desc { 499 u_int16_t fd_flags; 500 u_int16_t fd_reqcount; 501 u_int32_t fd_data; 502 u_int32_t fd_branch; 503 u_int16_t fd_status; 504 u_int16_t fd_rescount; 505 }; 506 #endif 507 #if BYTE_ORDER == LITTLE_ENDIAN 508 struct fwohci_desc { 509 u_int16_t fd_reqcount; 510 u_int16_t fd_flags; 511 u_int32_t fd_data; 512 u_int32_t fd_branch; 513 u_int16_t fd_rescount; 514 u_int16_t fd_status; 515 }; 516 #endif 517 #define fd_timestamp fd_rescount 518 519 #define OHCI_DESC_INPUT 0x2000 520 #define OHCI_DESC_LAST 0x1000 521 #define OHCI_DESC_STATUS 0x0800 522 #define OHCI_DESC_IMMED 0x0200 523 #define OHCI_DESC_PING 0x0080 524 #define OHCI_DESC_INTR_ALWAYS 0x0030 525 #define OHCI_DESC_INTR_ERR 0x0010 526 #define OHCI_DESC_BRANCH 0x000c 527 #define OHCI_DESC_WAIT 0x0003 528 529 #endif /* _DEV_IEEE1394_FWOHCIREG_ */ 530
Indexes created Tue Sep 30 11:09:46 GMT 2025