fwohcivar.h revision 1.19
1 /* $NetBSD: fwohcivar.h,v 1.19 2002/12/04 00:28:41 haya Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of the 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_IEEE1394_FWOHCIVAR_H_ 40 #define _DEV_IEEE1394_FWOHCIVAR_H_ 41 42 #include <sys/callout.h> 43 #include <sys/queue.h> 44 45 #include <machine/bus.h> 46 47 #define OHCI_PAGE_SIZE 0x0800 48 #define OHCI_BUF_ARRQ_CNT 16 49 #define OHCI_BUF_ARRS_CNT 8 50 #define OHCI_BUF_ATRQ_CNT (8*8) 51 #define OHCI_BUF_ATRS_CNT (8*8) 52 #define OHCI_BUF_IR_CNT 8 53 #define OHCI_BUF_CNT \ 54 (OHCI_BUF_ARRQ_CNT + OHCI_BUF_ARRS_CNT + OHCI_BUF_ATRQ_CNT + \ 55 OHCI_BUF_ATRS_CNT + OHCI_BUF_IR_CNT + 1 + 1) 56 57 #define OHCI_LOOP 1000 58 #define OHCI_SELFID_TIMEOUT (hz * 3) 59 #define OHCI_ASYNC_STREAM 0x100 60 61 struct fwohci_softc; 62 struct fwohci_pkt; 63 struct mbuf; 64 65 struct fwohci_buf { 66 TAILQ_ENTRY(fwohci_buf) fb_list; 67 bus_dma_segment_t fb_seg; 68 int fb_nseg; 69 bus_dmamap_t fb_dmamap; /* DMA map of the buffer */ 70 caddr_t fb_buf; /* kernel virtual addr of the buffer */ 71 struct fwohci_desc *fb_desc; /* kernel virtual addr of descriptor */ 72 bus_addr_t fb_daddr; /* physical addr of the descriptor */ 73 int fb_off; 74 struct mbuf *fb_m; 75 void *fb_statusarg; 76 void (*fb_callback)(struct device *, struct mbuf *); 77 int (*fb_statuscb)(struct fwohci_softc *, void *, struct fwohci_pkt *); 78 }; 79 80 struct fwohci_pkt { 81 int fp_tcode; 82 int fp_hlen; 83 int fp_dlen; 84 u_int32_t fp_hdr[4]; 85 struct uio fp_uio; 86 struct iovec fp_iov[6]; 87 u_int32_t *fp_trail; 88 struct mbuf *fp_m; 89 u_int16_t fp_status; 90 void *fp_statusarg; 91 int (*fp_statuscb)(struct fwohci_softc *, void *, struct fwohci_pkt *); 92 void (*fp_callback)(struct device *, struct mbuf *); 93 }; 94 95 struct fwohci_handler { 96 LIST_ENTRY(fwohci_handler) fh_list; 97 u_int32_t fh_tcode; /* ARRQ / ARRS / IR */ 98 u_int32_t fh_key1; /* addrhi / srcid / chan */ 99 u_int32_t fh_key2; /* addrlo / tlabel / tag */ 100 int (*fh_handler)(struct fwohci_softc *, void *, 101 struct fwohci_pkt *); 102 void *fh_handarg; 103 }; 104 105 struct fwohci_ctx { 106 int fc_ctx; 107 int fc_type; /* FWOHCI_CTX_(ASYNC|ISO_SINGLE|ISO_MULTI) */ 108 int fc_bufcnt; 109 u_int32_t *fc_branch; 110 TAILQ_HEAD(fwohci_buf_s, fwohci_buf) fc_buf; 111 struct fwohci_buf_s fc_buf2; /* for iso */ 112 LIST_HEAD(, fwohci_handler) fc_handler; 113 struct fwohci_buf *fc_buffers; 114 }; 115 116 117 118 struct fwohci_ir_ctx { 119 struct fwohci_softc *irc_sc; 120 121 int irc_num; /* context number */ 122 int irc_flags; /* IEEE1394_IR_* */ 123 int irc_status; 124 #define IRC_STATUS_READY 0x0001 125 #define IRC_STATUS_RUN 0x0002 126 #define IRC_STATUS_SLEEPING 0x0004 127 #define IRC_STATUS_RECEIVE 0x0008 128 129 int irc_pktcount; 130 131 int irc_channel; /* channel number */ 132 int irc_tagbm; /* tag bitmap */ 133 int irc_maxsize; /* maxmum data size for a packet */ 134 135 int irc_maxqueuelen; /* for debug purpose */ 136 int irc_maxqueuepos; 137 138 struct fwohci_desc *irc_readtop; /* where data start */ 139 struct fwohci_desc *irc_writeend; /* where branch addr is 0 */ 140 u_int32_t irc_savedbranch; 141 142 struct fwohci_iso_buf *irc_buf_ptr; 143 144 /* data for descriptor */ 145 bus_dma_segment_t irc_desc_seg; 146 bus_dmamap_t irc_desc_dmamap; 147 int irc_desc_num; /* number of descriptors */ 148 int irc_desc_size; /* actual size in byte */ 149 struct fwohci_desc *irc_desc_map; /* Do not change */ 150 int irc_desc_nsegs; 151 152 volatile void *irc_waitchan; /* wait channel */ 153 struct selinfo irc_sel; 154 155 /* data for buffer */ 156 bus_dma_segment_t irc_buf_segs[16]; 157 bus_dmamap_t irc_buf_dmamap; 158 int irc_buf_totalsize; 159 int irc_buf_nsegs; 160 u_int8_t *irc_buf; 161 162 /* for debug purpose */ 163 #ifdef FWOHCI_WAIT_DEBUG 164 u_int16_t irc_cycle[3]; /* 0 for wait time, 1 for intr time */ 165 #endif 166 }; 167 168 169 170 /* 171 * Context dedicated for isochronous transmit. Two data structure are 172 * defined. 173 */ 174 struct fwohci_it_ctx; 175 176 #define IEEE1394_IT_PKTHDR 0x0001 177 178 struct fwohci_it_dmabuf { 179 struct fwohci_it_ctx *itd_ctx; 180 int itd_num; 181 int itd_flags; 182 #define ITD_FLAGS_LOCK 0x0001 183 #define ITD_FLAGS_UNLOCK 0x0000 184 #define ITD_FLAGS_LOCK_MASK 0x0001 185 186 /* memory for descriptor */ 187 struct fwohci_desc *itd_desc; /* top of descriptor */ 188 bus_addr_t itd_desc_phys; /* physical addr of 1st descriptor */ 189 int itd_descsize; /* number of total descriptors */ 190 struct fwohci_desc *itd_lastdesc; /* last valid descriptor */ 191 192 int itd_maxpacket; /* maximum packets for the buffer */ 193 int itd_npacket; /* number of valid packets */ 194 int itd_maxsize; /* maximum packet size */ 195 196 /* DMA buffer */ 197 #define FWOHCI_MAX_ITDATASEG 8 198 bus_dma_segment_t itd_seg[FWOHCI_MAX_ITDATASEG]; 199 bus_dmamap_t itd_dmamap; 200 int itd_size; /* count in byte */ 201 u_int8_t *itd_buf; 202 int itd_nsegs; 203 204 /* header store descriptor */ 205 struct fwohci_desc *itd_store; 206 bus_addr_t itd_store_phys; 207 208 u_int32_t itd_savedbranch; 209 210 #if 0 211 int fwohci_itd_construct(struct fwohci_it_ctx *, struct fwohci_it_dmabuf *, int no, struct fwohci_desc *desc, int descsize, int maxsize, paddr_t scratch); 212 void fwohci_itd_destruct(struct fwohci_it_dmabuf *); 213 int fwohci_itd_writedata(struct fwohci_it_dmabuf *, int ndata, 214 struct ieee1394_it_datalist *); 215 int fwohci_itd_link(struct fwohci_it_dmabuf *, struct fwohci_it_dmabuf *); 216 bus_addr_t fwohci_itd_list_head(struct fwohci_it_dmabuf *); 217 void fwohci_itd_clean(struct fwohci_it_dmabuf *); 218 int fwohci_itd_isfilled(struct fwohci_it_dmabuf *); 219 int fwohci_itd_hasdata(struct fwohci_it_dmabuf *); 220 int fwohci_itd_isfull(struct fwohci_it_dmabuf *); 221 #endif 222 #define fwohci_itd_list_head(itd) (itd)->itd_desc_phys 223 #define fwohci_itd_hasdata(itd) (itd)->itd_npacket 224 #define fwohci_itd_isfull(itd) \ 225 ((itd)->itd_npacket == (itd)->itd_maxpacket) 226 #define fwohci_itd_islocked(itd) \ 227 ((itd)->itd_flags & ITD_FLAGS_LOCK) 228 }; 229 230 231 struct fwohci_it_ctx { 232 struct fwohci_softc *itc_sc; 233 234 int itc_num; /* context number */ 235 236 volatile int itc_flags; /* flags */ 237 #define ITC_FLAGS_RUN 0x0001 238 239 int itc_channel; /* channel number */ 240 int itc_tag; /* tag */ 241 int itc_maxsize; /* maxmum data size for a packet */ 242 int itc_speed; /* speed */ 243 244 struct fwohci_it_dmabuf *itc_buf; /* array for fwohci_it_dmabuf */ 245 int itc_bufnum; /* const: num of elements in itc_buf array */ 246 247 #if 1 248 volatile struct fwohci_it_dmabuf *itc_buf_start; 249 struct fwohci_it_dmabuf *itc_buf_end; 250 struct fwohci_it_dmabuf *itc_buf_linkend; 251 #endif 252 volatile int16_t itc_buf_cnt; /* # buffers which contain data */ 253 #if 0 254 int16_t itc_bufidx_start; 255 int16_t itc_bufidx_end; 256 int16_t itc_bufidx_linkend; 257 #endif 258 259 /* data for descriptor */ 260 bus_dma_segment_t itc_dseg; 261 bus_dmamap_t itc_ddmamap; 262 int itc_descsize; /* count in byte */ 263 u_int8_t *itc_descmap; 264 int itc_dnsegs; 265 266 volatile u_int32_t *itc_scratch; /* descriptor decoder will write */ 267 u_int32_t itc_scratch_paddr; 268 269 volatile void *itc_waitchan; /* wait channel */ 270 271 int itc_outpkt; /* only for debugging */ 272 273 #if 0 274 struct fwohci_it_ctx *fwohci_it_ctx_construct(int); 275 void fwohci_it_ctx_destruct(struct fwohci_it_ctx *); 276 void fwohci_it_ctx_intr(struct fwohci_it_ctx *); 277 int fwohci_it_ctx_writedata(ieee1394_it_tag_t, int ndata, 278 struct ieee1394_it_datalist *); 279 private: 280 void fwohci_it_ctx_run(struct fwohci_it_ctx *itc); 281 void fwohci_it_intr(struct fwohci_softc *, struct fwohci_it_ctx *); 282 #endif 283 #define INC_BUF(itc, buf) \ 284 do { \ 285 if (++buf == (itc)->itc_buf + (itc)->itc_bufnum) { \ 286 buf = &(itc)->itc_buf[0]; \ 287 } \ 288 } while (0) 289 }; 290 291 struct fwohci_uidtbl { 292 int fu_valid; 293 u_int8_t fu_uid[8]; 294 }; 295 296 /* 297 * Needed to keep track of outstanding packets during a read op. Since the 298 * packet stream is asynch it's possible to parse a response packet before the 299 * ack bits are processed. In this case something needs to track whether the 300 * abuf is still valid before possibly attempting to use items from within it. 301 */ 302 303 struct fwohci_cb { 304 struct ieee1394_abuf *ab; 305 int count; 306 int abuf_valid; 307 }; 308 309 struct fwohci_softc { 310 struct ieee1394_softc sc_sc1394; 311 struct evcnt sc_intrcnt; 312 struct evcnt sc_isocnt; 313 struct evcnt sc_ascnt; 314 struct evcnt sc_itintrcnt; 315 316 bus_space_tag_t sc_memt; 317 bus_space_handle_t sc_memh; 318 bus_dma_tag_t sc_dmat; 319 bus_size_t sc_memsize; 320 #if 0 321 322 /* Mandatory structures to get the link enabled 323 */ 324 bus_dmamap_t sc_configrom_map; 325 bus_dmamap_t sc_selfid_map; 326 u_int32_t *sc_selfid_buf; 327 u_int32_t *sc_configrom; 328 #endif 329 330 bus_dma_segment_t sc_dseg; 331 int sc_dnseg; 332 bus_dmamap_t sc_ddmamap; 333 struct fwohci_desc *sc_desc; 334 u_int8_t *sc_descmap; 335 int sc_descsize; 336 int sc_isoctx; 337 int sc_itctx; 338 339 void *sc_shutdownhook; 340 void *sc_powerhook; 341 struct callout sc_selfid_callout; 342 int sc_selfid_fail; 343 344 struct fwohci_ctx *sc_ctx_arrq; 345 struct fwohci_ctx *sc_ctx_arrs; 346 struct fwohci_ctx *sc_ctx_atrq; 347 struct fwohci_ctx *sc_ctx_atrs; 348 struct fwohci_ctx **sc_ctx_as; /* previously sc_ctx_ir */ 349 struct fwohci_buf sc_buf_cnfrom; 350 struct fwohci_buf sc_buf_selfid; 351 352 struct fwohci_ir_ctx **sc_ctx_ir; 353 struct fwohci_it_ctx **sc_ctx_it; 354 355 struct proc *sc_event_thread; 356 357 int sc_dying; 358 u_int32_t sc_intmask; 359 u_int32_t sc_iso; 360 361 u_int8_t sc_csr[CSR_SB_END]; 362 363 struct fwohci_uidtbl *sc_uidtbl; 364 u_int16_t sc_nodeid; /* Full Node ID of this node */ 365 u_int8_t sc_rootid; /* Phy ID of Root */ 366 u_int8_t sc_irmid; /* Phy ID of IRM */ 367 u_int8_t sc_tlabel; /* Transaction Label */ 368 369 LIST_HEAD(, ieee1394_softc) sc_nodelist; 370 }; 371 372 int fwohci_init (struct fwohci_softc *, const struct evcnt *); 373 int fwohci_intr (void *); 374 int fwohci_print (void *, const char *); 375 int fwohci_detach(struct fwohci_softc *, int); 376 int fwohci_activate(struct device *, enum devact); 377 378 /* Macros to read and write the OHCI registers 379 */ 380 #define OHCI_CSR_WRITE(sc, reg, val) \ 381 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, reg, htole32(val)) 382 #define OHCI_CSR_READ(sc, reg) \ 383 le32toh(bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, reg)) 384 385 #define FWOHCI_CTX_ASYNC 0 386 #define FWOHCI_CTX_ISO_SINGLE 1 /* for async stream */ 387 #define FWOHCI_CTX_ISO_MULTI 2 /* for isochronous */ 388 389 /* Locators. */ 390 391 #include "locators.h" 392 393 #define fwbuscf_idhi cf_loc[FWBUSCF_IDHI] 394 #define FWBUS_UNK_IDHI FWBUSCF_IDHI_DEFAULT 395 396 #define fwbuscf_idlo cf_loc[FWBUSCF_IDLO] 397 #define FWBUS_UNK_IDLO FWBUSCF_IDLO_DEFAULT 398 399 #endif /* _DEV_IEEE1394_FWOHCIVAR_H_ */ 400
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