ad1848_isa.c revision 1.14
1 /* $NetBSD: ad1848_isa.c,v 1.14 2000/02/07 22:07:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ken Hornstein and John Kohl. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Copyright (c) 1994 John Brezak 40 * Copyright (c) 1991-1993 Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the Computer Systems 54 * Engineering Group at Lawrence Berkeley Laboratory. 55 * 4. Neither the name of the University nor of the Laboratory may be used 56 * to endorse or promote products derived from this software without 57 * specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 */ 72 73 /* 74 * Copyright by Hannu Savolainen 1994 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions are 78 * met: 1. Redistributions of source code must retain the above copyright 79 * notice, this list of conditions and the following disclaimer. 2. 80 * Redistributions in binary form must reproduce the above copyright notice, 81 * this list of conditions and the following disclaimer in the documentation 82 * and/or other materials provided with the distribution. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 85 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 86 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 87 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 88 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 */ 97 /* 98 * Portions of this code are from the VOXware support for the ad1848 99 * by Hannu Savolainen <hannu (at) voxware.pp.fi> 100 * 101 * Portions also supplied from the SoundBlaster driver for NetBSD. 102 */ 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/errno.h> 107 #include <sys/ioctl.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/proc.h> 111 #include <sys/buf.h> 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 116 #include <sys/audioio.h> 117 #include <vm/vm.h> 118 119 #include <dev/audio_if.h> 120 #include <dev/auconv.h> 121 122 #include <dev/isa/isavar.h> 123 #include <dev/isa/isadmavar.h> 124 125 #include <dev/ic/ad1848reg.h> 126 #include <dev/ic/cs4231reg.h> 127 #include <dev/ic/cs4237reg.h> 128 #include <dev/isa/ad1848var.h> 129 #include <dev/isa/cs4231var.h> 130 131 #ifdef AUDIO_DEBUG 132 #define DPRINTF(x) if (ad1848debug) printf x 133 extern int ad1848debug; 134 #else 135 #define DPRINTF(x) 136 #endif 137 138 static int ad1848_isa_read __P(( struct ad1848_softc *, int)); 139 static void ad1848_isa_write __P(( struct ad1848_softc *, int, int)); 140 141 int 142 ad1848_isa_read(sc, index) 143 struct ad1848_softc *sc; 144 int index; 145 { 146 return (bus_space_read_1(sc->sc_iot, sc->sc_ioh, index)); 147 } 148 149 void 150 ad1848_isa_write(sc, index, value) 151 struct ad1848_softc *sc; 152 int index; 153 int value; 154 { 155 bus_space_write_1(sc->sc_iot, sc->sc_ioh, index, value); 156 } 157 158 /* 159 * Map and probe for the ad1848 chip 160 */ 161 int 162 ad1848_isa_mapprobe(isc, iobase) 163 struct ad1848_isa_softc *isc; 164 int iobase; 165 { 166 struct ad1848_softc *sc = &isc->sc_ad1848; 167 168 if (!AD1848_BASE_VALID(iobase)) { 169 #ifdef AUDIO_DEBUG 170 printf("ad1848: configured iobase %04x invalid\n", iobase); 171 #endif 172 return 0; 173 } 174 175 /* Map the AD1848 ports */ 176 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 177 return 0; 178 179 if (!ad1848_isa_probe(isc)) { 180 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 181 return 0; 182 } else 183 return 1; 184 } 185 186 /* 187 * Probe for the ad1848 chip 188 */ 189 int 190 ad1848_isa_probe(isc) 191 struct ad1848_isa_softc *isc; 192 { 193 struct ad1848_softc *sc = &isc->sc_ad1848; 194 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 195 int i; 196 197 sc->sc_readreg = ad1848_isa_read; 198 sc->sc_writereg = ad1848_isa_write; 199 200 /* Is there an ad1848 chip ? */ 201 sc->MCE_bit = MODE_CHANGE_ENABLE; 202 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 203 204 /* 205 * Check that the I/O address is in use. 206 * 207 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 208 * chip has performed its power-on initialization. Just assume 209 * this has happened before the OS is starting. 210 * 211 * If the I/O address is unused, inb() typically returns 0xff. 212 */ 213 tmp = ADREAD(sc, AD1848_IADDR); 214 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 215 DPRINTF(("ad_detect_A %x\n", tmp)); 216 goto bad; 217 } 218 219 /* 220 * Test if it's possible to change contents of the indirect registers. 221 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read 222 * only so try to avoid using it. The bit 0x20 is the mic preamp 223 * enable; on some chips it is always the same in both registers, so 224 * we avoid tests where they are different. 225 */ 226 ad_write(sc, 0, 0x8a); 227 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 228 tmp1 = ad_read(sc, 0); 229 tmp2 = ad_read(sc, 1); 230 231 if (tmp1 != 0x8a || tmp2 != 0x45) { 232 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 233 goto bad; 234 } 235 236 ad_write(sc, 0, 0x65); 237 ad_write(sc, 1, 0xaa); 238 tmp1 = ad_read(sc, 0); 239 tmp2 = ad_read(sc, 1); 240 241 if (tmp1 != 0x65 || tmp2 != 0xaa) { 242 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 243 goto bad; 244 } 245 246 /* 247 * The indirect register I12 has some read only bits. Lets 248 * try to change them. 249 */ 250 tmp = ad_read(sc, SP_MISC_INFO); 251 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 252 253 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 254 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 255 goto bad; 256 } 257 258 /* 259 * MSB and 4 LSBs of the reg I12 tell the chip revision. 260 * 261 * A preliminary version of the AD1846 data sheet stated that it 262 * used an ID field of 0x0B. The current version, however, 263 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 264 * 265 * this switch statement will need updating as newer clones arrive.... 266 */ 267 switch (tmp1 & 0x8f) { 268 case 0x09: 269 sc->chip_name = "AD1848J"; 270 break; 271 case 0x0A: 272 sc->chip_name = "AD1848K"; 273 break; 274 #if 0 /* See above */ 275 case 0x0B: 276 sc->chip_name = "AD1846"; 277 break; 278 #endif 279 case 0x81: 280 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 281 break; 282 case 0x89: 283 sc->chip_name = "CS4248"; 284 break; 285 case 0x8A: 286 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 287 break; 288 default: 289 sc->chip_name = "unknown"; 290 DPRINTF(("ad1848: unknown codec version 0x%02x\n", 291 tmp1 & 0x8f)); 292 break; 293 } 294 295 /* 296 * The original AD1848/CS4248 has just 16 indirect registers. This 297 * means that I0 and I16 should return the same value (etc.). 298 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test 299 * fails with CS4231, AD1845, etc. 300 */ 301 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 302 303 for (i = 0; i < 16; i++) 304 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 305 if (i != SP_TEST_AND_INIT) { 306 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 307 goto bad; 308 } 309 } 310 311 /* 312 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 313 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 314 */ 315 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 316 317 tmp1 = ad_read(sc, SP_MISC_INFO); 318 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 319 /* 320 * CS4231 or AD1845 detected - is it? 321 * 322 * Verify that setting I2 doesn't change I18. 323 */ 324 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 325 326 ad_write(sc, 2, 0x45); 327 if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */ 328 ad_write(sc, 2, 0xaa); 329 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */ 330 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 331 goto bad; 332 } 333 334 sc->mode = 2; 335 336 /* 337 * It's a CS4231, or another clone with 32 registers. 338 * Let's find out which by checking I25. 339 */ 340 if ((tmp1 & 0x8f) == 0x8a) { 341 tmp1 = ad_read(sc, CS_VERSION_ID); 342 switch (tmp1 & 0xe7) { 343 case 0xA0: 344 sc->chip_name = "CS4231A"; 345 break; 346 case 0x80: 347 /* XXX I25 no good, AD1845 same as CS4231 */ 348 sc->chip_name = "CS4231 or AD1845"; 349 break; 350 case 0x82: 351 sc->chip_name = "CS4232"; 352 break; 353 case 0x03: 354 case 0x83: 355 sc->chip_name = "CS4236"; 356 357 /* 358 * Try to switch to mode3 (CS4236B or 359 * CS4237B) by setting CMS to 3. A 360 * plain CS4236 will not react to 361 * LLBM settings. 362 */ 363 ad_write(sc, SP_MISC_INFO, MODE3); 364 365 tmp1 = ad_read(sc, CS_LEFT_LINE_CONTROL); 366 ad_write(sc, CS_LEFT_LINE_CONTROL, 0xe0); 367 tmp2 = ad_read(sc, CS_LEFT_LINE_CONTROL); 368 if (tmp2 == 0xe0) { 369 /* 370 * it's a CS4237B or another 371 * clone supporting mode 3. 372 * Let's determine which by 373 * enabling extended registers 374 * and checking X25. 375 */ 376 tmp2 = ad_xread(sc, CS_X_CHIP_VERSION); 377 switch (tmp2 & X_CHIP_VERSIONF_CID) { 378 case X_CHIP_CID_CS4236BB: 379 sc->chip_name = "CS4236BrevB"; 380 break; 381 case X_CHIP_CID_CS4236B: 382 sc->chip_name = "CS4236B"; 383 break; 384 case X_CHIP_CID_CS4237B: 385 sc->chip_name = "CS4237B"; 386 break; 387 default: 388 sc->chip_name = "CS4236B compatible"; 389 DPRINTF(("cs4236: unknown mode 3 compatible codec, version 0x%02x\n", tmp2)); 390 break; 391 } 392 sc->mode = 3; 393 } 394 395 /* restore volume control information */ 396 ad_write(sc, CS_LEFT_LINE_CONTROL, tmp1); 397 break; 398 } 399 } 400 } 401 } 402 403 /* Wait for 1848 to init */ 404 while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 405 ; 406 407 /* Wait for 1848 to autocal */ 408 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 409 while(ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 410 ; 411 412 return 1; 413 bad: 414 return 0; 415 } 416 417 /* Unmap the I/O ports */ 418 void 419 ad1848_isa_unmap(isc) 420 struct ad1848_isa_softc *isc; 421 { 422 struct ad1848_softc *sc = &isc->sc_ad1848; 423 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 424 } 425 426 /* 427 * Attach hardware to driver, attach hardware driver to audio 428 * pseudo-device driver . 429 */ 430 void 431 ad1848_isa_attach(isc) 432 struct ad1848_isa_softc *isc; 433 { 434 struct ad1848_softc *sc = &isc->sc_ad1848; 435 436 sc->sc_readreg = ad1848_isa_read; 437 sc->sc_writereg = ad1848_isa_write; 438 439 if (isc->sc_playdrq != -1) 440 isc->sc_play_maxsize = isa_dmamaxsize(isc->sc_ic, 441 isc->sc_playdrq); 442 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 443 isc->sc_rec_maxsize = isa_dmamaxsize(isc->sc_ic, 444 isc->sc_recdrq); 445 446 ad1848_attach(sc); 447 } 448 449 int 450 ad1848_isa_open(addr, flags) 451 void *addr; 452 int flags; 453 { 454 struct ad1848_isa_softc *isc = addr; 455 struct ad1848_softc *sc = &isc->sc_ad1848; 456 int error, state; 457 458 DPRINTF(("ad1848_isa_open: sc=%p\n", isc)); 459 state = 0; 460 461 if (isc->sc_playdrq != -1) { 462 error = isa_dmamap_create(isc->sc_ic, isc->sc_playdrq, 463 isc->sc_play_maxsize, BUS_DMA_NOWAIT); 464 if (error) { 465 printf("%s: can't create map for drq %d\n", 466 sc->sc_dev.dv_xname, isc->sc_playdrq); 467 goto bad; 468 } 469 state |= 1; 470 } 471 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) { 472 error = isa_dmamap_create(isc->sc_ic, isc->sc_recdrq, 473 isc->sc_rec_maxsize, BUS_DMA_NOWAIT); 474 if (error) { 475 printf("%s: can't create map for drq %d\n", 476 sc->sc_dev.dv_xname, isc->sc_recdrq); 477 goto bad; 478 } 479 state |= 2; 480 } 481 482 #ifndef AUDIO_NO_POWER_CTL 483 /* Power-up chip */ 484 if (isc->powerctl) 485 isc->powerctl(isc->powerarg, flags); 486 #endif 487 488 /* Init and mute wave output */ 489 ad1848_mute_wave_output(sc, WAVE_MUTE2_INIT, 1); 490 491 error = ad1848_open(sc, flags); 492 if (error) { 493 #ifndef AUDIO_NO_POWER_CTL 494 if (isc->powerctl) 495 isc->powerctl(isc->powerarg, 0); 496 #endif 497 goto bad; 498 } 499 500 DPRINTF(("ad1848_isa_open: opened\n")); 501 return (0); 502 503 bad: 504 if (state & 1) 505 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 506 if (state & 2) 507 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 508 509 return (error); 510 } 511 512 /* 513 * Close function is called at splaudio(). 514 */ 515 void 516 ad1848_isa_close(addr) 517 void *addr; 518 { 519 struct ad1848_isa_softc *isc = addr; 520 struct ad1848_softc *sc = &isc->sc_ad1848; 521 522 ad1848_isa_halt_output(isc); 523 ad1848_isa_halt_input(isc); 524 525 isc->sc_intr = 0; 526 527 if (isc->sc_playdrq != -1) 528 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 529 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 530 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 531 532 DPRINTF(("ad1848_isa_close: stop DMA\n")); 533 ad1848_close(sc); 534 535 #ifndef AUDIO_NO_POWER_CTL 536 /* Power-down chip */ 537 if (isc->powerctl) 538 isc->powerctl(isc->powerarg, 0); 539 #endif 540 } 541 542 int 543 ad1848_isa_trigger_input(addr, start, end, blksize, intr, arg, param) 544 void *addr; 545 void *start, *end; 546 int blksize; 547 void (*intr) __P((void *)); 548 void *arg; 549 struct audio_params *param; 550 { 551 struct ad1848_isa_softc *isc = addr; 552 struct ad1848_softc *sc = &isc->sc_ad1848; 553 u_int8_t reg; 554 555 isa_dmastart(isc->sc_ic, isc->sc_recdrq, start, 556 (char *)end - (char *)start, NULL, 557 DMAMODE_READ | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 558 559 isc->sc_recrun = 1; 560 isc->sc_intr = intr; 561 isc->sc_arg = arg; 562 563 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 564 565 if (sc->mode >= 2) { 566 ad_write(sc, CS_LOWER_REC_CNT, blksize & 0xff); 567 ad_write(sc, CS_UPPER_REC_CNT, blksize >> 8); 568 } else { 569 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 570 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 571 } 572 573 reg = ad_read(sc, SP_INTERFACE_CONFIG); 574 ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg); 575 576 return (0); 577 } 578 579 int 580 ad1848_isa_trigger_output(addr, start, end, blksize, intr, arg, param) 581 void *addr; 582 void *start, *end; 583 int blksize; 584 void (*intr) __P((void *)); 585 void *arg; 586 struct audio_params *param; 587 { 588 struct ad1848_isa_softc *isc = addr; 589 struct ad1848_softc *sc = &isc->sc_ad1848; 590 u_int8_t reg; 591 592 isa_dmastart(isc->sc_ic, isc->sc_playdrq, start, 593 (char *)end - (char *)start, NULL, 594 DMAMODE_WRITE | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 595 596 isc->sc_playrun = 1; 597 isc->sc_intr = intr; 598 isc->sc_arg = arg; 599 600 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 601 602 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 603 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 604 605 /* Unmute wave output */ 606 ad1848_mute_wave_output(sc, WAVE_MUTE2, 0); 607 608 reg = ad_read(sc, SP_INTERFACE_CONFIG); 609 ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg); 610 611 return (0); 612 } 613 614 int 615 ad1848_isa_halt_input(addr) 616 void *addr; 617 { 618 struct ad1848_isa_softc *isc = addr; 619 struct ad1848_softc *sc = &isc->sc_ad1848; 620 621 if (isc->sc_recrun) { 622 ad1848_halt_input(sc); 623 isa_dmaabort(isc->sc_ic, isc->sc_recdrq); 624 isc->sc_recrun = 0; 625 } 626 627 return (0); 628 } 629 630 int 631 ad1848_isa_halt_output(addr) 632 void *addr; 633 { 634 struct ad1848_isa_softc *isc = addr; 635 struct ad1848_softc *sc = &isc->sc_ad1848; 636 637 if (isc->sc_playrun) { 638 /* Mute wave output */ 639 ad1848_mute_wave_output(sc, WAVE_MUTE2, 1); 640 641 ad1848_halt_output(sc); 642 isa_dmaabort(isc->sc_ic, isc->sc_playdrq); 643 isc->sc_playrun = 0; 644 } 645 646 return (0); 647 } 648 649 int 650 ad1848_isa_intr(arg) 651 void *arg; 652 { 653 struct ad1848_isa_softc *isc = arg; 654 struct ad1848_softc *sc = &isc->sc_ad1848; 655 int retval = 0; 656 u_char status; 657 658 /* Get intr status */ 659 status = ADREAD(sc, AD1848_STATUS); 660 661 #ifdef AUDIO_DEBUG 662 if (ad1848debug > 1) 663 printf("ad1848_isa_intr: intr=%p status=%x\n", isc->sc_intr, status); 664 #endif 665 isc->sc_interrupts++; 666 667 /* Handle interrupt */ 668 if (isc->sc_intr && (status & INTERRUPT_STATUS)) { 669 (*isc->sc_intr)(isc->sc_arg); 670 retval = 1; 671 } 672 673 /* clear interrupt */ 674 if (status & INTERRUPT_STATUS) 675 ADWRITE(sc, AD1848_STATUS, 0); 676 677 return(retval); 678 } 679 680 void * 681 ad1848_isa_malloc(addr, direction, size, pool, flags) 682 void *addr; 683 int direction; 684 size_t size; 685 int pool, flags; 686 { 687 struct ad1848_isa_softc *isc = addr; 688 int drq; 689 690 if (direction == AUMODE_PLAY) 691 drq = isc->sc_playdrq; 692 else 693 drq = isc->sc_recdrq; 694 return (isa_malloc(isc->sc_ic, drq, size, pool, flags)); 695 } 696 697 void 698 ad1848_isa_free(addr, ptr, pool) 699 void *addr; 700 void *ptr; 701 int pool; 702 { 703 isa_free(ptr, pool); 704 } 705 706 size_t 707 ad1848_isa_round_buffersize(addr, direction, size) 708 void *addr; 709 int direction; 710 size_t size; 711 { 712 struct ad1848_isa_softc *isc = addr; 713 bus_size_t maxsize; 714 715 if (direction == AUMODE_PLAY) 716 maxsize = isc->sc_play_maxsize; 717 else if (isc->sc_recdrq == isc->sc_playdrq) 718 maxsize = isc->sc_play_maxsize; 719 else 720 maxsize = isc->sc_rec_maxsize; 721 722 if (size > maxsize) 723 size = maxsize; 724 return (size); 725 } 726 727 int 728 ad1848_isa_mappage(addr, mem, off, prot) 729 void *addr; 730 void *mem; 731 int off; 732 int prot; 733 { 734 return isa_mappage(mem, off, prot); 735 } 736 737 int 738 ad1848_isa_get_props(addr) 739 void *addr; 740 { 741 struct ad1848_isa_softc *isc = addr; 742 743 return (AUDIO_PROP_MMAP | 744 (isc->sc_playdrq != isc->sc_recdrq ? AUDIO_PROP_FULLDUPLEX : 0)); 745 } 746
Indexes created Fri Sep 26 20:09:58 GMT 2025