ad1848_isa.c revision 1.17
1 /* $NetBSD: ad1848_isa.c,v 1.17 2000/12/18 21:31:32 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ken Hornstein and John Kohl. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Copyright (c) 1994 John Brezak 40 * Copyright (c) 1991-1993 Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the Computer Systems 54 * Engineering Group at Lawrence Berkeley Laboratory. 55 * 4. Neither the name of the University nor of the Laboratory may be used 56 * to endorse or promote products derived from this software without 57 * specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 */ 72 73 /* 74 * Copyright by Hannu Savolainen 1994 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions are 78 * met: 1. Redistributions of source code must retain the above copyright 79 * notice, this list of conditions and the following disclaimer. 2. 80 * Redistributions in binary form must reproduce the above copyright notice, 81 * this list of conditions and the following disclaimer in the documentation 82 * and/or other materials provided with the distribution. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 85 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 86 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 87 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 88 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 */ 97 /* 98 * Portions of this code are from the VOXware support for the ad1848 99 * by Hannu Savolainen <hannu (at) voxware.pp.fi> 100 * 101 * Portions also supplied from the SoundBlaster driver for NetBSD. 102 */ 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/errno.h> 107 #include <sys/ioctl.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/proc.h> 111 #include <sys/buf.h> 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 116 #include <sys/audioio.h> 117 118 #include <dev/audio_if.h> 119 #include <dev/auconv.h> 120 121 #include <dev/isa/isavar.h> 122 #include <dev/isa/isadmavar.h> 123 124 #include <dev/ic/ad1848reg.h> 125 #include <dev/ic/cs4231reg.h> 126 #include <dev/ic/cs4237reg.h> 127 #include <dev/isa/ad1848var.h> 128 #include <dev/isa/cs4231var.h> 129 130 #ifdef AUDIO_DEBUG 131 #define DPRINTF(x) if (ad1848debug) printf x 132 extern int ad1848debug; 133 #else 134 #define DPRINTF(x) 135 #endif 136 137 static int ad1848_isa_read __P(( struct ad1848_softc *, int)); 138 static void ad1848_isa_write __P(( struct ad1848_softc *, int, int)); 139 140 int 141 ad1848_isa_read(sc, index) 142 struct ad1848_softc *sc; 143 int index; 144 { 145 return (bus_space_read_1(sc->sc_iot, sc->sc_ioh, index)); 146 } 147 148 void 149 ad1848_isa_write(sc, index, value) 150 struct ad1848_softc *sc; 151 int index; 152 int value; 153 { 154 bus_space_write_1(sc->sc_iot, sc->sc_ioh, index, value); 155 } 156 157 /* 158 * Map and probe for the ad1848 chip 159 */ 160 int 161 ad1848_isa_mapprobe(isc, iobase) 162 struct ad1848_isa_softc *isc; 163 int iobase; 164 { 165 struct ad1848_softc *sc = &isc->sc_ad1848; 166 167 if (!AD1848_BASE_VALID(iobase)) { 168 #ifdef AUDIO_DEBUG 169 printf("ad1848: configured iobase %04x invalid\n", iobase); 170 #endif 171 return 0; 172 } 173 174 /* Map the AD1848 ports */ 175 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 176 return 0; 177 178 if (!ad1848_isa_probe(isc)) { 179 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 180 return 0; 181 } else 182 return 1; 183 } 184 185 /* 186 * Probe for the ad1848 chip 187 */ 188 int 189 ad1848_isa_probe(isc) 190 struct ad1848_isa_softc *isc; 191 { 192 struct ad1848_softc *sc = &isc->sc_ad1848; 193 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 194 int i; 195 196 sc->sc_readreg = ad1848_isa_read; 197 sc->sc_writereg = ad1848_isa_write; 198 199 /* Is there an ad1848 chip ? */ 200 sc->MCE_bit = MODE_CHANGE_ENABLE; 201 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 202 203 /* 204 * Check that the I/O address is in use. 205 * 206 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 207 * chip has performed its power-on initialization. Just assume 208 * this has happened before the OS is starting. 209 * 210 * If the I/O address is unused, inb() typically returns 0xff. 211 */ 212 tmp = ADREAD(sc, AD1848_IADDR); 213 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 214 DPRINTF(("ad_detect_A %x\n", tmp)); 215 goto bad; 216 } 217 218 /* 219 * Test if it's possible to change contents of the indirect registers. 220 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read 221 * only so try to avoid using it. The bit 0x20 is the mic preamp 222 * enable; on some chips it is always the same in both registers, so 223 * we avoid tests where they are different. 224 */ 225 ad_write(sc, 0, 0x8a); 226 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 227 tmp1 = ad_read(sc, 0); 228 tmp2 = ad_read(sc, 1); 229 230 if (tmp1 != 0x8a || tmp2 != 0x45) { 231 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 232 goto bad; 233 } 234 235 ad_write(sc, 0, 0x65); 236 ad_write(sc, 1, 0xaa); 237 tmp1 = ad_read(sc, 0); 238 tmp2 = ad_read(sc, 1); 239 240 if (tmp1 != 0x65 || tmp2 != 0xaa) { 241 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 242 goto bad; 243 } 244 245 /* 246 * The indirect register I12 has some read only bits. Lets 247 * try to change them. 248 */ 249 tmp = ad_read(sc, SP_MISC_INFO); 250 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 251 252 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 253 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 254 goto bad; 255 } 256 257 /* 258 * MSB and 4 LSBs of the reg I12 tell the chip revision. 259 * 260 * A preliminary version of the AD1846 data sheet stated that it 261 * used an ID field of 0x0B. The current version, however, 262 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 263 * 264 * this switch statement will need updating as newer clones arrive.... 265 */ 266 switch (tmp1 & 0x8f) { 267 case 0x09: 268 sc->chip_name = "AD1848J"; 269 break; 270 case 0x0A: 271 sc->chip_name = "AD1848K"; 272 break; 273 #if 0 /* See above */ 274 case 0x0B: 275 sc->chip_name = "AD1846"; 276 break; 277 #endif 278 case 0x81: 279 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 280 break; 281 case 0x89: 282 sc->chip_name = "CS4248"; 283 break; 284 case 0x8A: 285 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 286 break; 287 default: 288 sc->chip_name = "unknown"; 289 DPRINTF(("ad1848: unknown codec version 0x%02x\n", 290 tmp1 & 0x8f)); 291 break; 292 } 293 294 /* 295 * The original AD1848/CS4248 has just 16 indirect registers. This 296 * means that I0 and I16 should return the same value (etc.). 297 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test 298 * fails with CS4231, AD1845, etc. 299 */ 300 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 301 302 for (i = 0; i < 16; i++) 303 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 304 if (i != SP_TEST_AND_INIT) { 305 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 306 goto bad; 307 } 308 } 309 310 /* 311 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 312 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 313 */ 314 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 315 316 tmp1 = ad_read(sc, SP_MISC_INFO); 317 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 318 /* 319 * CS4231 or AD1845 detected - is it? 320 * 321 * Verify that setting I2 doesn't change I18. 322 */ 323 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 324 325 ad_write(sc, 2, 0x45); 326 if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */ 327 ad_write(sc, 2, 0xaa); 328 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */ 329 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 330 goto bad; 331 } 332 333 sc->mode = 2; 334 335 /* 336 * It's a CS4231, or another clone with 32 registers. 337 * Let's find out which by checking I25. 338 */ 339 if ((tmp1 & 0x8f) == 0x8a) { 340 tmp1 = ad_read(sc, CS_VERSION_ID); 341 switch (tmp1 & 0xe7) { 342 case 0xA0: 343 sc->chip_name = "CS4231A"; 344 break; 345 case 0x80: 346 /* XXX I25 no good, AD1845 same as CS4231 */ 347 sc->chip_name = "CS4231 or AD1845"; 348 break; 349 case 0x82: 350 sc->chip_name = "CS4232"; 351 break; 352 case 0x03: 353 case 0x83: 354 sc->chip_name = "CS4236"; 355 356 /* 357 * Try to switch to mode3 (CS4236B or 358 * CS4237B) by setting CMS to 3. A 359 * plain CS4236 will not react to 360 * LLBM settings. 361 */ 362 ad_write(sc, SP_MISC_INFO, MODE3); 363 364 tmp1 = ad_read(sc, CS_LEFT_LINE_CONTROL); 365 ad_write(sc, CS_LEFT_LINE_CONTROL, 0xe0); 366 tmp2 = ad_read(sc, CS_LEFT_LINE_CONTROL); 367 if (tmp2 == 0xe0) { 368 /* 369 * it's a CS4237B or another 370 * clone supporting mode 3. 371 * Let's determine which by 372 * enabling extended registers 373 * and checking X25. 374 */ 375 tmp2 = ad_xread(sc, CS_X_CHIP_VERSION); 376 switch (tmp2 & X_CHIP_VERSIONF_CID) { 377 case X_CHIP_CID_CS4236BB: 378 sc->chip_name = "CS4236BrevB"; 379 break; 380 case X_CHIP_CID_CS4236B: 381 sc->chip_name = "CS4236B"; 382 break; 383 case X_CHIP_CID_CS4237B: 384 sc->chip_name = "CS4237B"; 385 break; 386 default: 387 sc->chip_name = "CS4236B compatible"; 388 DPRINTF(("cs4236: unknown mode 3 compatible codec, version 0x%02x\n", tmp2)); 389 break; 390 } 391 sc->mode = 3; 392 } 393 394 /* restore volume control information */ 395 ad_write(sc, CS_LEFT_LINE_CONTROL, tmp1); 396 break; 397 } 398 } 399 } 400 } 401 402 /* Wait for 1848 to init */ 403 while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 404 ; 405 406 /* Wait for 1848 to autocal */ 407 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 408 while(ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 409 ; 410 411 return 1; 412 bad: 413 return 0; 414 } 415 416 /* Unmap the I/O ports */ 417 void 418 ad1848_isa_unmap(isc) 419 struct ad1848_isa_softc *isc; 420 { 421 struct ad1848_softc *sc = &isc->sc_ad1848; 422 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 423 } 424 425 /* 426 * Attach hardware to driver, attach hardware driver to audio 427 * pseudo-device driver . 428 */ 429 void 430 ad1848_isa_attach(isc) 431 struct ad1848_isa_softc *isc; 432 { 433 struct ad1848_softc *sc = &isc->sc_ad1848; 434 435 sc->sc_readreg = ad1848_isa_read; 436 sc->sc_writereg = ad1848_isa_write; 437 438 if (isc->sc_playdrq != -1) 439 isc->sc_play_maxsize = isa_dmamaxsize(isc->sc_ic, 440 isc->sc_playdrq); 441 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 442 isc->sc_rec_maxsize = isa_dmamaxsize(isc->sc_ic, 443 isc->sc_recdrq); 444 445 ad1848_attach(sc); 446 } 447 448 int 449 ad1848_isa_open(addr, flags) 450 void *addr; 451 int flags; 452 { 453 struct ad1848_isa_softc *isc = addr; 454 struct ad1848_softc *sc = &isc->sc_ad1848; 455 int error, state; 456 457 DPRINTF(("ad1848_isa_open: sc=%p\n", isc)); 458 state = 0; 459 460 if (isc->sc_playdrq != -1) { 461 error = isa_dmamap_create(isc->sc_ic, isc->sc_playdrq, 462 isc->sc_play_maxsize, BUS_DMA_NOWAIT); 463 if (error) { 464 printf("%s: can't create map for drq %d\n", 465 sc->sc_dev.dv_xname, isc->sc_playdrq); 466 goto bad; 467 } 468 state |= 1; 469 } 470 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) { 471 error = isa_dmamap_create(isc->sc_ic, isc->sc_recdrq, 472 isc->sc_rec_maxsize, BUS_DMA_NOWAIT); 473 if (error) { 474 printf("%s: can't create map for drq %d\n", 475 sc->sc_dev.dv_xname, isc->sc_recdrq); 476 goto bad; 477 } 478 state |= 2; 479 } 480 481 #ifndef AUDIO_NO_POWER_CTL 482 /* Power-up chip */ 483 if (isc->powerctl) 484 isc->powerctl(isc->powerarg, flags); 485 #endif 486 487 /* Init and mute wave output */ 488 ad1848_mute_wave_output(sc, WAVE_MUTE2_INIT, 1); 489 490 error = ad1848_open(sc, flags); 491 if (error) { 492 #ifndef AUDIO_NO_POWER_CTL 493 if (isc->powerctl) 494 isc->powerctl(isc->powerarg, 0); 495 #endif 496 goto bad; 497 } 498 499 DPRINTF(("ad1848_isa_open: opened\n")); 500 return (0); 501 502 bad: 503 if (state & 1) 504 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 505 if (state & 2) 506 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 507 508 return (error); 509 } 510 511 /* 512 * Close function is called at splaudio(). 513 */ 514 void 515 ad1848_isa_close(addr) 516 void *addr; 517 { 518 struct ad1848_isa_softc *isc = addr; 519 struct ad1848_softc *sc = &isc->sc_ad1848; 520 521 ad1848_isa_halt_output(isc); 522 ad1848_isa_halt_input(isc); 523 524 isc->sc_pintr = isc->sc_rintr = NULL; 525 526 if (isc->sc_playdrq != -1) 527 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 528 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 529 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 530 531 DPRINTF(("ad1848_isa_close: stop DMA\n")); 532 ad1848_close(sc); 533 534 #ifndef AUDIO_NO_POWER_CTL 535 /* Power-down chip */ 536 if (isc->powerctl) 537 isc->powerctl(isc->powerarg, 0); 538 #endif 539 } 540 541 int 542 ad1848_isa_trigger_input(addr, start, end, blksize, intr, arg, param) 543 void *addr; 544 void *start, *end; 545 int blksize; 546 void (*intr) __P((void *)); 547 void *arg; 548 struct audio_params *param; 549 { 550 struct ad1848_isa_softc *isc = addr; 551 struct ad1848_softc *sc = &isc->sc_ad1848; 552 u_int8_t reg; 553 554 isa_dmastart(isc->sc_ic, isc->sc_recdrq, start, 555 (char *)end - (char *)start, NULL, 556 DMAMODE_READ | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 557 558 isc->sc_recrun = 1; 559 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 560 isc->sc_rintr = intr; 561 isc->sc_rarg = arg; 562 } else { 563 isc->sc_pintr = intr; 564 isc->sc_parg = arg; 565 } 566 567 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 568 569 if (sc->mode >= 2) { 570 ad_write(sc, CS_LOWER_REC_CNT, blksize & 0xff); 571 ad_write(sc, CS_UPPER_REC_CNT, blksize >> 8); 572 } else { 573 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 574 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 575 } 576 577 reg = ad_read(sc, SP_INTERFACE_CONFIG); 578 ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg); 579 580 return (0); 581 } 582 583 int 584 ad1848_isa_trigger_output(addr, start, end, blksize, intr, arg, param) 585 void *addr; 586 void *start, *end; 587 int blksize; 588 void (*intr) __P((void *)); 589 void *arg; 590 struct audio_params *param; 591 { 592 struct ad1848_isa_softc *isc = addr; 593 struct ad1848_softc *sc = &isc->sc_ad1848; 594 u_int8_t reg; 595 596 isa_dmastart(isc->sc_ic, isc->sc_playdrq, start, 597 (char *)end - (char *)start, NULL, 598 DMAMODE_WRITE | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 599 600 isc->sc_playrun = 1; 601 isc->sc_pintr = intr; 602 isc->sc_parg = arg; 603 604 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 605 606 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 607 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 608 609 /* Unmute wave output */ 610 ad1848_mute_wave_output(sc, WAVE_MUTE2, 0); 611 612 reg = ad_read(sc, SP_INTERFACE_CONFIG); 613 ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg); 614 615 return (0); 616 } 617 618 int 619 ad1848_isa_halt_input(addr) 620 void *addr; 621 { 622 struct ad1848_isa_softc *isc = addr; 623 struct ad1848_softc *sc = &isc->sc_ad1848; 624 625 if (isc->sc_recrun) { 626 ad1848_halt_input(sc); 627 isa_dmaabort(isc->sc_ic, isc->sc_recdrq); 628 isc->sc_recrun = 0; 629 } 630 631 return (0); 632 } 633 634 int 635 ad1848_isa_halt_output(addr) 636 void *addr; 637 { 638 struct ad1848_isa_softc *isc = addr; 639 struct ad1848_softc *sc = &isc->sc_ad1848; 640 641 if (isc->sc_playrun) { 642 /* Mute wave output */ 643 ad1848_mute_wave_output(sc, WAVE_MUTE2, 1); 644 645 ad1848_halt_output(sc); 646 isa_dmaabort(isc->sc_ic, isc->sc_playdrq); 647 isc->sc_playrun = 0; 648 } 649 650 return (0); 651 } 652 653 int 654 ad1848_isa_intr(arg) 655 void *arg; 656 { 657 struct ad1848_isa_softc *isc = arg; 658 struct ad1848_softc *sc = &isc->sc_ad1848; 659 int retval = 0; 660 u_char status; 661 662 /* Get intr status */ 663 status = ADREAD(sc, AD1848_STATUS); 664 665 #ifdef AUDIO_DEBUG 666 if (ad1848debug > 1) 667 printf("ad1848_isa_intr: intr=%p status=%x\n", isc->sc_intr, status); 668 #endif 669 isc->sc_interrupts++; 670 671 /* Handle interrupt */ 672 if ((status & INTERRUPT_STATUS) != 0) { 673 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 674 status = ad_read(sc, CS_IRQ_STATUS); 675 if ((status & CS_IRQ_PI) && isc->sc_pintr != NULL) { 676 (*isc->sc_pintr)(isc->sc_parg); 677 retval = 1; 678 } 679 if ((status & CS_IRQ_CI) && isc->sc_rintr != NULL) { 680 (*isc->sc_rintr)(isc->sc_rarg); 681 retval = 1; 682 } 683 } else { 684 if (isc->sc_pintr != NULL) { 685 (*isc->sc_pintr)(isc->sc_parg); 686 retval = 1; 687 } 688 } 689 690 /* Clear interrupt */ 691 ADWRITE(sc, AD1848_STATUS, 0); 692 } 693 return(retval); 694 } 695 696 void * 697 ad1848_isa_malloc(addr, direction, size, pool, flags) 698 void *addr; 699 int direction; 700 size_t size; 701 int pool, flags; 702 { 703 struct ad1848_isa_softc *isc = addr; 704 int drq; 705 706 if (direction == AUMODE_PLAY) 707 drq = isc->sc_playdrq; 708 else 709 drq = isc->sc_recdrq; 710 return (isa_malloc(isc->sc_ic, drq, size, pool, flags)); 711 } 712 713 void 714 ad1848_isa_free(addr, ptr, pool) 715 void *addr; 716 void *ptr; 717 int pool; 718 { 719 isa_free(ptr, pool); 720 } 721 722 size_t 723 ad1848_isa_round_buffersize(addr, direction, size) 724 void *addr; 725 int direction; 726 size_t size; 727 { 728 struct ad1848_isa_softc *isc = addr; 729 bus_size_t maxsize; 730 731 if (direction == AUMODE_PLAY) 732 maxsize = isc->sc_play_maxsize; 733 else if (isc->sc_recdrq == isc->sc_playdrq) 734 maxsize = isc->sc_play_maxsize; 735 else 736 maxsize = isc->sc_rec_maxsize; 737 738 if (size > maxsize) 739 size = maxsize; 740 return (size); 741 } 742 743 paddr_t 744 ad1848_isa_mappage(addr, mem, off, prot) 745 void *addr; 746 void *mem; 747 off_t off; 748 int prot; 749 { 750 return isa_mappage(mem, off, prot); 751 } 752 753 int 754 ad1848_isa_get_props(addr) 755 void *addr; 756 { 757 struct ad1848_isa_softc *isc = addr; 758 759 return (AUDIO_PROP_MMAP | 760 (isc->sc_playdrq != isc->sc_recdrq ? AUDIO_PROP_FULLDUPLEX : 0)); 761 } 762
Indexes created Mon Sep 29 21:09:56 GMT 2025