ad1848_isa.c revision 1.19
1 /* $NetBSD: ad1848_isa.c,v 1.19 2001/11/04 08:08:26 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ken Hornstein and John Kohl. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Copyright (c) 1994 John Brezak 40 * Copyright (c) 1991-1993 Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the Computer Systems 54 * Engineering Group at Lawrence Berkeley Laboratory. 55 * 4. Neither the name of the University nor of the Laboratory may be used 56 * to endorse or promote products derived from this software without 57 * specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 */ 72 73 /* 74 * Copyright by Hannu Savolainen 1994 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions are 78 * met: 1. Redistributions of source code must retain the above copyright 79 * notice, this list of conditions and the following disclaimer. 2. 80 * Redistributions in binary form must reproduce the above copyright notice, 81 * this list of conditions and the following disclaimer in the documentation 82 * and/or other materials provided with the distribution. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 85 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 86 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 87 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 88 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 */ 97 /* 98 * Portions of this code are from the VOXware support for the ad1848 99 * by Hannu Savolainen <hannu (at) voxware.pp.fi> 100 * 101 * Portions also supplied from the SoundBlaster driver for NetBSD. 102 */ 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/errno.h> 107 #include <sys/ioctl.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/proc.h> 111 #include <sys/buf.h> 112 113 #include <machine/cpu.h> 114 #include <machine/bus.h> 115 116 #include <sys/audioio.h> 117 118 #include <dev/audio_if.h> 119 #include <dev/auconv.h> 120 121 #include <dev/isa/isavar.h> 122 #include <dev/isa/isadmavar.h> 123 124 #include <dev/ic/ad1848reg.h> 125 #include <dev/ic/cs4231reg.h> 126 #include <dev/ic/cs4237reg.h> 127 #include <dev/isa/ad1848var.h> 128 #include <dev/isa/cs4231var.h> 129 130 #ifdef AUDIO_DEBUG 131 #define DPRINTF(x) if (ad1848debug) printf x 132 extern int ad1848debug; 133 #else 134 #define DPRINTF(x) 135 #endif 136 137 static int ad1848_isa_read __P(( struct ad1848_softc *, int)); 138 static void ad1848_isa_write __P(( struct ad1848_softc *, int, int)); 139 140 int 141 ad1848_isa_read(sc, index) 142 struct ad1848_softc *sc; 143 int index; 144 { 145 return (bus_space_read_1(sc->sc_iot, sc->sc_ioh, index)); 146 } 147 148 void 149 ad1848_isa_write(sc, index, value) 150 struct ad1848_softc *sc; 151 int index; 152 int value; 153 { 154 bus_space_write_1(sc->sc_iot, sc->sc_ioh, index, value); 155 } 156 157 /* 158 * Map and probe for the ad1848 chip 159 */ 160 int 161 ad1848_isa_mapprobe(isc, iobase) 162 struct ad1848_isa_softc *isc; 163 int iobase; 164 { 165 struct ad1848_softc *sc = &isc->sc_ad1848; 166 167 if (!AD1848_BASE_VALID(iobase)) { 168 #ifdef AUDIO_DEBUG 169 printf("ad1848: configured iobase %04x invalid\n", iobase); 170 #endif 171 return 0; 172 } 173 174 /* Map the AD1848 ports */ 175 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 176 return 0; 177 178 if (!ad1848_isa_probe(isc)) { 179 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 180 return 0; 181 } else 182 return 1; 183 } 184 185 /* 186 * Probe for the ad1848 chip 187 */ 188 int 189 ad1848_isa_probe(isc) 190 struct ad1848_isa_softc *isc; 191 { 192 struct ad1848_softc *sc = &isc->sc_ad1848; 193 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 194 int i, t; 195 196 sc->sc_readreg = ad1848_isa_read; 197 sc->sc_writereg = ad1848_isa_write; 198 199 /* Is there an ad1848 chip ? */ 200 sc->MCE_bit = MODE_CHANGE_ENABLE; 201 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 202 203 /* 204 * Check that the I/O address is in use. 205 * 206 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 207 * chip has performed its power-on initialization. Just assume 208 * this has happened before the OS is starting. 209 * 210 * If the I/O address is unused, inb() typically returns 0xff. 211 */ 212 tmp = ADREAD(sc, AD1848_IADDR); 213 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 214 DPRINTF(("ad_detect_A %x\n", tmp)); 215 goto bad; 216 } 217 218 /* 219 * Test if it's possible to change contents of the indirect registers. 220 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read 221 * only so try to avoid using it. The bit 0x20 is the mic preamp 222 * enable; on some chips it is always the same in both registers, so 223 * we avoid tests where they are different. 224 */ 225 ad_write(sc, 0, 0x8a); 226 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 227 tmp1 = ad_read(sc, 0); 228 tmp2 = ad_read(sc, 1); 229 230 if (tmp1 != 0x8a || tmp2 != 0x45) { 231 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 232 goto bad; 233 } 234 235 ad_write(sc, 0, 0x65); 236 ad_write(sc, 1, 0xaa); 237 tmp1 = ad_read(sc, 0); 238 tmp2 = ad_read(sc, 1); 239 240 if (tmp1 != 0x65 || tmp2 != 0xaa) { 241 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 242 goto bad; 243 } 244 245 /* 246 * The indirect register I12 has some read only bits. Lets 247 * try to change them. 248 */ 249 tmp = ad_read(sc, SP_MISC_INFO); 250 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 251 252 /* Here, AD1845 may sometimes be busy. Wait til it becomes ready. */ 253 for (t = 0; t < 100000 && ADREAD(sc, AD1848_IADDR) & SP_IN_INIT; t++) 254 ; 255 #ifdef AUDIO_DEBUG 256 if (t) 257 DPRINTF(("ad1848_isa_probe: t %d\n", t)); 258 #endif 259 260 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 261 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 262 goto bad; 263 } 264 265 /* 266 * MSB and 4 LSBs of the reg I12 tell the chip revision. 267 * 268 * A preliminary version of the AD1846 data sheet stated that it 269 * used an ID field of 0x0B. The current version, however, 270 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 271 * 272 * this switch statement will need updating as newer clones arrive.... 273 */ 274 switch (tmp1 & 0x8f) { 275 case 0x09: 276 sc->chip_name = "AD1848J"; 277 break; 278 case 0x0A: 279 sc->chip_name = "AD1848K"; 280 break; 281 #if 0 /* See above */ 282 case 0x0B: 283 sc->chip_name = "AD1846"; 284 break; 285 #endif 286 case 0x81: 287 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 288 break; 289 case 0x89: 290 sc->chip_name = "CS4248"; 291 break; 292 case 0x8A: 293 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 294 break; 295 default: 296 sc->chip_name = "unknown"; 297 DPRINTF(("ad1848: unknown codec version 0x%02x\n", 298 tmp1 & 0x8f)); 299 break; 300 } 301 302 /* 303 * The original AD1848/CS4248 has just 16 indirect registers. This 304 * means that I0 and I16 should return the same value (etc.). 305 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test 306 * fails with CS4231, AD1845, etc. 307 */ 308 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 309 310 for (i = 0; i < 16; i++) 311 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 312 if (i != SP_TEST_AND_INIT) { 313 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 314 goto bad; 315 } 316 } 317 318 /* 319 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 320 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 321 */ 322 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 323 324 tmp1 = ad_read(sc, SP_MISC_INFO); 325 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 326 /* 327 * CS4231 or AD1845 detected - is it? 328 * 329 * Verify that setting I2 doesn't change I18. 330 */ 331 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 332 333 ad_write(sc, 2, 0x45); 334 if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */ 335 ad_write(sc, 2, 0xaa); 336 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */ 337 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 338 goto bad; 339 } 340 341 sc->mode = 2; 342 343 /* 344 * It's a CS4231, or another clone with 32 registers. 345 * Let's find out which by checking I25. 346 */ 347 if ((tmp1 & 0x8f) == 0x8a) { 348 tmp1 = ad_read(sc, CS_VERSION_ID); 349 switch (tmp1 & 0xe7) { 350 case 0xA0: 351 sc->chip_name = "CS4231A"; 352 break; 353 case 0x80: 354 /* XXX I25 no good, AD1845 same as CS4231 */ 355 /* 356 * XXX 357 * This test is correct only after reset 358 */ 359 if (ad_read(sc, 17) & 0xf0) { 360 sc->chip_name = "AD1845"; 361 sc->is_ad1845 = 1; 362 } else 363 sc->chip_name = "CS4231"; 364 break; 365 case 0x82: 366 sc->chip_name = "CS4232"; 367 break; 368 case 0x03: 369 case 0x83: 370 sc->chip_name = "CS4236"; 371 372 /* 373 * Try to switch to mode3 (CS4236B or 374 * CS4237B) by setting CMS to 3. A 375 * plain CS4236 will not react to 376 * LLBM settings. 377 */ 378 ad_write(sc, SP_MISC_INFO, MODE3); 379 380 tmp1 = ad_read(sc, CS_LEFT_LINE_CONTROL); 381 ad_write(sc, CS_LEFT_LINE_CONTROL, 0xe0); 382 tmp2 = ad_read(sc, CS_LEFT_LINE_CONTROL); 383 if (tmp2 == 0xe0) { 384 /* 385 * it's a CS4237B or another 386 * clone supporting mode 3. 387 * Let's determine which by 388 * enabling extended registers 389 * and checking X25. 390 */ 391 tmp2 = ad_xread(sc, CS_X_CHIP_VERSION); 392 switch (tmp2 & X_CHIP_VERSIONF_CID) { 393 case X_CHIP_CID_CS4236BB: 394 sc->chip_name = "CS4236BrevB"; 395 break; 396 case X_CHIP_CID_CS4236B: 397 sc->chip_name = "CS4236B"; 398 break; 399 case X_CHIP_CID_CS4237B: 400 sc->chip_name = "CS4237B"; 401 break; 402 default: 403 sc->chip_name = "CS4236B compatible"; 404 DPRINTF(("cs4236: unknown mode 3 compatible codec, version 0x%02x\n", tmp2)); 405 break; 406 } 407 sc->mode = 3; 408 } 409 410 /* restore volume control information */ 411 ad_write(sc, CS_LEFT_LINE_CONTROL, tmp1); 412 break; 413 } 414 } 415 } 416 } 417 418 /* Wait for 1848 to init */ 419 while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 420 ; 421 422 /* Wait for 1848 to autocal */ 423 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 424 while(ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 425 ; 426 427 return 1; 428 bad: 429 return 0; 430 } 431 432 /* Unmap the I/O ports */ 433 void 434 ad1848_isa_unmap(isc) 435 struct ad1848_isa_softc *isc; 436 { 437 struct ad1848_softc *sc = &isc->sc_ad1848; 438 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 439 } 440 441 /* 442 * Attach hardware to driver, attach hardware driver to audio 443 * pseudo-device driver . 444 */ 445 void 446 ad1848_isa_attach(isc) 447 struct ad1848_isa_softc *isc; 448 { 449 struct ad1848_softc *sc = &isc->sc_ad1848; 450 451 sc->sc_readreg = ad1848_isa_read; 452 sc->sc_writereg = ad1848_isa_write; 453 454 if (isc->sc_playdrq != -1) 455 isc->sc_play_maxsize = isa_dmamaxsize(isc->sc_ic, 456 isc->sc_playdrq); 457 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 458 isc->sc_rec_maxsize = isa_dmamaxsize(isc->sc_ic, 459 isc->sc_recdrq); 460 461 ad1848_attach(sc); 462 } 463 464 int 465 ad1848_isa_open(addr, flags) 466 void *addr; 467 int flags; 468 { 469 struct ad1848_isa_softc *isc = addr; 470 struct ad1848_softc *sc = &isc->sc_ad1848; 471 int error, state; 472 473 DPRINTF(("ad1848_isa_open: sc=%p\n", isc)); 474 state = 0; 475 476 if (isc->sc_playdrq != -1) { 477 error = isa_dmamap_create(isc->sc_ic, isc->sc_playdrq, 478 isc->sc_play_maxsize, BUS_DMA_NOWAIT); 479 if (error) { 480 printf("%s: can't create map for drq %d\n", 481 sc->sc_dev.dv_xname, isc->sc_playdrq); 482 goto bad; 483 } 484 state |= 1; 485 } 486 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) { 487 error = isa_dmamap_create(isc->sc_ic, isc->sc_recdrq, 488 isc->sc_rec_maxsize, BUS_DMA_NOWAIT); 489 if (error) { 490 printf("%s: can't create map for drq %d\n", 491 sc->sc_dev.dv_xname, isc->sc_recdrq); 492 goto bad; 493 } 494 state |= 2; 495 } 496 497 #ifndef AUDIO_NO_POWER_CTL 498 /* Power-up chip */ 499 if (isc->powerctl) 500 isc->powerctl(isc->powerarg, flags); 501 #endif 502 503 /* Init and mute wave output */ 504 ad1848_mute_wave_output(sc, WAVE_MUTE2_INIT, 1); 505 506 error = ad1848_open(sc, flags); 507 if (error) { 508 #ifndef AUDIO_NO_POWER_CTL 509 if (isc->powerctl) 510 isc->powerctl(isc->powerarg, 0); 511 #endif 512 goto bad; 513 } 514 515 DPRINTF(("ad1848_isa_open: opened\n")); 516 return (0); 517 518 bad: 519 if (state & 1) 520 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 521 if (state & 2) 522 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 523 524 return (error); 525 } 526 527 /* 528 * Close function is called at splaudio(). 529 */ 530 void 531 ad1848_isa_close(addr) 532 void *addr; 533 { 534 struct ad1848_isa_softc *isc = addr; 535 struct ad1848_softc *sc = &isc->sc_ad1848; 536 537 ad1848_isa_halt_output(isc); 538 ad1848_isa_halt_input(isc); 539 540 isc->sc_pintr = isc->sc_rintr = NULL; 541 542 if (isc->sc_playdrq != -1) 543 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 544 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 545 isa_dmamap_destroy(isc->sc_ic, isc->sc_recdrq); 546 547 DPRINTF(("ad1848_isa_close: stop DMA\n")); 548 ad1848_close(sc); 549 550 #ifndef AUDIO_NO_POWER_CTL 551 /* Power-down chip */ 552 if (isc->powerctl) 553 isc->powerctl(isc->powerarg, 0); 554 #endif 555 } 556 557 int 558 ad1848_isa_trigger_input(addr, start, end, blksize, intr, arg, param) 559 void *addr; 560 void *start, *end; 561 int blksize; 562 void (*intr) __P((void *)); 563 void *arg; 564 struct audio_params *param; 565 { 566 struct ad1848_isa_softc *isc = addr; 567 struct ad1848_softc *sc = &isc->sc_ad1848; 568 u_int8_t reg; 569 570 isa_dmastart(isc->sc_ic, isc->sc_recdrq, start, 571 (char *)end - (char *)start, NULL, 572 DMAMODE_READ | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 573 574 isc->sc_recrun = 1; 575 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 576 isc->sc_rintr = intr; 577 isc->sc_rarg = arg; 578 } else { 579 isc->sc_pintr = intr; 580 isc->sc_parg = arg; 581 } 582 583 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 584 585 if (sc->mode >= 2) { 586 ad_write(sc, CS_LOWER_REC_CNT, blksize & 0xff); 587 ad_write(sc, CS_UPPER_REC_CNT, blksize >> 8); 588 } else { 589 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 590 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 591 } 592 593 reg = ad_read(sc, SP_INTERFACE_CONFIG); 594 ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg); 595 596 return (0); 597 } 598 599 int 600 ad1848_isa_trigger_output(addr, start, end, blksize, intr, arg, param) 601 void *addr; 602 void *start, *end; 603 int blksize; 604 void (*intr) __P((void *)); 605 void *arg; 606 struct audio_params *param; 607 { 608 struct ad1848_isa_softc *isc = addr; 609 struct ad1848_softc *sc = &isc->sc_ad1848; 610 u_int8_t reg; 611 612 isa_dmastart(isc->sc_ic, isc->sc_playdrq, start, 613 (char *)end - (char *)start, NULL, 614 DMAMODE_WRITE | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 615 616 isc->sc_playrun = 1; 617 isc->sc_pintr = intr; 618 isc->sc_parg = arg; 619 620 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 621 622 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 623 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 624 625 /* Unmute wave output */ 626 ad1848_mute_wave_output(sc, WAVE_MUTE2, 0); 627 628 reg = ad_read(sc, SP_INTERFACE_CONFIG); 629 ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg); 630 631 return (0); 632 } 633 634 int 635 ad1848_isa_halt_input(addr) 636 void *addr; 637 { 638 struct ad1848_isa_softc *isc = addr; 639 struct ad1848_softc *sc = &isc->sc_ad1848; 640 641 if (isc->sc_recrun) { 642 ad1848_halt_input(sc); 643 isa_dmaabort(isc->sc_ic, isc->sc_recdrq); 644 isc->sc_recrun = 0; 645 } 646 647 return (0); 648 } 649 650 int 651 ad1848_isa_halt_output(addr) 652 void *addr; 653 { 654 struct ad1848_isa_softc *isc = addr; 655 struct ad1848_softc *sc = &isc->sc_ad1848; 656 657 if (isc->sc_playrun) { 658 /* Mute wave output */ 659 ad1848_mute_wave_output(sc, WAVE_MUTE2, 1); 660 661 ad1848_halt_output(sc); 662 isa_dmaabort(isc->sc_ic, isc->sc_playdrq); 663 isc->sc_playrun = 0; 664 } 665 666 return (0); 667 } 668 669 int 670 ad1848_isa_intr(arg) 671 void *arg; 672 { 673 struct ad1848_isa_softc *isc = arg; 674 struct ad1848_softc *sc = &isc->sc_ad1848; 675 int retval = 0; 676 u_char status; 677 678 /* Get intr status */ 679 status = ADREAD(sc, AD1848_STATUS); 680 681 #ifdef AUDIO_DEBUG 682 if (ad1848debug > 1) 683 printf("ad1848_isa_intr: pintr=%p rintr=%p status=%x\n", 684 isc->sc_pintr, isc->sc_rintr, status); 685 #endif 686 isc->sc_interrupts++; 687 688 /* Handle interrupt */ 689 if ((status & INTERRUPT_STATUS) != 0) { 690 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 691 status = ad_read(sc, CS_IRQ_STATUS); 692 if ((status & CS_IRQ_PI) && isc->sc_pintr != NULL) { 693 (*isc->sc_pintr)(isc->sc_parg); 694 retval = 1; 695 } 696 if ((status & CS_IRQ_CI) && isc->sc_rintr != NULL) { 697 (*isc->sc_rintr)(isc->sc_rarg); 698 retval = 1; 699 } 700 } else { 701 if (isc->sc_pintr != NULL) { 702 (*isc->sc_pintr)(isc->sc_parg); 703 retval = 1; 704 } 705 } 706 707 /* Clear interrupt */ 708 ADWRITE(sc, AD1848_STATUS, 0); 709 } 710 return(retval); 711 } 712 713 void * 714 ad1848_isa_malloc(addr, direction, size, pool, flags) 715 void *addr; 716 int direction; 717 size_t size; 718 int pool, flags; 719 { 720 struct ad1848_isa_softc *isc = addr; 721 int drq; 722 723 if (direction == AUMODE_PLAY) 724 drq = isc->sc_playdrq; 725 else 726 drq = isc->sc_recdrq; 727 return (isa_malloc(isc->sc_ic, drq, size, pool, flags)); 728 } 729 730 void 731 ad1848_isa_free(addr, ptr, pool) 732 void *addr; 733 void *ptr; 734 int pool; 735 { 736 isa_free(ptr, pool); 737 } 738 739 size_t 740 ad1848_isa_round_buffersize(addr, direction, size) 741 void *addr; 742 int direction; 743 size_t size; 744 { 745 struct ad1848_isa_softc *isc = addr; 746 bus_size_t maxsize; 747 748 if (direction == AUMODE_PLAY) 749 maxsize = isc->sc_play_maxsize; 750 else if (isc->sc_recdrq == isc->sc_playdrq) 751 maxsize = isc->sc_play_maxsize; 752 else 753 maxsize = isc->sc_rec_maxsize; 754 755 if (size > maxsize) 756 size = maxsize; 757 return (size); 758 } 759 760 paddr_t 761 ad1848_isa_mappage(addr, mem, off, prot) 762 void *addr; 763 void *mem; 764 off_t off; 765 int prot; 766 { 767 return isa_mappage(mem, off, prot); 768 } 769 770 int 771 ad1848_isa_get_props(addr) 772 void *addr; 773 { 774 struct ad1848_isa_softc *isc = addr; 775 776 return (AUDIO_PROP_MMAP | 777 (isc->sc_playdrq != isc->sc_recdrq ? AUDIO_PROP_FULLDUPLEX : 0)); 778 } 779
Indexes created Mon Sep 29 21:09:56 GMT 2025