ad1848_isa.c revision 1.33.16.1
1 /* $NetBSD: ad1848_isa.c,v 1.33.16.1 2008/06/02 13:23:29 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ken Hornstein and John Kohl. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Copyright (c) 1994 John Brezak 33 * Copyright (c) 1991-1993 Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the Computer Systems 47 * Engineering Group at Lawrence Berkeley Laboratory. 48 * 4. Neither the name of the University nor of the Laboratory may be used 49 * to endorse or promote products derived from this software without 50 * specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 */ 65 66 /* 67 * Copyright by Hannu Savolainen 1994 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions are 71 * met: 1. Redistributions of source code must retain the above copyright 72 * notice, this list of conditions and the following disclaimer. 2. 73 * Redistributions in binary form must reproduce the above copyright notice, 74 * this list of conditions and the following disclaimer in the documentation 75 * and/or other materials provided with the distribution. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 78 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 79 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 80 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 81 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 82 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 83 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 84 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 85 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 86 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 87 * SUCH DAMAGE. 88 * 89 */ 90 /* 91 * Portions of this code are from the VOXware support for the ad1848 92 * by Hannu Savolainen <hannu (at) voxware.pp.fi> 93 * 94 * Portions also supplied from the SoundBlaster driver for NetBSD. 95 */ 96 97 #include <sys/cdefs.h> 98 __KERNEL_RCSID(0, "$NetBSD: ad1848_isa.c,v 1.33.16.1 2008/06/02 13:23:29 mjf Exp $"); 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/errno.h> 103 #include <sys/ioctl.h> 104 #include <sys/syslog.h> 105 #include <sys/device.h> 106 #include <sys/proc.h> 107 #include <sys/buf.h> 108 109 #include <sys/cpu.h> 110 #include <sys/bus.h> 111 112 #include <sys/audioio.h> 113 114 #include <dev/audio_if.h> 115 #include <dev/auconv.h> 116 117 #include <dev/isa/isavar.h> 118 #include <dev/isa/isadmavar.h> 119 120 #include <dev/ic/ad1848reg.h> 121 #include <dev/ic/cs4231reg.h> 122 #include <dev/ic/cs4237reg.h> 123 #include <dev/isa/ad1848var.h> 124 #include <dev/isa/cs4231var.h> 125 126 #ifdef AUDIO_DEBUG 127 #define DPRINTF(x) if (ad1848debug) printf x 128 extern int ad1848debug; 129 #else 130 #define DPRINTF(x) 131 #endif 132 133 static int ad1848_isa_read( struct ad1848_softc *, int); 134 static void ad1848_isa_write( struct ad1848_softc *, int, int); 135 136 int 137 ad1848_isa_read(struct ad1848_softc *sc, int index) 138 { 139 140 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, index); 141 } 142 143 void 144 ad1848_isa_write(struct ad1848_softc *sc, int index, int value) 145 { 146 147 bus_space_write_1(sc->sc_iot, sc->sc_ioh, index, value); 148 } 149 150 /* 151 * Map and probe for the ad1848 chip 152 */ 153 int 154 ad1848_isa_mapprobe(struct ad1848_isa_softc *isc, int iobase) 155 { 156 struct ad1848_softc *sc; 157 158 sc = &isc->sc_ad1848; 159 if (!AD1848_BASE_VALID(iobase)) { 160 #ifdef AUDIO_DEBUG 161 printf("ad1848: configured iobase %04x invalid\n", iobase); 162 #endif 163 return 0; 164 } 165 166 /* Map the AD1848 ports */ 167 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 168 return 0; 169 170 if (!ad1848_isa_probe(isc)) { 171 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 172 return 0; 173 } else 174 return 1; 175 } 176 177 /* 178 * Probe for the ad1848 chip 179 */ 180 int 181 ad1848_isa_probe(struct ad1848_isa_softc *isc) 182 { 183 struct ad1848_softc *sc; 184 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 185 int i, t; 186 187 sc = &isc->sc_ad1848; 188 sc->sc_readreg = ad1848_isa_read; 189 sc->sc_writereg = ad1848_isa_write; 190 191 /* Is there an ad1848 chip ? */ 192 sc->MCE_bit = MODE_CHANGE_ENABLE; 193 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 194 195 /* 196 * Check that the I/O address is in use. 197 * 198 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 199 * chip has performed its power-on initialization. Just assume 200 * this has happened before the OS is starting. 201 * 202 * If the I/O address is unused, inb() typically returns 0xff. 203 */ 204 tmp = ADREAD(sc, AD1848_IADDR); 205 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 206 DPRINTF(("ad_detect_A %x\n", tmp)); 207 goto bad; 208 } 209 210 /* 211 * Test if it's possible to change contents of the indirect registers. 212 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read 213 * only so try to avoid using it. The bit 0x20 is the mic preamp 214 * enable; on some chips it is always the same in both registers, so 215 * we avoid tests where they are different. 216 */ 217 ad_write(sc, 0, 0x8a); 218 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 219 tmp1 = ad_read(sc, 0); 220 tmp2 = ad_read(sc, 1); 221 222 if (tmp1 != 0x8a || tmp2 != 0x45) { 223 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 224 goto bad; 225 } 226 227 ad_write(sc, 0, 0x65); 228 ad_write(sc, 1, 0xaa); 229 tmp1 = ad_read(sc, 0); 230 tmp2 = ad_read(sc, 1); 231 232 if (tmp1 != 0x65 || tmp2 != 0xaa) { 233 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 234 goto bad; 235 } 236 237 /* 238 * The indirect register I12 has some read only bits. Lets 239 * try to change them. 240 */ 241 tmp = ad_read(sc, SP_MISC_INFO); 242 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 243 244 /* Here, AD1845 may sometimes be busy. Wait til it becomes ready. */ 245 for (t = 0; t < 100000 && ADREAD(sc, AD1848_IADDR) & SP_IN_INIT; t++) 246 ; 247 #ifdef AUDIO_DEBUG 248 if (t) 249 DPRINTF(("ad1848_isa_probe: t %d\n", t)); 250 #endif 251 252 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 253 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 254 goto bad; 255 } 256 257 /* 258 * MSB and 4 LSBs of the reg I12 tell the chip revision. 259 * 260 * A preliminary version of the AD1846 data sheet stated that it 261 * used an ID field of 0x0B. The current version, however, 262 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 263 * 264 * this switch statement will need updating as newer clones arrive.... 265 */ 266 switch (tmp1 & 0x8f) { 267 case 0x09: 268 sc->chip_name = "AD1848J"; 269 break; 270 case 0x0A: 271 sc->chip_name = "AD1848K"; 272 break; 273 #if 0 /* See above */ 274 case 0x0B: 275 sc->chip_name = "AD1846"; 276 break; 277 #endif 278 case 0x81: 279 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 280 break; 281 case 0x89: 282 sc->chip_name = "CS4248"; 283 break; 284 case 0x8A: 285 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 286 break; 287 default: 288 sc->chip_name = "unknown"; 289 DPRINTF(("ad1848: unknown codec version 0x%02x\n", 290 tmp1 & 0x8f)); 291 break; 292 } 293 294 /* 295 * The original AD1848/CS4248 has just 16 indirect registers. This 296 * means that I0 and I16 should return the same value (etc.). 297 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test 298 * fails with CS4231, AD1845, etc. 299 */ 300 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 301 302 for (i = 0; i < 16; i++) 303 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 304 if (i != SP_TEST_AND_INIT) { 305 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 306 goto bad; 307 } 308 } 309 310 /* 311 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 312 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 313 */ 314 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 315 316 tmp1 = ad_read(sc, SP_MISC_INFO); 317 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 318 /* 319 * CS4231 or AD1845 detected - is it? 320 * 321 * Verify that setting I2 doesn't change I18. 322 */ 323 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 324 325 ad_write(sc, 2, 0x45); 326 if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */ 327 ad_write(sc, 2, 0xaa); 328 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */ 329 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 330 goto bad; 331 } 332 333 sc->mode = 2; 334 335 /* 336 * It's a CS4231, or another clone with 32 registers. 337 * Let's find out which by checking I25. 338 */ 339 if ((tmp1 & 0x8f) == 0x8a) { 340 tmp1 = ad_read(sc, CS_VERSION_ID); 341 switch (tmp1 & 0xe7) { 342 case 0xA0: 343 sc->chip_name = "CS4231A"; 344 break; 345 case 0x80: 346 /* XXX I25 no good, AD1845 same as CS4231 */ 347 /* 348 * XXX 349 * This test is correct only after reset 350 */ 351 if (ad_read(sc, 17) & 0xf0) { 352 sc->chip_name = "AD1845"; 353 sc->is_ad1845 = 1; 354 } else 355 sc->chip_name = "CS4231"; 356 break; 357 case 0x82: 358 sc->chip_name = "CS4232"; 359 break; 360 case 0xa2: 361 sc->chip_name = "CS4232C"; 362 break; 363 case 0x03: 364 case 0x83: 365 sc->chip_name = "CS4236"; 366 367 /* 368 * Try to switch to mode3 (CS4236B or 369 * CS4237B) by setting CMS to 3. A 370 * plain CS4236 will not react to 371 * LLBM settings. 372 */ 373 ad_write(sc, SP_MISC_INFO, MODE3); 374 375 tmp1 = ad_read(sc, CS_LEFT_LINE_CONTROL); 376 ad_write(sc, CS_LEFT_LINE_CONTROL, 0xe0); 377 tmp2 = ad_read(sc, CS_LEFT_LINE_CONTROL); 378 if (tmp2 == 0xe0) { 379 /* 380 * it's a CS4237B or another 381 * clone supporting mode 3. 382 * Let's determine which by 383 * enabling extended registers 384 * and checking X25. 385 */ 386 tmp2 = ad_xread(sc, CS_X_CHIP_VERSION); 387 switch (tmp2 & X_CHIP_VERSIONF_CID) { 388 case X_CHIP_CID_CS4236BB: 389 sc->chip_name = "CS4236BrevB"; 390 break; 391 case X_CHIP_CID_CS4236B: 392 sc->chip_name = "CS4236B"; 393 break; 394 case X_CHIP_CID_CS4237B: 395 sc->chip_name = "CS4237B"; 396 break; 397 default: 398 sc->chip_name = "CS4236B compatible"; 399 DPRINTF(("cs4236: unknown mode 3 compatible codec, version 0x%02x\n", tmp2)); 400 break; 401 } 402 sc->mode = 3; 403 } 404 405 /* restore volume control information */ 406 ad_write(sc, CS_LEFT_LINE_CONTROL, tmp1); 407 break; 408 } 409 } 410 } 411 } 412 413 /* Wait for 1848 to init */ 414 while (ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 415 ; 416 417 /* Wait for 1848 to autocal */ 418 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 419 while (ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 420 ; 421 422 return 1; 423 bad: 424 return 0; 425 } 426 427 /* Unmap the I/O ports */ 428 void 429 ad1848_isa_unmap(struct ad1848_isa_softc *isc) 430 { 431 struct ad1848_softc *sc; 432 433 sc = &isc->sc_ad1848; 434 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 435 } 436 437 /* 438 * Attach hardware to driver, attach hardware driver to audio 439 * pseudo-device driver . 440 */ 441 void 442 ad1848_isa_attach(struct ad1848_isa_softc *isc) 443 { 444 struct ad1848_softc *sc; 445 int error; 446 447 sc = &isc->sc_ad1848; 448 sc->sc_readreg = ad1848_isa_read; 449 sc->sc_writereg = ad1848_isa_write; 450 451 if (isc->sc_playdrq != -1) { 452 isc->sc_play_maxsize = isa_dmamaxsize(isc->sc_ic, 453 isc->sc_playdrq); 454 error = isa_dmamap_create(isc->sc_ic, isc->sc_playdrq, 455 isc->sc_play_maxsize, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW); 456 if (error) { 457 aprint_error_dev(&sc->sc_dev, "can't create map for drq %d\n", 458 isc->sc_playdrq); 459 return; 460 } 461 } 462 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) { 463 isc->sc_rec_maxsize = isa_dmamaxsize(isc->sc_ic, 464 isc->sc_recdrq); 465 error = isa_dmamap_create(isc->sc_ic, isc->sc_recdrq, 466 isc->sc_rec_maxsize, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW); 467 if (error) { 468 aprint_error_dev(&sc->sc_dev, "can't create map for drq %d\n", 469 isc->sc_recdrq); 470 isa_dmamap_destroy(isc->sc_ic, isc->sc_playdrq); 471 return; 472 } 473 } 474 475 ad1848_attach(sc); 476 } 477 478 int 479 ad1848_isa_open(void *addr, int flags) 480 { 481 struct ad1848_isa_softc *isc; 482 struct ad1848_softc *sc; 483 int error, state; 484 485 isc = addr; 486 sc = &isc->sc_ad1848; 487 DPRINTF(("ad1848_isa_open: sc=%p\n", isc)); 488 state = 0; 489 490 if (isc->sc_playdrq != -1) { 491 error = isa_drq_alloc(isc->sc_ic, isc->sc_playdrq); 492 if (error != 0) 493 return EBUSY; 494 state |= 1; 495 } 496 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) { 497 error = isa_drq_alloc(isc->sc_ic, isc->sc_recdrq); 498 if (error != 0) 499 goto bad; 500 state |= 2; 501 } 502 503 #ifndef AUDIO_NO_POWER_CTL 504 /* Power-up chip */ 505 if (isc->powerctl) 506 isc->powerctl(isc->powerarg, flags); 507 #endif 508 509 /* Init and mute wave output */ 510 ad1848_mute_wave_output(sc, WAVE_MUTE2_INIT, 1); 511 512 error = ad1848_open(sc, flags); 513 if (error) { 514 #ifndef AUDIO_NO_POWER_CTL 515 if (isc->powerctl) 516 isc->powerctl(isc->powerarg, 0); 517 #endif 518 goto bad; 519 } 520 521 DPRINTF(("ad1848_isa_open: opened\n")); 522 return 0; 523 524 bad: 525 if (state & 1) 526 isa_drq_free(isc->sc_ic, isc->sc_playdrq); 527 if (state & 2) 528 isa_drq_free(isc->sc_ic, isc->sc_recdrq); 529 530 return error; 531 } 532 533 /* 534 * Close function is called at splaudio(). 535 */ 536 void 537 ad1848_isa_close(void *addr) 538 { 539 struct ad1848_isa_softc *isc; 540 struct ad1848_softc *sc; 541 542 DPRINTF(("ad1848_isa_close: stop DMA\n")); 543 isc = addr; 544 sc = &isc->sc_ad1848; 545 ad1848_close(sc); 546 547 #ifndef AUDIO_NO_POWER_CTL 548 /* Power-down chip */ 549 if (isc->powerctl) 550 isc->powerctl(isc->powerarg, 0); 551 #endif 552 553 if (isc->sc_playdrq != -1) 554 isa_drq_free(isc->sc_ic, isc->sc_playdrq); 555 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) 556 isa_drq_free(isc->sc_ic, isc->sc_recdrq); 557 } 558 559 int 560 ad1848_isa_trigger_input( 561 void *addr, 562 void *start, void *end, 563 int blksize, 564 void (*intr)(void *), 565 void *arg, 566 const audio_params_t *param) 567 { 568 struct ad1848_isa_softc *isc; 569 struct ad1848_softc *sc; 570 uint8_t reg; 571 572 isc = addr; 573 sc = &isc->sc_ad1848; 574 isa_dmastart(isc->sc_ic, isc->sc_recdrq, start, 575 (char *)end - (char *)start, NULL, 576 DMAMODE_READ | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 577 578 isc->sc_recrun = 1; 579 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 580 isc->sc_rintr = intr; 581 isc->sc_rarg = arg; 582 } else { 583 isc->sc_pintr = intr; 584 isc->sc_parg = arg; 585 } 586 587 /* 588 * Calculate number of transfers. 589 * Note that ADPCM is always transferred 4 bytes at at a time. 590 */ 591 blksize = (param->encoding == AUDIO_ENCODING_ADPCM) ? blksize / 4 - 1 : 592 (blksize * 8) / (param->precision * param->channels) - 1; 593 594 if (sc->mode >= 2) { 595 ad_write(sc, CS_LOWER_REC_CNT, blksize & 0xff); 596 ad_write(sc, CS_UPPER_REC_CNT, blksize >> 8); 597 } else { 598 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 599 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 600 } 601 602 reg = ad_read(sc, SP_INTERFACE_CONFIG); 603 ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg); 604 605 return 0; 606 } 607 608 int 609 ad1848_isa_trigger_output( 610 void *addr, 611 void *start, void *end, 612 int blksize, 613 void (*intr)(void *), 614 void *arg, 615 const audio_params_t *param) 616 { 617 struct ad1848_isa_softc *isc; 618 struct ad1848_softc *sc; 619 uint8_t reg; 620 621 isc = addr; 622 sc = &isc->sc_ad1848; 623 isa_dmastart(isc->sc_ic, isc->sc_playdrq, start, 624 (char *)end - (char *)start, NULL, 625 DMAMODE_WRITE | DMAMODE_LOOPDEMAND, BUS_DMA_NOWAIT); 626 627 isc->sc_playrun = 1; 628 isc->sc_pintr = intr; 629 isc->sc_parg = arg; 630 631 /* 632 * Calculate number of transfers. 633 * Note that ADPCM is always transferred 4 bytes at at a time. 634 */ 635 blksize = (param->encoding == AUDIO_ENCODING_ADPCM) ? blksize / 4 - 1 : 636 (blksize * 8) / (param->precision * param->channels) - 1; 637 638 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 639 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 640 641 /* Unmute wave output */ 642 ad1848_mute_wave_output(sc, WAVE_MUTE2, 0); 643 644 reg = ad_read(sc, SP_INTERFACE_CONFIG); 645 ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg); 646 647 return 0; 648 } 649 650 int 651 ad1848_isa_halt_input(void *addr) 652 { 653 struct ad1848_isa_softc *isc; 654 struct ad1848_softc *sc; 655 656 isc = addr; 657 sc = &isc->sc_ad1848; 658 if (isc->sc_recrun) { 659 ad1848_halt_input(sc); 660 isa_dmaabort(isc->sc_ic, isc->sc_recdrq); 661 isc->sc_recrun = 0; 662 } 663 664 return 0; 665 } 666 667 int 668 ad1848_isa_halt_output(void *addr) 669 { 670 struct ad1848_isa_softc *isc; 671 struct ad1848_softc *sc; 672 673 isc = addr; 674 sc = &isc->sc_ad1848; 675 if (isc->sc_playrun) { 676 /* Mute wave output */ 677 ad1848_mute_wave_output(sc, WAVE_MUTE2, 1); 678 679 ad1848_halt_output(sc); 680 isa_dmaabort(isc->sc_ic, isc->sc_playdrq); 681 isc->sc_playrun = 0; 682 } 683 684 return 0; 685 } 686 687 int 688 ad1848_isa_intr(void *arg) 689 { 690 struct ad1848_isa_softc *isc; 691 struct ad1848_softc *sc; 692 int retval; 693 u_char status; 694 695 isc = arg; 696 sc = &isc->sc_ad1848; 697 retval = 0; 698 /* Get intr status */ 699 status = ADREAD(sc, AD1848_STATUS); 700 701 #ifdef AUDIO_DEBUG 702 if (ad1848debug > 1) 703 printf("ad1848_isa_intr: pintr=%p rintr=%p status=%x\n", 704 isc->sc_pintr, isc->sc_rintr, status); 705 #endif 706 isc->sc_interrupts++; 707 708 /* Handle interrupt */ 709 if ((status & INTERRUPT_STATUS) != 0) { 710 if (sc->mode == 2 && isc->sc_playdrq != isc->sc_recdrq) { 711 status = ad_read(sc, CS_IRQ_STATUS); 712 if ((status & CS_IRQ_PI) && isc->sc_playrun) { 713 (*isc->sc_pintr)(isc->sc_parg); 714 retval = 1; 715 } 716 if ((status & CS_IRQ_CI) && isc->sc_recrun) { 717 (*isc->sc_rintr)(isc->sc_rarg); 718 retval = 1; 719 } 720 } else { 721 if (isc->sc_playrun) { 722 (*isc->sc_pintr)(isc->sc_parg); 723 retval = 1; 724 } 725 } 726 727 /* Clear interrupt */ 728 ADWRITE(sc, AD1848_STATUS, 0); 729 } 730 return retval; 731 } 732 733 void * 734 ad1848_isa_malloc( 735 void *addr, 736 int direction, 737 size_t size, 738 struct malloc_type *pool, 739 int flags) 740 { 741 struct ad1848_isa_softc *isc; 742 int drq; 743 744 isc = addr; 745 if (direction == AUMODE_PLAY) 746 drq = isc->sc_playdrq; 747 else 748 drq = isc->sc_recdrq; 749 return isa_malloc(isc->sc_ic, drq, size, pool, flags); 750 } 751 752 void 753 ad1848_isa_free(void *addr, void *ptr, struct malloc_type *pool) 754 { 755 756 isa_free(ptr, pool); 757 } 758 759 size_t 760 ad1848_isa_round_buffersize(void *addr, int direction, size_t size) 761 { 762 struct ad1848_isa_softc *isc; 763 bus_size_t maxsize; 764 765 isc = addr; 766 if (direction == AUMODE_PLAY) 767 maxsize = isc->sc_play_maxsize; 768 else if (isc->sc_recdrq == isc->sc_playdrq) 769 maxsize = isc->sc_play_maxsize; 770 else 771 maxsize = isc->sc_rec_maxsize; 772 773 if (size > maxsize) 774 size = maxsize; 775 return size; 776 } 777 778 paddr_t 779 ad1848_isa_mappage(void *addr, void *mem, off_t off, int prot) 780 { 781 return isa_mappage(mem, off, prot); 782 } 783 784 int 785 ad1848_isa_get_props(void *addr) 786 { 787 struct ad1848_isa_softc *isc; 788 789 isc = addr; 790 return AUDIO_PROP_MMAP | 791 (isc->sc_playdrq != isc->sc_recdrq ? AUDIO_PROP_FULLDUPLEX : 0); 792 } 793
Indexes created Wed Oct 15 16:09:53 GMT 2025