ad1848_isa.c revision 1.6
1 /* $NetBSD: ad1848_isa.c,v 1.6 1999/02/17 23:05:28 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1994 John Brezak 5 * Copyright (c) 1991-1993 Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the Computer Systems 19 * Engineering Group at Lawrence Berkeley Laboratory. 20 * 4. Neither the name of the University nor of the Laboratory may be used 21 * to endorse or promote products derived from this software without 22 * specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 /* 39 * Copyright by Hannu Savolainen 1994 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions are 43 * met: 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 2. 45 * Redistributions in binary form must reproduce the above copyright notice, 46 * this list of conditions and the following disclaimer in the documentation 47 * and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 50 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 51 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 52 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 53 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 55 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 56 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60 * 61 */ 62 /* 63 * Portions of this code are from the VOXware support for the ad1848 64 * by Hannu Savolainen <hannu (at) voxware.pp.fi> 65 * 66 * Portions also supplied from the SoundBlaster driver for NetBSD. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/proc.h> 76 #include <sys/buf.h> 77 78 #include <machine/cpu.h> 79 #include <machine/bus.h> 80 81 #include <sys/audioio.h> 82 #include <vm/vm.h> 83 84 #include <dev/audio_if.h> 85 #include <dev/auconv.h> 86 87 #include <dev/isa/isavar.h> 88 #include <dev/isa/isadmavar.h> 89 90 #include <dev/ic/ad1848reg.h> 91 #include <dev/ic/cs4231reg.h> 92 #include <dev/isa/ad1848var.h> 93 #include <dev/isa/cs4231var.h> 94 95 #ifdef AUDIO_DEBUG 96 #define DPRINTF(x) if (ad1848debug) printf x 97 extern int ad1848debug; 98 #else 99 #define DPRINTF(x) 100 #endif 101 102 static int ad1848_isa_read __P(( struct ad1848_softc *, int)); 103 static void ad1848_isa_write __P(( struct ad1848_softc *, int, int)); 104 105 int 106 ad1848_isa_read(sc, index) 107 struct ad1848_softc *sc; 108 int index; 109 { 110 struct ad1848_isa_softc *isc = (struct ad1848_isa_softc *)sc; 111 return (bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, 112 (isc)->sc_iooffs+(index))); 113 } 114 115 void 116 ad1848_isa_write(sc, index, value) 117 struct ad1848_softc *sc; 118 int index; 119 int value; 120 { 121 struct ad1848_isa_softc *isc = (struct ad1848_isa_softc *)sc; 122 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, 123 (isc)->sc_iooffs+(index), value); 124 } 125 126 /* 127 * Map and probe for the ad1848 chip 128 */ 129 int 130 ad1848_isa_mapprobe(isc, iobase) 131 struct ad1848_isa_softc *isc; 132 int iobase; 133 { 134 struct ad1848_softc *sc = (struct ad1848_softc *)&isc->sc_ad1848; 135 136 if (!AD1848_BASE_VALID(iobase)) { 137 #ifdef AUDIO_DEBUG 138 printf("ad1848: configured iobase %04x invalid\n", iobase); 139 #endif 140 return 0; 141 } 142 143 isc->sc_iooffs = 0; 144 /* Map the AD1848 ports */ 145 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 146 return 0; 147 148 if (!ad1848_isa_probe(isc)) { 149 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 150 return 0; 151 } else 152 return 1; 153 } 154 155 /* 156 * Probe for the ad1848 chip 157 */ 158 int 159 ad1848_isa_probe(isc) 160 struct ad1848_isa_softc *isc; 161 { 162 struct ad1848_softc *sc = (struct ad1848_softc *)&isc->sc_ad1848; 163 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 164 int i; 165 166 sc->sc_readreg = ad1848_isa_read; 167 sc->sc_writereg = ad1848_isa_write; 168 169 /* Is there an ad1848 chip ? */ 170 sc->MCE_bit = MODE_CHANGE_ENABLE; 171 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 172 173 /* 174 * Check that the I/O address is in use. 175 * 176 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 177 * chip has performed its power-on initialization. Just assume 178 * this has happened before the OS is starting. 179 * 180 * If the I/O address is unused, inb() typically returns 0xff. 181 */ 182 tmp = ADREAD(sc, AD1848_IADDR); 183 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 184 #if 0 185 DPRINTF(("ad_detect_A %x\n", tmp)); 186 #endif 187 goto bad; 188 } 189 190 /* 191 * Test if it's possible to change contents of the indirect registers. 192 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read 193 * only so try to avoid using it. 194 */ 195 ad_write(sc, 0, 0xaa); 196 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 197 198 if ((tmp1 = ad_read(sc, 0)) != 0xaa || 199 (tmp2 = ad_read(sc, 1)) != 0x45) { 200 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 201 goto bad; 202 } 203 204 ad_write(sc, 0, 0x45); 205 ad_write(sc, 1, 0xaa); 206 207 if ((tmp1 = ad_read(sc, 0)) != 0x45 || 208 (tmp2 = ad_read(sc, 1)) != 0xaa) { 209 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 210 goto bad; 211 } 212 213 /* 214 * The indirect register I12 has some read only bits. Lets 215 * try to change them. 216 */ 217 tmp = ad_read(sc, SP_MISC_INFO); 218 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 219 220 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 221 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 222 goto bad; 223 } 224 225 /* 226 * MSB and 4 LSBs of the reg I12 tell the chip revision. 227 * 228 * A preliminary version of the AD1846 data sheet stated that it 229 * used an ID field of 0x0B. The current version, however, 230 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 231 * 232 * this switch statement will need updating as newer clones arrive.... 233 */ 234 switch (tmp1 & 0x8f) { 235 case 0x09: 236 sc->chip_name = "AD1848J"; 237 break; 238 case 0x0A: 239 sc->chip_name = "AD1848K"; 240 break; 241 #if 0 /* See above */ 242 case 0x0B: 243 sc->chip_name = "AD1846"; 244 break; 245 #endif 246 case 0x81: 247 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 248 break; 249 case 0x89: 250 sc->chip_name = "CS4248"; 251 break; 252 case 0x8A: 253 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 254 break; 255 default: 256 sc->chip_name = "unknown"; 257 DPRINTF(("ad1848: unknown codec version 0x%02x\n", 258 tmp1 & 0x8f)); 259 break; 260 } 261 262 /* 263 * The original AD1848/CS4248 has just 16 indirect registers. This 264 * means that I0 and I16 should return the same value (etc.). 265 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test 266 * fails with CS4231, AD1845, etc. 267 */ 268 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 269 270 for (i = 0; i < 16; i++) 271 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 272 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 273 if (i != SP_TEST_AND_INIT) goto bad; 274 } 275 276 /* 277 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 278 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 279 */ 280 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 281 282 tmp1 = ad_read(sc, SP_MISC_INFO); 283 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 284 /* 285 * CS4231 or AD1845 detected - is it? 286 * 287 * Verify that setting I2 doesn't change I18. 288 */ 289 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 290 291 ad_write(sc, 2, 0x45); 292 if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */ 293 ad_write(sc, 2, 0xaa); 294 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */ 295 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 296 goto bad; 297 } 298 299 /* 300 * It's a CS4231, or another clone with 32 registers. 301 * Let's find out which by checking I25. 302 */ 303 if ((tmp1 & 0x8f) == 0x8a) { 304 tmp1 = ad_read(sc, CS_VERSION_ID); 305 switch (tmp1 & 0xe7) { 306 case 0xA0: 307 sc->chip_name = "CS4231A"; 308 break; 309 case 0x80: 310 /* XXX I25 no good, AD1845 same as CS4231 */ 311 sc->chip_name = "CS4231 or AD1845"; 312 break; 313 case 0x82: 314 sc->chip_name = "CS4232"; 315 break; 316 case 0x03: 317 case 0x83: 318 sc->chip_name = "CS4236/CS4236B"; 319 break; 320 } 321 } 322 sc->mode = 2; 323 } 324 } 325 326 /* Wait for 1848 to init */ 327 while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 328 ; 329 330 /* Wait for 1848 to autocal */ 331 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 332 while(ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 333 ; 334 335 return 1; 336 bad: 337 return 0; 338 } 339 340 /* Unmap the I/O ports */ 341 void 342 ad1848_isa_unmap(isc) 343 struct ad1848_isa_softc *isc; 344 { 345 struct ad1848_softc *sc = (struct ad1848_softc *)&isc->sc_ad1848; 346 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 347 } 348 349 /* 350 * Attach hardware to driver, attach hardware driver to audio 351 * pseudo-device driver . 352 */ 353 void 354 ad1848_isa_attach(isc) 355 struct ad1848_isa_softc *isc; 356 { 357 struct ad1848_softc *sc = (struct ad1848_softc *)&isc->sc_ad1848; 358 359 sc->sc_readreg = ad1848_isa_read; 360 sc->sc_writereg = ad1848_isa_write; 361 362 isc->sc_playrun = 0; 363 isc->sc_recrun = 0; 364 365 if (isc->sc_playdrq != -1) { 366 if (isa_dmamap_create(isc->sc_ic, isc->sc_playdrq, MAX_ISADMA, 367 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 368 printf("ad1848_attach: can't create map for drq %d\n", 369 isc->sc_playdrq); 370 return; 371 } 372 } 373 if (isc->sc_recdrq != -1 && isc->sc_recdrq != isc->sc_playdrq) { 374 if (isa_dmamap_create(isc->sc_ic, isc->sc_recdrq, MAX_ISADMA, 375 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 376 printf("ad1848_attach: can't create map for drq %d\n", 377 isc->sc_recdrq); 378 return; 379 } 380 } 381 382 ad1848_attach(sc); 383 } 384 385 int 386 ad1848_isa_open(addr, flags) 387 void *addr; 388 int flags; 389 { 390 struct ad1848_isa_softc *sc = addr; 391 392 DPRINTF(("ad1848_isa_open: sc=%p\n", sc)); 393 394 sc->sc_intr = 0; 395 396 return (ad1848_open(&sc->sc_ad1848, flags)); 397 } 398 399 /* 400 * Close function is called at splaudio(). 401 */ 402 void 403 ad1848_isa_close(addr) 404 void *addr; 405 { 406 struct ad1848_isa_softc *sc = addr; 407 408 sc->sc_intr = 0; 409 410 DPRINTF(("ad1848_isa_close: stop DMA\n")); 411 if (sc->sc_playrun) { 412 isa_dmaabort(sc->sc_ic, sc->sc_playdrq); 413 sc->sc_playrun = 0; 414 } 415 if (sc->sc_recrun) { 416 isa_dmaabort(sc->sc_ic, sc->sc_recdrq); 417 sc->sc_recrun = 0; 418 } 419 ad1848_close(&sc->sc_ad1848); 420 } 421 422 int 423 ad1848_isa_trigger_input(addr, start, end, blksize, intr, arg, param) 424 void *addr; 425 void *start, *end; 426 int blksize; 427 void (*intr) __P((void *)); 428 void *arg; 429 struct audio_params *param; 430 { 431 struct ad1848_isa_softc *isc = addr; 432 struct ad1848_softc *sc = (struct ad1848_softc *)&isc->sc_ad1848; 433 u_int8_t reg; 434 435 isa_dmastart(isc->sc_ic, isc->sc_recdrq, start, 436 (char *)end - (char *)start, NULL, DMAMODE_READ | DMAMODE_LOOP, 437 BUS_DMA_NOWAIT); 438 439 isc->sc_recrun = 1; 440 isc->sc_intr = intr; 441 isc->sc_arg = arg; 442 443 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 444 445 if (sc->mode == 2) { 446 ad_write(sc, CS_LOWER_REC_CNT, blksize & 0xff); 447 ad_write(sc, CS_UPPER_REC_CNT, blksize >> 8); 448 } else { 449 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 450 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 451 } 452 453 reg = ad_read(sc, SP_INTERFACE_CONFIG); 454 ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg); 455 456 return (0); 457 } 458 459 int 460 ad1848_isa_trigger_output(addr, start, end, blksize, intr, arg, param) 461 void *addr; 462 void *start, *end; 463 int blksize; 464 void (*intr) __P((void *)); 465 void *arg; 466 struct audio_params *param; 467 { 468 struct ad1848_isa_softc *isc = addr; 469 struct ad1848_softc *sc = (struct ad1848_softc *)&isc->sc_ad1848; 470 u_int8_t reg; 471 472 isa_dmastart(isc->sc_ic, isc->sc_playdrq, start, 473 (char *)end - (char *)start, NULL, DMAMODE_WRITE | DMAMODE_LOOP, 474 BUS_DMA_NOWAIT); 475 476 isc->sc_playrun = 1; 477 isc->sc_intr = intr; 478 isc->sc_arg = arg; 479 480 blksize = (blksize * 8) / (param->precision * param->factor * param->channels) - 1; 481 482 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 483 ad_write(sc, SP_UPPER_BASE_COUNT, blksize >> 8); 484 485 reg = ad_read(sc, SP_INTERFACE_CONFIG); 486 ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg); 487 488 return (0); 489 } 490 491 int 492 ad1848_isa_intr(arg) 493 void *arg; 494 { 495 struct ad1848_isa_softc *isc = arg; 496 struct ad1848_softc *sc = (struct ad1848_softc *)&isc->sc_ad1848; 497 int retval = 0; 498 u_char status; 499 500 /* Get intr status */ 501 status = ADREAD(sc, AD1848_STATUS); 502 503 #ifdef AUDIO_DEBUG 504 if (ad1848debug > 1) 505 printf("ad1848_isa_intr: intr=%p status=%x\n", isc->sc_intr, status); 506 #endif 507 isc->sc_interrupts++; 508 509 /* Handle interrupt */ 510 if (isc->sc_intr && (status & INTERRUPT_STATUS)) { 511 (*isc->sc_intr)(isc->sc_arg); 512 retval = 1; 513 } 514 515 /* clear interrupt */ 516 if (status & INTERRUPT_STATUS) 517 ADWRITE(sc, AD1848_STATUS, 0); 518 519 return(retval); 520 } 521 522 void * 523 ad1848_isa_malloc(addr, direction, size, pool, flags) 524 void *addr; 525 int direction; 526 size_t size; 527 int pool, flags; 528 { 529 struct ad1848_isa_softc *isc = addr; 530 int drq; 531 532 if (direction == AUMODE_PLAY) 533 drq = isc->sc_playdrq; 534 else 535 drq = isc->sc_recdrq; 536 return (isa_malloc(isc->sc_ic, drq, size, pool, flags)); 537 } 538 539 void 540 ad1848_isa_free(addr, ptr, pool) 541 void *addr; 542 void *ptr; 543 int pool; 544 { 545 isa_free(ptr, pool); 546 } 547 548 size_t 549 ad1848_isa_round_buffersize(addr, direction, size) 550 void *addr; 551 int direction; 552 size_t size; 553 { 554 if (size > MAX_ISADMA) 555 size = MAX_ISADMA; 556 return (size); 557 } 558 559 int 560 ad1848_isa_mappage(addr, mem, off, prot) 561 void *addr; 562 void *mem; 563 int off; 564 int prot; 565 { 566 return isa_mappage(mem, off, prot); 567 } 568 569 int 570 ad1848_isa_get_props(addr) 571 void *addr; 572 { 573 struct ad1848_isa_softc *isc = addr; 574 575 return (AUDIO_PROP_MMAP | 576 (isc->sc_playdrq != isc->sc_recdrq ? AUDIO_PROP_FULLDUPLEX : 0)); 577 } 578
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