addcom_isa.c revision 1.2.6.2
1 /* $NetBSD: addcom_isa.c,v 1.2.6.2 2000/11/20 11:41:11 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Michael Graff. All rights reserved. 5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1995 Charles M. Hannum. All rights reserved. 7 * 8 * This code is derived from public-domain software written by 9 * Roland McGrath, and information provided by David Muir Sharnoff. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Charles M. Hannum. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This code was written and tested with the Addonics FlexPort 8S. 39 * It has 8 ports, using 16650-compatible chips, sharing a single 40 * interrupt. 41 * 42 * An interrupt status register exists at 0x240, according to the 43 * skimpy documentation supplied. It doesn't change depending on 44 * io base address, so only one of these cards can ever be used at 45 * a time. 46 * 47 * This card is different from the boca or other cards in that ports 48 * 0..5 are from addresses 0x108..0x137, and 6..7 are from 0x200..0x20f, 49 * making a gap that the other cards do not have. 50 * 51 * The addresses which are documented are 0x108, 0x1108, 0x1d08, and 52 * 0x8508, for the base (port 0) address. 53 * 54 * --Michael <explorer (at) netbsd.org> -- April 21, 2000 55 */ 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/termios.h> 61 62 #include <machine/bus.h> 63 #include <machine/intr.h> 64 65 #include <dev/ic/comreg.h> 66 #include <dev/ic/comvar.h> 67 68 #include <dev/isa/isavar.h> 69 #include <dev/isa/com_multi.h> 70 71 #define NSLAVES 8 72 73 /* 74 * Grr. This card always uses 0x420 for the status register, regardless 75 * of io base address. 76 */ 77 #define STATUS_IOADDR 0x420 78 #define STATUS_SIZE 8 /* May be bogus... */ 79 80 struct addcom_softc { 81 struct device sc_dev; 82 void *sc_ih; 83 84 bus_space_tag_t sc_iot; 85 int sc_iobase; 86 87 int sc_alive; /* mask of slave units attached */ 88 void *sc_slaves[NSLAVES]; /* com device unit numbers */ 89 bus_space_handle_t sc_slaveioh[NSLAVES]; 90 bus_space_handle_t sc_statusioh; 91 }; 92 93 #define SLAVE_IOBASE_OFFSET 0x108 94 static int slave_iobases[8] = { 95 0x108, /* port 0, base port */ 96 0x110, 97 0x118, 98 0x120, 99 0x128, 100 0x130, 101 0x200, /* port 7, note address skip... */ 102 0x208 103 }; 104 105 int addcomprobe __P((struct device *, struct cfdata *, void *)); 106 void addcomattach __P((struct device *, struct device *, void *)); 107 int addcomintr __P((void *)); 108 int addcomprint __P((void *, const char *)); 109 110 struct cfattach addcom_isa_ca = { 111 sizeof(struct addcom_softc), addcomprobe, addcomattach, 112 }; 113 114 int 115 addcomprobe(struct device *parent, struct cfdata *self, void *aux) 116 { 117 struct isa_attach_args *ia = aux; 118 int iobase = ia->ia_iobase; 119 bus_space_tag_t iot = ia->ia_iot; 120 bus_space_handle_t ioh; 121 int i, rv = 1; 122 123 /* 124 * Do the normal com probe for the first UART and assume 125 * its presence, and the ability to map the other UARTS, 126 * means there is a multiport board there. 127 * XXX Needs more robustness. 128 */ 129 130 /* Disallow wildcarded i/o address. */ 131 if (ia->ia_iobase == ISACF_PORT_DEFAULT) 132 return (0); 133 134 /* if the first port is in use as console, then it. */ 135 if (com_is_console(iot, iobase, 0)) 136 goto checkmappings; 137 138 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) { 139 rv = 0; 140 goto out; 141 } 142 rv = comprobe1(iot, ioh); 143 bus_space_unmap(iot, ioh, COM_NPORTS); 144 if (rv == 0) 145 goto out; 146 147 checkmappings: 148 for (i = 1; i < NSLAVES; i++) { 149 iobase += slave_iobases[i] - slave_iobases[i - 1]; 150 151 if (com_is_console(iot, iobase, 0)) 152 continue; 153 154 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) { 155 rv = 0; 156 goto out; 157 } 158 bus_space_unmap(iot, ioh, COM_NPORTS); 159 } 160 161 out: 162 if (rv) 163 ia->ia_iosize = NSLAVES * COM_NPORTS; 164 return (rv); 165 } 166 167 int 168 addcomprint(void *aux, const char *pnp) 169 { 170 struct commulti_attach_args *ca = aux; 171 172 if (pnp) 173 printf("com at %s", pnp); 174 printf(" slave %d", ca->ca_slave); 175 return (UNCONF); 176 } 177 178 void 179 addcomattach(struct device *parent, struct device *self, void *aux) 180 { 181 struct addcom_softc *sc = (void *)self; 182 struct isa_attach_args *ia = aux; 183 struct commulti_attach_args ca; 184 bus_space_tag_t iot = ia->ia_iot; 185 int i, iobase; 186 187 printf("\n"); 188 189 sc->sc_iot = ia->ia_iot; 190 sc->sc_iobase = ia->ia_iobase; 191 192 if (bus_space_map(iot, STATUS_IOADDR, STATUS_SIZE, 193 0, &sc->sc_statusioh)) { 194 printf("%s: can't map status space\n", sc->sc_dev.dv_xname); 195 return; 196 } 197 198 for (i = 0; i < NSLAVES; i++) { 199 iobase = sc->sc_iobase 200 + slave_iobases[i] 201 - SLAVE_IOBASE_OFFSET; 202 if (!com_is_console(iot, iobase, &sc->sc_slaveioh[i]) && 203 bus_space_map(iot, iobase, COM_NPORTS, 0, 204 &sc->sc_slaveioh[i])) { 205 printf("%s: can't map i/o space for slave %d\n", 206 sc->sc_dev.dv_xname, i); 207 return; 208 } 209 } 210 211 for (i = 0; i < NSLAVES; i++) { 212 ca.ca_slave = i; 213 ca.ca_iot = sc->sc_iot; 214 ca.ca_ioh = sc->sc_slaveioh[i]; 215 ca.ca_iobase = sc->sc_iobase 216 + slave_iobases[i] 217 - SLAVE_IOBASE_OFFSET; 218 ca.ca_noien = 0; 219 220 sc->sc_slaves[i] = config_found(self, &ca, addcomprint); 221 if (sc->sc_slaves[i] != NULL) 222 sc->sc_alive |= 1 << i; 223 } 224 225 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 226 IPL_SERIAL, addcomintr, sc); 227 } 228 229 int 230 addcomintr(void *arg) 231 { 232 struct addcom_softc *sc = arg; 233 bus_space_tag_t iot = sc->sc_iot; 234 int alive = sc->sc_alive; 235 int bits; 236 237 bits = bus_space_read_1(iot, sc->sc_statusioh, 0) & alive; 238 if (bits == 0) 239 return (0); 240 241 for (;;) { 242 #define TRY(n) \ 243 if (bits & (1 << (n))) \ 244 comintr(sc->sc_slaves[n]); 245 TRY(0); 246 TRY(1); 247 TRY(2); 248 TRY(3); 249 TRY(4); 250 TRY(5); 251 TRY(6); 252 TRY(7); 253 #undef TRY 254 bits = bus_space_read_1(iot, sc->sc_statusioh, 0) & alive; 255 if (bits == 0) 256 return (1); 257 } 258 } 259
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