cs89x0isa.c revision 1.3.2.2
1 1.3.2.2 nathanw /* $NetBSD: cs89x0isa.c,v 1.3.2.2 2002/01/08 00:30:22 nathanw Exp $ */ 2 1.3.2.2 nathanw 3 1.3.2.2 nathanw /* 4 1.3.2.2 nathanw * Copyright 1997 5 1.3.2.2 nathanw * Digital Equipment Corporation. All rights reserved. 6 1.3.2.2 nathanw * 7 1.3.2.2 nathanw * This software is furnished under license and may be used and 8 1.3.2.2 nathanw * copied only in accordance with the following terms and conditions. 9 1.3.2.2 nathanw * Subject to these conditions, you may download, copy, install, 10 1.3.2.2 nathanw * use, modify and distribute this software in source and/or binary 11 1.3.2.2 nathanw * form. No title or ownership is transferred hereby. 12 1.3.2.2 nathanw * 13 1.3.2.2 nathanw * 1) Any source code used, modified or distributed must reproduce 14 1.3.2.2 nathanw * and retain this copyright notice and list of conditions as 15 1.3.2.2 nathanw * they appear in the source file. 16 1.3.2.2 nathanw * 17 1.3.2.2 nathanw * 2) No right is granted to use any trade name, trademark, or logo of 18 1.3.2.2 nathanw * Digital Equipment Corporation. Neither the "Digital Equipment 19 1.3.2.2 nathanw * Corporation" name nor any trademark or logo of Digital Equipment 20 1.3.2.2 nathanw * Corporation may be used to endorse or promote products derived 21 1.3.2.2 nathanw * from this software without the prior written permission of 22 1.3.2.2 nathanw * Digital Equipment Corporation. 23 1.3.2.2 nathanw * 24 1.3.2.2 nathanw * 3) This software is provided "AS-IS" and any express or implied 25 1.3.2.2 nathanw * warranties, including but not limited to, any implied warranties 26 1.3.2.2 nathanw * of merchantability, fitness for a particular purpose, or 27 1.3.2.2 nathanw * non-infringement are disclaimed. In no event shall DIGITAL be 28 1.3.2.2 nathanw * liable for any damages whatsoever, and in particular, DIGITAL 29 1.3.2.2 nathanw * shall not be liable for special, indirect, consequential, or 30 1.3.2.2 nathanw * incidental damages or damages for lost profits, loss of 31 1.3.2.2 nathanw * revenue or loss of use, whether such damages arise in contract, 32 1.3.2.2 nathanw * negligence, tort, under statute, in equity, at law or otherwise, 33 1.3.2.2 nathanw * even if advised of the possibility of such damage. 34 1.3.2.2 nathanw */ 35 1.3.2.2 nathanw 36 1.3.2.2 nathanw /* isa dma routines for cs89x0 */ 37 1.3.2.2 nathanw 38 1.3.2.2 nathanw #include <sys/cdefs.h> 39 1.3.2.2 nathanw __KERNEL_RCSID(0, "$NetBSD: cs89x0isa.c,v 1.3.2.2 2002/01/08 00:30:22 nathanw Exp $"); 40 1.3.2.2 nathanw 41 1.3.2.2 nathanw #include <sys/param.h> 42 1.3.2.2 nathanw #include <sys/systm.h> 43 1.3.2.2 nathanw #include <sys/mbuf.h> 44 1.3.2.2 nathanw #include <sys/socket.h> 45 1.3.2.2 nathanw #include <sys/device.h> 46 1.3.2.2 nathanw 47 1.3.2.2 nathanw #include "rnd.h" 48 1.3.2.2 nathanw #if NRND > 0 49 1.3.2.2 nathanw #include <sys/rnd.h> 50 1.3.2.2 nathanw #endif 51 1.3.2.2 nathanw 52 1.3.2.2 nathanw #include <net/if.h> 53 1.3.2.2 nathanw #include <net/if_ether.h> 54 1.3.2.2 nathanw #include <net/if_media.h> 55 1.3.2.2 nathanw 56 1.3.2.2 nathanw #include <machine/bus.h> 57 1.3.2.2 nathanw 58 1.3.2.2 nathanw #include <dev/isa/isareg.h> 59 1.3.2.2 nathanw #include <dev/isa/isavar.h> 60 1.3.2.2 nathanw #include <dev/isa/isadmavar.h> 61 1.3.2.2 nathanw 62 1.3.2.2 nathanw #include <dev/ic/cs89x0reg.h> 63 1.3.2.2 nathanw #include <dev/ic/cs89x0var.h> 64 1.3.2.2 nathanw #include <dev/isa/cs89x0isavar.h> 65 1.3.2.2 nathanw 66 1.3.2.2 nathanw #define DMA_STATUS_BITS 0x0007 /* bit masks for checking DMA status */ 67 1.3.2.2 nathanw #define DMA_STATUS_OK 0x0004 68 1.3.2.2 nathanw 69 1.3.2.2 nathanw void 70 1.3.2.2 nathanw cs_isa_dma_attach(struct cs_softc *sc) 71 1.3.2.2 nathanw { 72 1.3.2.2 nathanw struct cs_softc_isa *isc = (void *)sc; 73 1.3.2.2 nathanw 74 1.3.2.2 nathanw if (isc->sc_drq == ISACF_DRQ_DEFAULT) 75 1.3.2.2 nathanw printf("%s: DMA channel unspecified, not using DMA\n", 76 1.3.2.2 nathanw sc->sc_dev.dv_xname); 77 1.3.2.2 nathanw else if (isc->sc_drq < 5 || isc->sc_drq > 7) 78 1.3.2.2 nathanw printf("%s: invalid DMA channel, not using DMA\n", 79 1.3.2.2 nathanw sc->sc_dev.dv_xname); 80 1.3.2.2 nathanw else { 81 1.3.2.2 nathanw bus_size_t maxsize; 82 1.3.2.2 nathanw bus_addr_t dma_addr; 83 1.3.2.2 nathanw 84 1.3.2.2 nathanw maxsize = isa_dmamaxsize(isc->sc_ic, isc->sc_drq); 85 1.3.2.2 nathanw if (maxsize < CS8900_DMASIZE) { 86 1.3.2.2 nathanw printf("%s: max DMA size %lu is less than required %d\n", 87 1.3.2.2 nathanw sc->sc_dev.dv_xname, (u_long)maxsize, 88 1.3.2.2 nathanw CS8900_DMASIZE); 89 1.3.2.2 nathanw goto after_dma_block; 90 1.3.2.2 nathanw } 91 1.3.2.2 nathanw 92 1.3.2.2 nathanw if (isa_dmamap_create(isc->sc_ic, isc->sc_drq, 93 1.3.2.2 nathanw CS8900_DMASIZE, BUS_DMA_NOWAIT) != 0) { 94 1.3.2.2 nathanw printf("%s: unable to create ISA DMA map\n", 95 1.3.2.2 nathanw sc->sc_dev.dv_xname); 96 1.3.2.2 nathanw goto after_dma_block; 97 1.3.2.2 nathanw } 98 1.3.2.2 nathanw if (isa_dmamem_alloc(isc->sc_ic, isc->sc_drq, 99 1.3.2.2 nathanw CS8900_DMASIZE, &dma_addr, BUS_DMA_NOWAIT) != 0) { 100 1.3.2.2 nathanw printf("%s: unable to allocate DMA buffer\n", 101 1.3.2.2 nathanw sc->sc_dev.dv_xname); 102 1.3.2.2 nathanw goto after_dma_block; 103 1.3.2.2 nathanw } 104 1.3.2.2 nathanw if (isa_dmamem_map(isc->sc_ic, isc->sc_drq, dma_addr, 105 1.3.2.2 nathanw CS8900_DMASIZE, &isc->sc_dmabase, 106 1.3.2.2 nathanw BUS_DMA_NOWAIT | BUS_DMA_COHERENT /* XXX */ ) != 0) { 107 1.3.2.2 nathanw printf("%s: unable to map DMA buffer\n", 108 1.3.2.2 nathanw sc->sc_dev.dv_xname); 109 1.3.2.2 nathanw isa_dmamem_free(isc->sc_ic, isc->sc_drq, dma_addr, 110 1.3.2.2 nathanw CS8900_DMASIZE); 111 1.3.2.2 nathanw goto after_dma_block; 112 1.3.2.2 nathanw } 113 1.3.2.2 nathanw 114 1.3.2.2 nathanw isc->sc_dmasize = CS8900_DMASIZE; 115 1.3.2.2 nathanw sc->sc_cfgflags |= CFGFLG_DMA_MODE; 116 1.3.2.2 nathanw isc->sc_dmaaddr = dma_addr; 117 1.3.2.2 nathanw after_dma_block: 118 1.3.2.2 nathanw ; 119 1.3.2.2 nathanw } 120 1.3.2.2 nathanw } 121 1.3.2.2 nathanw 122 1.3.2.2 nathanw void cs_isa_dma_chipinit(struct cs_softc *sc) 123 1.3.2.2 nathanw { 124 1.3.2.2 nathanw struct cs_softc_isa *isc = (void *)sc; 125 1.3.2.2 nathanw 126 1.3.2.2 nathanw if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 127 1.3.2.2 nathanw /* 128 1.3.2.2 nathanw * First we program the DMA controller and ensure the memory 129 1.3.2.2 nathanw * buffer is valid. If it isn't then we just go on without 130 1.3.2.2 nathanw * DMA. 131 1.3.2.2 nathanw */ 132 1.3.2.2 nathanw if (isa_dmastart(isc->sc_ic, isc->sc_drq, isc->sc_dmabase, 133 1.3.2.2 nathanw isc->sc_dmasize, NULL, DMAMODE_READ | DMAMODE_LOOPDEMAND, 134 1.3.2.2 nathanw BUS_DMA_NOWAIT)) { 135 1.3.2.2 nathanw /* XXX XXX XXX */ 136 1.3.2.2 nathanw panic("%s: unable to start DMA\n", sc->sc_dev.dv_xname); 137 1.3.2.2 nathanw } 138 1.3.2.2 nathanw isc->sc_dmacur = isc->sc_dmabase; 139 1.3.2.2 nathanw 140 1.3.2.2 nathanw /* interrupt when a DMA'd frame is received */ 141 1.3.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 142 1.3.2.2 nathanw RX_CFG_ALL_IE | RX_CFG_RX_DMA_ONLY); 143 1.3.2.2 nathanw 144 1.3.2.2 nathanw /* 145 1.3.2.2 nathanw * set the DMA burst bit so we don't tie up the bus for too 146 1.3.2.2 nathanw * long. 147 1.3.2.2 nathanw */ 148 1.3.2.2 nathanw if (isc->sc_dmasize == 16384) { 149 1.3.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 150 1.3.2.2 nathanw ((CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & 151 1.3.2.2 nathanw ~BUS_CTL_DMA_SIZE) | BUS_CTL_DMA_BURST)); 152 1.3.2.2 nathanw } else { /* use 64K */ 153 1.3.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 154 1.3.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | 155 1.3.2.2 nathanw BUS_CTL_DMA_SIZE | BUS_CTL_DMA_BURST); 156 1.3.2.2 nathanw } 157 1.3.2.2 nathanw 158 1.3.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_DMA_CHANNEL, isc->sc_drq - 5); 159 1.3.2.2 nathanw } 160 1.3.2.2 nathanw } 161 1.3.2.2 nathanw 162 1.3.2.2 nathanw void cs_process_rx_dma(struct cs_softc *sc) 163 1.3.2.2 nathanw { 164 1.3.2.2 nathanw struct cs_softc_isa *isc = (void *)sc; 165 1.3.2.2 nathanw struct ifnet *ifp; 166 1.3.2.2 nathanw u_int16_t num_dma_frames; 167 1.3.2.2 nathanw u_int16_t pkt_length; 168 1.3.2.2 nathanw u_int16_t status; 169 1.3.2.2 nathanw u_int to_copy; 170 1.3.2.2 nathanw char *dma_mem_ptr; 171 1.3.2.2 nathanw struct mbuf *m; 172 1.3.2.2 nathanw u_char *pBuff; 173 1.3.2.2 nathanw int pad; 174 1.3.2.2 nathanw 175 1.3.2.2 nathanw /* initialise the pointers */ 176 1.3.2.2 nathanw ifp = &sc->sc_ethercom.ec_if; 177 1.3.2.2 nathanw 178 1.3.2.2 nathanw /* Read the number of frames DMAed. */ 179 1.3.2.2 nathanw num_dma_frames = CS_READ_PACKET_PAGE(sc, PKTPG_DMA_FRAME_COUNT); 180 1.3.2.2 nathanw num_dma_frames &= (u_int16_t) (0x0fff); 181 1.3.2.2 nathanw 182 1.3.2.2 nathanw /* 183 1.3.2.2 nathanw * Loop till number of DMA frames ready to read is zero. After 184 1.3.2.2 nathanw * reading the frame out of memory we must check if any have been 185 1.3.2.2 nathanw * received while we were processing 186 1.3.2.2 nathanw */ 187 1.3.2.2 nathanw while (num_dma_frames != 0) { 188 1.3.2.2 nathanw dma_mem_ptr = isc->sc_dmacur; 189 1.3.2.2 nathanw 190 1.3.2.2 nathanw /* 191 1.3.2.2 nathanw * process all of the dma frames in memory 192 1.3.2.2 nathanw * 193 1.3.2.2 nathanw * This loop relies on the dma_mem_ptr variable being set to the 194 1.3.2.2 nathanw * next frames start address. 195 1.3.2.2 nathanw */ 196 1.3.2.2 nathanw for (; num_dma_frames > 0; num_dma_frames--) { 197 1.3.2.2 nathanw 198 1.3.2.2 nathanw /* 199 1.3.2.2 nathanw * Get the length and status of the packet. Only the 200 1.3.2.2 nathanw * status is guarenteed to be at dma_mem_ptr, ie need 201 1.3.2.2 nathanw * to check for wraparound before reading the length 202 1.3.2.2 nathanw */ 203 1.3.2.2 nathanw status = *((unsigned short *) dma_mem_ptr)++; 204 1.3.2.2 nathanw if (dma_mem_ptr > (isc->sc_dmabase + isc->sc_dmasize)) { 205 1.3.2.2 nathanw dma_mem_ptr = isc->sc_dmabase; 206 1.3.2.2 nathanw } 207 1.3.2.2 nathanw pkt_length = *((unsigned short *) dma_mem_ptr)++; 208 1.3.2.2 nathanw 209 1.3.2.2 nathanw /* Do some sanity checks on the length and status. */ 210 1.3.2.2 nathanw if ((pkt_length > ETHER_MAX_LEN) || 211 1.3.2.2 nathanw ((status & DMA_STATUS_BITS) != DMA_STATUS_OK)) { 212 1.3.2.2 nathanw /* 213 1.3.2.2 nathanw * the SCO driver kills the adapter in this 214 1.3.2.2 nathanw * situation 215 1.3.2.2 nathanw */ 216 1.3.2.2 nathanw /* 217 1.3.2.2 nathanw * should increment the error count and reset 218 1.3.2.2 nathanw * the dma operation. 219 1.3.2.2 nathanw */ 220 1.3.2.2 nathanw printf("%s: cs_process_rx_dma: DMA buffer out of sync about to reset\n", 221 1.3.2.2 nathanw sc->sc_dev.dv_xname); 222 1.3.2.2 nathanw ifp->if_ierrors++; 223 1.3.2.2 nathanw 224 1.3.2.2 nathanw /* skip the rest of the DMA buffer */ 225 1.3.2.2 nathanw isa_dmaabort(isc->sc_ic, isc->sc_drq); 226 1.3.2.2 nathanw 227 1.3.2.2 nathanw /* now reset the chip and reinitialise */ 228 1.3.2.2 nathanw cs_init(&sc->sc_ethercom.ec_if); 229 1.3.2.2 nathanw return; 230 1.3.2.2 nathanw } 231 1.3.2.2 nathanw /* Check the status of the received packet. */ 232 1.3.2.2 nathanw if (status & RX_EVENT_RX_OK) { 233 1.3.2.2 nathanw /* get a new mbuf */ 234 1.3.2.2 nathanw MGETHDR(m, M_DONTWAIT, MT_DATA); 235 1.3.2.2 nathanw if (m == 0) { 236 1.3.2.2 nathanw printf("%s: cs_process_rx_dma: unable to allocate mbuf\n", 237 1.3.2.2 nathanw sc->sc_dev.dv_xname); 238 1.3.2.2 nathanw ifp->if_ierrors++; 239 1.3.2.2 nathanw /* 240 1.3.2.2 nathanw * couldn't allocate an mbuf so 241 1.3.2.2 nathanw * things are not good, may as well 242 1.3.2.2 nathanw * drop all the packets I think. 243 1.3.2.2 nathanw */ 244 1.3.2.2 nathanw CS_READ_PACKET_PAGE(sc, 245 1.3.2.2 nathanw PKTPG_DMA_FRAME_COUNT); 246 1.3.2.2 nathanw 247 1.3.2.2 nathanw /* now reset DMA operation */ 248 1.3.2.2 nathanw isa_dmaabort(isc->sc_ic, isc->sc_drq); 249 1.3.2.2 nathanw 250 1.3.2.2 nathanw /* 251 1.3.2.2 nathanw * now reset the chip and 252 1.3.2.2 nathanw * reinitialise 253 1.3.2.2 nathanw */ 254 1.3.2.2 nathanw cs_init(&sc->sc_ethercom.ec_if); 255 1.3.2.2 nathanw return; 256 1.3.2.2 nathanw } 257 1.3.2.2 nathanw /* 258 1.3.2.2 nathanw * save processing by always using a mbuf 259 1.3.2.2 nathanw * cluster, guarenteed to fit packet 260 1.3.2.2 nathanw */ 261 1.3.2.2 nathanw MCLGET(m, M_DONTWAIT); 262 1.3.2.2 nathanw if ((m->m_flags & M_EXT) == 0) { 263 1.3.2.2 nathanw /* couldn't allocate an mbuf cluster */ 264 1.3.2.2 nathanw printf("%s: cs_process_rx_dma: unable to allocate a cluster\n", 265 1.3.2.2 nathanw sc->sc_dev.dv_xname); 266 1.3.2.2 nathanw m_freem(m); 267 1.3.2.2 nathanw 268 1.3.2.2 nathanw /* skip the frame */ 269 1.3.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_DMA_FRAME_COUNT); 270 1.3.2.2 nathanw isa_dmaabort(isc->sc_ic, isc->sc_drq); 271 1.3.2.2 nathanw 272 1.3.2.2 nathanw /* 273 1.3.2.2 nathanw * now reset the chip and 274 1.3.2.2 nathanw * reinitialise 275 1.3.2.2 nathanw */ 276 1.3.2.2 nathanw cs_init(&sc->sc_ethercom.ec_if); 277 1.3.2.2 nathanw return; 278 1.3.2.2 nathanw } 279 1.3.2.2 nathanw m->m_pkthdr.rcvif = ifp; 280 1.3.2.2 nathanw m->m_pkthdr.len = pkt_length; 281 1.3.2.2 nathanw m->m_len = pkt_length; 282 1.3.2.2 nathanw 283 1.3.2.2 nathanw /* 284 1.3.2.2 nathanw * align ip header on word boundary for 285 1.3.2.2 nathanw * ipintr 286 1.3.2.2 nathanw */ 287 1.3.2.2 nathanw pad = ALIGN(sizeof(struct ether_header)) - 288 1.3.2.2 nathanw sizeof(struct ether_header); 289 1.3.2.2 nathanw m->m_data += pad; 290 1.3.2.2 nathanw 291 1.3.2.2 nathanw /* 292 1.3.2.2 nathanw * set up the buffer pointer to point to the 293 1.3.2.2 nathanw * data area 294 1.3.2.2 nathanw */ 295 1.3.2.2 nathanw pBuff = mtod(m, char *); 296 1.3.2.2 nathanw 297 1.3.2.2 nathanw /* 298 1.3.2.2 nathanw * Read the frame into free_pktbuf 299 1.3.2.2 nathanw * The buffer is circular buffer, either 300 1.3.2.2 nathanw * 16K or 64K in length. 301 1.3.2.2 nathanw * 302 1.3.2.2 nathanw * need to check where the end of the buffer 303 1.3.2.2 nathanw * is and go back to the start. 304 1.3.2.2 nathanw */ 305 1.3.2.2 nathanw if ((dma_mem_ptr + pkt_length) < 306 1.3.2.2 nathanw (isc->sc_dmabase + isc->sc_dmasize)) { 307 1.3.2.2 nathanw /* 308 1.3.2.2 nathanw * No wrap around. Copy the frame 309 1.3.2.2 nathanw * header 310 1.3.2.2 nathanw */ 311 1.3.2.2 nathanw memcpy(pBuff, dma_mem_ptr, pkt_length); 312 1.3.2.2 nathanw dma_mem_ptr += pkt_length; 313 1.3.2.2 nathanw } else { 314 1.3.2.2 nathanw to_copy = (u_int) 315 1.3.2.2 nathanw ((isc->sc_dmabase + isc->sc_dmasize) - 316 1.3.2.2 nathanw dma_mem_ptr); 317 1.3.2.2 nathanw 318 1.3.2.2 nathanw /* Copy the first half of the frame. */ 319 1.3.2.2 nathanw memcpy(pBuff, dma_mem_ptr, to_copy); 320 1.3.2.2 nathanw pBuff += to_copy; 321 1.3.2.2 nathanw 322 1.3.2.2 nathanw /* 323 1.3.2.2 nathanw * Rest of the frame is to be read 324 1.3.2.2 nathanw * from the first byte of the DMA 325 1.3.2.2 nathanw * memory. 326 1.3.2.2 nathanw */ 327 1.3.2.2 nathanw /* 328 1.3.2.2 nathanw * Get the number of bytes leftout in 329 1.3.2.2 nathanw * the frame. 330 1.3.2.2 nathanw */ 331 1.3.2.2 nathanw to_copy = pkt_length - to_copy; 332 1.3.2.2 nathanw 333 1.3.2.2 nathanw dma_mem_ptr = isc->sc_dmabase; 334 1.3.2.2 nathanw 335 1.3.2.2 nathanw /* Copy rest of the frame. */ 336 1.3.2.2 nathanw memcpy(pBuff, dma_mem_ptr, to_copy); 337 1.3.2.2 nathanw dma_mem_ptr += to_copy; 338 1.3.2.2 nathanw } 339 1.3.2.2 nathanw 340 1.3.2.2 nathanw cs_ether_input(sc, m); 341 1.3.2.2 nathanw } 342 1.3.2.2 nathanw /* (status & RX_OK) */ 343 1.3.2.2 nathanw else { 344 1.3.2.2 nathanw /* the frame was not received OK */ 345 1.3.2.2 nathanw /* Increment the input error count */ 346 1.3.2.2 nathanw ifp->if_ierrors++; 347 1.3.2.2 nathanw 348 1.3.2.2 nathanw /* 349 1.3.2.2 nathanw * If debugging is enabled then log error 350 1.3.2.2 nathanw * messages if we got any. 351 1.3.2.2 nathanw */ 352 1.3.2.2 nathanw if ((ifp->if_flags & IFF_DEBUG) && 353 1.3.2.2 nathanw status != REG_NUM_RX_EVENT) 354 1.3.2.2 nathanw cs_print_rx_errors(sc, status); 355 1.3.2.2 nathanw } 356 1.3.2.2 nathanw /* 357 1.3.2.2 nathanw * now update the current frame pointer. the 358 1.3.2.2 nathanw * dma_mem_ptr should point to the next packet to be 359 1.3.2.2 nathanw * received, without the alignment considerations. 360 1.3.2.2 nathanw * 361 1.3.2.2 nathanw * The cs8900 pads all frames to start at the next 32bit 362 1.3.2.2 nathanw * aligned addres. hence we need to pad our offset 363 1.3.2.2 nathanw * pointer. 364 1.3.2.2 nathanw */ 365 1.3.2.2 nathanw dma_mem_ptr += 3; 366 1.3.2.2 nathanw dma_mem_ptr = (char *) 367 1.3.2.2 nathanw ((long) dma_mem_ptr & 0xfffffffc); 368 1.3.2.2 nathanw if (dma_mem_ptr < (isc->sc_dmabase + isc->sc_dmasize)) { 369 1.3.2.2 nathanw isc->sc_dmacur = dma_mem_ptr; 370 1.3.2.2 nathanw } else { 371 1.3.2.2 nathanw dma_mem_ptr = isc->sc_dmacur = isc->sc_dmabase; 372 1.3.2.2 nathanw } 373 1.3.2.2 nathanw } /* for all frames */ 374 1.3.2.2 nathanw /* Read the number of frames DMAed again. */ 375 1.3.2.2 nathanw num_dma_frames = CS_READ_PACKET_PAGE(sc, PKTPG_DMA_FRAME_COUNT); 376 1.3.2.2 nathanw num_dma_frames &= (u_int16_t) (0x0fff); 377 1.3.2.2 nathanw } /* while there are frames left */ 378 1.3.2.2 nathanw } 379
Indexes created Wed Oct 01 15:09:59 GMT 2025