esp_isa.c revision 1.1
1 /* 2 * Copyright (c) 1997 Jason R. Thorpe. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed for the NetBSD Project 16 * by Jason R. Thorpe. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 /* 73 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 74 * (basically consisting of the match, a bit of the attach, and the 75 * "DMA" glue functions). 76 */ 77 /* 78 * Copyright (c) 1994, 1996, 1997 Charles M. Hannum. All rights reserved. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by Charles M. Hannum. 91 * 4. The name of the author may not be used to endorse or promote products 92 * derived from this software without specific prior written permission. 93 * 94 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 95 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 96 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 97 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 98 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 99 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 100 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 101 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 102 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 103 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 104 */ 105 106 /* 107 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 108 * All rights reserved. 109 * 110 * Redistribution and use in source and binary forms, with or without 111 * modification, are permitted provided that the following conditions 112 * are met: 113 * 1. Redistributions of source code must retain the above copyright 114 * notice, this list of conditions and the following disclaimer. 115 * 2. Redistributions in binary form must reproduce the above copyright 116 * notice, this list of conditions and the following disclaimer in the 117 * documentation and/or other materials provided with the distribution. 118 * 3. All advertising materials mentioning features or use of this software 119 * must display the following acknowledgement: 120 * This product includes software developed by Eric S. Hvozda. 121 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 122 * derived from this software without specific prior written permission. 123 * 124 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 125 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 126 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 127 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 128 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 129 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 130 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 131 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 132 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 133 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 134 */ 135 136 #include <sys/param.h> 137 #include <sys/systm.h> 138 #include <sys/device.h> 139 #include <sys/buf.h> 140 141 #include <machine/bus.h> 142 #include <machine/intr.h> 143 144 #include <scsi/scsi_all.h> 145 #include <scsi/scsiconf.h> 146 147 #include <dev/isa/isavar.h> 148 #include <dev/isa/isadmavar.h> 149 150 #include <dev/ic/ncr53c9xreg.h> 151 #include <dev/ic/ncr53c9xvar.h> 152 153 #include <dev/isa/espvar.h> 154 155 int esp_isa_match __P((struct device *, void *, void *)); 156 void esp_isa_attach __P((struct device *, struct device *, void *)); 157 158 struct cfattach esp_isa_ca = { 159 sizeof(struct esp_softc), esp_isa_match, esp_isa_attach 160 }; 161 162 struct cfdriver esp_cd = { 163 NULL, "esp", DV_DULL 164 }; 165 166 struct scsi_adapter esp_switch = { 167 ncr53c9x_scsi_cmd, 168 minphys, /* no max at this level; handled by DMA code */ 169 NULL, 170 NULL, 171 }; 172 173 struct scsi_device esp_dev = { 174 NULL, /* Use default error handler */ 175 NULL, /* have a queue, served by this */ 176 NULL, /* have no async handler */ 177 NULL, /* Use default 'done' routine */ 178 }; 179 180 int esp_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 181 182 /* 183 * Functions and the switch for the MI code. 184 */ 185 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 186 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 187 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 188 void esp_dma_reset __P((struct ncr53c9x_softc *)); 189 int esp_dma_intr __P((struct ncr53c9x_softc *)); 190 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 191 size_t *, int, size_t *)); 192 void esp_dma_go __P((struct ncr53c9x_softc *)); 193 void esp_dma_stop __P((struct ncr53c9x_softc *)); 194 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 195 196 struct ncr53c9x_glue esp_glue = { 197 esp_read_reg, 198 esp_write_reg, 199 esp_dma_isintr, 200 esp_dma_reset, 201 esp_dma_intr, 202 esp_dma_setup, 203 esp_dma_go, 204 esp_dma_stop, 205 esp_dma_isactive, 206 NULL, /* gl_clear_latched_intr */ 207 }; 208 209 /* 210 * Look for the board 211 */ 212 int 213 esp_find(iot, ioh, epd) 214 bus_space_tag_t iot; 215 bus_space_handle_t ioh; 216 struct esp_probe_data *epd; 217 { 218 u_int vers; 219 u_int p1; 220 u_int p2; 221 u_int jmp; 222 223 ESP_TRACE(("[esp_find] ")); 224 225 /* reset card before we probe? */ 226 227 /* 228 * Switch to the PIO regs and look for the bit pattern 229 * we expect... 230 */ 231 bus_space_write_1(iot, ioh, NCR_CFG4, 232 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 233 234 #define SIG_MASK 0x87 235 #define REV_MASK 0x70 236 #define M1 0x02 237 #define M2 0x05 238 #define ISNCR 0x80 239 #define ISESP406 0x40 240 241 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 242 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 243 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 244 245 ESP_MISC(("%s: 0x%0x 0x%0x 0x%0x\n", epd->sc_dev.dv_xname, 246 vers, p1, p2)); 247 248 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 249 return 0; 250 251 /* Ok, what is it? */ 252 epd->sc_isncr = (vers & ISNCR); 253 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 254 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 255 256 /* What do the jumpers tell us? */ 257 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 258 259 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 260 epd->sc_parity = jmp & NCRJMP_J2; 261 epd->sc_sync = jmp & NCRJMP_J4; 262 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 263 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 264 case NCRJMP_J0 | NCRJMP_J1: 265 epd->sc_irq = 11; 266 break; 267 case NCRJMP_J0: 268 epd->sc_irq = 10; 269 break; 270 case NCRJMP_J1: 271 epd->sc_irq = 15; 272 break; 273 default: 274 epd->sc_irq = 12; 275 break; 276 } 277 278 bus_space_write_1(iot, ioh, NCR_CFG4, 279 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 280 281 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 282 * NCRESPCFG3_FCLK even though it is documented. A bad 283 * batch of chips perhaps? 284 */ 285 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 286 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 287 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 288 & NCRESPCFG3_FCLK; 289 290 return 1; 291 } 292 293 void 294 esp_init(esc, epd) 295 struct esp_softc *esc; 296 struct esp_probe_data *epd; 297 { 298 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 299 300 ESP_TRACE(("[esp_init] ")); 301 302 /* 303 * Set up the glue for MI code early; we use some of it here. 304 */ 305 sc->sc_glue = &esp_glue; 306 307 sc->sc_rev = epd->sc_rev; 308 sc->sc_id = epd->sc_id; 309 310 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 311 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 312 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 313 sc->sc_freq = 40; 314 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 315 } 316 else 317 sc->sc_freq = 24; 318 319 /* Setup the register defaults */ 320 sc->sc_cfg1 = sc->sc_id; 321 if (epd->sc_parity) 322 sc->sc_cfg1 |= NCRCFG1_PARENB; 323 sc->sc_cfg2 = NCRCFG2_SCSI2; 324 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 325 326 /* 327 * This is the value used to start sync negotiations 328 * Note that the NCR register "SYNCTP" is programmed 329 * in "clocks per byte", and has a minimum value of 4. 330 * The SCSI period used in negotiation is one-fourth 331 * of the time (in nanoseconds) needed to transfer one byte. 332 * Since the chip's clock is given in MHz, we have the following 333 * formula: 4 * period = (1000 / freq) * 4 334 */ 335 if (epd->sc_sync) 336 { 337 #ifdef DIAGNOSTIC 338 printf("%s: sync requested, but not supported; will do async\n", 339 sc->sc_dev.dv_xname); 340 #endif 341 epd->sc_sync = 0; 342 } 343 344 sc->sc_minsync = 0; 345 346 /* Really no limit, but since we want to fit into the TCR... */ 347 sc->sc_maxxfer = 64 * 1024; 348 } 349 350 /* 351 * Check the slots looking for a board we recognise 352 * If we find one, note it's address (slot) and call 353 * the actual probe routine to check it out. 354 */ 355 int 356 esp_isa_match(parent, match, aux) 357 struct device *parent; 358 void *match, *aux; 359 { 360 struct ncr53c9x_softc *sc = match; 361 struct isa_attach_args *ia = aux; 362 bus_space_tag_t iot = ia->ia_iot; 363 bus_space_handle_t ioh; 364 struct esp_probe_data epd; 365 int rv; 366 367 ESP_TRACE(("[esp_isa_match] ")); 368 369 if (ia->ia_iobase != 0x230 && ia->ia_iobase != 0x330) { 370 #ifdef DIAGNOSTIC 371 printf("%s: invalid iobase 0x%0x, device not configured\n", 372 sc->sc_dev.dv_xname, ia->ia_iobase); 373 #endif 374 return 0; 375 } 376 377 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 378 #ifdef DIAGNOSTIC 379 printf("%s: bus_space_map() failed!\n", sc->sc_dev.dv_xname); 380 #endif 381 return 0; 382 } 383 384 epd.sc_dev = sc->sc_dev; 385 rv = esp_find(iot, ioh, &epd); 386 387 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 388 389 if (rv) { 390 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 391 #ifdef DIAGNOSTIC 392 printf("%s: configured IRQ (%0d) does not match board IRQ (%0d), device not configured\n", 393 sc->sc_dev.dv_xname, ia->ia_irq, epd.sc_irq); 394 #endif 395 return 0; 396 } 397 ia->ia_irq = epd.sc_irq; 398 ia->ia_msize = 0; 399 ia->ia_iosize = ESP_ISA_IOSIZE; 400 } 401 return (rv); 402 } 403 404 /* 405 * Attach this instance, and then all the sub-devices 406 */ 407 void 408 esp_isa_attach(parent, self, aux) 409 struct device *parent, *self; 410 void *aux; 411 { 412 struct isa_attach_args *ia = aux; 413 struct esp_softc *esc = (void *)self; 414 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 415 bus_space_tag_t iot = ia->ia_iot; 416 bus_space_handle_t ioh; 417 struct esp_probe_data epd; 418 isa_chipset_tag_t ic = ia->ia_ic; 419 420 printf("\n"); 421 ESP_TRACE(("[esp_isa_attach] ")); 422 423 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 424 panic("espattach: bus_space_map failed"); 425 426 epd.sc_dev = sc->sc_dev; 427 if (!esp_find(iot, ioh, &epd)) 428 panic("espattach: esp_find failed"); 429 430 if (ia->ia_drq != DRQUNK) 431 isa_dmacascade(ia->ia_drq); 432 433 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 434 (int (*)(void *))ncr53c9x_intr, esc); 435 if (esc->sc_ih == NULL) { 436 printf("%s: couldn't establish interrupt\n", 437 sc->sc_dev.dv_xname); 438 return; 439 } 440 441 esp_init(esc, &epd); 442 443 esc->sc_ioh = ioh; 444 esc->sc_iot = iot; 445 446 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 447 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 448 printf("%s", sc->sc_dev.dv_xname); 449 450 /* 451 * Now try to attach all the sub-devices 452 */ 453 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 454 } 455 456 /* 457 * Glue functions. 458 */ 459 u_char 460 esp_read_reg(sc, reg) 461 struct ncr53c9x_softc *sc; 462 int reg; 463 { 464 struct esp_softc *esc = (struct esp_softc *)sc; 465 u_char v; 466 467 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 468 469 ESP_REGS(("[esp_read_reg CRS%c 0x%02x=0x%02x] ", 470 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 471 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 472 473 return v; 474 } 475 476 void 477 esp_write_reg(sc, reg, val) 478 struct ncr53c9x_softc *sc; 479 int reg; 480 u_char val; 481 { 482 struct esp_softc *esc = (struct esp_softc *)sc; 483 u_char v = val; 484 485 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 486 v = NCRCMD_TRANS; 487 } 488 489 ESP_REGS(("[esp_write_reg CRS%c 0x%02x=0x%02x] ", 490 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 491 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 492 493 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 494 } 495 496 int 497 esp_dma_isintr(sc) 498 struct ncr53c9x_softc *sc; 499 { 500 ESP_TRACE(("[esp_dma_isintr] ")); 501 502 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 503 } 504 505 void 506 esp_dma_reset(sc) 507 struct ncr53c9x_softc *sc; 508 { 509 struct esp_softc *esc = (struct esp_softc *)sc; 510 511 ESP_TRACE(("[esp_dma_reset] ")); 512 513 esc->sc_active = 0; 514 esc->sc_tc = 0; 515 } 516 517 int 518 esp_dma_intr(sc) 519 struct ncr53c9x_softc *sc; 520 { 521 struct esp_softc *esc = (struct esp_softc *)sc; 522 u_char *p; 523 u_int espphase, espstat, espintr; 524 int cnt; 525 526 ESP_TRACE(("[esp_dma_intr] ")); 527 528 if (esc->sc_active == 0) { 529 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 530 return -1; 531 } 532 533 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 534 esc->sc_active = 0; 535 return 0; 536 } 537 538 cnt = *esc->sc_pdmalen; 539 if (*esc->sc_pdmalen == 0) { 540 printf("%s: data interrupt, but no count left\n", 541 sc->sc_dev.dv_xname); 542 } 543 544 p = *esc->sc_dmaaddr; 545 espphase = sc->sc_phase; 546 espstat = (u_int) sc->sc_espstat; 547 espintr = (u_int) sc->sc_espintr; 548 do { 549 if (esc->sc_datain) { 550 *p++ = NCR_READ_REG(sc, NCR_FIFO); 551 cnt--; 552 if (espphase == DATA_IN_PHASE) { 553 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 554 } else { 555 esc->sc_active = 0; 556 } 557 } else { 558 if ( (espphase == DATA_OUT_PHASE) 559 || (espphase == MESSAGE_OUT_PHASE)) { 560 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 561 cnt--; 562 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 563 } else { 564 esc->sc_active = 0; 565 } 566 } 567 568 if (esc->sc_active) { 569 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 570 espstat = NCR_READ_REG(sc, NCR_STAT); 571 espintr = NCR_READ_REG(sc, NCR_INTR); 572 espphase = (espintr & NCRINTR_DIS) 573 ? /* Disconnected */ BUSFREE_PHASE 574 : espstat & PHASE_MASK; 575 } 576 } while (esc->sc_active && espintr); 577 sc->sc_phase = espphase; 578 sc->sc_espstat = (u_char) espstat; 579 sc->sc_espintr = (u_char) espintr; 580 *esc->sc_dmaaddr = p; 581 *esc->sc_pdmalen = cnt; 582 583 if (*esc->sc_pdmalen == 0) { 584 esc->sc_tc = NCRSTAT_TC; 585 } 586 sc->sc_espstat |= esc->sc_tc; 587 return 0; 588 } 589 590 int 591 esp_dma_setup(sc, addr, len, datain, dmasize) 592 struct ncr53c9x_softc *sc; 593 caddr_t *addr; 594 size_t *len; 595 int datain; 596 size_t *dmasize; 597 { 598 struct esp_softc *esc = (struct esp_softc *)sc; 599 600 ESP_TRACE(("[esp_dma_setup] ")); 601 602 esc->sc_dmaaddr = addr; 603 esc->sc_pdmalen = len; 604 esc->sc_datain = datain; 605 esc->sc_dmasize = *dmasize; 606 esc->sc_tc = 0; 607 608 return 0; 609 } 610 611 void 612 esp_dma_go(sc) 613 struct ncr53c9x_softc *sc; 614 { 615 struct esp_softc *esc = (struct esp_softc *)sc; 616 617 ESP_TRACE(("[esp_dma_go] ")); 618 619 esc->sc_active = 1; 620 } 621 622 void 623 esp_dma_stop(sc) 624 struct ncr53c9x_softc *sc; 625 { 626 ESP_TRACE(("[esp_dma_stop] ")); 627 } 628 629 int 630 esp_dma_isactive(sc) 631 struct ncr53c9x_softc *sc; 632 { 633 struct esp_softc *esc = (struct esp_softc *)sc; 634 635 ESP_TRACE(("[esp_dma_isactive] ")); 636 637 return esc->sc_active; 638 } 639
Indexes created Mon Sep 22 21:09:42 GMT 2025