esp_isa.c revision 1.13
1 /* $NetBSD: esp_isa.c,v 1.13 1998/08/15 05:16:43 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * Copyright (c) 1995 Paul Kranenburg 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Peter Galbavy 56 * 4. The name of the author may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 61 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 62 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 67 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 68 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Based on aic6360 by Jarle Greipsland 74 * 75 * Acknowledgements: Many of the algorithms used in this driver are 76 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 77 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 78 */ 79 80 /* 81 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 82 * (basically consisting of the match, a bit of the attach, and the 83 * "DMA" glue functions). 84 */ 85 86 /* 87 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 88 * All rights reserved. 89 * 90 * Redistribution and use in source and binary forms, with or without 91 * modification, are permitted provided that the following conditions 92 * are met: 93 * 1. Redistributions of source code must retain the above copyright 94 * notice, this list of conditions and the following disclaimer. 95 * 2. Redistributions in binary form must reproduce the above copyright 96 * notice, this list of conditions and the following disclaimer in the 97 * documentation and/or other materials provided with the distribution. 98 * 3. All advertising materials mentioning features or use of this software 99 * must display the following acknowledgement: 100 * This product includes software developed by Eric S. Hvozda. 101 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 102 * derived from this software without specific prior written permission. 103 * 104 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 105 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 106 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 107 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 108 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 109 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 110 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 111 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 112 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 113 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 114 */ 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/device.h> 119 #include <sys/buf.h> 120 121 #include <machine/bus.h> 122 #include <machine/intr.h> 123 124 #include <dev/scsipi/scsi_all.h> 125 #include <dev/scsipi/scsipi_all.h> 126 #include <dev/scsipi/scsiconf.h> 127 128 #include <dev/isa/isavar.h> 129 #include <dev/isa/isadmavar.h> 130 131 #include <dev/ic/ncr53c9xreg.h> 132 #include <dev/ic/ncr53c9xvar.h> 133 134 #include <dev/isa/espvar.h> 135 136 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 137 void esp_isa_attach __P((struct device *, struct device *, void *)); 138 139 struct cfattach esp_isa_ca = { 140 sizeof(struct esp_softc), esp_isa_match, esp_isa_attach 141 }; 142 143 struct scsipi_adapter esp_switch = { 144 ncr53c9x_scsi_cmd, 145 minphys, /* no max at this level; handled by DMA code */ 146 NULL, 147 NULL, 148 }; 149 150 struct scsipi_device esp_dev = { 151 NULL, /* Use default error handler */ 152 NULL, /* have a queue, served by this */ 153 NULL, /* have no async handler */ 154 NULL, /* Use default 'done' routine */ 155 }; 156 157 int esp_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 158 159 /* 160 * Functions and the switch for the MI code. 161 */ 162 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 163 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 164 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 165 void esp_dma_reset __P((struct ncr53c9x_softc *)); 166 int esp_dma_intr __P((struct ncr53c9x_softc *)); 167 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 168 size_t *, int, size_t *)); 169 void esp_dma_go __P((struct ncr53c9x_softc *)); 170 void esp_dma_stop __P((struct ncr53c9x_softc *)); 171 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 172 173 struct ncr53c9x_glue esp_glue = { 174 esp_read_reg, 175 esp_write_reg, 176 esp_dma_isintr, 177 esp_dma_reset, 178 esp_dma_intr, 179 esp_dma_setup, 180 esp_dma_go, 181 esp_dma_stop, 182 esp_dma_isactive, 183 NULL, /* gl_clear_latched_intr */ 184 }; 185 186 /* 187 * Look for the board 188 */ 189 int 190 esp_find(iot, ioh, epd) 191 bus_space_tag_t iot; 192 bus_space_handle_t ioh; 193 struct esp_probe_data *epd; 194 { 195 u_int vers; 196 u_int p1; 197 u_int p2; 198 u_int jmp; 199 200 ESP_TRACE(("[esp_find] ")); 201 202 /* reset card before we probe? */ 203 204 /* 205 * Switch to the PIO regs and look for the bit pattern 206 * we expect... 207 */ 208 bus_space_write_1(iot, ioh, NCR_CFG4, 209 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 210 211 #define SIG_MASK 0x87 212 #define REV_MASK 0x70 213 #define M1 0x02 214 #define M2 0x05 215 #define ISNCR 0x80 216 #define ISESP406 0x40 217 218 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 219 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 220 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 221 222 ESP_MISC(("esp_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 223 224 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 225 return 0; 226 227 /* Ok, what is it? */ 228 epd->sc_isncr = (vers & ISNCR); 229 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 230 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 231 232 /* What do the jumpers tell us? */ 233 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 234 235 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 236 epd->sc_parity = jmp & NCRJMP_J2; 237 epd->sc_sync = jmp & NCRJMP_J4; 238 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 239 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 240 case NCRJMP_J0 | NCRJMP_J1: 241 epd->sc_irq = 11; 242 break; 243 case NCRJMP_J0: 244 epd->sc_irq = 10; 245 break; 246 case NCRJMP_J1: 247 epd->sc_irq = 15; 248 break; 249 default: 250 epd->sc_irq = 12; 251 break; 252 } 253 254 bus_space_write_1(iot, ioh, NCR_CFG4, 255 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 256 257 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 258 * NCRESPCFG3_FCLK even though it is documented. A bad 259 * batch of chips perhaps? 260 */ 261 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 262 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 263 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 264 & NCRESPCFG3_FCLK; 265 266 return 1; 267 } 268 269 void 270 esp_init(esc, epd) 271 struct esp_softc *esc; 272 struct esp_probe_data *epd; 273 { 274 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 275 276 ESP_TRACE(("[esp_init] ")); 277 278 /* 279 * Set up the glue for MI code early; we use some of it here. 280 */ 281 sc->sc_glue = &esp_glue; 282 283 sc->sc_rev = epd->sc_rev; 284 sc->sc_id = epd->sc_id; 285 286 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 287 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 288 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 289 sc->sc_freq = 40; 290 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 291 } 292 else 293 sc->sc_freq = 24; 294 295 /* Setup the register defaults */ 296 sc->sc_cfg1 = sc->sc_id; 297 if (epd->sc_parity) 298 sc->sc_cfg1 |= NCRCFG1_PARENB; 299 sc->sc_cfg2 = NCRCFG2_SCSI2; 300 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 301 302 /* 303 * This is the value used to start sync negotiations 304 * Note that the NCR register "SYNCTP" is programmed 305 * in "clocks per byte", and has a minimum value of 4. 306 * The SCSI period used in negotiation is one-fourth 307 * of the time (in nanoseconds) needed to transfer one byte. 308 * Since the chip's clock is given in MHz, we have the following 309 * formula: 4 * period = (1000 / freq) * 4 310 */ 311 if (epd->sc_sync) 312 { 313 #ifdef DIAGNOSTIC 314 printf("%s: sync requested, but not supported; will do async\n", 315 sc->sc_dev.dv_xname); 316 #endif 317 epd->sc_sync = 0; 318 } 319 320 sc->sc_minsync = 0; 321 322 /* Really no limit, but since we want to fit into the TCR... */ 323 sc->sc_maxxfer = 64 * 1024; 324 } 325 326 /* 327 * Check the slots looking for a board we recognise 328 * If we find one, note it's address (slot) and call 329 * the actual probe routine to check it out. 330 */ 331 int 332 esp_isa_match(parent, match, aux) 333 struct device *parent; 334 struct cfdata *match; 335 void *aux; 336 { 337 struct isa_attach_args *ia = aux; 338 bus_space_tag_t iot = ia->ia_iot; 339 bus_space_handle_t ioh; 340 struct esp_probe_data epd; 341 int rv; 342 343 ESP_TRACE(("[esp_isa_match] ")); 344 345 if (ia->ia_iobase != 0x230 && ia->ia_iobase != 0x330) 346 return 0; 347 348 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 349 return 0; 350 351 rv = esp_find(iot, ioh, &epd); 352 353 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 354 355 if (rv) { 356 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 357 #ifdef DIAGNOSTIC 358 printf("esp_isa_match: configured IRQ (%0d) does not " 359 "match board IRQ (%0d), device not configured\n", 360 ia->ia_irq, epd.sc_irq); 361 #endif 362 return 0; 363 } 364 ia->ia_irq = epd.sc_irq; 365 ia->ia_msize = 0; 366 ia->ia_iosize = ESP_ISA_IOSIZE; 367 } 368 return (rv); 369 } 370 371 /* 372 * Attach this instance, and then all the sub-devices 373 */ 374 void 375 esp_isa_attach(parent, self, aux) 376 struct device *parent, *self; 377 void *aux; 378 { 379 struct isa_attach_args *ia = aux; 380 struct esp_softc *esc = (void *)self; 381 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 382 bus_space_tag_t iot = ia->ia_iot; 383 bus_space_handle_t ioh; 384 struct esp_probe_data epd; 385 isa_chipset_tag_t ic = ia->ia_ic; 386 int error; 387 388 printf("\n"); 389 ESP_TRACE(("[esp_isa_attach] ")); 390 391 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 392 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 393 return; 394 } 395 396 if (!esp_find(iot, ioh, &epd)) { 397 printf("%s: esp_find failed\n", sc->sc_dev.dv_xname); 398 return; 399 } 400 401 if (ia->ia_drq != DRQUNK) { 402 if ((error = isa_dmacascade(ic, ia->ia_drq)) != 0) { 403 printf("%s: unable to cascade DRQ, error = %d\n", 404 sc->sc_dev.dv_xname, error); 405 return; 406 } 407 } 408 409 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 410 (int (*)(void *))ncr53c9x_intr, esc); 411 if (esc->sc_ih == NULL) { 412 printf("%s: couldn't establish interrupt\n", 413 sc->sc_dev.dv_xname); 414 return; 415 } 416 417 esp_init(esc, &epd); 418 419 esc->sc_ioh = ioh; 420 esc->sc_iot = iot; 421 422 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 423 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 424 printf("%s", sc->sc_dev.dv_xname); 425 426 /* 427 * Now try to attach all the sub-devices 428 */ 429 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 430 } 431 432 /* 433 * Glue functions. 434 */ 435 u_char 436 esp_read_reg(sc, reg) 437 struct ncr53c9x_softc *sc; 438 int reg; 439 { 440 struct esp_softc *esc = (struct esp_softc *)sc; 441 u_char v; 442 443 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 444 445 ESP_REGS(("[esp_read_reg CRS%c 0x%02x=0x%02x] ", 446 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 447 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 448 449 return v; 450 } 451 452 void 453 esp_write_reg(sc, reg, val) 454 struct ncr53c9x_softc *sc; 455 int reg; 456 u_char val; 457 { 458 struct esp_softc *esc = (struct esp_softc *)sc; 459 u_char v = val; 460 461 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 462 v = NCRCMD_TRANS; 463 } 464 465 ESP_REGS(("[esp_write_reg CRS%c 0x%02x=0x%02x] ", 466 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 467 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 468 469 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 470 } 471 472 int 473 esp_dma_isintr(sc) 474 struct ncr53c9x_softc *sc; 475 { 476 ESP_TRACE(("[esp_dma_isintr] ")); 477 478 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 479 } 480 481 void 482 esp_dma_reset(sc) 483 struct ncr53c9x_softc *sc; 484 { 485 struct esp_softc *esc = (struct esp_softc *)sc; 486 487 ESP_TRACE(("[esp_dma_reset] ")); 488 489 esc->sc_active = 0; 490 esc->sc_tc = 0; 491 } 492 493 int 494 esp_dma_intr(sc) 495 struct ncr53c9x_softc *sc; 496 { 497 struct esp_softc *esc = (struct esp_softc *)sc; 498 u_char *p; 499 u_int espphase, espstat, espintr; 500 int cnt; 501 502 ESP_TRACE(("[esp_dma_intr] ")); 503 504 if (esc->sc_active == 0) { 505 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 506 return -1; 507 } 508 509 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 510 esc->sc_active = 0; 511 return 0; 512 } 513 514 cnt = *esc->sc_pdmalen; 515 if (*esc->sc_pdmalen == 0) { 516 printf("%s: data interrupt, but no count left\n", 517 sc->sc_dev.dv_xname); 518 } 519 520 p = *esc->sc_dmaaddr; 521 espphase = sc->sc_phase; 522 espstat = (u_int) sc->sc_espstat; 523 espintr = (u_int) sc->sc_espintr; 524 do { 525 if (esc->sc_datain) { 526 *p++ = NCR_READ_REG(sc, NCR_FIFO); 527 cnt--; 528 if (espphase == DATA_IN_PHASE) { 529 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 530 } else { 531 esc->sc_active = 0; 532 } 533 } else { 534 if ( (espphase == DATA_OUT_PHASE) 535 || (espphase == MESSAGE_OUT_PHASE)) { 536 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 537 cnt--; 538 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 539 } else { 540 esc->sc_active = 0; 541 } 542 } 543 544 if (esc->sc_active) { 545 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 546 espstat = NCR_READ_REG(sc, NCR_STAT); 547 espintr = NCR_READ_REG(sc, NCR_INTR); 548 espphase = (espintr & NCRINTR_DIS) 549 ? /* Disconnected */ BUSFREE_PHASE 550 : espstat & PHASE_MASK; 551 } 552 } while (esc->sc_active && espintr); 553 sc->sc_phase = espphase; 554 sc->sc_espstat = (u_char) espstat; 555 sc->sc_espintr = (u_char) espintr; 556 *esc->sc_dmaaddr = p; 557 *esc->sc_pdmalen = cnt; 558 559 if (*esc->sc_pdmalen == 0) { 560 esc->sc_tc = NCRSTAT_TC; 561 } 562 sc->sc_espstat |= esc->sc_tc; 563 return 0; 564 } 565 566 int 567 esp_dma_setup(sc, addr, len, datain, dmasize) 568 struct ncr53c9x_softc *sc; 569 caddr_t *addr; 570 size_t *len; 571 int datain; 572 size_t *dmasize; 573 { 574 struct esp_softc *esc = (struct esp_softc *)sc; 575 576 ESP_TRACE(("[esp_dma_setup] ")); 577 578 esc->sc_dmaaddr = addr; 579 esc->sc_pdmalen = len; 580 esc->sc_datain = datain; 581 esc->sc_dmasize = *dmasize; 582 esc->sc_tc = 0; 583 584 return 0; 585 } 586 587 void 588 esp_dma_go(sc) 589 struct ncr53c9x_softc *sc; 590 { 591 struct esp_softc *esc = (struct esp_softc *)sc; 592 593 ESP_TRACE(("[esp_dma_go] ")); 594 595 esc->sc_active = 1; 596 } 597 598 void 599 esp_dma_stop(sc) 600 struct ncr53c9x_softc *sc; 601 { 602 ESP_TRACE(("[esp_dma_stop] ")); 603 } 604 605 int 606 esp_dma_isactive(sc) 607 struct ncr53c9x_softc *sc; 608 { 609 struct esp_softc *esc = (struct esp_softc *)sc; 610 611 ESP_TRACE(("[esp_dma_isactive] ")); 612 613 return esc->sc_active; 614 } 615
Indexes created Mon Sep 22 13:09:51 GMT 2025