esp_isa.c revision 1.14
1 /* $NetBSD: esp_isa.c,v 1.14 1998/09/05 17:23:09 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 81 * (basically consisting of the match, a bit of the attach, and the 82 * "DMA" glue functions). 83 */ 84 85 /* 86 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 87 * All rights reserved. 88 * 89 * Redistribution and use in source and binary forms, with or without 90 * modification, are permitted provided that the following conditions 91 * are met: 92 * 1. Redistributions of source code must retain the above copyright 93 * notice, this list of conditions and the following disclaimer. 94 * 2. Redistributions in binary form must reproduce the above copyright 95 * notice, this list of conditions and the following disclaimer in the 96 * documentation and/or other materials provided with the distribution. 97 * 3. All advertising materials mentioning features or use of this software 98 * must display the following acknowledgement: 99 * This product includes software developed by Eric S. Hvozda. 100 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 101 * derived from this software without specific prior written permission. 102 * 103 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 104 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 105 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 106 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 107 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 108 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 109 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 110 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 111 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 112 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 113 */ 114 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/device.h> 118 #include <sys/buf.h> 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 123 #include <dev/scsipi/scsi_all.h> 124 #include <dev/scsipi/scsipi_all.h> 125 #include <dev/scsipi/scsiconf.h> 126 127 #include <dev/isa/isavar.h> 128 #include <dev/isa/isadmavar.h> 129 130 #include <dev/ic/ncr53c9xreg.h> 131 #include <dev/ic/ncr53c9xvar.h> 132 133 #include <dev/isa/espvar.h> 134 135 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 136 void esp_isa_attach __P((struct device *, struct device *, void *)); 137 138 struct cfattach esp_isa_ca = { 139 sizeof(struct esp_softc), esp_isa_match, esp_isa_attach 140 }; 141 142 struct scsipi_adapter esp_switch = { 143 ncr53c9x_scsi_cmd, 144 minphys, /* no max at this level; handled by DMA code */ 145 NULL, 146 NULL, 147 }; 148 149 struct scsipi_device esp_dev = { 150 NULL, /* Use default error handler */ 151 NULL, /* have a queue, served by this */ 152 NULL, /* have no async handler */ 153 NULL, /* Use default 'done' routine */ 154 }; 155 156 int esp_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 157 158 /* 159 * Functions and the switch for the MI code. 160 */ 161 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 162 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 163 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 164 void esp_dma_reset __P((struct ncr53c9x_softc *)); 165 int esp_dma_intr __P((struct ncr53c9x_softc *)); 166 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 167 size_t *, int, size_t *)); 168 void esp_dma_go __P((struct ncr53c9x_softc *)); 169 void esp_dma_stop __P((struct ncr53c9x_softc *)); 170 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 171 172 struct ncr53c9x_glue esp_glue = { 173 esp_read_reg, 174 esp_write_reg, 175 esp_dma_isintr, 176 esp_dma_reset, 177 esp_dma_intr, 178 esp_dma_setup, 179 esp_dma_go, 180 esp_dma_stop, 181 esp_dma_isactive, 182 NULL, /* gl_clear_latched_intr */ 183 }; 184 185 /* 186 * Look for the board 187 */ 188 int 189 esp_find(iot, ioh, epd) 190 bus_space_tag_t iot; 191 bus_space_handle_t ioh; 192 struct esp_probe_data *epd; 193 { 194 u_int vers; 195 u_int p1; 196 u_int p2; 197 u_int jmp; 198 199 ESP_TRACE(("[esp_find] ")); 200 201 /* reset card before we probe? */ 202 203 /* 204 * Switch to the PIO regs and look for the bit pattern 205 * we expect... 206 */ 207 bus_space_write_1(iot, ioh, NCR_CFG4, 208 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 209 210 #define SIG_MASK 0x87 211 #define REV_MASK 0x70 212 #define M1 0x02 213 #define M2 0x05 214 #define ISNCR 0x80 215 #define ISESP406 0x40 216 217 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 218 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 219 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 220 221 ESP_MISC(("esp_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 222 223 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 224 return 0; 225 226 /* Ok, what is it? */ 227 epd->sc_isncr = (vers & ISNCR); 228 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 229 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 230 231 /* What do the jumpers tell us? */ 232 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 233 234 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 235 epd->sc_parity = jmp & NCRJMP_J2; 236 epd->sc_sync = jmp & NCRJMP_J4; 237 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 238 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 239 case NCRJMP_J0 | NCRJMP_J1: 240 epd->sc_irq = 11; 241 break; 242 case NCRJMP_J0: 243 epd->sc_irq = 10; 244 break; 245 case NCRJMP_J1: 246 epd->sc_irq = 15; 247 break; 248 default: 249 epd->sc_irq = 12; 250 break; 251 } 252 253 bus_space_write_1(iot, ioh, NCR_CFG4, 254 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 255 256 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 257 * NCRESPCFG3_FCLK even though it is documented. A bad 258 * batch of chips perhaps? 259 */ 260 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 261 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 262 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 263 & NCRESPCFG3_FCLK; 264 265 return 1; 266 } 267 268 void 269 esp_init(esc, epd) 270 struct esp_softc *esc; 271 struct esp_probe_data *epd; 272 { 273 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 274 275 ESP_TRACE(("[esp_init] ")); 276 277 /* 278 * Set up the glue for MI code early; we use some of it here. 279 */ 280 sc->sc_glue = &esp_glue; 281 282 sc->sc_rev = epd->sc_rev; 283 sc->sc_id = epd->sc_id; 284 285 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 286 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 287 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 288 sc->sc_freq = 40; 289 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 290 } 291 else 292 sc->sc_freq = 24; 293 294 /* Setup the register defaults */ 295 sc->sc_cfg1 = sc->sc_id; 296 if (epd->sc_parity) 297 sc->sc_cfg1 |= NCRCFG1_PARENB; 298 sc->sc_cfg2 = NCRCFG2_SCSI2; 299 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 300 301 /* 302 * This is the value used to start sync negotiations 303 * Note that the NCR register "SYNCTP" is programmed 304 * in "clocks per byte", and has a minimum value of 4. 305 * The SCSI period used in negotiation is one-fourth 306 * of the time (in nanoseconds) needed to transfer one byte. 307 * Since the chip's clock is given in MHz, we have the following 308 * formula: 4 * period = (1000 / freq) * 4 309 */ 310 if (epd->sc_sync) 311 { 312 #ifdef DIAGNOSTIC 313 printf("%s: sync requested, but not supported; will do async\n", 314 sc->sc_dev.dv_xname); 315 #endif 316 epd->sc_sync = 0; 317 } 318 319 sc->sc_minsync = 0; 320 321 /* Really no limit, but since we want to fit into the TCR... */ 322 sc->sc_maxxfer = 64 * 1024; 323 } 324 325 /* 326 * Check the slots looking for a board we recognise 327 * If we find one, note it's address (slot) and call 328 * the actual probe routine to check it out. 329 */ 330 int 331 esp_isa_match(parent, match, aux) 332 struct device *parent; 333 struct cfdata *match; 334 void *aux; 335 { 336 struct isa_attach_args *ia = aux; 337 bus_space_tag_t iot = ia->ia_iot; 338 bus_space_handle_t ioh; 339 struct esp_probe_data epd; 340 int rv; 341 342 ESP_TRACE(("[esp_isa_match] ")); 343 344 if (ia->ia_iobase != 0x230 && ia->ia_iobase != 0x330) 345 return 0; 346 347 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 348 return 0; 349 350 rv = esp_find(iot, ioh, &epd); 351 352 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 353 354 if (rv) { 355 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 356 #ifdef DIAGNOSTIC 357 printf("esp_isa_match: configured IRQ (%0d) does not " 358 "match board IRQ (%0d), device not configured\n", 359 ia->ia_irq, epd.sc_irq); 360 #endif 361 return 0; 362 } 363 ia->ia_irq = epd.sc_irq; 364 ia->ia_msize = 0; 365 ia->ia_iosize = ESP_ISA_IOSIZE; 366 } 367 return (rv); 368 } 369 370 /* 371 * Attach this instance, and then all the sub-devices 372 */ 373 void 374 esp_isa_attach(parent, self, aux) 375 struct device *parent, *self; 376 void *aux; 377 { 378 struct isa_attach_args *ia = aux; 379 struct esp_softc *esc = (void *)self; 380 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 381 bus_space_tag_t iot = ia->ia_iot; 382 bus_space_handle_t ioh; 383 struct esp_probe_data epd; 384 isa_chipset_tag_t ic = ia->ia_ic; 385 int error; 386 387 printf("\n"); 388 ESP_TRACE(("[esp_isa_attach] ")); 389 390 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 391 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 392 return; 393 } 394 395 if (!esp_find(iot, ioh, &epd)) { 396 printf("%s: esp_find failed\n", sc->sc_dev.dv_xname); 397 return; 398 } 399 400 if (ia->ia_drq != DRQUNK) { 401 if ((error = isa_dmacascade(ic, ia->ia_drq)) != 0) { 402 printf("%s: unable to cascade DRQ, error = %d\n", 403 sc->sc_dev.dv_xname, error); 404 return; 405 } 406 } 407 408 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 409 (int (*)(void *))ncr53c9x_intr, esc); 410 if (esc->sc_ih == NULL) { 411 printf("%s: couldn't establish interrupt\n", 412 sc->sc_dev.dv_xname); 413 return; 414 } 415 416 esp_init(esc, &epd); 417 418 esc->sc_ioh = ioh; 419 esc->sc_iot = iot; 420 421 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 422 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 423 printf("%s", sc->sc_dev.dv_xname); 424 425 /* 426 * Now try to attach all the sub-devices 427 */ 428 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 429 } 430 431 /* 432 * Glue functions. 433 */ 434 u_char 435 esp_read_reg(sc, reg) 436 struct ncr53c9x_softc *sc; 437 int reg; 438 { 439 struct esp_softc *esc = (struct esp_softc *)sc; 440 u_char v; 441 442 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 443 444 ESP_REGS(("[esp_read_reg CRS%c 0x%02x=0x%02x] ", 445 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 446 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 447 448 return v; 449 } 450 451 void 452 esp_write_reg(sc, reg, val) 453 struct ncr53c9x_softc *sc; 454 int reg; 455 u_char val; 456 { 457 struct esp_softc *esc = (struct esp_softc *)sc; 458 u_char v = val; 459 460 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 461 v = NCRCMD_TRANS; 462 } 463 464 ESP_REGS(("[esp_write_reg CRS%c 0x%02x=0x%02x] ", 465 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 466 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 467 468 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 469 } 470 471 int 472 esp_dma_isintr(sc) 473 struct ncr53c9x_softc *sc; 474 { 475 ESP_TRACE(("[esp_dma_isintr] ")); 476 477 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 478 } 479 480 void 481 esp_dma_reset(sc) 482 struct ncr53c9x_softc *sc; 483 { 484 struct esp_softc *esc = (struct esp_softc *)sc; 485 486 ESP_TRACE(("[esp_dma_reset] ")); 487 488 esc->sc_active = 0; 489 esc->sc_tc = 0; 490 } 491 492 int 493 esp_dma_intr(sc) 494 struct ncr53c9x_softc *sc; 495 { 496 struct esp_softc *esc = (struct esp_softc *)sc; 497 u_char *p; 498 u_int espphase, espstat, espintr; 499 int cnt; 500 501 ESP_TRACE(("[esp_dma_intr] ")); 502 503 if (esc->sc_active == 0) { 504 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 505 return -1; 506 } 507 508 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 509 esc->sc_active = 0; 510 return 0; 511 } 512 513 cnt = *esc->sc_pdmalen; 514 if (*esc->sc_pdmalen == 0) { 515 printf("%s: data interrupt, but no count left\n", 516 sc->sc_dev.dv_xname); 517 } 518 519 p = *esc->sc_dmaaddr; 520 espphase = sc->sc_phase; 521 espstat = (u_int) sc->sc_espstat; 522 espintr = (u_int) sc->sc_espintr; 523 do { 524 if (esc->sc_datain) { 525 *p++ = NCR_READ_REG(sc, NCR_FIFO); 526 cnt--; 527 if (espphase == DATA_IN_PHASE) { 528 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 529 } else { 530 esc->sc_active = 0; 531 } 532 } else { 533 if ( (espphase == DATA_OUT_PHASE) 534 || (espphase == MESSAGE_OUT_PHASE)) { 535 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 536 cnt--; 537 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 538 } else { 539 esc->sc_active = 0; 540 } 541 } 542 543 if (esc->sc_active) { 544 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 545 espstat = NCR_READ_REG(sc, NCR_STAT); 546 espintr = NCR_READ_REG(sc, NCR_INTR); 547 espphase = (espintr & NCRINTR_DIS) 548 ? /* Disconnected */ BUSFREE_PHASE 549 : espstat & PHASE_MASK; 550 } 551 } while (esc->sc_active && espintr); 552 sc->sc_phase = espphase; 553 sc->sc_espstat = (u_char) espstat; 554 sc->sc_espintr = (u_char) espintr; 555 *esc->sc_dmaaddr = p; 556 *esc->sc_pdmalen = cnt; 557 558 if (*esc->sc_pdmalen == 0) { 559 esc->sc_tc = NCRSTAT_TC; 560 } 561 sc->sc_espstat |= esc->sc_tc; 562 return 0; 563 } 564 565 int 566 esp_dma_setup(sc, addr, len, datain, dmasize) 567 struct ncr53c9x_softc *sc; 568 caddr_t *addr; 569 size_t *len; 570 int datain; 571 size_t *dmasize; 572 { 573 struct esp_softc *esc = (struct esp_softc *)sc; 574 575 ESP_TRACE(("[esp_dma_setup] ")); 576 577 esc->sc_dmaaddr = addr; 578 esc->sc_pdmalen = len; 579 esc->sc_datain = datain; 580 esc->sc_dmasize = *dmasize; 581 esc->sc_tc = 0; 582 583 return 0; 584 } 585 586 void 587 esp_dma_go(sc) 588 struct ncr53c9x_softc *sc; 589 { 590 struct esp_softc *esc = (struct esp_softc *)sc; 591 592 ESP_TRACE(("[esp_dma_go] ")); 593 594 esc->sc_active = 1; 595 } 596 597 void 598 esp_dma_stop(sc) 599 struct ncr53c9x_softc *sc; 600 { 601 ESP_TRACE(("[esp_dma_stop] ")); 602 } 603 604 int 605 esp_dma_isactive(sc) 606 struct ncr53c9x_softc *sc; 607 { 608 struct esp_softc *esc = (struct esp_softc *)sc; 609 610 ESP_TRACE(("[esp_dma_isactive] ")); 611 612 return esc->sc_active; 613 } 614
Indexes created Mon Oct 13 21:09:55 GMT 2025