esp_isa.c revision 1.15
1 /* $NetBSD: esp_isa.c,v 1.15 1998/10/10 00:28:34 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 81 * (basically consisting of the match, a bit of the attach, and the 82 * "DMA" glue functions). 83 */ 84 85 /* 86 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 87 * All rights reserved. 88 * 89 * Redistribution and use in source and binary forms, with or without 90 * modification, are permitted provided that the following conditions 91 * are met: 92 * 1. Redistributions of source code must retain the above copyright 93 * notice, this list of conditions and the following disclaimer. 94 * 2. Redistributions in binary form must reproduce the above copyright 95 * notice, this list of conditions and the following disclaimer in the 96 * documentation and/or other materials provided with the distribution. 97 * 3. All advertising materials mentioning features or use of this software 98 * must display the following acknowledgement: 99 * This product includes software developed by Eric S. Hvozda. 100 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 101 * derived from this software without specific prior written permission. 102 * 103 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 104 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 105 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 106 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 107 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 108 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 109 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 110 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 111 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 112 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 113 */ 114 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/device.h> 118 #include <sys/buf.h> 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 123 #include <dev/scsipi/scsi_all.h> 124 #include <dev/scsipi/scsipi_all.h> 125 #include <dev/scsipi/scsiconf.h> 126 127 #include <dev/isa/isavar.h> 128 #include <dev/isa/isadmavar.h> 129 130 #include <dev/ic/ncr53c9xreg.h> 131 #include <dev/ic/ncr53c9xvar.h> 132 133 #include <dev/isa/espvar.h> 134 135 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 136 void esp_isa_attach __P((struct device *, struct device *, void *)); 137 138 struct cfattach esp_isa_ca = { 139 sizeof(struct esp_softc), esp_isa_match, esp_isa_attach 140 }; 141 142 struct scsipi_adapter esp_switch = { 143 ncr53c9x_scsi_cmd, 144 minphys, /* no max at this level; handled by DMA code */ 145 NULL, /* scsipi_ioctl */ 146 }; 147 148 struct scsipi_device esp_dev = { 149 NULL, /* Use default error handler */ 150 NULL, /* have a queue, served by this */ 151 NULL, /* have no async handler */ 152 NULL, /* Use default 'done' routine */ 153 }; 154 155 int esp_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 156 157 /* 158 * Functions and the switch for the MI code. 159 */ 160 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 161 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 162 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 163 void esp_dma_reset __P((struct ncr53c9x_softc *)); 164 int esp_dma_intr __P((struct ncr53c9x_softc *)); 165 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 166 size_t *, int, size_t *)); 167 void esp_dma_go __P((struct ncr53c9x_softc *)); 168 void esp_dma_stop __P((struct ncr53c9x_softc *)); 169 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 170 171 struct ncr53c9x_glue esp_glue = { 172 esp_read_reg, 173 esp_write_reg, 174 esp_dma_isintr, 175 esp_dma_reset, 176 esp_dma_intr, 177 esp_dma_setup, 178 esp_dma_go, 179 esp_dma_stop, 180 esp_dma_isactive, 181 NULL, /* gl_clear_latched_intr */ 182 }; 183 184 /* 185 * Look for the board 186 */ 187 int 188 esp_find(iot, ioh, epd) 189 bus_space_tag_t iot; 190 bus_space_handle_t ioh; 191 struct esp_probe_data *epd; 192 { 193 u_int vers; 194 u_int p1; 195 u_int p2; 196 u_int jmp; 197 198 ESP_TRACE(("[esp_find] ")); 199 200 /* reset card before we probe? */ 201 202 /* 203 * Switch to the PIO regs and look for the bit pattern 204 * we expect... 205 */ 206 bus_space_write_1(iot, ioh, NCR_CFG4, 207 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 208 209 #define SIG_MASK 0x87 210 #define REV_MASK 0x70 211 #define M1 0x02 212 #define M2 0x05 213 #define ISNCR 0x80 214 #define ISESP406 0x40 215 216 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 217 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 218 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 219 220 ESP_MISC(("esp_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 221 222 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 223 return 0; 224 225 /* Ok, what is it? */ 226 epd->sc_isncr = (vers & ISNCR); 227 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 228 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 229 230 /* What do the jumpers tell us? */ 231 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 232 233 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 234 epd->sc_parity = jmp & NCRJMP_J2; 235 epd->sc_sync = jmp & NCRJMP_J4; 236 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 237 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 238 case NCRJMP_J0 | NCRJMP_J1: 239 epd->sc_irq = 11; 240 break; 241 case NCRJMP_J0: 242 epd->sc_irq = 10; 243 break; 244 case NCRJMP_J1: 245 epd->sc_irq = 15; 246 break; 247 default: 248 epd->sc_irq = 12; 249 break; 250 } 251 252 bus_space_write_1(iot, ioh, NCR_CFG4, 253 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 254 255 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 256 * NCRESPCFG3_FCLK even though it is documented. A bad 257 * batch of chips perhaps? 258 */ 259 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 260 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 261 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 262 & NCRESPCFG3_FCLK; 263 264 return 1; 265 } 266 267 void 268 esp_init(esc, epd) 269 struct esp_softc *esc; 270 struct esp_probe_data *epd; 271 { 272 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 273 274 ESP_TRACE(("[esp_init] ")); 275 276 /* 277 * Set up the glue for MI code early; we use some of it here. 278 */ 279 sc->sc_glue = &esp_glue; 280 281 sc->sc_rev = epd->sc_rev; 282 sc->sc_id = epd->sc_id; 283 284 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 285 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 286 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 287 sc->sc_freq = 40; 288 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 289 } 290 else 291 sc->sc_freq = 24; 292 293 /* Setup the register defaults */ 294 sc->sc_cfg1 = sc->sc_id; 295 if (epd->sc_parity) 296 sc->sc_cfg1 |= NCRCFG1_PARENB; 297 sc->sc_cfg2 = NCRCFG2_SCSI2; 298 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 299 300 /* 301 * This is the value used to start sync negotiations 302 * Note that the NCR register "SYNCTP" is programmed 303 * in "clocks per byte", and has a minimum value of 4. 304 * The SCSI period used in negotiation is one-fourth 305 * of the time (in nanoseconds) needed to transfer one byte. 306 * Since the chip's clock is given in MHz, we have the following 307 * formula: 4 * period = (1000 / freq) * 4 308 */ 309 if (epd->sc_sync) 310 { 311 #ifdef DIAGNOSTIC 312 printf("%s: sync requested, but not supported; will do async\n", 313 sc->sc_dev.dv_xname); 314 #endif 315 epd->sc_sync = 0; 316 } 317 318 sc->sc_minsync = 0; 319 320 /* Really no limit, but since we want to fit into the TCR... */ 321 sc->sc_maxxfer = 64 * 1024; 322 } 323 324 /* 325 * Check the slots looking for a board we recognise 326 * If we find one, note it's address (slot) and call 327 * the actual probe routine to check it out. 328 */ 329 int 330 esp_isa_match(parent, match, aux) 331 struct device *parent; 332 struct cfdata *match; 333 void *aux; 334 { 335 struct isa_attach_args *ia = aux; 336 bus_space_tag_t iot = ia->ia_iot; 337 bus_space_handle_t ioh; 338 struct esp_probe_data epd; 339 int rv; 340 341 ESP_TRACE(("[esp_isa_match] ")); 342 343 if (ia->ia_iobase != 0x230 && ia->ia_iobase != 0x330) 344 return 0; 345 346 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 347 return 0; 348 349 rv = esp_find(iot, ioh, &epd); 350 351 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 352 353 if (rv) { 354 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 355 #ifdef DIAGNOSTIC 356 printf("esp_isa_match: configured IRQ (%0d) does not " 357 "match board IRQ (%0d), device not configured\n", 358 ia->ia_irq, epd.sc_irq); 359 #endif 360 return 0; 361 } 362 ia->ia_irq = epd.sc_irq; 363 ia->ia_msize = 0; 364 ia->ia_iosize = ESP_ISA_IOSIZE; 365 } 366 return (rv); 367 } 368 369 /* 370 * Attach this instance, and then all the sub-devices 371 */ 372 void 373 esp_isa_attach(parent, self, aux) 374 struct device *parent, *self; 375 void *aux; 376 { 377 struct isa_attach_args *ia = aux; 378 struct esp_softc *esc = (void *)self; 379 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 380 bus_space_tag_t iot = ia->ia_iot; 381 bus_space_handle_t ioh; 382 struct esp_probe_data epd; 383 isa_chipset_tag_t ic = ia->ia_ic; 384 int error; 385 386 printf("\n"); 387 ESP_TRACE(("[esp_isa_attach] ")); 388 389 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 390 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 391 return; 392 } 393 394 if (!esp_find(iot, ioh, &epd)) { 395 printf("%s: esp_find failed\n", sc->sc_dev.dv_xname); 396 return; 397 } 398 399 if (ia->ia_drq != DRQUNK) { 400 if ((error = isa_dmacascade(ic, ia->ia_drq)) != 0) { 401 printf("%s: unable to cascade DRQ, error = %d\n", 402 sc->sc_dev.dv_xname, error); 403 return; 404 } 405 } 406 407 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 408 (int (*)(void *))ncr53c9x_intr, esc); 409 if (esc->sc_ih == NULL) { 410 printf("%s: couldn't establish interrupt\n", 411 sc->sc_dev.dv_xname); 412 return; 413 } 414 415 esp_init(esc, &epd); 416 417 esc->sc_ioh = ioh; 418 esc->sc_iot = iot; 419 420 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 421 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 422 printf("%s", sc->sc_dev.dv_xname); 423 424 /* 425 * Now try to attach all the sub-devices 426 */ 427 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 428 } 429 430 /* 431 * Glue functions. 432 */ 433 u_char 434 esp_read_reg(sc, reg) 435 struct ncr53c9x_softc *sc; 436 int reg; 437 { 438 struct esp_softc *esc = (struct esp_softc *)sc; 439 u_char v; 440 441 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 442 443 ESP_REGS(("[esp_read_reg CRS%c 0x%02x=0x%02x] ", 444 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 445 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 446 447 return v; 448 } 449 450 void 451 esp_write_reg(sc, reg, val) 452 struct ncr53c9x_softc *sc; 453 int reg; 454 u_char val; 455 { 456 struct esp_softc *esc = (struct esp_softc *)sc; 457 u_char v = val; 458 459 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 460 v = NCRCMD_TRANS; 461 } 462 463 ESP_REGS(("[esp_write_reg CRS%c 0x%02x=0x%02x] ", 464 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 465 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 466 467 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 468 } 469 470 int 471 esp_dma_isintr(sc) 472 struct ncr53c9x_softc *sc; 473 { 474 ESP_TRACE(("[esp_dma_isintr] ")); 475 476 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 477 } 478 479 void 480 esp_dma_reset(sc) 481 struct ncr53c9x_softc *sc; 482 { 483 struct esp_softc *esc = (struct esp_softc *)sc; 484 485 ESP_TRACE(("[esp_dma_reset] ")); 486 487 esc->sc_active = 0; 488 esc->sc_tc = 0; 489 } 490 491 int 492 esp_dma_intr(sc) 493 struct ncr53c9x_softc *sc; 494 { 495 struct esp_softc *esc = (struct esp_softc *)sc; 496 u_char *p; 497 u_int espphase, espstat, espintr; 498 int cnt; 499 500 ESP_TRACE(("[esp_dma_intr] ")); 501 502 if (esc->sc_active == 0) { 503 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 504 return -1; 505 } 506 507 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 508 esc->sc_active = 0; 509 return 0; 510 } 511 512 cnt = *esc->sc_pdmalen; 513 if (*esc->sc_pdmalen == 0) { 514 printf("%s: data interrupt, but no count left\n", 515 sc->sc_dev.dv_xname); 516 } 517 518 p = *esc->sc_dmaaddr; 519 espphase = sc->sc_phase; 520 espstat = (u_int) sc->sc_espstat; 521 espintr = (u_int) sc->sc_espintr; 522 do { 523 if (esc->sc_datain) { 524 *p++ = NCR_READ_REG(sc, NCR_FIFO); 525 cnt--; 526 if (espphase == DATA_IN_PHASE) { 527 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 528 } else { 529 esc->sc_active = 0; 530 } 531 } else { 532 if ( (espphase == DATA_OUT_PHASE) 533 || (espphase == MESSAGE_OUT_PHASE)) { 534 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 535 cnt--; 536 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 537 } else { 538 esc->sc_active = 0; 539 } 540 } 541 542 if (esc->sc_active) { 543 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 544 espstat = NCR_READ_REG(sc, NCR_STAT); 545 espintr = NCR_READ_REG(sc, NCR_INTR); 546 espphase = (espintr & NCRINTR_DIS) 547 ? /* Disconnected */ BUSFREE_PHASE 548 : espstat & PHASE_MASK; 549 } 550 } while (esc->sc_active && espintr); 551 sc->sc_phase = espphase; 552 sc->sc_espstat = (u_char) espstat; 553 sc->sc_espintr = (u_char) espintr; 554 *esc->sc_dmaaddr = p; 555 *esc->sc_pdmalen = cnt; 556 557 if (*esc->sc_pdmalen == 0) { 558 esc->sc_tc = NCRSTAT_TC; 559 } 560 sc->sc_espstat |= esc->sc_tc; 561 return 0; 562 } 563 564 int 565 esp_dma_setup(sc, addr, len, datain, dmasize) 566 struct ncr53c9x_softc *sc; 567 caddr_t *addr; 568 size_t *len; 569 int datain; 570 size_t *dmasize; 571 { 572 struct esp_softc *esc = (struct esp_softc *)sc; 573 574 ESP_TRACE(("[esp_dma_setup] ")); 575 576 esc->sc_dmaaddr = addr; 577 esc->sc_pdmalen = len; 578 esc->sc_datain = datain; 579 esc->sc_dmasize = *dmasize; 580 esc->sc_tc = 0; 581 582 return 0; 583 } 584 585 void 586 esp_dma_go(sc) 587 struct ncr53c9x_softc *sc; 588 { 589 struct esp_softc *esc = (struct esp_softc *)sc; 590 591 ESP_TRACE(("[esp_dma_go] ")); 592 593 esc->sc_active = 1; 594 } 595 596 void 597 esp_dma_stop(sc) 598 struct ncr53c9x_softc *sc; 599 { 600 ESP_TRACE(("[esp_dma_stop] ")); 601 } 602 603 int 604 esp_dma_isactive(sc) 605 struct ncr53c9x_softc *sc; 606 { 607 struct esp_softc *esc = (struct esp_softc *)sc; 608 609 ESP_TRACE(("[esp_dma_isactive] ")); 610 611 return esc->sc_active; 612 } 613
Indexes created Wed Oct 15 07:09:58 GMT 2025