esp_isa.c revision 1.17
1 /* $NetBSD: esp_isa.c,v 1.17 2000/03/18 21:49:33 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 81 * (basically consisting of the match, a bit of the attach, and the 82 * "DMA" glue functions). 83 */ 84 85 /* 86 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 87 * All rights reserved. 88 * 89 * Redistribution and use in source and binary forms, with or without 90 * modification, are permitted provided that the following conditions 91 * are met: 92 * 1. Redistributions of source code must retain the above copyright 93 * notice, this list of conditions and the following disclaimer. 94 * 2. Redistributions in binary form must reproduce the above copyright 95 * notice, this list of conditions and the following disclaimer in the 96 * documentation and/or other materials provided with the distribution. 97 * 3. All advertising materials mentioning features or use of this software 98 * must display the following acknowledgement: 99 * This product includes software developed by Eric S. Hvozda. 100 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 101 * derived from this software without specific prior written permission. 102 * 103 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 104 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 105 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 106 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 107 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 108 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 109 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 110 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 111 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 112 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 113 */ 114 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/device.h> 118 #include <sys/buf.h> 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 123 #include <dev/scsipi/scsi_all.h> 124 #include <dev/scsipi/scsipi_all.h> 125 #include <dev/scsipi/scsiconf.h> 126 127 #include <dev/isa/isavar.h> 128 #include <dev/isa/isadmavar.h> 129 130 #include <dev/ic/ncr53c9xreg.h> 131 #include <dev/ic/ncr53c9xvar.h> 132 133 #include <dev/isa/espvar.h> 134 135 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 136 void esp_isa_attach __P((struct device *, struct device *, void *)); 137 138 struct cfattach esp_isa_ca = { 139 sizeof(struct esp_isa_softc), esp_isa_match, esp_isa_attach 140 }; 141 142 struct scsipi_device esp_isa_dev = { 143 NULL, /* Use default error handler */ 144 NULL, /* have a queue, served by this */ 145 NULL, /* have no async handler */ 146 NULL, /* Use default 'done' routine */ 147 }; 148 149 int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 150 151 /* 152 * Functions and the switch for the MI code. 153 */ 154 u_char esp_isa_read_reg __P((struct ncr53c9x_softc *, int)); 155 void esp_isa_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 156 int esp_isa_dma_isintr __P((struct ncr53c9x_softc *)); 157 void esp_isa_dma_reset __P((struct ncr53c9x_softc *)); 158 int esp_isa_dma_intr __P((struct ncr53c9x_softc *)); 159 int esp_isa_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 160 size_t *, int, size_t *)); 161 void esp_isa_dma_go __P((struct ncr53c9x_softc *)); 162 void esp_isa_dma_stop __P((struct ncr53c9x_softc *)); 163 int esp_isa_dma_isactive __P((struct ncr53c9x_softc *)); 164 165 struct ncr53c9x_glue esp_isa_glue = { 166 esp_isa_read_reg, 167 esp_isa_write_reg, 168 esp_isa_dma_isintr, 169 esp_isa_dma_reset, 170 esp_isa_dma_intr, 171 esp_isa_dma_setup, 172 esp_isa_dma_go, 173 esp_isa_dma_stop, 174 esp_isa_dma_isactive, 175 NULL, /* gl_clear_latched_intr */ 176 }; 177 178 /* 179 * Look for the board 180 */ 181 int 182 esp_isa_find(iot, ioh, epd) 183 bus_space_tag_t iot; 184 bus_space_handle_t ioh; 185 struct esp_isa_probe_data *epd; 186 { 187 u_int vers; 188 u_int p1; 189 u_int p2; 190 u_int jmp; 191 192 ESP_TRACE(("[esp_isa_find] ")); 193 194 /* reset card before we probe? */ 195 196 /* 197 * Switch to the PIO regs and look for the bit pattern 198 * we expect... 199 */ 200 bus_space_write_1(iot, ioh, NCR_CFG4, 201 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 202 203 #define SIG_MASK 0x87 204 #define REV_MASK 0x70 205 #define M1 0x02 206 #define M2 0x05 207 #define ISNCR 0x80 208 #define ISESP406 0x40 209 210 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 211 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 212 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 213 214 ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 215 216 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 217 return 0; 218 219 /* Ok, what is it? */ 220 epd->sc_isncr = (vers & ISNCR); 221 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 222 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 223 224 /* What do the jumpers tell us? */ 225 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 226 227 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 228 epd->sc_parity = jmp & NCRJMP_J2; 229 epd->sc_sync = jmp & NCRJMP_J4; 230 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 231 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 232 case NCRJMP_J0 | NCRJMP_J1: 233 epd->sc_irq = 11; 234 break; 235 case NCRJMP_J0: 236 epd->sc_irq = 10; 237 break; 238 case NCRJMP_J1: 239 epd->sc_irq = 15; 240 break; 241 default: 242 epd->sc_irq = 12; 243 break; 244 } 245 246 bus_space_write_1(iot, ioh, NCR_CFG4, 247 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 248 249 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 250 * NCRESPCFG3_FCLK even though it is documented. A bad 251 * batch of chips perhaps? 252 */ 253 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 254 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 255 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 256 & NCRESPCFG3_FCLK; 257 258 return 1; 259 } 260 261 void 262 esp_isa_init(esc, epd) 263 struct esp_isa_softc *esc; 264 struct esp_isa_probe_data *epd; 265 { 266 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 267 268 ESP_TRACE(("[esp_isa_init] ")); 269 270 /* 271 * Set up the glue for MI code early; we use some of it here. 272 */ 273 sc->sc_glue = &esp_isa_glue; 274 275 sc->sc_rev = epd->sc_rev; 276 sc->sc_id = epd->sc_id; 277 278 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 279 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 280 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 281 sc->sc_freq = 40; 282 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 283 } 284 else 285 sc->sc_freq = 24; 286 287 /* Setup the register defaults */ 288 sc->sc_cfg1 = sc->sc_id; 289 if (epd->sc_parity) 290 sc->sc_cfg1 |= NCRCFG1_PARENB; 291 sc->sc_cfg2 = NCRCFG2_SCSI2; 292 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 293 294 /* 295 * This is the value used to start sync negotiations 296 * Note that the NCR register "SYNCTP" is programmed 297 * in "clocks per byte", and has a minimum value of 4. 298 * The SCSI period used in negotiation is one-fourth 299 * of the time (in nanoseconds) needed to transfer one byte. 300 * Since the chip's clock is given in MHz, we have the following 301 * formula: 4 * period = (1000 / freq) * 4 302 */ 303 if (epd->sc_sync) 304 { 305 #ifdef DIAGNOSTIC 306 printf("%s: sync requested, but not supported; will do async\n", 307 sc->sc_dev.dv_xname); 308 #endif 309 epd->sc_sync = 0; 310 } 311 312 sc->sc_minsync = 0; 313 314 /* Really no limit, but since we want to fit into the TCR... */ 315 sc->sc_maxxfer = 64 * 1024; 316 } 317 318 /* 319 * Check the slots looking for a board we recognise 320 * If we find one, note it's address (slot) and call 321 * the actual probe routine to check it out. 322 */ 323 int 324 esp_isa_match(parent, match, aux) 325 struct device *parent; 326 struct cfdata *match; 327 void *aux; 328 { 329 struct isa_attach_args *ia = aux; 330 bus_space_tag_t iot = ia->ia_iot; 331 bus_space_handle_t ioh; 332 struct esp_isa_probe_data epd; 333 int rv; 334 335 ESP_TRACE(("[esp_isa_match] ")); 336 337 if (ia->ia_iobase == -1) 338 return 0; 339 340 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 341 return 0; 342 343 rv = esp_isa_find(iot, ioh, &epd); 344 345 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 346 347 if (rv) { 348 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 349 #ifdef DIAGNOSTIC 350 printf("esp_isa_match: configured IRQ (%0d) does not " 351 "match board IRQ (%0d), device not configured\n", 352 ia->ia_irq, epd.sc_irq); 353 #endif 354 return 0; 355 } 356 ia->ia_irq = epd.sc_irq; 357 ia->ia_msize = 0; 358 ia->ia_iosize = ESP_ISA_IOSIZE; 359 } 360 return (rv); 361 } 362 363 /* 364 * Attach this instance, and then all the sub-devices 365 */ 366 void 367 esp_isa_attach(parent, self, aux) 368 struct device *parent, *self; 369 void *aux; 370 { 371 struct isa_attach_args *ia = aux; 372 struct esp_isa_softc *esc = (void *)self; 373 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 374 bus_space_tag_t iot = ia->ia_iot; 375 bus_space_handle_t ioh; 376 struct esp_isa_probe_data epd; 377 isa_chipset_tag_t ic = ia->ia_ic; 378 int error; 379 380 printf("\n"); 381 ESP_TRACE(("[esp_isa_attach] ")); 382 383 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 384 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 385 return; 386 } 387 388 if (!esp_isa_find(iot, ioh, &epd)) { 389 printf("%s: esp_isa_find failed\n", sc->sc_dev.dv_xname); 390 return; 391 } 392 393 if (ia->ia_drq != DRQUNK) { 394 if ((error = isa_dmacascade(ic, ia->ia_drq)) != 0) { 395 printf("%s: unable to cascade DRQ, error = %d\n", 396 sc->sc_dev.dv_xname, error); 397 return; 398 } 399 } 400 401 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 402 (int (*)(void *))ncr53c9x_intr, esc); 403 if (esc->sc_ih == NULL) { 404 printf("%s: couldn't establish interrupt\n", 405 sc->sc_dev.dv_xname); 406 return; 407 } 408 409 esc->sc_ioh = ioh; 410 esc->sc_iot = iot; 411 esp_isa_init(esc, &epd); 412 413 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 414 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 415 printf("%s", sc->sc_dev.dv_xname); 416 417 /* 418 * Now try to attach all the sub-devices 419 */ 420 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 421 sc->sc_adapter.scsipi_minphys = minphys; 422 ncr53c9x_attach(sc, &esp_isa_dev); 423 } 424 425 /* 426 * Glue functions. 427 */ 428 u_char 429 esp_isa_read_reg(sc, reg) 430 struct ncr53c9x_softc *sc; 431 int reg; 432 { 433 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 434 u_char v; 435 436 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 437 438 ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ", 439 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 440 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 441 442 return v; 443 } 444 445 void 446 esp_isa_write_reg(sc, reg, val) 447 struct ncr53c9x_softc *sc; 448 int reg; 449 u_char val; 450 { 451 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 452 u_char v = val; 453 454 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 455 v = NCRCMD_TRANS; 456 } 457 458 ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ", 459 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 460 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 461 462 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 463 } 464 465 int 466 esp_isa_dma_isintr(sc) 467 struct ncr53c9x_softc *sc; 468 { 469 ESP_TRACE(("[esp_isa_dma_isintr] ")); 470 471 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 472 } 473 474 void 475 esp_isa_dma_reset(sc) 476 struct ncr53c9x_softc *sc; 477 { 478 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 479 480 ESP_TRACE(("[esp_isa_dma_reset] ")); 481 482 esc->sc_active = 0; 483 esc->sc_tc = 0; 484 } 485 486 int 487 esp_isa_dma_intr(sc) 488 struct ncr53c9x_softc *sc; 489 { 490 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 491 u_char *p; 492 u_int espphase, espstat, espintr; 493 int cnt; 494 495 ESP_TRACE(("[esp_isa_dma_intr] ")); 496 497 if (esc->sc_active == 0) { 498 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 499 return -1; 500 } 501 502 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 503 esc->sc_active = 0; 504 return 0; 505 } 506 507 cnt = *esc->sc_pdmalen; 508 if (*esc->sc_pdmalen == 0) { 509 printf("%s: data interrupt, but no count left\n", 510 sc->sc_dev.dv_xname); 511 } 512 513 p = *esc->sc_dmaaddr; 514 espphase = sc->sc_phase; 515 espstat = (u_int) sc->sc_espstat; 516 espintr = (u_int) sc->sc_espintr; 517 do { 518 if (esc->sc_datain) { 519 *p++ = NCR_READ_REG(sc, NCR_FIFO); 520 cnt--; 521 if (espphase == DATA_IN_PHASE) { 522 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 523 } else { 524 esc->sc_active = 0; 525 } 526 } else { 527 if ( (espphase == DATA_OUT_PHASE) 528 || (espphase == MESSAGE_OUT_PHASE)) { 529 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 530 cnt--; 531 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 532 } else { 533 esc->sc_active = 0; 534 } 535 } 536 537 if (esc->sc_active) { 538 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 539 espstat = NCR_READ_REG(sc, NCR_STAT); 540 espintr = NCR_READ_REG(sc, NCR_INTR); 541 espphase = (espintr & NCRINTR_DIS) 542 ? /* Disconnected */ BUSFREE_PHASE 543 : espstat & PHASE_MASK; 544 } 545 } while (esc->sc_active && espintr); 546 sc->sc_phase = espphase; 547 sc->sc_espstat = (u_char) espstat; 548 sc->sc_espintr = (u_char) espintr; 549 *esc->sc_dmaaddr = p; 550 *esc->sc_pdmalen = cnt; 551 552 if (*esc->sc_pdmalen == 0) { 553 esc->sc_tc = NCRSTAT_TC; 554 } 555 sc->sc_espstat |= esc->sc_tc; 556 return 0; 557 } 558 559 int 560 esp_isa_dma_setup(sc, addr, len, datain, dmasize) 561 struct ncr53c9x_softc *sc; 562 caddr_t *addr; 563 size_t *len; 564 int datain; 565 size_t *dmasize; 566 { 567 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 568 569 ESP_TRACE(("[esp_isa_dma_setup] ")); 570 571 esc->sc_dmaaddr = addr; 572 esc->sc_pdmalen = len; 573 esc->sc_datain = datain; 574 esc->sc_dmasize = *dmasize; 575 esc->sc_tc = 0; 576 577 return 0; 578 } 579 580 void 581 esp_isa_dma_go(sc) 582 struct ncr53c9x_softc *sc; 583 { 584 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 585 586 ESP_TRACE(("[esp_isa_dma_go] ")); 587 588 esc->sc_active = 1; 589 } 590 591 void 592 esp_isa_dma_stop(sc) 593 struct ncr53c9x_softc *sc; 594 { 595 ESP_TRACE(("[esp_isa_dma_stop] ")); 596 } 597 598 int 599 esp_isa_dma_isactive(sc) 600 struct ncr53c9x_softc *sc; 601 { 602 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 603 604 ESP_TRACE(("[esp_isa_dma_isactive] ")); 605 606 return esc->sc_active; 607 } 608
Indexes created Mon Sep 22 21:09:42 GMT 2025