esp_isa.c revision 1.19
1 /* $NetBSD: esp_isa.c,v 1.19 2000/03/19 21:27:01 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 81 * (basically consisting of the match, a bit of the attach, and the 82 * "DMA" glue functions). 83 */ 84 85 /* 86 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 87 * All rights reserved. 88 * 89 * Redistribution and use in source and binary forms, with or without 90 * modification, are permitted provided that the following conditions 91 * are met: 92 * 1. Redistributions of source code must retain the above copyright 93 * notice, this list of conditions and the following disclaimer. 94 * 2. Redistributions in binary form must reproduce the above copyright 95 * notice, this list of conditions and the following disclaimer in the 96 * documentation and/or other materials provided with the distribution. 97 * 3. All advertising materials mentioning features or use of this software 98 * must display the following acknowledgement: 99 * This product includes software developed by Eric S. Hvozda. 100 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 101 * derived from this software without specific prior written permission. 102 * 103 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 104 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 105 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 106 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 107 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 108 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 109 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 110 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 111 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 112 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 113 */ 114 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/device.h> 118 #include <sys/buf.h> 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 123 #include <dev/scsipi/scsi_all.h> 124 #include <dev/scsipi/scsipi_all.h> 125 #include <dev/scsipi/scsiconf.h> 126 127 #include <dev/isa/isavar.h> 128 #include <dev/isa/isadmavar.h> 129 130 #include <dev/ic/ncr53c9xreg.h> 131 #include <dev/ic/ncr53c9xvar.h> 132 133 #include <dev/isa/esp_isavar.h> 134 135 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 136 void esp_isa_attach __P((struct device *, struct device *, void *)); 137 138 struct cfattach esp_isa_ca = { 139 sizeof(struct esp_isa_softc), esp_isa_match, esp_isa_attach 140 }; 141 142 struct scsipi_device esp_isa_dev = { 143 NULL, /* Use default error handler */ 144 NULL, /* have a queue, served by this */ 145 NULL, /* have no async handler */ 146 NULL, /* Use default 'done' routine */ 147 }; 148 149 int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 150 151 /* 152 * Functions and the switch for the MI code. 153 */ 154 u_char esp_isa_read_reg __P((struct ncr53c9x_softc *, int)); 155 void esp_isa_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 156 int esp_isa_dma_isintr __P((struct ncr53c9x_softc *)); 157 void esp_isa_dma_reset __P((struct ncr53c9x_softc *)); 158 int esp_isa_dma_intr __P((struct ncr53c9x_softc *)); 159 int esp_isa_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 160 size_t *, int, size_t *)); 161 void esp_isa_dma_go __P((struct ncr53c9x_softc *)); 162 void esp_isa_dma_stop __P((struct ncr53c9x_softc *)); 163 int esp_isa_dma_isactive __P((struct ncr53c9x_softc *)); 164 165 struct ncr53c9x_glue esp_isa_glue = { 166 esp_isa_read_reg, 167 esp_isa_write_reg, 168 esp_isa_dma_isintr, 169 esp_isa_dma_reset, 170 esp_isa_dma_intr, 171 esp_isa_dma_setup, 172 esp_isa_dma_go, 173 esp_isa_dma_stop, 174 esp_isa_dma_isactive, 175 NULL, /* gl_clear_latched_intr */ 176 }; 177 178 /* 179 * Look for the board 180 */ 181 int 182 esp_isa_find(iot, ioh, epd) 183 bus_space_tag_t iot; 184 bus_space_handle_t ioh; 185 struct esp_isa_probe_data *epd; 186 { 187 u_int vers; 188 u_int p1; 189 u_int p2; 190 u_int jmp; 191 192 ESP_TRACE(("[esp_isa_find] ")); 193 194 /* reset card before we probe? */ 195 196 epd->sc_cfg4 = NCRCFG4_ACTNEG; 197 epd->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC; 198 199 /* 200 * Switch to the PIO regs and look for the bit pattern 201 * we expect... 202 */ 203 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 204 205 #define SIG_MASK 0x87 206 #define REV_MASK 0x70 207 #define M1 0x02 208 #define M2 0x05 209 #define ISNCR 0x80 210 #define ISESP406 0x40 211 212 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 213 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 214 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 215 216 ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 217 218 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 219 return 0; 220 221 /* Ok, what is it? */ 222 epd->sc_isncr = (vers & ISNCR); 223 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 224 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 225 226 /* What do the jumpers tell us? */ 227 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 228 229 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 230 epd->sc_parity = jmp & NCRJMP_J2; 231 epd->sc_sync = jmp & NCRJMP_J4; 232 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 233 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 234 case NCRJMP_J0 | NCRJMP_J1: 235 epd->sc_irq = 11; 236 break; 237 case NCRJMP_J0: 238 epd->sc_irq = 10; 239 break; 240 case NCRJMP_J1: 241 epd->sc_irq = 15; 242 break; 243 default: 244 epd->sc_irq = 12; 245 break; 246 } 247 248 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 249 250 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 251 * NCRESPCFG3_FCLK even though it is documented. A bad 252 * batch of chips perhaps? 253 */ 254 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 255 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 256 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 257 & NCRESPCFG3_FCLK; 258 259 return 1; 260 } 261 262 void 263 esp_isa_init(esc, epd) 264 struct esp_isa_softc *esc; 265 struct esp_isa_probe_data *epd; 266 { 267 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 268 269 ESP_TRACE(("[esp_isa_init] ")); 270 271 /* 272 * Set up the glue for MI code early; we use some of it here. 273 */ 274 sc->sc_glue = &esp_isa_glue; 275 276 sc->sc_rev = epd->sc_rev; 277 sc->sc_id = epd->sc_id; 278 279 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 280 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 281 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 282 sc->sc_freq = 40; 283 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 284 } else 285 sc->sc_freq = 24; 286 287 /* Setup the register defaults */ 288 sc->sc_cfg1 = sc->sc_id; 289 if (epd->sc_parity) 290 sc->sc_cfg1 |= NCRCFG1_PARENB; 291 sc->sc_cfg2 = NCRCFG2_SCSI2; 292 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 293 sc->sc_cfg4 = epd->sc_cfg4; 294 sc->sc_cfg5 = epd->sc_cfg5; 295 296 /* 297 * This is the value used to start sync negotiations 298 * Note that the NCR register "SYNCTP" is programmed 299 * in "clocks per byte", and has a minimum value of 4. 300 * The SCSI period used in negotiation is one-fourth 301 * of the time (in nanoseconds) needed to transfer one byte. 302 * Since the chip's clock is given in MHz, we have the following 303 * formula: 4 * period = (1000 / freq) * 4 304 */ 305 if (epd->sc_sync) 306 { 307 #ifdef DIAGNOSTIC 308 printf("%s: sync requested, but not supported; will do async\n", 309 sc->sc_dev.dv_xname); 310 #endif 311 epd->sc_sync = 0; 312 } 313 314 sc->sc_minsync = 0; 315 316 /* Really no limit, but since we want to fit into the TCR... */ 317 sc->sc_maxxfer = 64 * 1024; 318 } 319 320 /* 321 * Check the slots looking for a board we recognise 322 * If we find one, note it's address (slot) and call 323 * the actual probe routine to check it out. 324 */ 325 int 326 esp_isa_match(parent, match, aux) 327 struct device *parent; 328 struct cfdata *match; 329 void *aux; 330 { 331 struct isa_attach_args *ia = aux; 332 bus_space_tag_t iot = ia->ia_iot; 333 bus_space_handle_t ioh; 334 struct esp_isa_probe_data epd; 335 int rv; 336 337 ESP_TRACE(("[esp_isa_match] ")); 338 339 if (ia->ia_iobase == -1) 340 return 0; 341 342 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 343 return 0; 344 345 rv = esp_isa_find(iot, ioh, &epd); 346 347 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 348 349 if (rv) { 350 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 351 #ifdef DIAGNOSTIC 352 printf("esp_isa_match: configured IRQ (%0d) does not " 353 "match board IRQ (%0d), device not configured\n", 354 ia->ia_irq, epd.sc_irq); 355 #endif 356 return 0; 357 } 358 ia->ia_irq = epd.sc_irq; 359 ia->ia_msize = 0; 360 ia->ia_iosize = ESP_ISA_IOSIZE; 361 } 362 return (rv); 363 } 364 365 /* 366 * Attach this instance, and then all the sub-devices 367 */ 368 void 369 esp_isa_attach(parent, self, aux) 370 struct device *parent, *self; 371 void *aux; 372 { 373 struct isa_attach_args *ia = aux; 374 struct esp_isa_softc *esc = (void *)self; 375 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 376 bus_space_tag_t iot = ia->ia_iot; 377 bus_space_handle_t ioh; 378 struct esp_isa_probe_data epd; 379 isa_chipset_tag_t ic = ia->ia_ic; 380 int error; 381 382 printf("\n"); 383 ESP_TRACE(("[esp_isa_attach] ")); 384 385 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 386 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 387 return; 388 } 389 390 if (!esp_isa_find(iot, ioh, &epd)) { 391 printf("%s: esp_isa_find failed\n", sc->sc_dev.dv_xname); 392 return; 393 } 394 395 if (ia->ia_drq != DRQUNK) { 396 if ((error = isa_dmacascade(ic, ia->ia_drq)) != 0) { 397 printf("%s: unable to cascade DRQ, error = %d\n", 398 sc->sc_dev.dv_xname, error); 399 return; 400 } 401 } 402 403 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 404 (int (*)(void *))ncr53c9x_intr, esc); 405 if (esc->sc_ih == NULL) { 406 printf("%s: couldn't establish interrupt\n", 407 sc->sc_dev.dv_xname); 408 return; 409 } 410 411 esc->sc_ioh = ioh; 412 esc->sc_iot = iot; 413 esp_isa_init(esc, &epd); 414 415 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 416 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 417 printf("%s", sc->sc_dev.dv_xname); 418 419 /* 420 * Now try to attach all the sub-devices 421 */ 422 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 423 sc->sc_adapter.scsipi_minphys = minphys; 424 ncr53c9x_attach(sc, &esp_isa_dev); 425 } 426 427 /* 428 * Glue functions. 429 */ 430 u_char 431 esp_isa_read_reg(sc, reg) 432 struct ncr53c9x_softc *sc; 433 int reg; 434 { 435 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 436 u_char v; 437 438 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 439 440 ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ", 441 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 442 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 443 444 return v; 445 } 446 447 void 448 esp_isa_write_reg(sc, reg, val) 449 struct ncr53c9x_softc *sc; 450 int reg; 451 u_char val; 452 { 453 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 454 u_char v = val; 455 456 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 457 v = NCRCMD_TRANS; 458 } 459 460 ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ", 461 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 462 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 463 464 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 465 } 466 467 int 468 esp_isa_dma_isintr(sc) 469 struct ncr53c9x_softc *sc; 470 { 471 ESP_TRACE(("[esp_isa_dma_isintr] ")); 472 473 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 474 } 475 476 void 477 esp_isa_dma_reset(sc) 478 struct ncr53c9x_softc *sc; 479 { 480 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 481 482 ESP_TRACE(("[esp_isa_dma_reset] ")); 483 484 esc->sc_active = 0; 485 esc->sc_tc = 0; 486 } 487 488 int 489 esp_isa_dma_intr(sc) 490 struct ncr53c9x_softc *sc; 491 { 492 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 493 u_char *p; 494 u_int espphase, espstat, espintr; 495 int cnt; 496 497 ESP_TRACE(("[esp_isa_dma_intr] ")); 498 499 if (esc->sc_active == 0) { 500 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 501 return -1; 502 } 503 504 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 505 esc->sc_active = 0; 506 return 0; 507 } 508 509 cnt = *esc->sc_pdmalen; 510 if (*esc->sc_pdmalen == 0) { 511 printf("%s: data interrupt, but no count left\n", 512 sc->sc_dev.dv_xname); 513 } 514 515 p = *esc->sc_dmaaddr; 516 espphase = sc->sc_phase; 517 espstat = (u_int) sc->sc_espstat; 518 espintr = (u_int) sc->sc_espintr; 519 do { 520 if (esc->sc_datain) { 521 *p++ = NCR_READ_REG(sc, NCR_FIFO); 522 cnt--; 523 if (espphase == DATA_IN_PHASE) { 524 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 525 } else { 526 esc->sc_active = 0; 527 } 528 } else { 529 if ( (espphase == DATA_OUT_PHASE) 530 || (espphase == MESSAGE_OUT_PHASE)) { 531 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 532 cnt--; 533 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 534 } else { 535 esc->sc_active = 0; 536 } 537 } 538 539 if (esc->sc_active) { 540 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 541 espstat = NCR_READ_REG(sc, NCR_STAT); 542 espintr = NCR_READ_REG(sc, NCR_INTR); 543 espphase = (espintr & NCRINTR_DIS) 544 ? /* Disconnected */ BUSFREE_PHASE 545 : espstat & PHASE_MASK; 546 } 547 } while (esc->sc_active && espintr); 548 sc->sc_phase = espphase; 549 sc->sc_espstat = (u_char) espstat; 550 sc->sc_espintr = (u_char) espintr; 551 *esc->sc_dmaaddr = p; 552 *esc->sc_pdmalen = cnt; 553 554 if (*esc->sc_pdmalen == 0) { 555 esc->sc_tc = NCRSTAT_TC; 556 } 557 sc->sc_espstat |= esc->sc_tc; 558 return 0; 559 } 560 561 int 562 esp_isa_dma_setup(sc, addr, len, datain, dmasize) 563 struct ncr53c9x_softc *sc; 564 caddr_t *addr; 565 size_t *len; 566 int datain; 567 size_t *dmasize; 568 { 569 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 570 571 ESP_TRACE(("[esp_isa_dma_setup] ")); 572 573 esc->sc_dmaaddr = addr; 574 esc->sc_pdmalen = len; 575 esc->sc_datain = datain; 576 esc->sc_dmasize = *dmasize; 577 esc->sc_tc = 0; 578 579 return 0; 580 } 581 582 void 583 esp_isa_dma_go(sc) 584 struct ncr53c9x_softc *sc; 585 { 586 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 587 588 ESP_TRACE(("[esp_isa_dma_go] ")); 589 590 esc->sc_active = 1; 591 } 592 593 void 594 esp_isa_dma_stop(sc) 595 struct ncr53c9x_softc *sc; 596 { 597 ESP_TRACE(("[esp_isa_dma_stop] ")); 598 } 599 600 int 601 esp_isa_dma_isactive(sc) 602 struct ncr53c9x_softc *sc; 603 { 604 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 605 606 ESP_TRACE(("[esp_isa_dma_isactive] ")); 607 608 return esc->sc_active; 609 } 610
Indexes created Tue Sep 23 07:09:52 GMT 2025