esp_isa.c revision 1.22
1 /* $NetBSD: esp_isa.c,v 1.22 2001/04/25 17:53:35 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 81 * (basically consisting of the match, a bit of the attach, and the 82 * "DMA" glue functions). 83 */ 84 85 /* 86 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 87 * All rights reserved. 88 * 89 * Redistribution and use in source and binary forms, with or without 90 * modification, are permitted provided that the following conditions 91 * are met: 92 * 1. Redistributions of source code must retain the above copyright 93 * notice, this list of conditions and the following disclaimer. 94 * 2. Redistributions in binary form must reproduce the above copyright 95 * notice, this list of conditions and the following disclaimer in the 96 * documentation and/or other materials provided with the distribution. 97 * 3. All advertising materials mentioning features or use of this software 98 * must display the following acknowledgement: 99 * This product includes software developed by Eric S. Hvozda. 100 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 101 * derived from this software without specific prior written permission. 102 * 103 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 104 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 105 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 106 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 107 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 108 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 109 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 110 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 111 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 112 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 113 */ 114 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/device.h> 118 #include <sys/buf.h> 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 123 #include <dev/scsipi/scsipi_all.h> 124 #include <dev/scsipi/scsi_all.h> 125 #include <dev/scsipi/scsiconf.h> 126 127 #include <dev/isa/isavar.h> 128 #include <dev/isa/isadmavar.h> 129 130 #include <dev/ic/ncr53c9xreg.h> 131 #include <dev/ic/ncr53c9xvar.h> 132 133 #include <dev/isa/esp_isavar.h> 134 135 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 136 void esp_isa_attach __P((struct device *, struct device *, void *)); 137 138 struct cfattach esp_isa_ca = { 139 sizeof(struct esp_isa_softc), esp_isa_match, esp_isa_attach 140 }; 141 142 int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 143 144 /* 145 * Functions and the switch for the MI code. 146 */ 147 u_char esp_isa_read_reg __P((struct ncr53c9x_softc *, int)); 148 void esp_isa_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 149 int esp_isa_dma_isintr __P((struct ncr53c9x_softc *)); 150 void esp_isa_dma_reset __P((struct ncr53c9x_softc *)); 151 int esp_isa_dma_intr __P((struct ncr53c9x_softc *)); 152 int esp_isa_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 153 size_t *, int, size_t *)); 154 void esp_isa_dma_go __P((struct ncr53c9x_softc *)); 155 void esp_isa_dma_stop __P((struct ncr53c9x_softc *)); 156 int esp_isa_dma_isactive __P((struct ncr53c9x_softc *)); 157 158 struct ncr53c9x_glue esp_isa_glue = { 159 esp_isa_read_reg, 160 esp_isa_write_reg, 161 esp_isa_dma_isintr, 162 esp_isa_dma_reset, 163 esp_isa_dma_intr, 164 esp_isa_dma_setup, 165 esp_isa_dma_go, 166 esp_isa_dma_stop, 167 esp_isa_dma_isactive, 168 NULL, /* gl_clear_latched_intr */ 169 }; 170 171 /* 172 * Look for the board 173 */ 174 int 175 esp_isa_find(iot, ioh, epd) 176 bus_space_tag_t iot; 177 bus_space_handle_t ioh; 178 struct esp_isa_probe_data *epd; 179 { 180 u_int vers; 181 u_int p1; 182 u_int p2; 183 u_int jmp; 184 185 ESP_TRACE(("[esp_isa_find] ")); 186 187 /* reset card before we probe? */ 188 189 epd->sc_cfg4 = NCRCFG4_ACTNEG; 190 epd->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC; 191 192 /* 193 * Switch to the PIO regs and look for the bit pattern 194 * we expect... 195 */ 196 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 197 198 #define SIG_MASK 0x87 199 #define REV_MASK 0x70 200 #define M1 0x02 201 #define M2 0x05 202 #define ISNCR 0x80 203 #define ISESP406 0x40 204 205 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 206 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 207 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 208 209 ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 210 211 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 212 return 0; 213 214 /* Ok, what is it? */ 215 epd->sc_isncr = (vers & ISNCR); 216 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 217 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 218 219 /* What do the jumpers tell us? */ 220 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 221 222 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 223 epd->sc_parity = jmp & NCRJMP_J2; 224 epd->sc_sync = jmp & NCRJMP_J4; 225 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 226 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 227 case NCRJMP_J0 | NCRJMP_J1: 228 epd->sc_irq = 11; 229 break; 230 case NCRJMP_J0: 231 epd->sc_irq = 10; 232 break; 233 case NCRJMP_J1: 234 epd->sc_irq = 15; 235 break; 236 default: 237 epd->sc_irq = 12; 238 break; 239 } 240 241 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 242 243 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 244 * NCRESPCFG3_FCLK even though it is documented. A bad 245 * batch of chips perhaps? 246 */ 247 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 248 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 249 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 250 & NCRESPCFG3_FCLK; 251 252 return 1; 253 } 254 255 void 256 esp_isa_init(esc, epd) 257 struct esp_isa_softc *esc; 258 struct esp_isa_probe_data *epd; 259 { 260 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 261 262 ESP_TRACE(("[esp_isa_init] ")); 263 264 /* 265 * Set up the glue for MI code early; we use some of it here. 266 */ 267 sc->sc_glue = &esp_isa_glue; 268 269 sc->sc_rev = epd->sc_rev; 270 sc->sc_id = epd->sc_id; 271 272 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 273 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 274 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 275 sc->sc_freq = 40; 276 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 277 } else 278 sc->sc_freq = 24; 279 280 /* Setup the register defaults */ 281 sc->sc_cfg1 = sc->sc_id; 282 if (epd->sc_parity) 283 sc->sc_cfg1 |= NCRCFG1_PARENB; 284 sc->sc_cfg2 = NCRCFG2_SCSI2; 285 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 286 sc->sc_cfg4 = epd->sc_cfg4; 287 sc->sc_cfg5 = epd->sc_cfg5; 288 289 /* 290 * This is the value used to start sync negotiations 291 * Note that the NCR register "SYNCTP" is programmed 292 * in "clocks per byte", and has a minimum value of 4. 293 * The SCSI period used in negotiation is one-fourth 294 * of the time (in nanoseconds) needed to transfer one byte. 295 * Since the chip's clock is given in MHz, we have the following 296 * formula: 4 * period = (1000 / freq) * 4 297 */ 298 if (epd->sc_sync) 299 { 300 #ifdef DIAGNOSTIC 301 printf("%s: sync requested, but not supported; will do async\n", 302 sc->sc_dev.dv_xname); 303 #endif 304 epd->sc_sync = 0; 305 } 306 307 sc->sc_minsync = 0; 308 309 /* Really no limit, but since we want to fit into the TCR... */ 310 sc->sc_maxxfer = 64 * 1024; 311 } 312 313 /* 314 * Check the slots looking for a board we recognise 315 * If we find one, note it's address (slot) and call 316 * the actual probe routine to check it out. 317 */ 318 int 319 esp_isa_match(parent, match, aux) 320 struct device *parent; 321 struct cfdata *match; 322 void *aux; 323 { 324 struct isa_attach_args *ia = aux; 325 bus_space_tag_t iot = ia->ia_iot; 326 bus_space_handle_t ioh; 327 struct esp_isa_probe_data epd; 328 int rv; 329 330 ESP_TRACE(("[esp_isa_match] ")); 331 332 if (ia->ia_iobase == -1) 333 return 0; 334 335 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 336 return 0; 337 338 rv = esp_isa_find(iot, ioh, &epd); 339 340 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 341 342 if (rv) { 343 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 344 #ifdef DIAGNOSTIC 345 printf("esp_isa_match: configured IRQ (%0d) does not " 346 "match board IRQ (%0d), device not configured\n", 347 ia->ia_irq, epd.sc_irq); 348 #endif 349 return 0; 350 } 351 ia->ia_irq = epd.sc_irq; 352 ia->ia_msize = 0; 353 ia->ia_iosize = ESP_ISA_IOSIZE; 354 } 355 return (rv); 356 } 357 358 /* 359 * Attach this instance, and then all the sub-devices 360 */ 361 void 362 esp_isa_attach(parent, self, aux) 363 struct device *parent, *self; 364 void *aux; 365 { 366 struct isa_attach_args *ia = aux; 367 struct esp_isa_softc *esc = (void *)self; 368 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 369 bus_space_tag_t iot = ia->ia_iot; 370 bus_space_handle_t ioh; 371 struct esp_isa_probe_data epd; 372 isa_chipset_tag_t ic = ia->ia_ic; 373 int error; 374 375 printf("\n"); 376 ESP_TRACE(("[esp_isa_attach] ")); 377 378 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 379 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 380 return; 381 } 382 383 if (!esp_isa_find(iot, ioh, &epd)) { 384 printf("%s: esp_isa_find failed\n", sc->sc_dev.dv_xname); 385 return; 386 } 387 388 if (ia->ia_drq != DRQUNK) { 389 if ((error = isa_dmacascade(ic, ia->ia_drq)) != 0) { 390 printf("%s: unable to cascade DRQ, error = %d\n", 391 sc->sc_dev.dv_xname, error); 392 return; 393 } 394 } 395 396 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 397 ncr53c9x_intr, esc); 398 if (esc->sc_ih == NULL) { 399 printf("%s: couldn't establish interrupt\n", 400 sc->sc_dev.dv_xname); 401 return; 402 } 403 404 esc->sc_ioh = ioh; 405 esc->sc_iot = iot; 406 esp_isa_init(esc, &epd); 407 408 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 409 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 410 printf("%s", sc->sc_dev.dv_xname); 411 412 /* 413 * Now try to attach all the sub-devices 414 */ 415 sc->sc_adapter.adapt_minphys = minphys; 416 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 417 ncr53c9x_attach(sc); 418 } 419 420 /* 421 * Glue functions. 422 */ 423 u_char 424 esp_isa_read_reg(sc, reg) 425 struct ncr53c9x_softc *sc; 426 int reg; 427 { 428 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 429 u_char v; 430 431 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 432 433 ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ", 434 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 435 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 436 437 return v; 438 } 439 440 void 441 esp_isa_write_reg(sc, reg, val) 442 struct ncr53c9x_softc *sc; 443 int reg; 444 u_char val; 445 { 446 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 447 u_char v = val; 448 449 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 450 v = NCRCMD_TRANS; 451 } 452 453 ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ", 454 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 455 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 456 457 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 458 } 459 460 int 461 esp_isa_dma_isintr(sc) 462 struct ncr53c9x_softc *sc; 463 { 464 ESP_TRACE(("[esp_isa_dma_isintr] ")); 465 466 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 467 } 468 469 void 470 esp_isa_dma_reset(sc) 471 struct ncr53c9x_softc *sc; 472 { 473 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 474 475 ESP_TRACE(("[esp_isa_dma_reset] ")); 476 477 esc->sc_active = 0; 478 esc->sc_tc = 0; 479 } 480 481 int 482 esp_isa_dma_intr(sc) 483 struct ncr53c9x_softc *sc; 484 { 485 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 486 u_char *p; 487 u_int espphase, espstat, espintr; 488 int cnt; 489 490 ESP_TRACE(("[esp_isa_dma_intr] ")); 491 492 if (esc->sc_active == 0) { 493 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 494 return -1; 495 } 496 497 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 498 esc->sc_active = 0; 499 return 0; 500 } 501 502 cnt = *esc->sc_pdmalen; 503 if (*esc->sc_pdmalen == 0) { 504 printf("%s: data interrupt, but no count left\n", 505 sc->sc_dev.dv_xname); 506 } 507 508 p = *esc->sc_dmaaddr; 509 espphase = sc->sc_phase; 510 espstat = (u_int) sc->sc_espstat; 511 espintr = (u_int) sc->sc_espintr; 512 do { 513 if (esc->sc_datain) { 514 *p++ = NCR_READ_REG(sc, NCR_FIFO); 515 cnt--; 516 if (espphase == DATA_IN_PHASE) { 517 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 518 } else { 519 esc->sc_active = 0; 520 } 521 } else { 522 if ( (espphase == DATA_OUT_PHASE) 523 || (espphase == MESSAGE_OUT_PHASE)) { 524 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 525 cnt--; 526 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 527 } else { 528 esc->sc_active = 0; 529 } 530 } 531 532 if (esc->sc_active) { 533 while (!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT)); 534 espstat = NCR_READ_REG(sc, NCR_STAT); 535 espintr = NCR_READ_REG(sc, NCR_INTR); 536 espphase = (espintr & NCRINTR_DIS) 537 ? /* Disconnected */ BUSFREE_PHASE 538 : espstat & PHASE_MASK; 539 } 540 } while (esc->sc_active && espintr); 541 sc->sc_phase = espphase; 542 sc->sc_espstat = (u_char) espstat; 543 sc->sc_espintr = (u_char) espintr; 544 *esc->sc_dmaaddr = p; 545 *esc->sc_pdmalen = cnt; 546 547 if (*esc->sc_pdmalen == 0) { 548 esc->sc_tc = NCRSTAT_TC; 549 } 550 sc->sc_espstat |= esc->sc_tc; 551 return 0; 552 } 553 554 int 555 esp_isa_dma_setup(sc, addr, len, datain, dmasize) 556 struct ncr53c9x_softc *sc; 557 caddr_t *addr; 558 size_t *len; 559 int datain; 560 size_t *dmasize; 561 { 562 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 563 564 ESP_TRACE(("[esp_isa_dma_setup] ")); 565 566 esc->sc_dmaaddr = addr; 567 esc->sc_pdmalen = len; 568 esc->sc_datain = datain; 569 esc->sc_dmasize = *dmasize; 570 esc->sc_tc = 0; 571 572 return 0; 573 } 574 575 void 576 esp_isa_dma_go(sc) 577 struct ncr53c9x_softc *sc; 578 { 579 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 580 581 ESP_TRACE(("[esp_isa_dma_go] ")); 582 583 esc->sc_active = 1; 584 } 585 586 void 587 esp_isa_dma_stop(sc) 588 struct ncr53c9x_softc *sc; 589 { 590 ESP_TRACE(("[esp_isa_dma_stop] ")); 591 } 592 593 int 594 esp_isa_dma_isactive(sc) 595 struct ncr53c9x_softc *sc; 596 { 597 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 598 599 ESP_TRACE(("[esp_isa_dma_isactive] ")); 600 601 return esc->sc_active; 602 } 603
Indexes created Mon Sep 22 13:09:51 GMT 2025