esp_isa.c revision 1.24
1 /* $NetBSD: esp_isa.c,v 1.24 2002/01/08 17:20:44 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 81 * (basically consisting of the match, a bit of the attach, and the 82 * "DMA" glue functions). 83 */ 84 85 /* 86 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 87 * All rights reserved. 88 * 89 * Redistribution and use in source and binary forms, with or without 90 * modification, are permitted provided that the following conditions 91 * are met: 92 * 1. Redistributions of source code must retain the above copyright 93 * notice, this list of conditions and the following disclaimer. 94 * 2. Redistributions in binary form must reproduce the above copyright 95 * notice, this list of conditions and the following disclaimer in the 96 * documentation and/or other materials provided with the distribution. 97 * 3. All advertising materials mentioning features or use of this software 98 * must display the following acknowledgement: 99 * This product includes software developed by Eric S. Hvozda. 100 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 101 * derived from this software without specific prior written permission. 102 * 103 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 104 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 105 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 106 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 107 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 108 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 109 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 110 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 111 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 112 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 113 */ 114 115 #include <sys/cdefs.h> 116 __KERNEL_RCSID(0, "$NetBSD: esp_isa.c,v 1.24 2002/01/08 17:20:44 christos Exp $"); 117 118 #include <sys/param.h> 119 #include <sys/systm.h> 120 #include <sys/device.h> 121 #include <sys/buf.h> 122 123 #include <machine/bus.h> 124 #include <machine/intr.h> 125 126 #include <dev/scsipi/scsipi_all.h> 127 #include <dev/scsipi/scsi_all.h> 128 #include <dev/scsipi/scsiconf.h> 129 130 #include <dev/isa/isavar.h> 131 #include <dev/isa/isadmavar.h> 132 133 #include <dev/ic/ncr53c9xreg.h> 134 #include <dev/ic/ncr53c9xvar.h> 135 136 #include <dev/isa/esp_isavar.h> 137 138 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 139 void esp_isa_attach __P((struct device *, struct device *, void *)); 140 141 struct cfattach esp_isa_ca = { 142 sizeof(struct esp_isa_softc), esp_isa_match, esp_isa_attach 143 }; 144 145 int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 146 147 /* 148 * Functions and the switch for the MI code. 149 */ 150 u_char esp_isa_read_reg __P((struct ncr53c9x_softc *, int)); 151 void esp_isa_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 152 int esp_isa_dma_isintr __P((struct ncr53c9x_softc *)); 153 void esp_isa_dma_reset __P((struct ncr53c9x_softc *)); 154 int esp_isa_dma_intr __P((struct ncr53c9x_softc *)); 155 int esp_isa_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 156 size_t *, int, size_t *)); 157 void esp_isa_dma_go __P((struct ncr53c9x_softc *)); 158 void esp_isa_dma_stop __P((struct ncr53c9x_softc *)); 159 int esp_isa_dma_isactive __P((struct ncr53c9x_softc *)); 160 161 struct ncr53c9x_glue esp_isa_glue = { 162 esp_isa_read_reg, 163 esp_isa_write_reg, 164 esp_isa_dma_isintr, 165 esp_isa_dma_reset, 166 esp_isa_dma_intr, 167 esp_isa_dma_setup, 168 esp_isa_dma_go, 169 esp_isa_dma_stop, 170 esp_isa_dma_isactive, 171 NULL, /* gl_clear_latched_intr */ 172 }; 173 174 /* 175 * Look for the board 176 */ 177 int 178 esp_isa_find(iot, ioh, epd) 179 bus_space_tag_t iot; 180 bus_space_handle_t ioh; 181 struct esp_isa_probe_data *epd; 182 { 183 u_int vers; 184 u_int p1; 185 u_int p2; 186 u_int jmp; 187 188 ESP_TRACE(("[esp_isa_find] ")); 189 190 /* reset card before we probe? */ 191 192 epd->sc_cfg4 = NCRCFG4_ACTNEG; 193 epd->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC; 194 195 /* 196 * Switch to the PIO regs and look for the bit pattern 197 * we expect... 198 */ 199 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 200 201 #define SIG_MASK 0x87 202 #define REV_MASK 0x70 203 #define M1 0x02 204 #define M2 0x05 205 #define ISNCR 0x80 206 #define ISESP406 0x40 207 208 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 209 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 210 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 211 212 ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 213 214 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 215 return 0; 216 217 /* Ok, what is it? */ 218 epd->sc_isncr = (vers & ISNCR); 219 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 220 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 221 222 /* What do the jumpers tell us? */ 223 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 224 225 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 226 epd->sc_parity = jmp & NCRJMP_J2; 227 epd->sc_sync = jmp & NCRJMP_J4; 228 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 229 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 230 case NCRJMP_J0 | NCRJMP_J1: 231 epd->sc_irq = 11; 232 break; 233 case NCRJMP_J0: 234 epd->sc_irq = 10; 235 break; 236 case NCRJMP_J1: 237 epd->sc_irq = 15; 238 break; 239 default: 240 epd->sc_irq = 12; 241 break; 242 } 243 244 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 245 246 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 247 * NCRESPCFG3_FCLK even though it is documented. A bad 248 * batch of chips perhaps? 249 */ 250 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 251 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 252 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 253 & NCRESPCFG3_FCLK; 254 255 return 1; 256 } 257 258 void 259 esp_isa_init(esc, epd) 260 struct esp_isa_softc *esc; 261 struct esp_isa_probe_data *epd; 262 { 263 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 264 265 ESP_TRACE(("[esp_isa_init] ")); 266 267 /* 268 * Set up the glue for MI code early; we use some of it here. 269 */ 270 sc->sc_glue = &esp_isa_glue; 271 272 sc->sc_rev = epd->sc_rev; 273 sc->sc_id = epd->sc_id; 274 275 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 276 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 277 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 278 sc->sc_freq = 40; 279 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 280 } else 281 sc->sc_freq = 24; 282 283 /* Setup the register defaults */ 284 sc->sc_cfg1 = sc->sc_id; 285 if (epd->sc_parity) 286 sc->sc_cfg1 |= NCRCFG1_PARENB; 287 sc->sc_cfg2 = NCRCFG2_SCSI2; 288 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 289 sc->sc_cfg4 = epd->sc_cfg4; 290 sc->sc_cfg5 = epd->sc_cfg5; 291 292 /* 293 * This is the value used to start sync negotiations 294 * Note that the NCR register "SYNCTP" is programmed 295 * in "clocks per byte", and has a minimum value of 4. 296 * The SCSI period used in negotiation is one-fourth 297 * of the time (in nanoseconds) needed to transfer one byte. 298 * Since the chip's clock is given in MHz, we have the following 299 * formula: 4 * period = (1000 / freq) * 4 300 */ 301 if (epd->sc_sync) 302 { 303 #ifdef DIAGNOSTIC 304 printf("%s: sync requested, but not supported; will do async\n", 305 sc->sc_dev.dv_xname); 306 #endif 307 epd->sc_sync = 0; 308 } 309 310 sc->sc_minsync = 0; 311 312 /* Really no limit, but since we want to fit into the TCR... */ 313 sc->sc_maxxfer = 64 * 1024; 314 } 315 316 /* 317 * Check the slots looking for a board we recognise 318 * If we find one, note it's address (slot) and call 319 * the actual probe routine to check it out. 320 */ 321 int 322 esp_isa_match(parent, match, aux) 323 struct device *parent; 324 struct cfdata *match; 325 void *aux; 326 { 327 struct isa_attach_args *ia = aux; 328 bus_space_tag_t iot = ia->ia_iot; 329 bus_space_handle_t ioh; 330 struct esp_isa_probe_data epd; 331 int rv; 332 333 if (ia->ia_nio < 1) 334 return (0); 335 if (ia->ia_nirq < 1) 336 return (0); 337 if (ia->ia_ndrq < 1) 338 return (0); 339 340 if (ISA_DIRECT_CONFIG(ia)) 341 return (0); 342 343 ESP_TRACE(("[esp_isa_match] ")); 344 345 if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT) 346 return 0; 347 348 if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) 349 return 0; 350 351 rv = esp_isa_find(iot, ioh, &epd); 352 353 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 354 355 if (rv) { 356 if (ia->ia_irq[0].ir_irq != ISACF_IRQ_DEFAULT && 357 ia->ia_irq[0].ir_irq != epd.sc_irq) { 358 #ifdef DIAGNOSTIC 359 printf("esp_isa_match: configured IRQ (%0d) does not " 360 "match board IRQ (%0d), device not configured\n", 361 ia->ia_irq[0].ir_irq, epd.sc_irq); 362 #endif 363 return 0; 364 } 365 ia->ia_irq[0].ir_irq = epd.sc_irq; 366 ia->ia_iomem[0].ir_size = 0; 367 ia->ia_io[0].ir_size = ESP_ISA_IOSIZE; 368 } 369 return (rv); 370 } 371 372 /* 373 * Attach this instance, and then all the sub-devices 374 */ 375 void 376 esp_isa_attach(parent, self, aux) 377 struct device *parent, *self; 378 void *aux; 379 { 380 struct isa_attach_args *ia = aux; 381 struct esp_isa_softc *esc = (void *)self; 382 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 383 bus_space_tag_t iot = ia->ia_iot; 384 bus_space_handle_t ioh; 385 struct esp_isa_probe_data epd; 386 isa_chipset_tag_t ic = ia->ia_ic; 387 int error; 388 389 printf("\n"); 390 ESP_TRACE(("[esp_isa_attach] ")); 391 392 if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) { 393 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 394 return; 395 } 396 397 if (!esp_isa_find(iot, ioh, &epd)) { 398 printf("%s: esp_isa_find failed\n", sc->sc_dev.dv_xname); 399 return; 400 } 401 402 if (ia->ia_drq[0].ir_drq != ISACF_DRQ_DEFAULT) { 403 if ((error = isa_dmacascade(ic, ia->ia_drq[0].ir_drq)) != 0) { 404 printf("%s: unable to cascade DRQ, error = %d\n", 405 sc->sc_dev.dv_xname, error); 406 return; 407 } 408 } 409 410 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq[0].ir_irq, IST_EDGE, 411 IPL_BIO, ncr53c9x_intr, esc); 412 if (esc->sc_ih == NULL) { 413 printf("%s: couldn't establish interrupt\n", 414 sc->sc_dev.dv_xname); 415 return; 416 } 417 418 esc->sc_ioh = ioh; 419 esc->sc_iot = iot; 420 esp_isa_init(esc, &epd); 421 422 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 423 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 424 printf("%s", sc->sc_dev.dv_xname); 425 426 /* 427 * Now try to attach all the sub-devices 428 */ 429 sc->sc_adapter.adapt_minphys = minphys; 430 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 431 ncr53c9x_attach(sc); 432 } 433 434 /* 435 * Glue functions. 436 */ 437 u_char 438 esp_isa_read_reg(sc, reg) 439 struct ncr53c9x_softc *sc; 440 int reg; 441 { 442 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 443 u_char v; 444 445 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 446 447 ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ", 448 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 449 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 450 451 return v; 452 } 453 454 void 455 esp_isa_write_reg(sc, reg, val) 456 struct ncr53c9x_softc *sc; 457 int reg; 458 u_char val; 459 { 460 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 461 u_char v = val; 462 463 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 464 v = NCRCMD_TRANS; 465 } 466 467 ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ", 468 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 469 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 470 471 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 472 } 473 474 int 475 esp_isa_dma_isintr(sc) 476 struct ncr53c9x_softc *sc; 477 { 478 ESP_TRACE(("[esp_isa_dma_isintr] ")); 479 480 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 481 } 482 483 void 484 esp_isa_dma_reset(sc) 485 struct ncr53c9x_softc *sc; 486 { 487 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 488 489 ESP_TRACE(("[esp_isa_dma_reset] ")); 490 491 esc->sc_active = 0; 492 esc->sc_tc = 0; 493 } 494 495 int 496 esp_isa_dma_intr(sc) 497 struct ncr53c9x_softc *sc; 498 { 499 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 500 u_char *p; 501 u_int espphase, espstat, espintr; 502 int cnt; 503 504 ESP_TRACE(("[esp_isa_dma_intr] ")); 505 506 if (esc->sc_active == 0) { 507 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 508 return -1; 509 } 510 511 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 512 esc->sc_active = 0; 513 return 0; 514 } 515 516 cnt = *esc->sc_pdmalen; 517 if (*esc->sc_pdmalen == 0) { 518 printf("%s: data interrupt, but no count left\n", 519 sc->sc_dev.dv_xname); 520 } 521 522 p = *esc->sc_dmaaddr; 523 espphase = sc->sc_phase; 524 espstat = (u_int) sc->sc_espstat; 525 espintr = (u_int) sc->sc_espintr; 526 do { 527 if (esc->sc_datain) { 528 *p++ = NCR_READ_REG(sc, NCR_FIFO); 529 cnt--; 530 if (espphase == DATA_IN_PHASE) { 531 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 532 } else { 533 esc->sc_active = 0; 534 } 535 } else { 536 if ( (espphase == DATA_OUT_PHASE) 537 || (espphase == MESSAGE_OUT_PHASE)) { 538 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 539 cnt--; 540 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 541 } else { 542 esc->sc_active = 0; 543 } 544 } 545 546 if (esc->sc_active) { 547 while (!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT)); 548 espstat = NCR_READ_REG(sc, NCR_STAT); 549 espintr = NCR_READ_REG(sc, NCR_INTR); 550 espphase = (espintr & NCRINTR_DIS) 551 ? /* Disconnected */ BUSFREE_PHASE 552 : espstat & PHASE_MASK; 553 } 554 } while (esc->sc_active && espintr); 555 sc->sc_phase = espphase; 556 sc->sc_espstat = (u_char) espstat; 557 sc->sc_espintr = (u_char) espintr; 558 *esc->sc_dmaaddr = p; 559 *esc->sc_pdmalen = cnt; 560 561 if (*esc->sc_pdmalen == 0) { 562 esc->sc_tc = NCRSTAT_TC; 563 } 564 sc->sc_espstat |= esc->sc_tc; 565 return 0; 566 } 567 568 int 569 esp_isa_dma_setup(sc, addr, len, datain, dmasize) 570 struct ncr53c9x_softc *sc; 571 caddr_t *addr; 572 size_t *len; 573 int datain; 574 size_t *dmasize; 575 { 576 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 577 578 ESP_TRACE(("[esp_isa_dma_setup] ")); 579 580 esc->sc_dmaaddr = addr; 581 esc->sc_pdmalen = len; 582 esc->sc_datain = datain; 583 esc->sc_dmasize = *dmasize; 584 esc->sc_tc = 0; 585 586 return 0; 587 } 588 589 void 590 esp_isa_dma_go(sc) 591 struct ncr53c9x_softc *sc; 592 { 593 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 594 595 ESP_TRACE(("[esp_isa_dma_go] ")); 596 597 esc->sc_active = 1; 598 } 599 600 void 601 esp_isa_dma_stop(sc) 602 struct ncr53c9x_softc *sc; 603 { 604 ESP_TRACE(("[esp_isa_dma_stop] ")); 605 } 606 607 int 608 esp_isa_dma_isactive(sc) 609 struct ncr53c9x_softc *sc; 610 { 611 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 612 613 ESP_TRACE(("[esp_isa_dma_isactive] ")); 614 615 return esc->sc_active; 616 } 617
Indexes created Tue Sep 23 23:09:58 GMT 2025