esp_isa.c revision 1.35
1 /* $NetBSD: esp_isa.c,v 1.35 2008/04/13 04:55:53 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 81 * (basically consisting of the match, a bit of the attach, and the 82 * "DMA" glue functions). 83 */ 84 85 /* 86 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 87 * All rights reserved. 88 * 89 * Redistribution and use in source and binary forms, with or without 90 * modification, are permitted provided that the following conditions 91 * are met: 92 * 1. Redistributions of source code must retain the above copyright 93 * notice, this list of conditions and the following disclaimer. 94 * 2. Redistributions in binary form must reproduce the above copyright 95 * notice, this list of conditions and the following disclaimer in the 96 * documentation and/or other materials provided with the distribution. 97 * 3. All advertising materials mentioning features or use of this software 98 * must display the following acknowledgement: 99 * This product includes software developed by Eric S. Hvozda. 100 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 101 * derived from this software without specific prior written permission. 102 * 103 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 104 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 105 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 106 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 107 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 108 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 109 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 110 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 111 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 112 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 113 */ 114 115 #include <sys/cdefs.h> 116 __KERNEL_RCSID(0, "$NetBSD: esp_isa.c,v 1.35 2008/04/13 04:55:53 tsutsui Exp $"); 117 118 #include <sys/param.h> 119 #include <sys/systm.h> 120 #include <sys/device.h> 121 #include <sys/buf.h> 122 123 #include <sys/bus.h> 124 #include <sys/intr.h> 125 126 #include <dev/scsipi/scsipi_all.h> 127 #include <dev/scsipi/scsi_all.h> 128 #include <dev/scsipi/scsiconf.h> 129 130 #include <dev/isa/isavar.h> 131 #include <dev/isa/isadmavar.h> 132 133 #include <dev/ic/ncr53c9xreg.h> 134 #include <dev/ic/ncr53c9xvar.h> 135 136 #include <dev/isa/esp_isavar.h> 137 138 int esp_isa_match(device_t, cfdata_t, void *); 139 void esp_isa_attach(device_t, device_t, void *); 140 141 CFATTACH_DECL_NEW(esp_isa, sizeof(struct esp_isa_softc), 142 esp_isa_match, esp_isa_attach, NULL, NULL); 143 144 int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 145 146 /* 147 * Functions and the switch for the MI code. 148 */ 149 uint8_t esp_isa_read_reg(struct ncr53c9x_softc *, int); 150 void esp_isa_write_reg(struct ncr53c9x_softc *, int, uint8_t); 151 int esp_isa_dma_isintr(struct ncr53c9x_softc *); 152 void esp_isa_dma_reset(struct ncr53c9x_softc *); 153 int esp_isa_dma_intr(struct ncr53c9x_softc *); 154 int esp_isa_dma_setup(struct ncr53c9x_softc *, uint8_t **, 155 size_t *, int, size_t *); 156 void esp_isa_dma_go(struct ncr53c9x_softc *); 157 void esp_isa_dma_stop(struct ncr53c9x_softc *); 158 int esp_isa_dma_isactive(struct ncr53c9x_softc *); 159 160 struct ncr53c9x_glue esp_isa_glue = { 161 esp_isa_read_reg, 162 esp_isa_write_reg, 163 esp_isa_dma_isintr, 164 esp_isa_dma_reset, 165 esp_isa_dma_intr, 166 esp_isa_dma_setup, 167 esp_isa_dma_go, 168 esp_isa_dma_stop, 169 esp_isa_dma_isactive, 170 NULL, /* gl_clear_latched_intr */ 171 }; 172 173 /* 174 * Look for the board 175 */ 176 int 177 esp_isa_find(bus_space_tag_t iot, bus_space_handle_t ioh, 178 struct esp_isa_probe_data *epd) 179 { 180 u_int vers; 181 u_int p1; 182 u_int p2; 183 u_int jmp; 184 185 ESP_TRACE(("[esp_isa_find] ")); 186 187 /* reset card before we probe? */ 188 189 epd->sc_cfg4 = NCRCFG4_ACTNEG; 190 epd->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC; 191 192 /* 193 * Switch to the PIO regs and look for the bit pattern 194 * we expect... 195 */ 196 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 197 198 #define SIG_MASK 0x87 199 #define REV_MASK 0x70 200 #define M1 0x02 201 #define M2 0x05 202 #define ISNCR 0x80 203 #define ISESP406 0x40 204 205 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 206 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 207 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 208 209 ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 210 211 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 212 return 0; 213 214 /* Ok, what is it? */ 215 epd->sc_isncr = (vers & ISNCR); 216 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 217 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 218 219 /* What do the jumpers tell us? */ 220 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 221 222 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 223 epd->sc_parity = jmp & NCRJMP_J2; 224 epd->sc_sync = jmp & NCRJMP_J4; 225 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 226 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 227 case NCRJMP_J0 | NCRJMP_J1: 228 epd->sc_irq = 11; 229 break; 230 case NCRJMP_J0: 231 epd->sc_irq = 10; 232 break; 233 case NCRJMP_J1: 234 epd->sc_irq = 15; 235 break; 236 default: 237 epd->sc_irq = 12; 238 break; 239 } 240 241 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 242 243 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 244 * NCRESPCFG3_FCLK even though it is documented. A bad 245 * batch of chips perhaps? 246 */ 247 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 248 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 249 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 250 & NCRESPCFG3_FCLK; 251 252 return 1; 253 } 254 255 void 256 esp_isa_init(struct esp_isa_softc *esc, struct esp_isa_probe_data *epd) 257 { 258 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 259 260 ESP_TRACE(("[esp_isa_init] ")); 261 262 /* 263 * Set up the glue for MI code early; we use some of it here. 264 */ 265 sc->sc_glue = &esp_isa_glue; 266 267 sc->sc_rev = epd->sc_rev; 268 sc->sc_id = epd->sc_id; 269 270 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 271 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 272 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 273 sc->sc_freq = 40; 274 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 275 } else 276 sc->sc_freq = 24; 277 278 /* Setup the register defaults */ 279 sc->sc_cfg1 = sc->sc_id; 280 if (epd->sc_parity) 281 sc->sc_cfg1 |= NCRCFG1_PARENB; 282 sc->sc_cfg2 = NCRCFG2_SCSI2; 283 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 284 sc->sc_cfg4 = epd->sc_cfg4; 285 sc->sc_cfg5 = epd->sc_cfg5; 286 287 /* 288 * This is the value used to start sync negotiations 289 * Note that the NCR register "SYNCTP" is programmed 290 * in "clocks per byte", and has a minimum value of 4. 291 * The SCSI period used in negotiation is one-fourth 292 * of the time (in nanoseconds) needed to transfer one byte. 293 * Since the chip's clock is given in MHz, we have the following 294 * formula: 4 * period = (1000 / freq) * 4 295 */ 296 if (epd->sc_sync) { 297 #ifdef DIAGNOSTIC 298 aprint_normal_dev(sc->sc_dev, 299 "sync requested, but not supported; will do async\n"); 300 #endif 301 epd->sc_sync = 0; 302 } 303 304 sc->sc_minsync = 0; 305 306 /* Really no limit, but since we want to fit into the TCR... */ 307 sc->sc_maxxfer = 64 * 1024; 308 } 309 310 /* 311 * Check the slots looking for a board we recognise 312 * If we find one, note it's address (slot) and call 313 * the actual probe routine to check it out. 314 */ 315 int 316 esp_isa_match(device_t parent, cfdata_t cf, void *aux) 317 { 318 struct isa_attach_args *ia = aux; 319 bus_space_tag_t iot = ia->ia_iot; 320 bus_space_handle_t ioh; 321 struct esp_isa_probe_data epd; 322 int rv; 323 324 if (ia->ia_nio < 1) 325 return 0; 326 if (ia->ia_nirq < 1) 327 return 0; 328 if (ia->ia_ndrq < 1) 329 return 0; 330 331 if (ISA_DIRECT_CONFIG(ia)) 332 return 0; 333 334 ESP_TRACE(("[esp_isa_match] ")); 335 336 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 337 return 0; 338 339 if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) 340 return 0; 341 342 rv = esp_isa_find(iot, ioh, &epd); 343 344 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 345 346 if (rv) { 347 if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ && 348 ia->ia_irq[0].ir_irq != epd.sc_irq) { 349 #ifdef DIAGNOSTIC 350 printf("%s: configured IRQ (%0d) does not " 351 "match board IRQ (%0d), device not configured\n", 352 __func__, ia->ia_irq[0].ir_irq, epd.sc_irq); 353 #endif 354 return 0; 355 } 356 ia->ia_irq[0].ir_irq = epd.sc_irq; 357 ia->ia_iomem[0].ir_size = 0; 358 ia->ia_io[0].ir_size = ESP_ISA_IOSIZE; 359 } 360 return rv; 361 } 362 363 /* 364 * Attach this instance, and then all the sub-devices 365 */ 366 void 367 esp_isa_attach(device_t parent, device_t self, void *aux) 368 { 369 struct esp_isa_softc *esc = device_private(self); 370 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 371 struct isa_attach_args *ia = aux; 372 bus_space_tag_t iot = ia->ia_iot; 373 bus_space_handle_t ioh; 374 struct esp_isa_probe_data epd; 375 isa_chipset_tag_t ic = ia->ia_ic; 376 int error; 377 378 sc->sc_dev = self; 379 aprint_normal("\n"); 380 ESP_TRACE(("[esp_isa_attach] ")); 381 382 if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) { 383 aprint_error_dev(self, "can't map i/o space\n"); 384 return; 385 } 386 387 if (!esp_isa_find(iot, ioh, &epd)) { 388 aprint_error_dev(self, "esp_isa_find failed\n"); 389 return; 390 } 391 392 if (ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ) { 393 if ((error = isa_dmacascade(ic, ia->ia_drq[0].ir_drq)) != 0) { 394 aprint_error_dev(self, 395 "unable to cascade DRQ, error = %d\n", error); 396 return; 397 } 398 } 399 400 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq[0].ir_irq, IST_EDGE, 401 IPL_BIO, ncr53c9x_intr, esc); 402 if (esc->sc_ih == NULL) { 403 aprint_error_dev(self, "couldn't establish interrupt\n"); 404 return; 405 } 406 407 esc->sc_ioh = ioh; 408 esc->sc_iot = iot; 409 esp_isa_init(esc, &epd); 410 411 aprint_normal_dev(self, "%ssync,%sparity\n", 412 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 413 aprint_normal("%s", device_xname(self)); 414 415 /* 416 * Now try to attach all the sub-devices 417 */ 418 sc->sc_adapter.adapt_minphys = minphys; 419 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 420 ncr53c9x_attach(sc); 421 } 422 423 /* 424 * Glue functions. 425 */ 426 uint8_t 427 esp_isa_read_reg(struct ncr53c9x_softc *sc, int reg) 428 { 429 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 430 uint8_t v; 431 432 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 433 434 ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ", 435 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 436 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 437 438 return v; 439 } 440 441 void 442 esp_isa_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 443 { 444 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 445 uint8_t v = val; 446 447 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 448 v = NCRCMD_TRANS; 449 } 450 451 ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ", 452 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 453 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 454 455 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 456 } 457 458 int 459 esp_isa_dma_isintr(struct ncr53c9x_softc *sc) 460 { 461 462 ESP_TRACE(("[esp_isa_dma_isintr] ")); 463 464 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 465 } 466 467 void 468 esp_isa_dma_reset(struct ncr53c9x_softc *sc) 469 { 470 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 471 472 ESP_TRACE(("[esp_isa_dma_reset] ")); 473 474 esc->sc_active = 0; 475 esc->sc_tc = 0; 476 } 477 478 int 479 esp_isa_dma_intr(struct ncr53c9x_softc *sc) 480 { 481 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 482 uint8_t*p; 483 u_int espphase, espstat, espintr; 484 int cnt; 485 486 ESP_TRACE(("[esp_isa_dma_intr] ")); 487 488 if (esc->sc_active == 0) { 489 printf("%s: dma_intr--inactive DMA\n", 490 device_xname(sc->sc_dev)); 491 return -1; 492 } 493 494 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 495 esc->sc_active = 0; 496 return 0; 497 } 498 499 cnt = *esc->sc_pdmalen; 500 if (*esc->sc_pdmalen == 0) { 501 printf("%s: data interrupt, but no count left\n", 502 device_xname(sc->sc_dev)); 503 } 504 505 p = *esc->sc_dmaaddr; 506 espphase = sc->sc_phase; 507 espstat = (u_int)sc->sc_espstat; 508 espintr = (u_int)sc->sc_espintr; 509 do { 510 if (esc->sc_datain) { 511 *p++ = NCR_READ_REG(sc, NCR_FIFO); 512 cnt--; 513 if (espphase == DATA_IN_PHASE) { 514 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 515 } else { 516 esc->sc_active = 0; 517 } 518 } else { 519 if ((espphase == DATA_OUT_PHASE) || 520 (espphase == MESSAGE_OUT_PHASE)) { 521 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 522 cnt--; 523 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 524 } else { 525 esc->sc_active = 0; 526 } 527 } 528 529 if (esc->sc_active) { 530 while ((NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) == 0) 531 ; 532 espstat = NCR_READ_REG(sc, NCR_STAT); 533 espintr = NCR_READ_REG(sc, NCR_INTR); 534 espphase = (espintr & NCRINTR_DIS) ? 535 /* Disconnected */ BUSFREE_PHASE : 536 espstat & PHASE_MASK; 537 } 538 } while (esc->sc_active && espintr); 539 sc->sc_phase = espphase; 540 sc->sc_espstat = (uint8_t)espstat; 541 sc->sc_espintr = (uint8_t)espintr; 542 *esc->sc_dmaaddr = p; 543 *esc->sc_pdmalen = cnt; 544 545 if (*esc->sc_pdmalen == 0) { 546 esc->sc_tc = NCRSTAT_TC; 547 } 548 sc->sc_espstat |= esc->sc_tc; 549 return 0; 550 } 551 552 int 553 esp_isa_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 554 int datain, size_t *dmasize) 555 { 556 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 557 558 ESP_TRACE(("[esp_isa_dma_setup] ")); 559 560 esc->sc_dmaaddr = addr; 561 esc->sc_pdmalen = len; 562 esc->sc_datain = datain; 563 esc->sc_dmasize = *dmasize; 564 esc->sc_tc = 0; 565 566 return 0; 567 } 568 569 void 570 esp_isa_dma_go(struct ncr53c9x_softc *sc) 571 { 572 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 573 574 ESP_TRACE(("[esp_isa_dma_go] ")); 575 576 esc->sc_active = 1; 577 } 578 579 void 580 esp_isa_dma_stop(struct ncr53c9x_softc *sc) 581 { 582 ESP_TRACE(("[esp_isa_dma_stop] ")); 583 } 584 585 int 586 esp_isa_dma_isactive(struct ncr53c9x_softc *sc) 587 { 588 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 589 590 ESP_TRACE(("[esp_isa_dma_isactive] ")); 591 592 return esc->sc_active; 593 } 594
Indexes created Tue Sep 23 14:10:03 GMT 2025