esp_isa.c revision 1.4
1 /* $NetBSD: esp_isa.c,v 1.4 1997/08/27 11:25:08 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Jason R. Thorpe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project 18 * by Jason R. Thorpe. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1994 Peter Galbavy 36 * Copyright (c) 1995 Paul Kranenburg 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Peter Galbavy 50 * 4. The name of the author may not be used to endorse or promote products 51 * derived from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 55 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 56 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 61 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 62 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 63 * POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Based on aic6360 by Jarle Greipsland 68 * 69 * Acknowledgements: Many of the algorithms used in this driver are 70 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 71 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 72 */ 73 74 /* 75 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 76 * (basically consisting of the match, a bit of the attach, and the 77 * "DMA" glue functions). 78 */ 79 /* 80 * Copyright (c) 1994, 1996, 1997 Charles M. Hannum. All rights reserved. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by Charles M. Hannum. 93 * 4. The name of the author may not be used to endorse or promote products 94 * derived from this software without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 97 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 98 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 99 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 100 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 101 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 102 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 103 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 104 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 105 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 106 */ 107 108 /* 109 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 110 * All rights reserved. 111 * 112 * Redistribution and use in source and binary forms, with or without 113 * modification, are permitted provided that the following conditions 114 * are met: 115 * 1. Redistributions of source code must retain the above copyright 116 * notice, this list of conditions and the following disclaimer. 117 * 2. Redistributions in binary form must reproduce the above copyright 118 * notice, this list of conditions and the following disclaimer in the 119 * documentation and/or other materials provided with the distribution. 120 * 3. All advertising materials mentioning features or use of this software 121 * must display the following acknowledgement: 122 * This product includes software developed by Eric S. Hvozda. 123 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 124 * derived from this software without specific prior written permission. 125 * 126 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 127 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 128 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 129 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 130 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 131 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 132 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 133 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 134 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 135 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 136 */ 137 138 #include <sys/param.h> 139 #include <sys/systm.h> 140 #include <sys/device.h> 141 #include <sys/buf.h> 142 143 #include <machine/bus.h> 144 #include <machine/intr.h> 145 146 #include <dev/scsipi/scsi_all.h> 147 #include <dev/scsipi/scsipi_all.h> 148 #include <dev/scsipi/scsiconf.h> 149 150 #include <dev/isa/isavar.h> 151 #include <dev/isa/isadmavar.h> 152 153 #include <dev/ic/ncr53c9xreg.h> 154 #include <dev/ic/ncr53c9xvar.h> 155 156 #include <dev/isa/espvar.h> 157 158 int esp_isa_match __P((struct device *, void *, void *)); 159 void esp_isa_attach __P((struct device *, struct device *, void *)); 160 161 struct cfattach esp_isa_ca = { 162 sizeof(struct esp_softc), esp_isa_match, esp_isa_attach 163 }; 164 165 struct cfdriver esp_cd = { 166 NULL, "esp", DV_DULL 167 }; 168 169 struct scsipi_adapter esp_switch = { 170 ncr53c9x_scsi_cmd, 171 minphys, /* no max at this level; handled by DMA code */ 172 NULL, 173 NULL, 174 }; 175 176 struct scsipi_device esp_dev = { 177 NULL, /* Use default error handler */ 178 NULL, /* have a queue, served by this */ 179 NULL, /* have no async handler */ 180 NULL, /* Use default 'done' routine */ 181 }; 182 183 int esp_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 184 185 /* 186 * Functions and the switch for the MI code. 187 */ 188 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 189 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 190 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 191 void esp_dma_reset __P((struct ncr53c9x_softc *)); 192 int esp_dma_intr __P((struct ncr53c9x_softc *)); 193 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 194 size_t *, int, size_t *)); 195 void esp_dma_go __P((struct ncr53c9x_softc *)); 196 void esp_dma_stop __P((struct ncr53c9x_softc *)); 197 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 198 199 struct ncr53c9x_glue esp_glue = { 200 esp_read_reg, 201 esp_write_reg, 202 esp_dma_isintr, 203 esp_dma_reset, 204 esp_dma_intr, 205 esp_dma_setup, 206 esp_dma_go, 207 esp_dma_stop, 208 esp_dma_isactive, 209 NULL, /* gl_clear_latched_intr */ 210 }; 211 212 /* 213 * Look for the board 214 */ 215 int 216 esp_find(iot, ioh, epd) 217 bus_space_tag_t iot; 218 bus_space_handle_t ioh; 219 struct esp_probe_data *epd; 220 { 221 u_int vers; 222 u_int p1; 223 u_int p2; 224 u_int jmp; 225 226 ESP_TRACE(("[esp_find] ")); 227 228 /* reset card before we probe? */ 229 230 /* 231 * Switch to the PIO regs and look for the bit pattern 232 * we expect... 233 */ 234 bus_space_write_1(iot, ioh, NCR_CFG4, 235 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 236 237 #define SIG_MASK 0x87 238 #define REV_MASK 0x70 239 #define M1 0x02 240 #define M2 0x05 241 #define ISNCR 0x80 242 #define ISESP406 0x40 243 244 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 245 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 246 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 247 248 ESP_MISC(("%s: 0x%0x 0x%0x 0x%0x\n", epd->sc_dev.dv_xname, 249 vers, p1, p2)); 250 251 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 252 return 0; 253 254 /* Ok, what is it? */ 255 epd->sc_isncr = (vers & ISNCR); 256 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 257 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 258 259 /* What do the jumpers tell us? */ 260 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 261 262 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 263 epd->sc_parity = jmp & NCRJMP_J2; 264 epd->sc_sync = jmp & NCRJMP_J4; 265 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 266 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 267 case NCRJMP_J0 | NCRJMP_J1: 268 epd->sc_irq = 11; 269 break; 270 case NCRJMP_J0: 271 epd->sc_irq = 10; 272 break; 273 case NCRJMP_J1: 274 epd->sc_irq = 15; 275 break; 276 default: 277 epd->sc_irq = 12; 278 break; 279 } 280 281 bus_space_write_1(iot, ioh, NCR_CFG4, 282 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 283 284 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 285 * NCRESPCFG3_FCLK even though it is documented. A bad 286 * batch of chips perhaps? 287 */ 288 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 289 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 290 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 291 & NCRESPCFG3_FCLK; 292 293 return 1; 294 } 295 296 void 297 esp_init(esc, epd) 298 struct esp_softc *esc; 299 struct esp_probe_data *epd; 300 { 301 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 302 303 ESP_TRACE(("[esp_init] ")); 304 305 /* 306 * Set up the glue for MI code early; we use some of it here. 307 */ 308 sc->sc_glue = &esp_glue; 309 310 sc->sc_rev = epd->sc_rev; 311 sc->sc_id = epd->sc_id; 312 313 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 314 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 315 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 316 sc->sc_freq = 40; 317 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 318 } 319 else 320 sc->sc_freq = 24; 321 322 /* Setup the register defaults */ 323 sc->sc_cfg1 = sc->sc_id; 324 if (epd->sc_parity) 325 sc->sc_cfg1 |= NCRCFG1_PARENB; 326 sc->sc_cfg2 = NCRCFG2_SCSI2; 327 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 328 329 /* 330 * This is the value used to start sync negotiations 331 * Note that the NCR register "SYNCTP" is programmed 332 * in "clocks per byte", and has a minimum value of 4. 333 * The SCSI period used in negotiation is one-fourth 334 * of the time (in nanoseconds) needed to transfer one byte. 335 * Since the chip's clock is given in MHz, we have the following 336 * formula: 4 * period = (1000 / freq) * 4 337 */ 338 if (epd->sc_sync) 339 { 340 #ifdef DIAGNOSTIC 341 printf("%s: sync requested, but not supported; will do async\n", 342 sc->sc_dev.dv_xname); 343 #endif 344 epd->sc_sync = 0; 345 } 346 347 sc->sc_minsync = 0; 348 349 /* Really no limit, but since we want to fit into the TCR... */ 350 sc->sc_maxxfer = 64 * 1024; 351 } 352 353 /* 354 * Check the slots looking for a board we recognise 355 * If we find one, note it's address (slot) and call 356 * the actual probe routine to check it out. 357 */ 358 int 359 esp_isa_match(parent, match, aux) 360 struct device *parent; 361 void *match, *aux; 362 { 363 struct ncr53c9x_softc *sc = match; 364 struct isa_attach_args *ia = aux; 365 bus_space_tag_t iot = ia->ia_iot; 366 bus_space_handle_t ioh; 367 struct esp_probe_data epd; 368 int rv; 369 370 ESP_TRACE(("[esp_isa_match] ")); 371 372 if (ia->ia_iobase != 0x230 && ia->ia_iobase != 0x330) { 373 #ifdef DIAGNOSTIC 374 printf("%s: invalid iobase 0x%0x, device not configured\n", 375 sc->sc_dev.dv_xname, ia->ia_iobase); 376 #endif 377 return 0; 378 } 379 380 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 381 #ifdef DIAGNOSTIC 382 printf("%s: bus_space_map() failed!\n", sc->sc_dev.dv_xname); 383 #endif 384 return 0; 385 } 386 387 epd.sc_dev = sc->sc_dev; 388 rv = esp_find(iot, ioh, &epd); 389 390 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 391 392 if (rv) { 393 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 394 #ifdef DIAGNOSTIC 395 printf("%s: configured IRQ (%0d) does not match board IRQ (%0d), device not configured\n", 396 sc->sc_dev.dv_xname, ia->ia_irq, epd.sc_irq); 397 #endif 398 return 0; 399 } 400 ia->ia_irq = epd.sc_irq; 401 ia->ia_msize = 0; 402 ia->ia_iosize = ESP_ISA_IOSIZE; 403 } 404 return (rv); 405 } 406 407 /* 408 * Attach this instance, and then all the sub-devices 409 */ 410 void 411 esp_isa_attach(parent, self, aux) 412 struct device *parent, *self; 413 void *aux; 414 { 415 struct isa_attach_args *ia = aux; 416 struct esp_softc *esc = (void *)self; 417 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 418 bus_space_tag_t iot = ia->ia_iot; 419 bus_space_handle_t ioh; 420 struct esp_probe_data epd; 421 isa_chipset_tag_t ic = ia->ia_ic; 422 423 printf("\n"); 424 ESP_TRACE(("[esp_isa_attach] ")); 425 426 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 427 panic("espattach: bus_space_map failed"); 428 429 epd.sc_dev = sc->sc_dev; 430 if (!esp_find(iot, ioh, &epd)) 431 panic("espattach: esp_find failed"); 432 433 if (ia->ia_drq != DRQUNK) 434 isa_dmacascade(parent, ia->ia_drq); 435 436 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 437 (int (*)(void *))ncr53c9x_intr, esc); 438 if (esc->sc_ih == NULL) { 439 printf("%s: couldn't establish interrupt\n", 440 sc->sc_dev.dv_xname); 441 return; 442 } 443 444 esp_init(esc, &epd); 445 446 esc->sc_ioh = ioh; 447 esc->sc_iot = iot; 448 449 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 450 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 451 printf("%s", sc->sc_dev.dv_xname); 452 453 /* 454 * Now try to attach all the sub-devices 455 */ 456 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 457 } 458 459 /* 460 * Glue functions. 461 */ 462 u_char 463 esp_read_reg(sc, reg) 464 struct ncr53c9x_softc *sc; 465 int reg; 466 { 467 struct esp_softc *esc = (struct esp_softc *)sc; 468 u_char v; 469 470 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 471 472 ESP_REGS(("[esp_read_reg CRS%c 0x%02x=0x%02x] ", 473 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 474 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 475 476 return v; 477 } 478 479 void 480 esp_write_reg(sc, reg, val) 481 struct ncr53c9x_softc *sc; 482 int reg; 483 u_char val; 484 { 485 struct esp_softc *esc = (struct esp_softc *)sc; 486 u_char v = val; 487 488 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 489 v = NCRCMD_TRANS; 490 } 491 492 ESP_REGS(("[esp_write_reg CRS%c 0x%02x=0x%02x] ", 493 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 494 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 495 496 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 497 } 498 499 int 500 esp_dma_isintr(sc) 501 struct ncr53c9x_softc *sc; 502 { 503 ESP_TRACE(("[esp_dma_isintr] ")); 504 505 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 506 } 507 508 void 509 esp_dma_reset(sc) 510 struct ncr53c9x_softc *sc; 511 { 512 struct esp_softc *esc = (struct esp_softc *)sc; 513 514 ESP_TRACE(("[esp_dma_reset] ")); 515 516 esc->sc_active = 0; 517 esc->sc_tc = 0; 518 } 519 520 int 521 esp_dma_intr(sc) 522 struct ncr53c9x_softc *sc; 523 { 524 struct esp_softc *esc = (struct esp_softc *)sc; 525 u_char *p; 526 u_int espphase, espstat, espintr; 527 int cnt; 528 529 ESP_TRACE(("[esp_dma_intr] ")); 530 531 if (esc->sc_active == 0) { 532 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 533 return -1; 534 } 535 536 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 537 esc->sc_active = 0; 538 return 0; 539 } 540 541 cnt = *esc->sc_pdmalen; 542 if (*esc->sc_pdmalen == 0) { 543 printf("%s: data interrupt, but no count left\n", 544 sc->sc_dev.dv_xname); 545 } 546 547 p = *esc->sc_dmaaddr; 548 espphase = sc->sc_phase; 549 espstat = (u_int) sc->sc_espstat; 550 espintr = (u_int) sc->sc_espintr; 551 do { 552 if (esc->sc_datain) { 553 *p++ = NCR_READ_REG(sc, NCR_FIFO); 554 cnt--; 555 if (espphase == DATA_IN_PHASE) { 556 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 557 } else { 558 esc->sc_active = 0; 559 } 560 } else { 561 if ( (espphase == DATA_OUT_PHASE) 562 || (espphase == MESSAGE_OUT_PHASE)) { 563 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 564 cnt--; 565 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 566 } else { 567 esc->sc_active = 0; 568 } 569 } 570 571 if (esc->sc_active) { 572 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 573 espstat = NCR_READ_REG(sc, NCR_STAT); 574 espintr = NCR_READ_REG(sc, NCR_INTR); 575 espphase = (espintr & NCRINTR_DIS) 576 ? /* Disconnected */ BUSFREE_PHASE 577 : espstat & PHASE_MASK; 578 } 579 } while (esc->sc_active && espintr); 580 sc->sc_phase = espphase; 581 sc->sc_espstat = (u_char) espstat; 582 sc->sc_espintr = (u_char) espintr; 583 *esc->sc_dmaaddr = p; 584 *esc->sc_pdmalen = cnt; 585 586 if (*esc->sc_pdmalen == 0) { 587 esc->sc_tc = NCRSTAT_TC; 588 } 589 sc->sc_espstat |= esc->sc_tc; 590 return 0; 591 } 592 593 int 594 esp_dma_setup(sc, addr, len, datain, dmasize) 595 struct ncr53c9x_softc *sc; 596 caddr_t *addr; 597 size_t *len; 598 int datain; 599 size_t *dmasize; 600 { 601 struct esp_softc *esc = (struct esp_softc *)sc; 602 603 ESP_TRACE(("[esp_dma_setup] ")); 604 605 esc->sc_dmaaddr = addr; 606 esc->sc_pdmalen = len; 607 esc->sc_datain = datain; 608 esc->sc_dmasize = *dmasize; 609 esc->sc_tc = 0; 610 611 return 0; 612 } 613 614 void 615 esp_dma_go(sc) 616 struct ncr53c9x_softc *sc; 617 { 618 struct esp_softc *esc = (struct esp_softc *)sc; 619 620 ESP_TRACE(("[esp_dma_go] ")); 621 622 esc->sc_active = 1; 623 } 624 625 void 626 esp_dma_stop(sc) 627 struct ncr53c9x_softc *sc; 628 { 629 ESP_TRACE(("[esp_dma_stop] ")); 630 } 631 632 int 633 esp_dma_isactive(sc) 634 struct ncr53c9x_softc *sc; 635 { 636 struct esp_softc *esc = (struct esp_softc *)sc; 637 638 ESP_TRACE(("[esp_dma_isactive] ")); 639 640 return esc->sc_active; 641 } 642
Indexes created Mon Sep 22 13:09:51 GMT 2025