esp_isa.c revision 1.6
1 /* $NetBSD: esp_isa.c,v 1.6 1997/10/20 18:43:09 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * Copyright (c) 1995 Paul Kranenburg 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Peter Galbavy 56 * 4. The name of the author may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 61 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 62 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 67 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 68 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Based on aic6360 by Jarle Greipsland 74 * 75 * Acknowledgements: Many of the algorithms used in this driver are 76 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 77 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 78 */ 79 80 /* 81 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 82 * (basically consisting of the match, a bit of the attach, and the 83 * "DMA" glue functions). 84 */ 85 /* 86 * Copyright (c) 1994, 1996, 1997 Charles M. Hannum. All rights reserved. 87 * 88 * Redistribution and use in source and binary forms, with or without 89 * modification, are permitted provided that the following conditions 90 * are met: 91 * 1. Redistributions of source code must retain the above copyright 92 * notice, this list of conditions and the following disclaimer. 93 * 2. Redistributions in binary form must reproduce the above copyright 94 * notice, this list of conditions and the following disclaimer in the 95 * documentation and/or other materials provided with the distribution. 96 * 3. All advertising materials mentioning features or use of this software 97 * must display the following acknowledgement: 98 * This product includes software developed by Charles M. Hannum. 99 * 4. The name of the author may not be used to endorse or promote products 100 * derived from this software without specific prior written permission. 101 * 102 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 103 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 104 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 105 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 106 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 107 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 108 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 109 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 110 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 111 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 /* 115 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 116 * All rights reserved. 117 * 118 * Redistribution and use in source and binary forms, with or without 119 * modification, are permitted provided that the following conditions 120 * are met: 121 * 1. Redistributions of source code must retain the above copyright 122 * notice, this list of conditions and the following disclaimer. 123 * 2. Redistributions in binary form must reproduce the above copyright 124 * notice, this list of conditions and the following disclaimer in the 125 * documentation and/or other materials provided with the distribution. 126 * 3. All advertising materials mentioning features or use of this software 127 * must display the following acknowledgement: 128 * This product includes software developed by Eric S. Hvozda. 129 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 130 * derived from this software without specific prior written permission. 131 * 132 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 133 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 134 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 135 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 136 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 137 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 138 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 139 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 140 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 141 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 142 */ 143 144 #include <sys/param.h> 145 #include <sys/systm.h> 146 #include <sys/device.h> 147 #include <sys/buf.h> 148 149 #include <machine/bus.h> 150 #include <machine/intr.h> 151 152 #include <dev/scsipi/scsi_all.h> 153 #include <dev/scsipi/scsipi_all.h> 154 #include <dev/scsipi/scsiconf.h> 155 156 #include <dev/isa/isavar.h> 157 #include <dev/isa/isadmavar.h> 158 159 #include <dev/ic/ncr53c9xreg.h> 160 #include <dev/ic/ncr53c9xvar.h> 161 162 #include <dev/isa/espvar.h> 163 164 int esp_isa_match __P((struct device *, void *, void *)); 165 void esp_isa_attach __P((struct device *, struct device *, void *)); 166 167 struct cfattach esp_isa_ca = { 168 sizeof(struct esp_softc), esp_isa_match, esp_isa_attach 169 }; 170 171 struct cfdriver esp_cd = { 172 NULL, "esp", DV_DULL 173 }; 174 175 struct scsipi_adapter esp_switch = { 176 ncr53c9x_scsi_cmd, 177 minphys, /* no max at this level; handled by DMA code */ 178 NULL, 179 NULL, 180 }; 181 182 struct scsipi_device esp_dev = { 183 NULL, /* Use default error handler */ 184 NULL, /* have a queue, served by this */ 185 NULL, /* have no async handler */ 186 NULL, /* Use default 'done' routine */ 187 }; 188 189 int esp_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 190 191 /* 192 * Functions and the switch for the MI code. 193 */ 194 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 195 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 196 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 197 void esp_dma_reset __P((struct ncr53c9x_softc *)); 198 int esp_dma_intr __P((struct ncr53c9x_softc *)); 199 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 200 size_t *, int, size_t *)); 201 void esp_dma_go __P((struct ncr53c9x_softc *)); 202 void esp_dma_stop __P((struct ncr53c9x_softc *)); 203 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 204 205 struct ncr53c9x_glue esp_glue = { 206 esp_read_reg, 207 esp_write_reg, 208 esp_dma_isintr, 209 esp_dma_reset, 210 esp_dma_intr, 211 esp_dma_setup, 212 esp_dma_go, 213 esp_dma_stop, 214 esp_dma_isactive, 215 NULL, /* gl_clear_latched_intr */ 216 }; 217 218 /* 219 * Look for the board 220 */ 221 int 222 esp_find(iot, ioh, epd) 223 bus_space_tag_t iot; 224 bus_space_handle_t ioh; 225 struct esp_probe_data *epd; 226 { 227 u_int vers; 228 u_int p1; 229 u_int p2; 230 u_int jmp; 231 232 ESP_TRACE(("[esp_find] ")); 233 234 /* reset card before we probe? */ 235 236 /* 237 * Switch to the PIO regs and look for the bit pattern 238 * we expect... 239 */ 240 bus_space_write_1(iot, ioh, NCR_CFG4, 241 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 242 243 #define SIG_MASK 0x87 244 #define REV_MASK 0x70 245 #define M1 0x02 246 #define M2 0x05 247 #define ISNCR 0x80 248 #define ISESP406 0x40 249 250 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 251 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 252 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 253 254 ESP_MISC(("%s: 0x%0x 0x%0x 0x%0x\n", epd->sc_dev.dv_xname, 255 vers, p1, p2)); 256 257 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 258 return 0; 259 260 /* Ok, what is it? */ 261 epd->sc_isncr = (vers & ISNCR); 262 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 263 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 264 265 /* What do the jumpers tell us? */ 266 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 267 268 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 269 epd->sc_parity = jmp & NCRJMP_J2; 270 epd->sc_sync = jmp & NCRJMP_J4; 271 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 272 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 273 case NCRJMP_J0 | NCRJMP_J1: 274 epd->sc_irq = 11; 275 break; 276 case NCRJMP_J0: 277 epd->sc_irq = 10; 278 break; 279 case NCRJMP_J1: 280 epd->sc_irq = 15; 281 break; 282 default: 283 epd->sc_irq = 12; 284 break; 285 } 286 287 bus_space_write_1(iot, ioh, NCR_CFG4, 288 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 289 290 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 291 * NCRESPCFG3_FCLK even though it is documented. A bad 292 * batch of chips perhaps? 293 */ 294 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 295 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 296 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 297 & NCRESPCFG3_FCLK; 298 299 return 1; 300 } 301 302 void 303 esp_init(esc, epd) 304 struct esp_softc *esc; 305 struct esp_probe_data *epd; 306 { 307 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 308 309 ESP_TRACE(("[esp_init] ")); 310 311 /* 312 * Set up the glue for MI code early; we use some of it here. 313 */ 314 sc->sc_glue = &esp_glue; 315 316 sc->sc_rev = epd->sc_rev; 317 sc->sc_id = epd->sc_id; 318 319 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 320 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 321 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 322 sc->sc_freq = 40; 323 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 324 } 325 else 326 sc->sc_freq = 24; 327 328 /* Setup the register defaults */ 329 sc->sc_cfg1 = sc->sc_id; 330 if (epd->sc_parity) 331 sc->sc_cfg1 |= NCRCFG1_PARENB; 332 sc->sc_cfg2 = NCRCFG2_SCSI2; 333 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 334 335 /* 336 * This is the value used to start sync negotiations 337 * Note that the NCR register "SYNCTP" is programmed 338 * in "clocks per byte", and has a minimum value of 4. 339 * The SCSI period used in negotiation is one-fourth 340 * of the time (in nanoseconds) needed to transfer one byte. 341 * Since the chip's clock is given in MHz, we have the following 342 * formula: 4 * period = (1000 / freq) * 4 343 */ 344 if (epd->sc_sync) 345 { 346 #ifdef DIAGNOSTIC 347 printf("%s: sync requested, but not supported; will do async\n", 348 sc->sc_dev.dv_xname); 349 #endif 350 epd->sc_sync = 0; 351 } 352 353 sc->sc_minsync = 0; 354 355 /* Really no limit, but since we want to fit into the TCR... */ 356 sc->sc_maxxfer = 64 * 1024; 357 } 358 359 /* 360 * Check the slots looking for a board we recognise 361 * If we find one, note it's address (slot) and call 362 * the actual probe routine to check it out. 363 */ 364 int 365 esp_isa_match(parent, match, aux) 366 struct device *parent; 367 void *match, *aux; 368 { 369 struct ncr53c9x_softc *sc = match; 370 struct isa_attach_args *ia = aux; 371 bus_space_tag_t iot = ia->ia_iot; 372 bus_space_handle_t ioh; 373 struct esp_probe_data epd; 374 int rv; 375 376 ESP_TRACE(("[esp_isa_match] ")); 377 378 if (ia->ia_iobase != 0x230 && ia->ia_iobase != 0x330) 379 return 0; 380 381 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 382 return 0; 383 384 epd.sc_dev = sc->sc_dev; 385 rv = esp_find(iot, ioh, &epd); 386 387 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 388 389 if (rv) { 390 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 391 #ifdef DIAGNOSTIC 392 printf("%s: configured IRQ (%0d) does not match board IRQ (%0d), device not configured\n", 393 sc->sc_dev.dv_xname, ia->ia_irq, epd.sc_irq); 394 #endif 395 return 0; 396 } 397 ia->ia_irq = epd.sc_irq; 398 ia->ia_msize = 0; 399 ia->ia_iosize = ESP_ISA_IOSIZE; 400 } 401 return (rv); 402 } 403 404 /* 405 * Attach this instance, and then all the sub-devices 406 */ 407 void 408 esp_isa_attach(parent, self, aux) 409 struct device *parent, *self; 410 void *aux; 411 { 412 struct isa_attach_args *ia = aux; 413 struct esp_softc *esc = (void *)self; 414 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 415 bus_space_tag_t iot = ia->ia_iot; 416 bus_space_handle_t ioh; 417 struct esp_probe_data epd; 418 isa_chipset_tag_t ic = ia->ia_ic; 419 420 printf("\n"); 421 ESP_TRACE(("[esp_isa_attach] ")); 422 423 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 424 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 425 return; 426 } 427 428 epd.sc_dev = sc->sc_dev; 429 if (!esp_find(iot, ioh, &epd)) { 430 printf("%s: esp_find failed\n", sc->sc_dev.dv_xname); 431 return; 432 } 433 434 if (ia->ia_drq != DRQUNK) 435 isa_dmacascade(parent, ia->ia_drq); 436 437 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 438 (int (*)(void *))ncr53c9x_intr, esc); 439 if (esc->sc_ih == NULL) { 440 printf("%s: couldn't establish interrupt\n", 441 sc->sc_dev.dv_xname); 442 return; 443 } 444 445 esp_init(esc, &epd); 446 447 esc->sc_ioh = ioh; 448 esc->sc_iot = iot; 449 450 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 451 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 452 printf("%s", sc->sc_dev.dv_xname); 453 454 /* 455 * Now try to attach all the sub-devices 456 */ 457 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 458 } 459 460 /* 461 * Glue functions. 462 */ 463 u_char 464 esp_read_reg(sc, reg) 465 struct ncr53c9x_softc *sc; 466 int reg; 467 { 468 struct esp_softc *esc = (struct esp_softc *)sc; 469 u_char v; 470 471 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 472 473 ESP_REGS(("[esp_read_reg CRS%c 0x%02x=0x%02x] ", 474 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 475 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 476 477 return v; 478 } 479 480 void 481 esp_write_reg(sc, reg, val) 482 struct ncr53c9x_softc *sc; 483 int reg; 484 u_char val; 485 { 486 struct esp_softc *esc = (struct esp_softc *)sc; 487 u_char v = val; 488 489 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 490 v = NCRCMD_TRANS; 491 } 492 493 ESP_REGS(("[esp_write_reg CRS%c 0x%02x=0x%02x] ", 494 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 495 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 496 497 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 498 } 499 500 int 501 esp_dma_isintr(sc) 502 struct ncr53c9x_softc *sc; 503 { 504 ESP_TRACE(("[esp_dma_isintr] ")); 505 506 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 507 } 508 509 void 510 esp_dma_reset(sc) 511 struct ncr53c9x_softc *sc; 512 { 513 struct esp_softc *esc = (struct esp_softc *)sc; 514 515 ESP_TRACE(("[esp_dma_reset] ")); 516 517 esc->sc_active = 0; 518 esc->sc_tc = 0; 519 } 520 521 int 522 esp_dma_intr(sc) 523 struct ncr53c9x_softc *sc; 524 { 525 struct esp_softc *esc = (struct esp_softc *)sc; 526 u_char *p; 527 u_int espphase, espstat, espintr; 528 int cnt; 529 530 ESP_TRACE(("[esp_dma_intr] ")); 531 532 if (esc->sc_active == 0) { 533 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 534 return -1; 535 } 536 537 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 538 esc->sc_active = 0; 539 return 0; 540 } 541 542 cnt = *esc->sc_pdmalen; 543 if (*esc->sc_pdmalen == 0) { 544 printf("%s: data interrupt, but no count left\n", 545 sc->sc_dev.dv_xname); 546 } 547 548 p = *esc->sc_dmaaddr; 549 espphase = sc->sc_phase; 550 espstat = (u_int) sc->sc_espstat; 551 espintr = (u_int) sc->sc_espintr; 552 do { 553 if (esc->sc_datain) { 554 *p++ = NCR_READ_REG(sc, NCR_FIFO); 555 cnt--; 556 if (espphase == DATA_IN_PHASE) { 557 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 558 } else { 559 esc->sc_active = 0; 560 } 561 } else { 562 if ( (espphase == DATA_OUT_PHASE) 563 || (espphase == MESSAGE_OUT_PHASE)) { 564 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 565 cnt--; 566 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 567 } else { 568 esc->sc_active = 0; 569 } 570 } 571 572 if (esc->sc_active) { 573 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 574 espstat = NCR_READ_REG(sc, NCR_STAT); 575 espintr = NCR_READ_REG(sc, NCR_INTR); 576 espphase = (espintr & NCRINTR_DIS) 577 ? /* Disconnected */ BUSFREE_PHASE 578 : espstat & PHASE_MASK; 579 } 580 } while (esc->sc_active && espintr); 581 sc->sc_phase = espphase; 582 sc->sc_espstat = (u_char) espstat; 583 sc->sc_espintr = (u_char) espintr; 584 *esc->sc_dmaaddr = p; 585 *esc->sc_pdmalen = cnt; 586 587 if (*esc->sc_pdmalen == 0) { 588 esc->sc_tc = NCRSTAT_TC; 589 } 590 sc->sc_espstat |= esc->sc_tc; 591 return 0; 592 } 593 594 int 595 esp_dma_setup(sc, addr, len, datain, dmasize) 596 struct ncr53c9x_softc *sc; 597 caddr_t *addr; 598 size_t *len; 599 int datain; 600 size_t *dmasize; 601 { 602 struct esp_softc *esc = (struct esp_softc *)sc; 603 604 ESP_TRACE(("[esp_dma_setup] ")); 605 606 esc->sc_dmaaddr = addr; 607 esc->sc_pdmalen = len; 608 esc->sc_datain = datain; 609 esc->sc_dmasize = *dmasize; 610 esc->sc_tc = 0; 611 612 return 0; 613 } 614 615 void 616 esp_dma_go(sc) 617 struct ncr53c9x_softc *sc; 618 { 619 struct esp_softc *esc = (struct esp_softc *)sc; 620 621 ESP_TRACE(("[esp_dma_go] ")); 622 623 esc->sc_active = 1; 624 } 625 626 void 627 esp_dma_stop(sc) 628 struct ncr53c9x_softc *sc; 629 { 630 ESP_TRACE(("[esp_dma_stop] ")); 631 } 632 633 int 634 esp_dma_isactive(sc) 635 struct ncr53c9x_softc *sc; 636 { 637 struct esp_softc *esc = (struct esp_softc *)sc; 638 639 ESP_TRACE(("[esp_dma_isactive] ")); 640 641 return esc->sc_active; 642 } 643
Indexes created Tue Sep 23 23:09:58 GMT 2025