esp_isa.c revision 1.8
1 /* $NetBSD: esp_isa.c,v 1.8 1998/01/14 12:14:43 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * Copyright (c) 1995 Paul Kranenburg 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Peter Galbavy 56 * 4. The name of the author may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 61 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 62 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 67 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 68 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Based on aic6360 by Jarle Greipsland 74 * 75 * Acknowledgements: Many of the algorithms used in this driver are 76 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 77 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 78 */ 79 80 /* 81 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 82 * (basically consisting of the match, a bit of the attach, and the 83 * "DMA" glue functions). 84 */ 85 /* 86 * Copyright (c) 1994, 1996, 1997 Charles M. Hannum. All rights reserved. 87 * 88 * Redistribution and use in source and binary forms, with or without 89 * modification, are permitted provided that the following conditions 90 * are met: 91 * 1. Redistributions of source code must retain the above copyright 92 * notice, this list of conditions and the following disclaimer. 93 * 2. Redistributions in binary form must reproduce the above copyright 94 * notice, this list of conditions and the following disclaimer in the 95 * documentation and/or other materials provided with the distribution. 96 * 3. All advertising materials mentioning features or use of this software 97 * must display the following acknowledgement: 98 * This product includes software developed by Charles M. Hannum. 99 * 4. The name of the author may not be used to endorse or promote products 100 * derived from this software without specific prior written permission. 101 * 102 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 103 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 104 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 105 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 106 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 107 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 108 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 109 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 110 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 111 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 /* 115 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 116 * All rights reserved. 117 * 118 * Redistribution and use in source and binary forms, with or without 119 * modification, are permitted provided that the following conditions 120 * are met: 121 * 1. Redistributions of source code must retain the above copyright 122 * notice, this list of conditions and the following disclaimer. 123 * 2. Redistributions in binary form must reproduce the above copyright 124 * notice, this list of conditions and the following disclaimer in the 125 * documentation and/or other materials provided with the distribution. 126 * 3. All advertising materials mentioning features or use of this software 127 * must display the following acknowledgement: 128 * This product includes software developed by Eric S. Hvozda. 129 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 130 * derived from this software without specific prior written permission. 131 * 132 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 133 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 134 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 135 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 136 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 137 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 138 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 139 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 140 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 141 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 142 */ 143 144 #include <sys/param.h> 145 #include <sys/systm.h> 146 #include <sys/device.h> 147 #include <sys/buf.h> 148 149 #include <machine/bus.h> 150 #include <machine/intr.h> 151 152 #include <dev/scsipi/scsi_all.h> 153 #include <dev/scsipi/scsipi_all.h> 154 #include <dev/scsipi/scsiconf.h> 155 156 #include <dev/isa/isavar.h> 157 #include <dev/isa/isadmavar.h> 158 159 #include <dev/ic/ncr53c9xreg.h> 160 #include <dev/ic/ncr53c9xvar.h> 161 162 #include <dev/isa/espvar.h> 163 164 #ifdef __BROKEN_INDIRECT_CONFIG 165 int esp_isa_match __P((struct device *, void *, void *)); 166 #else 167 int esp_isa_match __P((struct device *, struct cfdata *, void *)); 168 #endif 169 void esp_isa_attach __P((struct device *, struct device *, void *)); 170 171 struct cfattach esp_isa_ca = { 172 sizeof(struct esp_softc), esp_isa_match, esp_isa_attach 173 }; 174 175 struct scsipi_adapter esp_switch = { 176 ncr53c9x_scsi_cmd, 177 minphys, /* no max at this level; handled by DMA code */ 178 NULL, 179 NULL, 180 }; 181 182 struct scsipi_device esp_dev = { 183 NULL, /* Use default error handler */ 184 NULL, /* have a queue, served by this */ 185 NULL, /* have no async handler */ 186 NULL, /* Use default 'done' routine */ 187 }; 188 189 int esp_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 190 191 /* 192 * Functions and the switch for the MI code. 193 */ 194 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 195 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 196 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 197 void esp_dma_reset __P((struct ncr53c9x_softc *)); 198 int esp_dma_intr __P((struct ncr53c9x_softc *)); 199 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 200 size_t *, int, size_t *)); 201 void esp_dma_go __P((struct ncr53c9x_softc *)); 202 void esp_dma_stop __P((struct ncr53c9x_softc *)); 203 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 204 205 struct ncr53c9x_glue esp_glue = { 206 esp_read_reg, 207 esp_write_reg, 208 esp_dma_isintr, 209 esp_dma_reset, 210 esp_dma_intr, 211 esp_dma_setup, 212 esp_dma_go, 213 esp_dma_stop, 214 esp_dma_isactive, 215 NULL, /* gl_clear_latched_intr */ 216 }; 217 218 /* 219 * Look for the board 220 */ 221 int 222 esp_find(iot, ioh, epd) 223 bus_space_tag_t iot; 224 bus_space_handle_t ioh; 225 struct esp_probe_data *epd; 226 { 227 u_int vers; 228 u_int p1; 229 u_int p2; 230 u_int jmp; 231 232 ESP_TRACE(("[esp_find] ")); 233 234 /* reset card before we probe? */ 235 236 /* 237 * Switch to the PIO regs and look for the bit pattern 238 * we expect... 239 */ 240 bus_space_write_1(iot, ioh, NCR_CFG4, 241 NCRCFG4_CRS1 | bus_space_read_1(iot, ioh, NCR_CFG4)); 242 243 #define SIG_MASK 0x87 244 #define REV_MASK 0x70 245 #define M1 0x02 246 #define M2 0x05 247 #define ISNCR 0x80 248 #define ISESP406 0x40 249 250 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 251 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 252 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 253 254 ESP_MISC(("esp_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 255 256 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 257 return 0; 258 259 /* Ok, what is it? */ 260 epd->sc_isncr = (vers & ISNCR); 261 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 262 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 263 264 /* What do the jumpers tell us? */ 265 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 266 267 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 268 epd->sc_parity = jmp & NCRJMP_J2; 269 epd->sc_sync = jmp & NCRJMP_J4; 270 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 271 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 272 case NCRJMP_J0 | NCRJMP_J1: 273 epd->sc_irq = 11; 274 break; 275 case NCRJMP_J0: 276 epd->sc_irq = 10; 277 break; 278 case NCRJMP_J1: 279 epd->sc_irq = 15; 280 break; 281 default: 282 epd->sc_irq = 12; 283 break; 284 } 285 286 bus_space_write_1(iot, ioh, NCR_CFG4, 287 ~NCRCFG4_CRS1 & bus_space_read_1(iot, ioh, NCR_CFG4)); 288 289 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 290 * NCRESPCFG3_FCLK even though it is documented. A bad 291 * batch of chips perhaps? 292 */ 293 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 294 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 295 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 296 & NCRESPCFG3_FCLK; 297 298 return 1; 299 } 300 301 void 302 esp_init(esc, epd) 303 struct esp_softc *esc; 304 struct esp_probe_data *epd; 305 { 306 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 307 308 ESP_TRACE(("[esp_init] ")); 309 310 /* 311 * Set up the glue for MI code early; we use some of it here. 312 */ 313 sc->sc_glue = &esp_glue; 314 315 sc->sc_rev = epd->sc_rev; 316 sc->sc_id = epd->sc_id; 317 318 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 319 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 320 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 321 sc->sc_freq = 40; 322 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 323 } 324 else 325 sc->sc_freq = 24; 326 327 /* Setup the register defaults */ 328 sc->sc_cfg1 = sc->sc_id; 329 if (epd->sc_parity) 330 sc->sc_cfg1 |= NCRCFG1_PARENB; 331 sc->sc_cfg2 = NCRCFG2_SCSI2; 332 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 333 334 /* 335 * This is the value used to start sync negotiations 336 * Note that the NCR register "SYNCTP" is programmed 337 * in "clocks per byte", and has a minimum value of 4. 338 * The SCSI period used in negotiation is one-fourth 339 * of the time (in nanoseconds) needed to transfer one byte. 340 * Since the chip's clock is given in MHz, we have the following 341 * formula: 4 * period = (1000 / freq) * 4 342 */ 343 if (epd->sc_sync) 344 { 345 #ifdef DIAGNOSTIC 346 printf("%s: sync requested, but not supported; will do async\n", 347 sc->sc_dev.dv_xname); 348 #endif 349 epd->sc_sync = 0; 350 } 351 352 sc->sc_minsync = 0; 353 354 /* Really no limit, but since we want to fit into the TCR... */ 355 sc->sc_maxxfer = 64 * 1024; 356 } 357 358 /* 359 * Check the slots looking for a board we recognise 360 * If we find one, note it's address (slot) and call 361 * the actual probe routine to check it out. 362 */ 363 int 364 esp_isa_match(parent, match, aux) 365 struct device *parent; 366 #ifdef __BROKEN_INDIRECT_CONFIG 367 void *match; 368 #else 369 struct cfdata *match; 370 #endif 371 void *aux; 372 { 373 struct isa_attach_args *ia = aux; 374 bus_space_tag_t iot = ia->ia_iot; 375 bus_space_handle_t ioh; 376 struct esp_probe_data epd; 377 int rv; 378 379 ESP_TRACE(("[esp_isa_match] ")); 380 381 if (ia->ia_iobase != 0x230 && ia->ia_iobase != 0x330) 382 return 0; 383 384 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) 385 return 0; 386 387 rv = esp_find(iot, ioh, &epd); 388 389 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 390 391 if (rv) { 392 if (ia->ia_irq != IRQUNK && ia->ia_irq != epd.sc_irq) { 393 #ifdef DIAGNOSTIC 394 printf("esp_isa_match: configured IRQ (%0d) does not " 395 "match board IRQ (%0d), device not configured\n", 396 ia->ia_irq, epd.sc_irq); 397 #endif 398 return 0; 399 } 400 ia->ia_irq = epd.sc_irq; 401 ia->ia_msize = 0; 402 ia->ia_iosize = ESP_ISA_IOSIZE; 403 } 404 return (rv); 405 } 406 407 /* 408 * Attach this instance, and then all the sub-devices 409 */ 410 void 411 esp_isa_attach(parent, self, aux) 412 struct device *parent, *self; 413 void *aux; 414 { 415 struct isa_attach_args *ia = aux; 416 struct esp_softc *esc = (void *)self; 417 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 418 bus_space_tag_t iot = ia->ia_iot; 419 bus_space_handle_t ioh; 420 struct esp_probe_data epd; 421 isa_chipset_tag_t ic = ia->ia_ic; 422 423 printf("\n"); 424 ESP_TRACE(("[esp_isa_attach] ")); 425 426 if (bus_space_map(iot, ia->ia_iobase, ESP_ISA_IOSIZE, 0, &ioh)) { 427 printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 428 return; 429 } 430 431 if (!esp_find(iot, ioh, &epd)) { 432 printf("%s: esp_find failed\n", sc->sc_dev.dv_xname); 433 return; 434 } 435 436 if (ia->ia_drq != DRQUNK) 437 isa_dmacascade(parent, ia->ia_drq); 438 439 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO, 440 (int (*)(void *))ncr53c9x_intr, esc); 441 if (esc->sc_ih == NULL) { 442 printf("%s: couldn't establish interrupt\n", 443 sc->sc_dev.dv_xname); 444 return; 445 } 446 447 esp_init(esc, &epd); 448 449 esc->sc_ioh = ioh; 450 esc->sc_iot = iot; 451 452 printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname, 453 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 454 printf("%s", sc->sc_dev.dv_xname); 455 456 /* 457 * Now try to attach all the sub-devices 458 */ 459 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 460 } 461 462 /* 463 * Glue functions. 464 */ 465 u_char 466 esp_read_reg(sc, reg) 467 struct ncr53c9x_softc *sc; 468 int reg; 469 { 470 struct esp_softc *esc = (struct esp_softc *)sc; 471 u_char v; 472 473 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 474 475 ESP_REGS(("[esp_read_reg CRS%c 0x%02x=0x%02x] ", 476 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 477 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 478 479 return v; 480 } 481 482 void 483 esp_write_reg(sc, reg, val) 484 struct ncr53c9x_softc *sc; 485 int reg; 486 u_char val; 487 { 488 struct esp_softc *esc = (struct esp_softc *)sc; 489 u_char v = val; 490 491 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 492 v = NCRCMD_TRANS; 493 } 494 495 ESP_REGS(("[esp_write_reg CRS%c 0x%02x=0x%02x] ", 496 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 497 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 498 499 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 500 } 501 502 int 503 esp_dma_isintr(sc) 504 struct ncr53c9x_softc *sc; 505 { 506 ESP_TRACE(("[esp_dma_isintr] ")); 507 508 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 509 } 510 511 void 512 esp_dma_reset(sc) 513 struct ncr53c9x_softc *sc; 514 { 515 struct esp_softc *esc = (struct esp_softc *)sc; 516 517 ESP_TRACE(("[esp_dma_reset] ")); 518 519 esc->sc_active = 0; 520 esc->sc_tc = 0; 521 } 522 523 int 524 esp_dma_intr(sc) 525 struct ncr53c9x_softc *sc; 526 { 527 struct esp_softc *esc = (struct esp_softc *)sc; 528 u_char *p; 529 u_int espphase, espstat, espintr; 530 int cnt; 531 532 ESP_TRACE(("[esp_dma_intr] ")); 533 534 if (esc->sc_active == 0) { 535 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 536 return -1; 537 } 538 539 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 540 esc->sc_active = 0; 541 return 0; 542 } 543 544 cnt = *esc->sc_pdmalen; 545 if (*esc->sc_pdmalen == 0) { 546 printf("%s: data interrupt, but no count left\n", 547 sc->sc_dev.dv_xname); 548 } 549 550 p = *esc->sc_dmaaddr; 551 espphase = sc->sc_phase; 552 espstat = (u_int) sc->sc_espstat; 553 espintr = (u_int) sc->sc_espintr; 554 do { 555 if (esc->sc_datain) { 556 *p++ = NCR_READ_REG(sc, NCR_FIFO); 557 cnt--; 558 if (espphase == DATA_IN_PHASE) { 559 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 560 } else { 561 esc->sc_active = 0; 562 } 563 } else { 564 if ( (espphase == DATA_OUT_PHASE) 565 || (espphase == MESSAGE_OUT_PHASE)) { 566 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 567 cnt--; 568 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 569 } else { 570 esc->sc_active = 0; 571 } 572 } 573 574 if (esc->sc_active) { 575 while (!(NCR_READ_REG(sc, NCR_STAT) & 0x80)); 576 espstat = NCR_READ_REG(sc, NCR_STAT); 577 espintr = NCR_READ_REG(sc, NCR_INTR); 578 espphase = (espintr & NCRINTR_DIS) 579 ? /* Disconnected */ BUSFREE_PHASE 580 : espstat & PHASE_MASK; 581 } 582 } while (esc->sc_active && espintr); 583 sc->sc_phase = espphase; 584 sc->sc_espstat = (u_char) espstat; 585 sc->sc_espintr = (u_char) espintr; 586 *esc->sc_dmaaddr = p; 587 *esc->sc_pdmalen = cnt; 588 589 if (*esc->sc_pdmalen == 0) { 590 esc->sc_tc = NCRSTAT_TC; 591 } 592 sc->sc_espstat |= esc->sc_tc; 593 return 0; 594 } 595 596 int 597 esp_dma_setup(sc, addr, len, datain, dmasize) 598 struct ncr53c9x_softc *sc; 599 caddr_t *addr; 600 size_t *len; 601 int datain; 602 size_t *dmasize; 603 { 604 struct esp_softc *esc = (struct esp_softc *)sc; 605 606 ESP_TRACE(("[esp_dma_setup] ")); 607 608 esc->sc_dmaaddr = addr; 609 esc->sc_pdmalen = len; 610 esc->sc_datain = datain; 611 esc->sc_dmasize = *dmasize; 612 esc->sc_tc = 0; 613 614 return 0; 615 } 616 617 void 618 esp_dma_go(sc) 619 struct ncr53c9x_softc *sc; 620 { 621 struct esp_softc *esc = (struct esp_softc *)sc; 622 623 ESP_TRACE(("[esp_dma_go] ")); 624 625 esc->sc_active = 1; 626 } 627 628 void 629 esp_dma_stop(sc) 630 struct ncr53c9x_softc *sc; 631 { 632 ESP_TRACE(("[esp_dma_stop] ")); 633 } 634 635 int 636 esp_dma_isactive(sc) 637 struct ncr53c9x_softc *sc; 638 { 639 struct esp_softc *esc = (struct esp_softc *)sc; 640 641 ESP_TRACE(("[esp_dma_isactive] ")); 642 643 return esc->sc_active; 644 } 645
Indexes created Tue Sep 23 02:09:52 GMT 2025