essreg.h revision 1.5
1 /* 2 * Copyright 1997 3 * Digital Equipment Corporation. All rights reserved. 4 * 5 * This software is furnished under license and may be used and 6 * copied only in accordance with the following terms and conditions. 7 * Subject to these conditions, you may download, copy, install, 8 * use, modify and distribute this software in source and/or binary 9 * form. No title or ownership is transferred hereby. 10 * 11 * 1) Any source code used, modified or distributed must reproduce 12 * and retain this copyright notice and list of conditions as 13 * they appear in the source file. 14 * 15 * 2) No right is granted to use any trade name, trademark, or logo of 16 * Digital Equipment Corporation. Neither the "Digital Equipment 17 * Corporation" name nor any trademark or logo of Digital Equipment 18 * Corporation may be used to endorse or promote products derived 19 * from this software without the prior written permission of 20 * Digital Equipment Corporation. 21 * 22 * 3) This software is provided "AS-IS" and any express or implied 23 * warranties, including but not limited to, any implied warranties 24 * of merchantability, fitness for a particular purpose, or 25 * non-infringement are disclaimed. In no event shall DIGITAL be 26 * liable for any damages whatsoever, and in particular, DIGITAL 27 * shall not be liable for special, indirect, consequential, or 28 * incidental damages or damages for lost profits, loss of 29 * revenue or loss of use, whether such damages arise in contract, 30 * negligence, tort, under statute, in equity, at law or otherwise, 31 * even if advised of the possibility of such damage. 32 */ 33 34 /* 35 ** @(#) $RCSfile: essreg.h,v $ $Revision: 1.5 $ (SHARK) $Date: 1998/08/09 02:05:53 $ 36 ** 37 **++ 38 ** 39 ** essreg.h 40 ** 41 ** FACILITY: 42 ** 43 ** DIGITAL Network Appliance Reference Design (DNARD) 44 ** 45 ** MODULE DESCRIPTION: 46 ** 47 ** This module contains the constant definitions for the device 48 ** registers on the ESS Technologies 1888/1887/888 sound chip. 49 ** 50 ** AUTHORS: 51 ** 52 ** Blair Fidler Software Engineering Australia 53 ** Gold Coast, Australia. 54 ** 55 ** CREATION DATE: 56 ** 57 ** March 10, 1997. 58 ** 59 ** MODIFICATION HISTORY: 60 ** 61 **-- 62 */ 63 64 /* 65 * DSP commands. This unit handles MIDI and audio capabilities. 66 * The DSP can be reset, data/commands can be read or written to it, 67 * and it can generate interrupts. Interrupts are generated for MIDI 68 * input or DMA completion. They seem to have neglected the fact 69 * that it would be nice to have a MIDI transmission complete interrupt. 70 * Worse, the DMA engine is half-duplex. This means you need to do 71 * (timed) programmed I/O to be able to record and play simulataneously. 72 */ 73 #define ESS_ACMD_DAC8WRITE 0x10 /* direct-mode 8-bit DAC write */ 74 #define ESS_ACMD_DAC16WRITE 0x11 /* direct-mode 16-bit DAC write */ 75 #define ESS_ACMD_DMA8OUT 0x14 /* 8-bit linear DMA output */ 76 #define ESS_ACMD_DMA16OUT 0x15 /* 16-bit linear DMA output */ 77 #define ESS_ACMD_AUTODMA8OUT 0x1C /* auto-init 8-bit linear DMA output */ 78 #define ESS_ACMD_AUTODMA16OUT 0x1D /* auto-init 16-bit linear DMA output */ 79 #define ESS_ACMD_ADC8READ 0x20 /* direct-mode 8-bit ADC read */ 80 #define ESS_ACMD_ADC16READ 0x21 /* direct-mode 16-bit ADC read */ 81 #define ESS_ACMD_DMA8IN 0x24 /* 8-bit linear DMA input */ 82 #define ESS_ACMD_DMA16IN 0x25 /* 16-bit linear DMA input */ 83 #define ESS_ACMD_AUTODMA8IN 0x2C /* auto-init 8-bit linear DMA input */ 84 #define ESS_ACMD_AUTODMA16IN 0x2D /* auto-init 16-bit linear DMA input */ 85 #define ESS_ACMD_SETTIMECONST1 0x40 /* set time constant (1MHz base) */ 86 #define ESS_ACMD_SETTIMECONST15 0x41 /* set time constant (1.5MHz base) */ 87 #define ESS_ACMD_SETFILTER 0x42 /* set filter clock independently */ 88 #define ESS_ACMD_BLOCKSIZE 0x48 /* set blk size for high speed xfer */ 89 90 #define ESS_ACMD_DMA4OUT 0x74 /* 4-bit ADPCM DMA output */ 91 #define ESS_ACMD_DMA4OUTREF 0x75 /* 4-bit ADPCM DMA output with ref */ 92 #define ESS_ACMD_DMA2_6OUT 0x76 /* 2.6-bit ADPCM DMA output */ 93 #define ESS_ACMD_DMA2_6OUTREF 0x77 /* 2.6-bit ADPCM DMA output with ref */ 94 #define ESS_ACMD_DMA2OUT 0x7A /* 2-bit ADPCM DMA output */ 95 #define ESS_ACMD_DMA2OUTREF 0x7B /* 2-bit ADPCM DMA output with ref */ 96 #define ESS_ACMD_SILENCEOUT 0x80 /* output a block of silence */ 97 #define ESS_ACMD_START_AUTO_OUT 0x90 /* start auto-init 8-bit DMA output */ 98 #define ESS_ACMD_START_OUT 0x91 /* start 8-bit DMA output */ 99 #define ESS_ACMD_START_AUTO_IN 0x98 /* start auto-init 8-bit DMA input */ 100 #define ESS_ACMD_START_IN 0x99 /* start 8-bit DMA input */ 101 102 #define ESS_XCMD_SAMPLE_RATE 0xA1 /* sample rate for Audio1 channel */ 103 #define ESS_XCMD_FILTER_CLOCK 0xA2 /* filter clock for Audio1 channel*/ 104 #define ESS_XCMD_XFER_COUNTLO 0xA4 /* */ 105 #define ESS_XCMD_XFER_COUNTHI 0xA5 /* */ 106 #define ESS_XCMD_AUDIO_CTRL 0xA8 /* */ 107 #define ESS_AUDIO_CTRL_MONITOR 0x08 /* 0=disable/1=enable */ 108 #define ESS_AUDIO_CTRL_MONO 0x02 /* 0=disable/1=enable */ 109 #define ESS_AUDIO_CTRL_STEREO 0x01 /* 0=disable/1=enable */ 110 #define ESS_XCMD_PREAMP_CTRL 0xA9 /* */ 111 #define ESS_PREAMP_CTRL_ENABLE 0x04 112 113 #define ESS_XCMD_IRQ_CTRL 0xB1 /* legacy audio interrupt control */ 114 #define ESS_IRQ_CTRL_INTRA 0x00 115 #define ESS_IRQ_CTRL_INTRB 0x04 116 #define ESS_IRQ_CTRL_INTRC 0x08 117 #define ESS_IRQ_CTRL_INTRD 0x0C 118 #define ESS_IRQ_CTRL_MASK 0x10 119 #define ESS_IRQ_CTRL_EXT 0x40 120 #define ESS_XCMD_DRQ_CTRL 0xB2 /* audio DRQ control */ 121 #define ESS_DRQ_CTRL_DRQA 0x04 122 #define ESS_DRQ_CTRL_DRQB 0x08 123 #define ESS_DRQ_CTRL_DRQC 0x0C 124 #define ESS_DRQ_CTRL_PU 0x10 125 #define ESS_DRQ_CTRL_EXT 0x40 126 #define ESS_XCMD_VOLIN_CTRL 0xB4 /* stereo input volume control */ 127 #define ESS_XCMD_AUDIO1_CTRL1 0xB7 /* */ 128 #define ESS_AUDIO1_CTRL1_FIFO_SIGNED 0x20 /* 0=unsigned/1=signed */ 129 #define ESS_AUDIO1_CTRL1_FIFO_SIZE 0x04 /* 0=8-bit/1=16-bit */ 130 #define ESS_XCMD_AUDIO1_CTRL2 0xB8 /* */ 131 #define ESS_AUDIO1_CTRL2_FIFO_ENABLE 0x01 /* 0=disable/1=enable */ 132 #define ESS_AUDIO1_CTRL2_DMA_READ 0x02 /* 0=DMA write/1=DMA read */ 133 #define ESS_AUDIO1_CTRL2_AUTO_INIT 0x04 134 #define ESS_AUDIO1_CTRL2_ADC_ENABLE 0x08 /* 0=DAC mode/1=ADC mode */ 135 #define ESS_XCMD_DEMAND_CTRL 0xB9 /* */ 136 #define ESS_DEMAND_CTRL_SINGLE 0x00 /* 1-byte transfers */ 137 #define ESS_DEMAND_CTRL_DEMAND_2 0x01 /* 2-byte transfers */ 138 #define ESS_DEMAND_CTRL_DEMAND_4 0x02 /* 4-byte transfers */ 139 140 #define ESS_ACMD_ENABLE_EXT 0xC6 /* enable ESS extension commands */ 141 #define ESS_ACMD_DISABLE_EXT 0xC7 /* enable ESS extension commands */ 142 143 #define ESS_ACMD_PAUSE_DMA 0xD0 /* pause DMA */ 144 #define ESS_ACMD_ENABLE_SPKR 0xD1 /* enable Audio1 DAC input to mixer */ 145 #define ESS_ACMD_DISABLE_SPKR 0xD3 /* disable Audio1 DAC input to mixer */ 146 #define ESS_ACMD_CONT_DMA 0xD4 /* continue paused DMA */ 147 #define ESS_ACMD_SPKR_STATUS 0xD8 /* return Audio1 DAC status: */ 148 #define ESS_SPKR_OFF 0x00 149 #define ESS_SPKR_ON 0xFF 150 #define ESS_ACMD_VERSION 0xE1 /* get version number */ 151 #define ESS_ACMD_LEGACY_ID 0xE7 /* get legacy ES688/ES1688 ID bytes */ 152 153 #define ESS_MINRATE 5000 /* XXX */ 154 #define ESS_MAXRATE 50000 /* XXX */ 155 156 /* 157 * Macros to detect valid hardware configuration data. 158 */ 159 #define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250) 160 #define ESS_IRQ1_VALID(irq) ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10) 161 162 #define ESS_IRQ2_VALID(irq) ((irq) == 15) 163 164 #define ESS_IRQ12_VALID(irq) ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10 || (irq) == 15) 165 166 #define ESS_DRQ1_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3) 167 168 #define ESS_DRQ2_VALID(chan, model) (((model) != ESS_1887) ? ((chan) == 5) : ((chan) == 0 || (chan) == 1 || (chan) == 3 || (chan) == 5)) 169 170 #define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250) 171 172 /* 173 * Macros to manipulate gain values 174 */ 175 #define ESS_4BIT_GAIN(x) ((x) & 0xf0) 176 #define ESS_3BIT_GAIN(x) (((x) & 0xe0) >> 1) 177 #define ESS_STEREO_GAIN(l, r) ((l) | ((r) >> 4)) 178 #define ESS_MONO_GAIN(x) ((x) >> 4) 179 180 #ifdef ESS_AMODE_LOW 181 /* 182 * Registers used to configure ESS chip via Read Key Sequence 183 */ 184 #define ESS_CONFIG_KEY_BASE 0x229 185 #define ESS_CONFIG_KEY_PORTS 3 186 #else 187 /* 188 * Registers used to configure ESS chip via System Control Register (SCR) 189 */ 190 #define ESS_SCR_ACCESS_BASE 0xF9 191 #define ESS_SCR_ACCESS_PORTS 3 192 #define ESS_SCR_LOCK 0 193 #define ESS_SCR_UNLOCK 2 194 195 #define ESS_SCR_BASE 0xE0 196 #define ESS_SCR_PORTS 2 197 #define ESS_SCR_INDEX 0 198 #define ESS_SCR_DATA 1 199 200 /* 201 * Bit definitions for SCR 202 */ 203 #define ESS_SCR_AUDIO_ENABLE 0x04 204 #define ESS_SCR_AUDIO_220 0x00 205 #define ESS_SCR_AUDIO_230 0x01 206 #define ESS_SCR_AUDIO_240 0x02 207 #define ESS_SCR_AUDIO_250 0x03 208 #endif 209 210 /*****************************************************************************/ 211 /* DSP Timeout Definitions */ 212 /*****************************************************************************/ 213 #define ESS_READ_TIMEOUT 5000 /* number of times to try a read, 5ms*/ 214 #define ESS_WRITE_TIMEOUT 5000 /* number of times to try a write, 5ms */ 215 216 217 #define ESS_NPORT 16 218 #define ESS_DSP_RESET 0x06 219 #define ESS_RESET_EXT 0x03 /* reset and use second DMA */ 220 #define ESS_MAGIC 0xAA /* response to successful reset */ 221 222 #define ESS_DSP_READ 0x0A 223 #define ESS_DSP_WRITE 0x0C 224 225 #define ESS_DSP_RW_STATUS 0x0C 226 #define ESS_CLEAR_INTR 0x0E 227 228 #define ESS_DSP_READ_STATUS 0x0C 229 #define ESS_DSP_READ_MASK 0x40 230 #define ESS_DSP_READ_READY 0x40 231 232 #define ESS_DSP_WRITE_STATUS 0x0C 233 #define ESS_DSP_WRITE_MASK 0x80 234 #define ESS_DSP_WRITE_READY 0x00 235 236 237 #define ESS_MIX_REG_SELECT 0x04 238 #define ESS_MIX_REG_DATA 0x05 239 #define ESS_MIX_RESET 0x00 /* mixer reset port and value */ 240 241 242 /* 243 * ESS Mixer registers 244 */ 245 #define ESS_MREG_SAMPLE_RATE 0x70 /* sample rate for Audio2 channel */ 246 #define ESS_MREG_FILTER_CLOCK 0x72 /* filter clock for Audio2 channel */ 247 #define ESS_MREG_XFER_COUNTLO 0x74 /* low-byte of DMA transfer size */ 248 #define ESS_MREG_XFER_COUNTHI 0x76 /* high-byte of DMA transfer size */ 249 #define ESS_MREG_AUDIO2_CTRL1 0x78 /* control register 1 for Audio2: */ 250 #define ESS_AUDIO2_CTRL1_SINGLE 0x00 251 #define ESS_AUDIO2_CTRL1_DEMAND_2 0x40 252 #define ESS_AUDIO2_CTRL1_DEMAND_4 0x80 253 #define ESS_AUDIO2_CTRL1_DEMAND_8 0xC0 254 #define ESS_AUDIO2_CTRL1_XFER_SIZE 0x20 /* 0=8-bit/1=16-bit */ 255 #define ESS_AUDIO2_CTRL1_AUTO_INIT 0x10 256 #define ESS_AUDIO2_CTRL1_FIFO_ENABLE 0x02 /* 0=disable/1=enable */ 257 #define ESS_AUDIO2_CTRL1_DAC_ENABLE 0x01 /* 0=disable/1=enable */ 258 #define ESS_MREG_AUDIO2_CTRL2 0x7A /* control register 2 for Audio2: */ 259 #define ESS_AUDIO2_CTRL2_FIFO_SIZE 0x01 /* 0=8-bit/1=16-bit */ 260 #define ESS_AUDIO2_CTRL2_CHANNELS 0x02 /* 0=mono/1=stereo */ 261 #define ESS_AUDIO2_CTRL2_FIFO_SIGNED 0x04 /* 0=unsigned/1=signed */ 262 #define ESS_AUDIO2_CTRL2_DMA_ENABLE 0x20 /* 0=disable/1=enable */ 263 #define ESS_AUDIO2_CTRL2_IRQ2_ENABLE 0x40 264 #define ESS_AUDIO2_CTRL2_IRQ_LATCH 0x80 265 #define ESS_MREG_AUDIO2_CTRL3 0x7D 266 #define ESS_AUDIO2_CTRL3_DRQA 0x00 267 #define ESS_AUDIO2_CTRL3_DRQB 0x01 268 #define ESS_AUDIO2_CTRL3_DRQC 0x02 269 #define ESS_AUDIO2_CTRL3_DRQD 0x03 270 #define ESS_AUDIO2_CTRL3_DRQ_PD 0x04 271 #define ESS_MREG_INTR_ST 0x7F 272 #define ESS_IS_SELECT_IRQ 0x01 273 #define ESS_IS_ES1888 0x00 274 #define ESS_IS_INTRA 0x02 275 #define ESS_IS_INTRB 0x04 276 #define ESS_IS_INTRC 0x06 277 #define ESS_IS_INTRD 0x08 278 #define ESS_IS_INTRE 0x0A 279
Indexes created Mon Sep 22 21:09:42 GMT 2025