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      1  1.5   andvar /*	$NetBSD: if_elreg.h,v 1.5 2022/05/20 19:34:23 andvar Exp $	*/
      2  1.4      cgd 
      3  1.2      cgd /*
      4  1.2      cgd  * Copyright (c) 1994, Matthew E. Kimmel.  Permission is hereby granted
      5  1.1  hpeyerl  * to use, copy, modify and distribute this software provided that both
      6  1.1  hpeyerl  * the copyright notice and this permission notice appear in all copies
      7  1.1  hpeyerl  * of the software, derivative works or modified versions, and any
      8  1.1  hpeyerl  * portions thereof.
      9  1.1  hpeyerl  */
     10  1.1  hpeyerl 
     11  1.2      cgd /*
     12  1.2      cgd  * 3COM Etherlink 3C501 Register Definitions
     13  1.2      cgd  */
     14  1.2      cgd 
     15  1.2      cgd /*
     16  1.2      cgd  * I/O Ports
     17  1.2      cgd  */
     18  1.2      cgd #define	EL_RXS		0x6	/* Receive status register */
     19  1.2      cgd #define	EL_RXC		0x6	/* Receive command register */
     20  1.2      cgd #define	EL_TXS		0x7	/* Transmit status register */
     21  1.2      cgd #define	EL_TXC		0x7	/* Transmit command register */
     22  1.2      cgd #define	EL_GPBL		0x8	/* GP buffer ptr low byte */
     23  1.2      cgd #define	EL_GPBH		0x9	/* GP buffer ptr high byte */
     24  1.2      cgd #define	EL_RBL		0xa	/* Receive buffer ptr low byte */
     25  1.2      cgd #define	EL_RBC		0xa	/* Receive buffer clear */
     26  1.2      cgd #define	EL_RBH		0xb	/* Receive buffer ptr high byte */
     27  1.2      cgd #define	EL_EAW		0xc	/* Ethernet address window */
     28  1.5   andvar #define	EL_AS		0xe	/* Auxiliary status register */
     29  1.5   andvar #define	EL_AC		0xe	/* Auxiliary command register */
     30  1.2      cgd #define	EL_BUF		0xf	/* Data buffer */
     31  1.1  hpeyerl 
     32  1.1  hpeyerl /* Receive status register bits */
     33  1.2      cgd #define	EL_RXS_OFLOW	0x01	/* Overflow error */
     34  1.2      cgd #define	EL_RXS_FCS	0x02	/* FCS error */
     35  1.2      cgd #define	EL_RXS_DRIB	0x04	/* Dribble error */
     36  1.2      cgd #define	EL_RXS_SHORT	0x08	/* Short frame */
     37  1.2      cgd #define	EL_RXS_NOFLOW	0x10	/* No overflow */
     38  1.1  hpeyerl #define	EL_RXS_GOOD	0x20	/* Received good frame */
     39  1.2      cgd #define	EL_RXS_STALE	0x80	/* Stale receive status */
     40  1.1  hpeyerl 
     41  1.1  hpeyerl /* Receive command register bits */
     42  1.2      cgd #define	EL_RXC_DISABLE	0x00	/* Receiver disabled */
     43  1.2      cgd #define	EL_RXC_DOFLOW	0x01	/* Detect overflow */
     44  1.2      cgd #define	EL_RXC_DFCS	0x02	/* Detect FCS errs */
     45  1.2      cgd #define	EL_RXC_DDRIB	0x04	/* Detect dribble errors */
     46  1.2      cgd #define	EL_RXC_DSHORT	0x08	/* Detect short frames */
     47  1.2      cgd #define	EL_RXC_DNOFLOW	0x10	/* Detect frames w/o overflow ??? */
     48  1.2      cgd #define	EL_RXC_AGF	0x20	/* Accept Good Frames */
     49  1.2      cgd #define	EL_RXC_PROMISC	0x40	/* Promiscuous mode */
     50  1.2      cgd #define	EL_RXC_ABROAD	0x80	/* Accept address, broadcast */
     51  1.2      cgd #define	EL_RXC_AMULTI	0xc0	/* Accept address, multicast */
     52  1.1  hpeyerl 
     53  1.1  hpeyerl /* Transmit status register bits */
     54  1.2      cgd #define	EL_TXS_UFLOW	0x01	/* Underflow */
     55  1.2      cgd #define	EL_TXS_COLL	0x02	/* Collision */
     56  1.2      cgd #define	EL_TXS_COLL16	0x04	/* Collision 16 */
     57  1.2      cgd #define	EL_TXS_READY	0x08	/* Ready for new frame */
     58  1.1  hpeyerl 
     59  1.1  hpeyerl /* Transmit command register bits */
     60  1.2      cgd #define	EL_TXC_DUFLOW	0x01	/* Detect underflow */
     61  1.2      cgd #define	EL_TXC_DCOLL	0x02	/* Detect collisions */
     62  1.2      cgd #define	EL_TXC_DCOLL16	0x04	/* Detect collision 16 */
     63  1.2      cgd #define	EL_TXC_DSUCCESS	0x08	/* Detect success */
     64  1.1  hpeyerl 
     65  1.5   andvar /* Auxiliary status register bits */
     66  1.2      cgd #define	EL_AS_RXBUSY	0x01	/* Receive busy */
     67  1.2      cgd #define	EL_AS_DMADONE	0x10	/* DMA finished */
     68  1.2      cgd #define	EL_AS_TXBUSY	0x80	/* Transmit busy */
     69  1.1  hpeyerl 
     70  1.5   andvar /* Auxiliary command register bits */
     71  1.2      cgd #define	EL_AC_HOST	0x00	/* System bus can access buffer */
     72  1.2      cgd #define	EL_AC_IRQE	0x01	/* IRQ enable */
     73  1.2      cgd #define	EL_AC_TXBAD	0x02	/* Transmit frames with bad FCS */
     74  1.2      cgd #define	EL_AC_TXFRX	0x04	/* Transmit followed by receive */
     75  1.2      cgd #define	EL_AC_RX	0x08	/* Receive */
     76  1.2      cgd #define	EL_AC_LB	0x0c	/* Loopback */
     77  1.2      cgd #define	EL_AC_DRQ	0x20	/* DMA request */
     78  1.2      cgd #define	EL_AC_RIDE	0x40	/* DRQ and IRQ enabled */
     79  1.2      cgd #define	EL_AC_RESET	0x80	/* Reset */
     80  1.1  hpeyerl 
     81  1.1  hpeyerl /* Packet buffer size */
     82  1.2      cgd #define	EL_BUFSIZ	2048
     83