if_ix.c revision 1.28.2.1
1 /* $NetBSD: if_ix.c,v 1.28.2.1 2008/05/18 12:34:03 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Rafal K. Boni. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ix.c,v 1.28.2.1 2008/05/18 12:34:03 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/protosw.h> 41 #include <sys/socket.h> 42 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_types.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 49 #include <sys/cpu.h> 50 #include <sys/bus.h> 51 #include <sys/intr.h> 52 53 #include <dev/isa/isareg.h> 54 #include <dev/isa/isavar.h> 55 56 #include <dev/ic/i82586reg.h> 57 #include <dev/ic/i82586var.h> 58 #include <dev/isa/if_ixreg.h> 59 60 #ifdef IX_DEBUG 61 #define DPRINTF(x) printf x 62 #else 63 #define DPRINTF(x) 64 #endif 65 66 int ix_media[] = { 67 IFM_ETHER | IFM_10_5, 68 IFM_ETHER | IFM_10_2, 69 IFM_ETHER | IFM_10_T, 70 }; 71 #define NIX_MEDIA (sizeof(ix_media) / sizeof(ix_media[0])) 72 73 struct ix_softc { 74 struct ie_softc sc_ie; 75 76 bus_space_tag_t sc_regt; /* space tag for registers */ 77 bus_space_handle_t sc_regh; /* space handle for registers */ 78 79 u_int8_t use_pio; /* use PIO rather than shared mem */ 80 u_int16_t irq_encoded; /* encoded IRQ */ 81 void *sc_ih; /* interrupt handle */ 82 }; 83 84 static void ix_reset(struct ie_softc *, int); 85 static void ix_atten(struct ie_softc *, int); 86 static int ix_intrhook(struct ie_softc *, int); 87 88 static void ix_copyin(struct ie_softc *, void *, int, size_t); 89 static void ix_copyout(struct ie_softc *, const void *, int, size_t); 90 91 static void ix_bus_barrier(struct ie_softc *, int, int, int); 92 93 static u_int16_t ix_read_16(struct ie_softc *, int); 94 static void ix_write_16(struct ie_softc *, int, u_int16_t); 95 static void ix_write_24(struct ie_softc *, int, int); 96 static void ix_zeromem (struct ie_softc *, int, int); 97 98 static void ix_mediastatus(struct ie_softc *, struct ifmediareq *); 99 100 static u_int16_t ix_read_eeprom(bus_space_tag_t, bus_space_handle_t, int); 101 static void ix_eeprom_outbits(bus_space_tag_t, bus_space_handle_t, int, int); 102 static int ix_eeprom_inbits (bus_space_tag_t, bus_space_handle_t); 103 static void ix_eeprom_clock (bus_space_tag_t, bus_space_handle_t, int); 104 105 int ix_match(struct device *, struct cfdata *, void *); 106 void ix_attach(struct device *, struct device *, void *); 107 108 /* 109 * EtherExpress/16 support routines 110 */ 111 static void 112 ix_reset(sc, why) 113 struct ie_softc *sc; 114 int why; 115 { 116 struct ix_softc* isc = (struct ix_softc *) sc; 117 118 switch (why) { 119 case CHIP_PROBE: 120 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 121 IX_RESET_586); 122 delay(100); 123 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 0); 124 delay(100); 125 break; 126 127 case CARD_RESET: 128 break; 129 } 130 } 131 132 static void 133 ix_atten(struct ie_softc *sc, int why) 134 { 135 struct ix_softc* isc = (struct ix_softc *) sc; 136 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ATTN, 0); 137 } 138 139 static u_int16_t 140 ix_read_eeprom(iot, ioh, location) 141 bus_space_tag_t iot; 142 bus_space_handle_t ioh; 143 int location; 144 { 145 int ectrl, edata; 146 147 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 148 ectrl &= IX_ECTRL_MASK; 149 ectrl |= IX_ECTRL_EECS; 150 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 151 152 ix_eeprom_outbits(iot, ioh, IX_EEPROM_READ, IX_EEPROM_OPSIZE1); 153 ix_eeprom_outbits(iot, ioh, location, IX_EEPROM_ADDR_SIZE); 154 edata = ix_eeprom_inbits(iot, ioh); 155 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 156 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EEDI | IX_ECTRL_EECS); 157 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 158 ix_eeprom_clock(iot, ioh, 1); 159 ix_eeprom_clock(iot, ioh, 0); 160 return (edata); 161 } 162 163 static void 164 ix_eeprom_outbits(iot, ioh, edata, count) 165 bus_space_tag_t iot; 166 bus_space_handle_t ioh; 167 int edata, count; 168 { 169 int ectrl, i; 170 171 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 172 ectrl &= ~IX_RESET_ASIC; 173 for (i = count - 1; i >= 0; i--) { 174 ectrl &= ~IX_ECTRL_EEDI; 175 if (edata & (1 << i)) { 176 ectrl |= IX_ECTRL_EEDI; 177 } 178 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 179 delay(1); /* eeprom data must be setup for 0.4 uSec */ 180 ix_eeprom_clock(iot, ioh, 1); 181 ix_eeprom_clock(iot, ioh, 0); 182 } 183 ectrl &= ~IX_ECTRL_EEDI; 184 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 185 delay(1); /* eeprom data must be held for 0.4 uSec */ 186 } 187 188 static int 189 ix_eeprom_inbits(iot, ioh) 190 bus_space_tag_t iot; 191 bus_space_handle_t ioh; 192 { 193 int ectrl, edata, i; 194 195 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 196 ectrl &= ~IX_RESET_ASIC; 197 for (edata = 0, i = 0; i < 16; i++) { 198 edata = edata << 1; 199 ix_eeprom_clock(iot, ioh, 1); 200 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 201 if (ectrl & IX_ECTRL_EEDO) { 202 edata |= 1; 203 } 204 ix_eeprom_clock(iot, ioh, 0); 205 } 206 return (edata); 207 } 208 209 static void 210 ix_eeprom_clock(iot, ioh, state) 211 bus_space_tag_t iot; 212 bus_space_handle_t ioh; 213 int state; 214 { 215 int ectrl; 216 217 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 218 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EESK); 219 if (state) { 220 ectrl |= IX_ECTRL_EESK; 221 } 222 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 223 delay(9); /* EESK must be stable for 8.38 uSec */ 224 } 225 226 static int 227 ix_intrhook(sc, where) 228 struct ie_softc *sc; 229 int where; 230 { 231 struct ix_softc* isc = (struct ix_softc *) sc; 232 233 switch (where) { 234 case INTR_ENTER: 235 /* entering ISR: disable card interrupts */ 236 bus_space_write_1(isc->sc_regt, isc->sc_regh, 237 IX_IRQ, isc->irq_encoded); 238 break; 239 240 case INTR_EXIT: 241 /* exiting ISR: re-enable card interrupts */ 242 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_IRQ, 243 isc->irq_encoded | IX_IRQ_ENABLE); 244 break; 245 } 246 247 return 1; 248 } 249 250 251 static void 252 ix_copyin (sc, dst, offset, size) 253 struct ie_softc *sc; 254 void *dst; 255 int offset; 256 size_t size; 257 { 258 int i, dribble; 259 u_int8_t* bptr = dst; 260 u_int16_t* wptr = dst; 261 struct ix_softc* isc = (struct ix_softc *) sc; 262 263 if (isc->use_pio) { 264 /* Reset read pointer to the specified offset */ 265 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 266 BUS_SPACE_BARRIER_READ); 267 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 268 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 269 BUS_SPACE_BARRIER_WRITE); 270 } else { 271 bus_space_barrier(sc->bt, sc->bh, offset, size, 272 BUS_SPACE_BARRIER_READ); 273 } 274 275 if (offset % 2) { 276 if (isc->use_pio) 277 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 278 else 279 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 280 offset++; bptr++; size--; 281 } 282 283 dribble = size % 2; 284 wptr = (u_int16_t*) bptr; 285 286 if (isc->use_pio) { 287 for(i = 0; i < size / 2; i++) { 288 *wptr = bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 289 wptr++; 290 } 291 } else { 292 bus_space_read_region_2(sc->bt, sc->bh, offset, 293 (u_int16_t *) bptr, size / 2); 294 } 295 296 if (dribble) { 297 bptr += size - 1; 298 offset += size - 1; 299 300 if (isc->use_pio) 301 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 302 else 303 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 304 } 305 } 306 307 static void 308 ix_copyout (sc, src, offset, size) 309 struct ie_softc *sc; 310 const void *src; 311 int offset; 312 size_t size; 313 { 314 int i, dribble; 315 int osize = size; 316 int ooffset = offset; 317 const u_int8_t* bptr = src; 318 const u_int16_t* wptr = src; 319 struct ix_softc* isc = (struct ix_softc *) sc; 320 321 if (isc->use_pio) { 322 /* Reset write pointer to the specified offset */ 323 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 324 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 325 BUS_SPACE_BARRIER_WRITE); 326 } 327 328 if (offset % 2) { 329 if (isc->use_pio) 330 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 331 else 332 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 333 offset++; bptr++; size--; 334 } 335 336 dribble = size % 2; 337 wptr = (const u_int16_t*) bptr; 338 339 if (isc->use_pio) { 340 for(i = 0; i < size / 2; i++) { 341 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, *wptr); 342 wptr++; 343 } 344 } else { 345 bus_space_write_region_2(sc->bt, sc->bh, offset, 346 (const u_int16_t *)bptr, size / 2); 347 } 348 349 if (dribble) { 350 bptr += size - 1; 351 offset += size - 1; 352 353 if (isc->use_pio) 354 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 355 else 356 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 357 } 358 359 if (isc->use_pio) 360 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 361 BUS_SPACE_BARRIER_WRITE); 362 else 363 bus_space_barrier(sc->bt, sc->bh, ooffset, osize, 364 BUS_SPACE_BARRIER_WRITE); 365 } 366 367 static void 368 ix_bus_barrier(sc, offset, length, flags) 369 struct ie_softc *sc; 370 int offset, length, flags; 371 { 372 struct ix_softc* isc = (struct ix_softc *) sc; 373 374 if (isc->use_pio) 375 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, flags); 376 else 377 bus_space_barrier(sc->bt, sc->bh, offset, length, flags); 378 } 379 380 static u_int16_t 381 ix_read_16 (sc, offset) 382 struct ie_softc *sc; 383 int offset; 384 { 385 struct ix_softc* isc = (struct ix_softc *) sc; 386 387 if (isc->use_pio) { 388 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 389 BUS_SPACE_BARRIER_READ); 390 391 /* Reset read pointer to the specified offset */ 392 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 393 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 394 BUS_SPACE_BARRIER_WRITE); 395 396 return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 397 } else { 398 bus_space_barrier(sc->bt, sc->bh, offset, 2, 399 BUS_SPACE_BARRIER_READ); 400 return bus_space_read_2(sc->bt, sc->bh, offset); 401 } 402 } 403 404 static void 405 ix_write_16 (sc, offset, value) 406 struct ie_softc *sc; 407 int offset; 408 u_int16_t value; 409 { 410 struct ix_softc* isc = (struct ix_softc *) sc; 411 412 if (isc->use_pio) { 413 /* Reset write pointer to the specified offset */ 414 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 415 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 416 BUS_SPACE_BARRIER_WRITE); 417 418 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); 419 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 420 BUS_SPACE_BARRIER_WRITE); 421 } else { 422 bus_space_write_2(sc->bt, sc->bh, offset, value); 423 bus_space_barrier(sc->bt, sc->bh, offset, 2, 424 BUS_SPACE_BARRIER_WRITE); 425 } 426 } 427 428 static void 429 ix_write_24 (sc, offset, addr) 430 struct ie_softc *sc; 431 int offset, addr; 432 { 433 char* ptr; 434 struct ix_softc* isc = (struct ix_softc *) sc; 435 int val = addr + (u_long) sc->sc_maddr - (u_long) sc->sc_iobase; 436 437 if (isc->use_pio) { 438 /* Reset write pointer to the specified offset */ 439 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 440 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 441 BUS_SPACE_BARRIER_WRITE); 442 443 ptr = (char*) &val; 444 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 445 *((u_int16_t *)ptr)); 446 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 447 *((u_int16_t *)(ptr + 2))); 448 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 449 BUS_SPACE_BARRIER_WRITE); 450 } else { 451 bus_space_write_4(sc->bt, sc->bh, offset, val); 452 bus_space_barrier(sc->bt, sc->bh, offset, 4, 453 BUS_SPACE_BARRIER_WRITE); 454 } 455 } 456 457 static void 458 ix_zeromem(sc, offset, count) 459 struct ie_softc *sc; 460 int offset, count; 461 { 462 int i; 463 int dribble; 464 struct ix_softc* isc = (struct ix_softc *) sc; 465 466 if (isc->use_pio) { 467 /* Reset write pointer to the specified offset */ 468 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 469 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 470 BUS_SPACE_BARRIER_WRITE); 471 472 if (offset % 2) { 473 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 474 count--; 475 } 476 477 dribble = count % 2; 478 for(i = 0; i < count / 2; i++) 479 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 0); 480 481 if (dribble) 482 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 483 484 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 485 BUS_SPACE_BARRIER_WRITE); 486 } else { 487 bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); 488 bus_space_barrier(sc->bt, sc->bh, offset, count, 489 BUS_SPACE_BARRIER_WRITE); 490 } 491 } 492 493 static void 494 ix_mediastatus(sc, ifmr) 495 struct ie_softc *sc; 496 struct ifmediareq *ifmr; 497 { 498 struct ifmedia *ifm = &sc->sc_media; 499 500 /* 501 * The currently selected media is always the active media. 502 */ 503 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 504 } 505 506 int 507 ix_match(struct device *parent, struct cfdata *cf, void *aux) 508 { 509 int i; 510 int rv = 0; 511 bus_addr_t maddr; 512 bus_size_t msiz; 513 u_short checksum = 0; 514 bus_space_handle_t ioh; 515 bus_space_tag_t iot; 516 u_int8_t val, bart_config; 517 u_short pg, adjust, decode, edecode; 518 u_short board_id, id_var1, id_var2, irq, irq_encoded; 519 struct isa_attach_args * const ia = aux; 520 short irq_translate[] = {0, 0x09, 0x03, 0x04, 0x05, 0x0a, 0x0b, 0}; 521 522 if (ia->ia_nio < 1) 523 return (0); 524 if (ia->ia_niomem < 1) 525 return (0); 526 if (ia->ia_nirq < 1) 527 return (0); 528 529 if (ISA_DIRECT_CONFIG(ia)) 530 return (0); 531 532 iot = ia->ia_iot; 533 534 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 535 return (0); 536 537 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 538 IX_IOSIZE, 0, &ioh) != 0) { 539 DPRINTF(("Can't map io space at 0x%x\n", ia->ia_iobase)); 540 return (0); 541 } 542 543 /* XXX: reset any ee16 at the current iobase */ 544 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_ASIC); 545 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 546 delay(240); 547 548 /* now look for ee16. */ 549 board_id = id_var1 = id_var2 = 0; 550 for (i = 0; i < 4 ; i++) { 551 id_var1 = bus_space_read_1(iot, ioh, IX_ID_PORT); 552 id_var2 = ((id_var1 & 0x03) << 2); 553 board_id |= (( id_var1 >> 4) << id_var2); 554 } 555 556 if (board_id != IX_ID) { 557 DPRINTF(("BART ID mismatch (got 0x%04x, expected 0x%04x)\n", 558 board_id, IX_ID)); 559 goto out; 560 } 561 562 /* 563 * The shared RAM size and location of the EE16 is encoded into 564 * EEPROM location 6. The location of the first set bit tells us 565 * the memory address (0xc0000 + (0x4000 * FSB)), where FSB is the 566 * number of the first set bit. The zeroes are then shifted out, 567 * and the results is the memory size (1 = 16k, 3 = 32k, 7 = 48k, 568 * 0x0f = 64k). 569 * 570 * Examples: 571 * 0x3c -> 64k@0xc8000, 0x70 -> 48k@0xd0000, 0xc0 -> 32k@0xd8000 572 * 0x80 -> 16k@0xdc000. 573 * 574 * Side note: this comes from reading the old driver rather than 575 * from a more definitive source, so it could be out-of-whack 576 * with what the card can do... 577 */ 578 579 val = ix_read_eeprom(iot, ioh, 6) & 0xff; 580 for (pg = 0; pg < 8; pg++) { 581 if (val & 1) 582 break; 583 val >>= 1; 584 } 585 586 maddr = 0xc0000 + (pg * 0x4000); 587 588 switch (val) { 589 case 0x00: 590 maddr = 0; 591 msiz = 0; 592 break; 593 594 case 0x01: 595 msiz = 16 * 1024; 596 break; 597 598 case 0x03: 599 msiz = 32 * 1024; 600 break; 601 602 case 0x07: 603 msiz = 48 * 1024; 604 break; 605 606 case 0x0f: 607 msiz = 64 * 1024; 608 break; 609 610 default: 611 DPRINTF(("invalid memory size %02x\n", val)); 612 goto out; 613 } 614 615 if (ia->ia_iomem[0].ir_addr != ISA_UNKNOWN_IOMEM && 616 ia->ia_iomem[0].ir_addr != maddr) { 617 DPRINTF(( 618 "ix_match: memaddr of board @ 0x%x doesn't match config\n", 619 ia->ia_iobase)); 620 goto out; 621 } 622 623 if (ia->ia_iomem[0].ir_size != ISA_UNKNOWN_IOSIZ && 624 ia->ia_iomem[0].ir_size != msiz) { 625 DPRINTF(( 626 "ix_match: memsize of board @ 0x%x doesn't match config\n", 627 ia->ia_iobase)); 628 goto out; 629 } 630 631 /* need to put the 586 in RESET, and leave it */ 632 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_586); 633 634 /* read the eeprom and checksum it, should == IX_ID */ 635 for(i = 0; i < 0x40; i++) 636 checksum += ix_read_eeprom(iot, ioh, i); 637 638 if (checksum != IX_ID) { 639 DPRINTF(("checksum mismatch (got 0x%04x, expected 0x%04x\n", 640 checksum, IX_ID)); 641 goto out; 642 } 643 644 /* 645 * Only do the following bit if using memory-mapped access. For 646 * boards with no mapped memory, we use PIO. We also use PIO for 647 * boards with 16K of mapped memory, as those setups don't seem 648 * to work otherwise. 649 */ 650 if (msiz != 0 && msiz != 16384) { 651 /* Set board up with memory-mapping info */ 652 adjust = IX_MCTRL_FMCS16 | (pg & 0x3) << 2; 653 decode = ((1 << (ia->ia_iomem[0].ir_size / 16384)) - 1) << pg; 654 edecode = ((~decode >> 4) & 0xF0) | (decode >> 8); 655 656 bus_space_write_1(iot, ioh, IX_MEMDEC, decode & 0xFF); 657 bus_space_write_1(iot, ioh, IX_MCTRL, adjust); 658 bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); 659 660 /* XXX disable Exxx */ 661 bus_space_write_1(iot, ioh, IX_MECTRL, edecode); 662 } 663 664 /* 665 * Get the encoded interrupt number from the EEPROM, check it 666 * against the passed in IRQ. Issue a warning if they do not 667 * match, and fail the probe. If irq is 'ISA_UNKNOWN_IRQ' then we 668 * use the EEPROM irq, and continue. 669 */ 670 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 671 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 672 irq = irq_translate[irq_encoded]; 673 if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ && 674 irq != ia->ia_irq[0].ir_irq) { 675 DPRINTF(("board IRQ %d does not match config\n", irq)); 676 goto out; 677 } 678 679 /* disable the board interrupts */ 680 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded); 681 682 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 683 bart_config |= IX_BART_LOOPBACK; 684 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 685 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 686 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 687 688 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 689 delay(100); 690 691 rv = 1; 692 693 ia->ia_nio = 1; 694 ia->ia_io[0].ir_size = IX_IOSIZE; 695 696 ia->ia_niomem = 1; 697 ia->ia_iomem[0].ir_addr = maddr; 698 ia->ia_iomem[0].ir_size = msiz; 699 700 ia->ia_nirq = 1; 701 ia->ia_irq[0].ir_irq = irq; 702 703 DPRINTF(("ix_match: found board @ 0x%x\n", ia->ia_iobase)); 704 705 out: 706 bus_space_unmap(iot, ioh, IX_IOSIZE); 707 return (rv); 708 } 709 710 void 711 ix_attach(struct device *parent, struct device *self, void *aux) 712 { 713 struct ix_softc *isc = (void *)self; 714 struct ie_softc *sc = &isc->sc_ie; 715 struct isa_attach_args *ia = aux; 716 717 int media; 718 int i, memsize; 719 u_int8_t bart_config; 720 bus_space_tag_t iot; 721 u_int8_t bpat, bval; 722 u_int16_t wpat, wval; 723 bus_space_handle_t ioh, memh; 724 u_short irq_encoded; 725 u_int8_t ethaddr[ETHER_ADDR_LEN]; 726 727 iot = ia->ia_iot; 728 729 /* 730 * Shared memory access seems to fail on 16K mapped boards, so 731 * disable shared memory access if the board is in 16K mode. If 732 * no memory is mapped, we have no choice but to use PIO 733 */ 734 isc->use_pio = (ia->ia_iomem[0].ir_size <= (16 * 1024)); 735 736 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 737 ia->ia_io[0].ir_size, 0, &ioh) != 0) { 738 739 DPRINTF(("\n%s: can't map i/o space 0x%x-0x%x\n", 740 device_xname(&sc->sc_dev), ia->ia_[0].ir_addr, 741 ia->ia_io[0].ir_addr + ia->ia_io[0].ir_size - 1)); 742 return; 743 } 744 745 /* We map memory even if using PIO so something else doesn't grab it */ 746 if (ia->ia_iomem[0].ir_size) { 747 if (bus_space_map(ia->ia_memt, ia->ia_iomem[0].ir_addr, 748 ia->ia_iomem[0].ir_size, 0, &memh) != 0) { 749 DPRINTF(("\n%s: can't map iomem space 0x%x-0x%x\n", 750 device_xname(&sc->sc_dev), ia->ia_iomem[0].ir_addr, 751 ia->ia_iomem[0].ir_addr + ia->ia_iomem[0].ir_size - 1)); 752 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 753 return; 754 } 755 } 756 757 isc->sc_regt = iot; 758 isc->sc_regh = ioh; 759 760 /* 761 * Get the hardware ethernet address from the EEPROM and 762 * save it in the softc for use by the 586 setup code. 763 */ 764 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_HIGH); 765 ethaddr[1] = wval & 0xFF; 766 ethaddr[0] = wval >> 8; 767 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_MID); 768 ethaddr[3] = wval & 0xFF; 769 ethaddr[2] = wval >> 8; 770 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_LOW); 771 ethaddr[5] = wval & 0xFF; 772 ethaddr[4] = wval >> 8; 773 774 sc->hwinit = NULL; 775 sc->hwreset = ix_reset; 776 sc->chan_attn = ix_atten; 777 sc->intrhook = ix_intrhook; 778 779 sc->memcopyin = ix_copyin; 780 sc->memcopyout = ix_copyout; 781 782 /* If using PIO, make sure to setup single-byte read/write functions */ 783 if (isc->use_pio) { 784 sc->ie_bus_barrier = ix_bus_barrier; 785 } else { 786 sc->ie_bus_barrier = NULL; 787 } 788 789 sc->ie_bus_read16 = ix_read_16; 790 sc->ie_bus_write16 = ix_write_16; 791 sc->ie_bus_write24 = ix_write_24; 792 793 sc->do_xmitnopchain = 0; 794 795 sc->sc_mediachange = NULL; 796 sc->sc_mediastatus = ix_mediastatus; 797 798 if (isc->use_pio) { 799 sc->bt = iot; 800 sc->bh = ioh; 801 802 /* 803 * If using PIO, the memory size is bounded by on-card memory, 804 * not by how much is mapped into the memory-mapped region, so 805 * determine how much total memory we have to play with here. 806 */ 807 for(memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { 808 /* warm up shared memory, the zero it all out */ 809 ix_zeromem(sc, 0, 32); 810 ix_zeromem(sc, 0, memsize); 811 812 /* Reset write pointer to the start of RAM */ 813 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 814 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 815 BUS_SPACE_BARRIER_WRITE); 816 817 /* write test pattern */ 818 for(i = 0, wpat = 1; i < memsize; i += 2) { 819 bus_space_write_2(iot, ioh, IX_DATAPORT, wpat); 820 wpat += 3; 821 } 822 823 /* Flush all reads & writes to data port */ 824 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 825 BUS_SPACE_BARRIER_READ | 826 BUS_SPACE_BARRIER_WRITE); 827 828 /* Reset read pointer to beginning of card RAM */ 829 bus_space_write_2(iot, ioh, IX_READPTR, 0); 830 bus_space_barrier(iot, ioh, IX_READPTR, 2, 831 BUS_SPACE_BARRIER_WRITE); 832 833 /* read and verify test pattern */ 834 for(i = 0, wpat = 1; i < memsize; i += 2) { 835 wval = bus_space_read_2(iot, ioh, IX_DATAPORT); 836 837 if (wval != wpat) 838 break; 839 840 wpat += 3; 841 } 842 843 /* If we failed, try next size down */ 844 if (i != memsize) 845 continue; 846 847 /* Now try it all with byte reads/writes */ 848 ix_zeromem(sc, 0, 32); 849 ix_zeromem(sc, 0, memsize); 850 851 /* Reset write pointer to start of card RAM */ 852 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 853 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 854 BUS_SPACE_BARRIER_WRITE); 855 856 /* write out test pattern */ 857 for(i = 0, bpat = 1; i < memsize; i++) { 858 bus_space_write_1(iot, ioh, IX_DATAPORT, bpat); 859 bpat += 3; 860 } 861 862 /* Flush all reads & writes to data port */ 863 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 864 BUS_SPACE_BARRIER_READ | 865 BUS_SPACE_BARRIER_WRITE); 866 867 /* Reset read pointer to beginning of card RAM */ 868 bus_space_write_2(iot, ioh, IX_READPTR, 0); 869 bus_space_barrier(iot, ioh, IX_READPTR, 2, 870 BUS_SPACE_BARRIER_WRITE); 871 872 /* read and verify test pattern */ 873 for(i = 0, bpat = 1; i < memsize; i++) { 874 bval = bus_space_read_1(iot, ioh, IX_DATAPORT); 875 876 if (bval != bpat) 877 bpat += 3; 878 } 879 880 /* If we got through all of memory, we're done! */ 881 if (i == memsize) 882 break; 883 } 884 885 /* Memory tests failed, punt... */ 886 if (memsize == 0) { 887 DPRINTF(("\n%s: can't determine size of on-card RAM\n", 888 device_xname(&sc->sc_dev))); 889 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 890 return; 891 } 892 893 sc->bt = iot; 894 sc->bh = ioh; 895 896 sc->sc_msize = memsize; 897 sc->sc_maddr = (void*) 0; 898 } else { 899 sc->bt = ia->ia_memt; 900 sc->bh = memh; 901 902 sc->sc_msize = ia->ia_iomem[0].ir_size; 903 sc->sc_maddr = (void *)memh; 904 } 905 906 /* Map i/o space. */ 907 sc->sc_iobase = (char *)sc->sc_maddr + sc->sc_msize - (1 << 24); 908 909 /* set up pointers to important on-card control structures */ 910 sc->iscp = 0; 911 sc->scb = IE_ISCP_SZ; 912 sc->scp = sc->sc_msize + IE_SCP_ADDR - (1 << 24); 913 914 sc->buf_area = sc->scb + IE_SCB_SZ; 915 sc->buf_area_sz = sc->sc_msize - IE_ISCP_SZ - IE_SCB_SZ - IE_SCP_SZ; 916 917 /* zero card memory */ 918 ix_zeromem(sc, 0, 32); 919 ix_zeromem(sc, 0, sc->sc_msize); 920 921 /* set card to 16-bit bus mode */ 922 if (isc->use_pio) { 923 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, 924 IE_SCP_BUS_USE((u_long)sc->scp)); 925 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 926 BUS_SPACE_BARRIER_WRITE); 927 928 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 929 IE_SYSBUS_16BIT); 930 } else { 931 bus_space_write_1(sc->bt, sc->bh, 932 IE_SCP_BUS_USE((u_long)sc->scp), 933 IE_SYSBUS_16BIT); 934 } 935 936 /* set up pointers to key structures */ 937 ix_write_24(sc, IE_SCP_ISCP((u_long)sc->scp), (u_long) sc->iscp); 938 ix_write_16(sc, IE_ISCP_SCB((u_long)sc->iscp), (u_long) sc->scb); 939 ix_write_24(sc, IE_ISCP_BASE((u_long)sc->iscp), (u_long) sc->iscp); 940 941 /* flush setup of pointers, check if chip answers */ 942 if (isc->use_pio) { 943 bus_space_barrier(sc->bt, sc->bh, 0, IX_IOSIZE, 944 BUS_SPACE_BARRIER_WRITE); 945 } else { 946 bus_space_barrier(sc->bt, sc->bh, 0, sc->sc_msize, 947 BUS_SPACE_BARRIER_WRITE); 948 } 949 950 if (!i82586_proberam(sc)) { 951 DPRINTF(("\n%s: Can't talk to i82586!\n", 952 device_xname(&sc->sc_dev))); 953 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 954 955 if (ia->ia_iomem[0].ir_size) 956 bus_space_unmap(ia->ia_memt, memh, ia->ia_iomem[0].ir_size); 957 return; 958 } 959 960 /* Figure out which media is being used... */ 961 if (ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1) & 962 IX_EEPROM_MEDIA_EXT) { 963 if (ix_read_eeprom(iot, ioh, IX_EEPROM_MEDIA) & 964 IX_EEPROM_MEDIA_TP) 965 media = IFM_ETHER | IFM_10_T; 966 else 967 media = IFM_ETHER | IFM_10_2; 968 } else 969 media = IFM_ETHER | IFM_10_5; 970 971 /* Take the card out of lookback */ 972 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 973 bart_config &= ~IX_BART_LOOPBACK; 974 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 975 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 976 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 977 978 irq_encoded = ix_read_eeprom(iot, ioh, 979 IX_EEPROM_CONFIG1); 980 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 981 982 /* Enable interrupts */ 983 bus_space_write_1(iot, ioh, IX_IRQ, 984 irq_encoded | IX_IRQ_ENABLE); 985 986 /* Flush all writes to registers */ 987 bus_space_barrier(iot, ioh, 0, ia->ia_io[0].ir_size, 988 BUS_SPACE_BARRIER_WRITE); 989 990 isc->irq_encoded = irq_encoded; 991 992 i82586_attach(sc, "EtherExpress/16", ethaddr, 993 ix_media, NIX_MEDIA, media); 994 995 if (isc->use_pio) 996 aprint_error_dev(&sc->sc_dev, "unsupported memory config, using PIO to access %d bytes of memory\n", sc->sc_msize); 997 998 isc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 999 IST_EDGE, IPL_NET, i82586_intr, sc); 1000 if (isc->sc_ih == NULL) { 1001 DPRINTF(("\n%s: can't establish interrupt\n", 1002 device_xname(&sc->sc_dev))); 1003 } 1004 } 1005 1006 CFATTACH_DECL(ix, sizeof(struct ix_softc), 1007 ix_match, ix_attach, NULL, NULL); 1008
Indexes created Thu Oct 02 01:09:59 GMT 2025