if_ix.c revision 1.8
1 /* $NetBSD: if_ix.c,v 1.8 2001/01/22 22:28:46 bjh21 Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Rafal K. Boni. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/protosw.h> 45 #include <sys/socket.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_types.h> 50 #include <net/if_media.h> 51 #include <net/if_ether.h> 52 53 #include <machine/cpu.h> 54 #include <machine/bus.h> 55 #include <machine/intr.h> 56 57 #include <dev/isa/isareg.h> 58 #include <dev/isa/isavar.h> 59 60 #include <dev/ic/i82586reg.h> 61 #include <dev/ic/i82586var.h> 62 #include <dev/isa/if_ixreg.h> 63 64 #ifdef IX_DEBUG 65 #define DPRINTF(x) printf x 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 int ix_media[] = { 71 IFM_ETHER | IFM_10_5, 72 IFM_ETHER | IFM_10_2, 73 IFM_ETHER | IFM_10_T, 74 }; 75 #define NIX_MEDIA (sizeof(ix_media) / sizeof(ix_media[0])) 76 77 struct ix_softc { 78 struct ie_softc sc_ie; 79 80 bus_space_tag_t sc_regt; /* space tag for registers */ 81 bus_space_handle_t sc_regh; /* space handle for registers */ 82 83 u_int8_t use_pio; /* use PIO rather than shared mem */ 84 u_int16_t irq_encoded; /* encoded IRQ */ 85 void *sc_ih; /* interrupt handle */ 86 }; 87 88 static void ix_reset __P((struct ie_softc *, int)); 89 static void ix_atten __P((struct ie_softc *)); 90 static int ix_intrhook __P((struct ie_softc *, int)); 91 92 static void ix_copyin __P((struct ie_softc *, void *, int, size_t)); 93 static void ix_copyout __P((struct ie_softc *, const void *, int, size_t)); 94 95 static void ix_bus_barrier __P((struct ie_softc *, int, int, int)); 96 97 static u_int16_t ix_read_16 __P((struct ie_softc *, int)); 98 static void ix_write_16 __P((struct ie_softc *, int, u_int16_t)); 99 static void ix_write_24 __P((struct ie_softc *, int, int)); 100 static void ix_zeromem __P((struct ie_softc *, int, int)); 101 102 static void ix_mediastatus __P((struct ie_softc *, struct ifmediareq *)); 103 104 static u_int16_t ix_read_eeprom __P((bus_space_tag_t, bus_space_handle_t, int)); 105 static void ix_eeprom_outbits __P((bus_space_tag_t, bus_space_handle_t, int, int)); 106 static int ix_eeprom_inbits __P((bus_space_tag_t, bus_space_handle_t)); 107 static void ix_eeprom_clock __P((bus_space_tag_t, bus_space_handle_t, int)); 108 109 int ix_match __P((struct device *, struct cfdata *, void *)); 110 void ix_attach __P((struct device *, struct device *, void *)); 111 112 /* 113 * EtherExpress/16 support routines 114 */ 115 static void 116 ix_reset(sc, why) 117 struct ie_softc *sc; 118 int why; 119 { 120 struct ix_softc* isc = (struct ix_softc *) sc; 121 122 switch (why) { 123 case CHIP_PROBE: 124 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 125 IX_RESET_586); 126 delay(100); 127 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 0); 128 delay(100); 129 break; 130 131 case CARD_RESET: 132 break; 133 } 134 } 135 136 static void 137 ix_atten(sc) 138 struct ie_softc *sc; 139 { 140 struct ix_softc* isc = (struct ix_softc *) sc; 141 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ATTN, 0); 142 } 143 144 static u_int16_t 145 ix_read_eeprom(iot, ioh, location) 146 bus_space_tag_t iot; 147 bus_space_handle_t ioh; 148 int location; 149 { 150 int ectrl, edata; 151 152 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 153 ectrl &= IX_ECTRL_MASK; 154 ectrl |= IX_ECTRL_EECS; 155 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 156 157 ix_eeprom_outbits(iot, ioh, IX_EEPROM_READ, IX_EEPROM_OPSIZE1); 158 ix_eeprom_outbits(iot, ioh, location, IX_EEPROM_ADDR_SIZE); 159 edata = ix_eeprom_inbits(iot, ioh); 160 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 161 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EEDI | IX_ECTRL_EECS); 162 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 163 ix_eeprom_clock(iot, ioh, 1); 164 ix_eeprom_clock(iot, ioh, 0); 165 return (edata); 166 } 167 168 static void 169 ix_eeprom_outbits(iot, ioh, edata, count) 170 bus_space_tag_t iot; 171 bus_space_handle_t ioh; 172 int edata, count; 173 { 174 int ectrl, i; 175 176 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 177 ectrl &= ~IX_RESET_ASIC; 178 for (i = count - 1; i >= 0; i--) { 179 ectrl &= ~IX_ECTRL_EEDI; 180 if (edata & (1 << i)) { 181 ectrl |= IX_ECTRL_EEDI; 182 } 183 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 184 delay(1); /* eeprom data must be setup for 0.4 uSec */ 185 ix_eeprom_clock(iot, ioh, 1); 186 ix_eeprom_clock(iot, ioh, 0); 187 } 188 ectrl &= ~IX_ECTRL_EEDI; 189 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 190 delay(1); /* eeprom data must be held for 0.4 uSec */ 191 } 192 193 static int 194 ix_eeprom_inbits(iot, ioh) 195 bus_space_tag_t iot; 196 bus_space_handle_t ioh; 197 { 198 int ectrl, edata, i; 199 200 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 201 ectrl &= ~IX_RESET_ASIC; 202 for (edata = 0, i = 0; i < 16; i++) { 203 edata = edata << 1; 204 ix_eeprom_clock(iot, ioh, 1); 205 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 206 if (ectrl & IX_ECTRL_EEDO) { 207 edata |= 1; 208 } 209 ix_eeprom_clock(iot, ioh, 0); 210 } 211 return (edata); 212 } 213 214 static void 215 ix_eeprom_clock(iot, ioh, state) 216 bus_space_tag_t iot; 217 bus_space_handle_t ioh; 218 int state; 219 { 220 int ectrl; 221 222 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 223 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EESK); 224 if (state) { 225 ectrl |= IX_ECTRL_EESK; 226 } 227 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 228 delay(9); /* EESK must be stable for 8.38 uSec */ 229 } 230 231 static int 232 ix_intrhook(sc, where) 233 struct ie_softc *sc; 234 int where; 235 { 236 struct ix_softc* isc = (struct ix_softc *) sc; 237 238 switch (where) { 239 case INTR_ENTER: 240 /* entering ISR: disable card interrupts */ 241 bus_space_write_1(isc->sc_regt, isc->sc_regh, 242 IX_IRQ, isc->irq_encoded); 243 break; 244 245 case INTR_EXIT: 246 /* exiting ISR: re-enable card interrupts */ 247 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_IRQ, 248 isc->irq_encoded | IX_IRQ_ENABLE); 249 break; 250 } 251 252 return 1; 253 } 254 255 256 static void 257 ix_copyin (sc, dst, offset, size) 258 struct ie_softc *sc; 259 void *dst; 260 int offset; 261 size_t size; 262 { 263 int i, dribble; 264 u_int8_t* bptr = dst; 265 u_int16_t* wptr = dst; 266 struct ix_softc* isc = (struct ix_softc *) sc; 267 268 if (isc->use_pio) { 269 /* Reset read pointer to the specified offset */ 270 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 271 BUS_SPACE_BARRIER_READ); 272 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 273 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 274 BUS_SPACE_BARRIER_WRITE); 275 } else { 276 bus_space_barrier(sc->bt, sc->bh, offset, size, 277 BUS_SPACE_BARRIER_READ); 278 } 279 280 if (offset % 2) { 281 if (isc->use_pio) 282 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 283 else 284 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 285 offset++; bptr++; size--; 286 } 287 288 dribble = size % 2; 289 wptr = (u_int16_t*) bptr; 290 291 if (isc->use_pio) { 292 for(i = 0; i < size / 2; i++) { 293 *wptr = bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 294 wptr++; 295 } 296 } else { 297 bus_space_read_region_2(sc->bt, sc->bh, offset, 298 (u_int16_t *) bptr, size / 2); 299 } 300 301 if (dribble) { 302 bptr += size - 1; 303 offset += size - 1; 304 305 if (isc->use_pio) 306 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 307 else 308 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 309 } 310 } 311 312 static void 313 ix_copyout (sc, src, offset, size) 314 struct ie_softc *sc; 315 const void *src; 316 int offset; 317 size_t size; 318 { 319 int i, dribble; 320 int osize = size; 321 int ooffset = offset; 322 const u_int8_t* bptr = src; 323 const u_int16_t* wptr = src; 324 struct ix_softc* isc = (struct ix_softc *) sc; 325 326 if (isc->use_pio) { 327 /* Reset write pointer to the specified offset */ 328 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 329 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 330 BUS_SPACE_BARRIER_WRITE); 331 } 332 333 if (offset % 2) { 334 if (isc->use_pio) 335 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 336 else 337 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 338 offset++; bptr++; size--; 339 } 340 341 dribble = size % 2; 342 wptr = (u_int16_t*) bptr; 343 344 if (isc->use_pio) { 345 for(i = 0; i < size / 2; i++) { 346 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, *wptr); 347 wptr++; 348 } 349 } else { 350 bus_space_write_region_2(sc->bt, sc->bh, offset, 351 (u_int16_t *)bptr, size / 2); 352 } 353 354 if (dribble) { 355 bptr += size - 1; 356 offset += size - 1; 357 358 if (isc->use_pio) 359 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 360 else 361 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 362 } 363 364 if (isc->use_pio) 365 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 366 BUS_SPACE_BARRIER_WRITE); 367 else 368 bus_space_barrier(sc->bt, sc->bh, ooffset, osize, 369 BUS_SPACE_BARRIER_WRITE); 370 } 371 372 static void 373 ix_bus_barrier(sc, offset, length, flags) 374 struct ie_softc *sc; 375 int offset, length, flags; 376 { 377 struct ix_softc* isc = (struct ix_softc *) sc; 378 379 if (isc->use_pio) 380 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, flags); 381 else 382 bus_space_barrier(sc->bt, sc->bh, offset, length, flags); 383 } 384 385 static u_int16_t 386 ix_read_16 (sc, offset) 387 struct ie_softc *sc; 388 int offset; 389 { 390 struct ix_softc* isc = (struct ix_softc *) sc; 391 392 if (isc->use_pio) { 393 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 394 BUS_SPACE_BARRIER_READ); 395 396 /* Reset read pointer to the specified offset */ 397 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 398 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 399 BUS_SPACE_BARRIER_WRITE); 400 401 return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 402 } else { 403 bus_space_barrier(sc->bt, sc->bh, offset, 2, 404 BUS_SPACE_BARRIER_READ); 405 return bus_space_read_2(sc->bt, sc->bh, offset); 406 } 407 } 408 409 static void 410 ix_write_16 (sc, offset, value) 411 struct ie_softc *sc; 412 int offset; 413 u_int16_t value; 414 { 415 struct ix_softc* isc = (struct ix_softc *) sc; 416 417 if (isc->use_pio) { 418 /* Reset write pointer to the specified offset */ 419 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 420 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 421 BUS_SPACE_BARRIER_WRITE); 422 423 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); 424 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 425 BUS_SPACE_BARRIER_WRITE); 426 } else { 427 bus_space_write_2(sc->bt, sc->bh, offset, value); 428 bus_space_barrier(sc->bt, sc->bh, offset, 2, 429 BUS_SPACE_BARRIER_WRITE); 430 } 431 } 432 433 static void 434 ix_write_24 (sc, offset, addr) 435 struct ie_softc *sc; 436 int offset, addr; 437 { 438 char* ptr; 439 struct ix_softc* isc = (struct ix_softc *) sc; 440 int val = addr + (u_long) sc->sc_maddr - (u_long) sc->sc_iobase; 441 442 if (isc->use_pio) { 443 /* Reset write pointer to the specified offset */ 444 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 445 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 446 BUS_SPACE_BARRIER_WRITE); 447 448 ptr = (char*) &val; 449 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 450 *((u_int16_t *)ptr)); 451 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 452 *((u_int16_t *)(ptr + 2))); 453 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 454 BUS_SPACE_BARRIER_WRITE); 455 } else { 456 bus_space_write_4(sc->bt, sc->bh, offset, val); 457 bus_space_barrier(sc->bt, sc->bh, offset, 4, 458 BUS_SPACE_BARRIER_WRITE); 459 } 460 } 461 462 static void 463 ix_zeromem(sc, offset, count) 464 struct ie_softc *sc; 465 int offset, count; 466 { 467 int i; 468 int dribble; 469 struct ix_softc* isc = (struct ix_softc *) sc; 470 471 if (isc->use_pio) { 472 /* Reset write pointer to the specified offset */ 473 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 474 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 475 BUS_SPACE_BARRIER_WRITE); 476 477 if (offset % 2) { 478 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 479 count--; 480 } 481 482 dribble = count % 2; 483 for(i = 0; i < count / 2; i++) 484 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 0); 485 486 if (dribble) 487 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 488 489 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 490 BUS_SPACE_BARRIER_WRITE); 491 } else { 492 bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); 493 bus_space_barrier(sc->bt, sc->bh, offset, count, 494 BUS_SPACE_BARRIER_WRITE); 495 } 496 } 497 498 static void 499 ix_mediastatus(sc, ifmr) 500 struct ie_softc *sc; 501 struct ifmediareq *ifmr; 502 { 503 struct ifmedia *ifm = &sc->sc_media; 504 505 /* 506 * The currently selected media is always the active media. 507 */ 508 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 509 } 510 511 int 512 ix_match(parent, cf, aux) 513 struct device *parent; 514 struct cfdata *cf; 515 void *aux; 516 { 517 int i; 518 int rv = 0; 519 bus_addr_t maddr; 520 bus_size_t msize; 521 u_short checksum = 0; 522 bus_space_handle_t ioh; 523 bus_space_tag_t iot; 524 u_int8_t val, bart_config; 525 u_short pg, adjust, decode, edecode; 526 u_short board_id, id_var1, id_var2, irq, irq_encoded; 527 struct isa_attach_args * const ia = aux; 528 short irq_translate[] = {0, 0x09, 0x03, 0x04, 0x05, 0x0a, 0x0b, 0}; 529 530 iot = ia->ia_iot; 531 532 if (bus_space_map(iot, ia->ia_iobase, 533 IX_IOSIZE, 0, &ioh) != 0) { 534 DPRINTF(("Can't map io space at 0x%x\n", ia->ia_iobase)); 535 return (0); 536 } 537 538 /* XXX: reset any ee16 at the current iobase */ 539 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_ASIC); 540 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 541 delay(240); 542 543 /* now look for ee16. */ 544 board_id = id_var1 = id_var2 = 0; 545 for (i = 0; i < 4 ; i++) { 546 id_var1 = bus_space_read_1(iot, ioh, IX_ID_PORT); 547 id_var2 = ((id_var1 & 0x03) << 2); 548 board_id |= (( id_var1 >> 4) << id_var2); 549 } 550 551 if (board_id != IX_ID) { 552 DPRINTF(("BART ID mismatch (got 0x%04x, expected 0x%04x)\n", 553 board_id, IX_ID)); 554 goto out; 555 } 556 557 /* 558 * The shared RAM size and location of the EE16 is encoded into 559 * EEPROM location 6. The location of the first set bit tells us 560 * the memory address (0xc0000 + (0x4000 * FSB)), where FSB is the 561 * number of the first set bit. The zeroes are then shifted out, 562 * and the results is the memory size (1 = 16k, 3 = 32k, 7 = 48k, 563 * 0x0f = 64k). 564 * 565 * Examples: 566 * 0x3c -> 64k@0xc8000, 0x70 -> 48k@0xd0000, 0xc0 -> 32k@0xd8000 567 * 0x80 -> 16k@0xdc000. 568 * 569 * Side note: this comes from reading the old driver rather than 570 * from a more definitive source, so it could be out-of-whack 571 * with what the card can do... 572 */ 573 574 val = ix_read_eeprom(iot, ioh, 6) & 0xff; 575 for(pg = 0; pg < 8; pg++) { 576 if (val & 1) 577 break; 578 val = val >> 1; 579 } 580 581 if (pg == 8) { 582 DPRINTF(("Invalid or unsupported memory config\n")); 583 goto out; 584 } 585 586 maddr = 0xc0000 + (pg * 0x4000); 587 588 switch (val) { 589 case 0x00: 590 msize = 0; 591 break; 592 593 case 0x01: 594 msize = 16 * 1024; 595 break; 596 597 case 0x03: 598 msize = 32 * 1024; 599 break; 600 601 case 0x07: 602 msize = 48 * 1024; 603 break; 604 605 case 0x0f: 606 msize = 64 * 1024; 607 break; 608 609 default: 610 DPRINTF(("invalid memory size %02x\n", val)); 611 goto out; 612 } 613 614 if (ia->ia_maddr == ISACF_IOMEM_DEFAULT) 615 ia->ia_maddr = maddr; 616 else if (ia->ia_maddr != maddr) { 617 DPRINTF(( 618 "ix_match: memaddr of board @ 0x%x doesn't match config\n", 619 ia->ia_iobase)); 620 goto out; 621 } 622 623 if (ia->ia_msize == ISACF_IOSIZ_DEFAULT) 624 ia->ia_msize = msize; 625 else if (ia->ia_msize != msize) { 626 DPRINTF(( 627 "ix_match: memsize of board @ 0x%x doesn't match config\n", 628 ia->ia_iobase)); 629 goto out; 630 } 631 632 /* need to put the 586 in RESET, and leave it */ 633 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_586); 634 635 /* read the eeprom and checksum it, should == IX_ID */ 636 for(i = 0; i < 0x40; i++) 637 checksum += ix_read_eeprom(iot, ioh, i); 638 639 if (checksum != IX_ID) { 640 DPRINTF(("checksum mismatch (got 0x%04x, expected 0x%04x\n", 641 checksum, IX_ID)); 642 goto out; 643 } 644 645 /* 646 * Only do the following bit if using memory-mapped access. For 647 * boards with no mapped memory, we use PIO. We also use PIO for 648 * boards with 16K of mapped memory, as those setups don't seem 649 * to work otherwise. 650 */ 651 if (msize != 0 && msize != 16384) { 652 /* Set board up with memory-mapping info */ 653 adjust = IX_MCTRL_FMCS16 | (pg & 0x3) << 2; 654 decode = ((1 << (ia->ia_msize / 16384)) - 1) << pg; 655 edecode = ((~decode >> 4) & 0xF0) | (decode >> 8); 656 657 bus_space_write_1(iot, ioh, IX_MEMDEC, decode & 0xFF); 658 bus_space_write_1(iot, ioh, IX_MCTRL, adjust); 659 bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); 660 661 /* XXX disable Exxx */ 662 bus_space_write_1(iot, ioh, IX_MECTRL, edecode); 663 } 664 665 /* 666 * Get the encoded interrupt number from the EEPROM, check it 667 * against the passed in IRQ. Issue a warning if they do not 668 * match, and fail the probe. If irq is 'IRQUNK' then we 669 * use the EEPROM irq, and continue. 670 */ 671 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 672 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 673 irq = irq_translate[irq_encoded]; 674 if (ia->ia_irq == ISACF_IRQ_DEFAULT) 675 ia->ia_irq = irq; 676 else if (irq != ia->ia_irq) { 677 DPRINTF(("board IRQ %d does not match config\n", irq)); 678 goto out; 679 } 680 681 /* disable the board interrupts */ 682 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded); 683 684 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 685 bart_config |= IX_BART_LOOPBACK; 686 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 687 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 688 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 689 690 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 691 delay(100); 692 693 rv = 1; 694 ia->ia_iosize = IX_IOSIZE; 695 DPRINTF(("ix_match: found board @ 0x%x\n", ia->ia_iobase)); 696 697 out: 698 bus_space_unmap(iot, ioh, IX_IOSIZE); 699 return (rv); 700 } 701 702 void 703 ix_attach(parent, self, aux) 704 struct device *parent; 705 struct device *self; 706 void *aux; 707 { 708 struct ix_softc *isc = (void *)self; 709 struct ie_softc *sc = &isc->sc_ie; 710 struct isa_attach_args *ia = aux; 711 712 int media; 713 int i, memsize; 714 u_int8_t bart_config; 715 bus_space_tag_t iot; 716 u_int8_t bpat, bval; 717 u_int16_t wpat, wval; 718 bus_space_handle_t ioh, memh; 719 u_short irq_encoded; 720 u_int8_t ethaddr[ETHER_ADDR_LEN]; 721 722 iot = ia->ia_iot; 723 724 /* 725 * Shared memory access seems to fail on 16K mapped boards, so 726 * disable shared memory access if the board is in 16K mode. If 727 * no memory is mapped, we have no choice but to use PIO 728 */ 729 isc->use_pio = (ia->ia_msize <= (16 * 1024)); 730 731 if (bus_space_map(iot, ia->ia_iobase, 732 ia->ia_iosize, 0, &ioh) != 0) { 733 734 DPRINTF(("\n%s: can't map i/o space 0x%x-0x%x\n", 735 sc->sc_dev.dv_xname, ia->ia_iobase, 736 ia->ia_iobase + ia->ia_iosize - 1)); 737 return; 738 } 739 740 /* We map memory even if using PIO so something else doesn't grab it */ 741 if (ia->ia_msize) { 742 if (bus_space_map(ia->ia_memt, ia->ia_maddr, 743 ia->ia_msize, 0, &memh) != 0) { 744 DPRINTF(("\n%s: can't map iomem space 0x%x-0x%x\n", 745 sc->sc_dev.dv_xname, ia->ia_maddr, 746 ia->ia_maddr + ia->ia_msize - 1)); 747 bus_space_unmap(iot, ioh, ia->ia_iosize); 748 return; 749 } 750 } 751 752 isc->sc_regt = iot; 753 isc->sc_regh = ioh; 754 755 /* 756 * Get the hardware ethernet address from the EEPROM and 757 * save it in the softc for use by the 586 setup code. 758 */ 759 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_HIGH); 760 ethaddr[1] = wval & 0xFF; 761 ethaddr[0] = wval >> 8; 762 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_MID); 763 ethaddr[3] = wval & 0xFF; 764 ethaddr[2] = wval >> 8; 765 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_LOW); 766 ethaddr[5] = wval & 0xFF; 767 ethaddr[4] = wval >> 8; 768 769 sc->hwinit = NULL; 770 sc->hwreset = ix_reset; 771 sc->chan_attn = ix_atten; 772 sc->intrhook = ix_intrhook; 773 774 sc->memcopyin = ix_copyin; 775 sc->memcopyout = ix_copyout; 776 777 /* If using PIO, make sure to setup single-byte read/write functions */ 778 if (isc->use_pio) { 779 sc->ie_bus_barrier = ix_bus_barrier; 780 } else { 781 sc->ie_bus_barrier = NULL; 782 } 783 784 sc->ie_bus_read16 = ix_read_16; 785 sc->ie_bus_write16 = ix_write_16; 786 sc->ie_bus_write24 = ix_write_24; 787 788 sc->do_xmitnopchain = 0; 789 790 sc->sc_mediachange = NULL; 791 sc->sc_mediastatus = ix_mediastatus; 792 793 if (isc->use_pio) { 794 sc->bt = iot; 795 sc->bh = ioh; 796 797 /* 798 * If using PIO, the memory size is bounded by on-card memory, 799 * not by how much is mapped into the memory-mapped region, so 800 * determine how much total memory we have to play with here. 801 */ 802 for(memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { 803 /* warm up shared memory, the zero it all out */ 804 ix_zeromem(sc, 0, 32); 805 ix_zeromem(sc, 0, memsize); 806 807 /* Reset write pointer to the start of RAM */ 808 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 809 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 810 BUS_SPACE_BARRIER_WRITE); 811 812 /* write test pattern */ 813 for(i = 0; i < memsize; i += 2) { 814 bus_space_write_2(iot, ioh, IX_DATAPORT, wpat); 815 wpat += 3; 816 } 817 818 /* Flush all reads & writes to data port */ 819 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 820 BUS_SPACE_BARRIER_READ | 821 BUS_SPACE_BARRIER_WRITE); 822 823 /* Reset read pointer to beginning of card RAM */ 824 bus_space_write_2(iot, ioh, IX_READPTR, 0); 825 bus_space_barrier(iot, ioh, IX_READPTR, 2, 826 BUS_SPACE_BARRIER_WRITE); 827 828 /* read and verify test pattern */ 829 for(i = 0, wpat = 1; i < memsize; i += 2) { 830 wval = bus_space_read_2(iot, ioh, IX_DATAPORT); 831 832 if (wval != wpat) 833 break; 834 835 wpat += 3; 836 } 837 838 /* If we failed, try next size down */ 839 if (i != memsize) 840 continue; 841 842 /* Now try it all with byte reads/writes */ 843 ix_zeromem(sc, 0, 32); 844 ix_zeromem(sc, 0, memsize); 845 846 /* Reset write pointer to start of card RAM */ 847 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 848 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 849 BUS_SPACE_BARRIER_WRITE); 850 851 /* write out test pattern */ 852 for(i = 0, bpat = 1; i < memsize; i++) { 853 bus_space_write_1(iot, ioh, IX_DATAPORT, bpat); 854 bpat += 3; 855 } 856 857 /* Flush all reads & writes to data port */ 858 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 859 BUS_SPACE_BARRIER_READ | 860 BUS_SPACE_BARRIER_WRITE); 861 862 /* Reset read pointer to beginning of card RAM */ 863 bus_space_write_2(iot, ioh, IX_READPTR, 0); 864 bus_space_barrier(iot, ioh, IX_READPTR, 2, 865 BUS_SPACE_BARRIER_WRITE); 866 867 /* read and verify test pattern */ 868 for(i = 0, bpat = 1; i < memsize; i++) { 869 bval = bus_space_read_1(iot, ioh, IX_DATAPORT); 870 871 if (bval != bpat) 872 bpat += 3; 873 } 874 875 /* If we got through all of memory, we're done! */ 876 if (i == memsize) 877 break; 878 } 879 880 /* Memory tests failed, punt... */ 881 if (memsize == 0) { 882 DPRINTF(("\n%s: can't determine size of on-card RAM\n", 883 sc->sc_dev.dv_xname)); 884 bus_space_unmap(iot, ioh, ia->ia_iosize); 885 return; 886 } 887 888 sc->bt = iot; 889 sc->bh = ioh; 890 891 sc->sc_msize = memsize; 892 sc->sc_maddr = (void*) 0; 893 } else { 894 sc->bt = ia->ia_memt; 895 sc->bh = memh; 896 897 sc->sc_msize = ia->ia_msize; 898 sc->sc_maddr = (void *)memh; 899 } 900 901 /* Map i/o space. */ 902 sc->sc_iobase = (char *)sc->sc_maddr + sc->sc_msize - (1 << 24); 903 904 /* set up pointers to important on-card control structures */ 905 sc->iscp = 0; 906 sc->scb = IE_ISCP_SZ; 907 sc->scp = sc->sc_msize + IE_SCP_ADDR - (1 << 24); 908 909 sc->buf_area = sc->scb + IE_SCB_SZ; 910 sc->buf_area_sz = sc->sc_msize - IE_ISCP_SZ - IE_SCB_SZ - IE_SCP_SZ; 911 912 /* zero card memory */ 913 ix_zeromem(sc, 0, 32); 914 ix_zeromem(sc, 0, sc->sc_msize); 915 916 /* set card to 16-bit bus mode */ 917 if (isc->use_pio) { 918 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, 919 IE_SCP_BUS_USE((u_long)sc->scp)); 920 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 921 BUS_SPACE_BARRIER_WRITE); 922 923 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 924 } else { 925 bus_space_write_1(sc->bt, sc->bh, 926 IE_SCP_BUS_USE((u_long)sc->scp), 0); 927 } 928 929 /* set up pointers to key structures */ 930 ix_write_24(sc, IE_SCP_ISCP((u_long)sc->scp), (u_long) sc->iscp); 931 ix_write_16(sc, IE_ISCP_SCB((u_long)sc->iscp), (u_long) sc->scb); 932 ix_write_24(sc, IE_ISCP_BASE((u_long)sc->iscp), (u_long) sc->iscp); 933 934 /* flush setup of pointers, check if chip answers */ 935 if (isc->use_pio) { 936 bus_space_barrier(sc->bt, sc->bh, 0, IX_IOSIZE, 937 BUS_SPACE_BARRIER_WRITE); 938 } else { 939 bus_space_barrier(sc->bt, sc->bh, 0, sc->sc_msize, 940 BUS_SPACE_BARRIER_WRITE); 941 } 942 943 if (!i82586_proberam(sc)) { 944 DPRINTF(("\n%s: Can't talk to i82586!\n", 945 sc->sc_dev.dv_xname)); 946 bus_space_unmap(iot, ioh, ia->ia_iosize); 947 948 if (ia->ia_msize) 949 bus_space_unmap(ia->ia_memt, memh, ia->ia_msize); 950 return; 951 } 952 953 /* Figure out which media is being used... */ 954 if (ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1) & 955 IX_EEPROM_MEDIA_EXT) { 956 if (ix_read_eeprom(iot, ioh, IX_EEPROM_MEDIA) & 957 IX_EEPROM_MEDIA_TP) 958 media = IFM_ETHER | IFM_10_T; 959 else 960 media = IFM_ETHER | IFM_10_2; 961 } else 962 media = IFM_ETHER | IFM_10_5; 963 964 /* Take the card out of lookback */ 965 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 966 bart_config &= ~IX_BART_LOOPBACK; 967 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 968 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 969 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 970 971 irq_encoded = ix_read_eeprom(iot, ioh, 972 IX_EEPROM_CONFIG1); 973 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 974 975 /* Enable interrupts */ 976 bus_space_write_1(iot, ioh, IX_IRQ, 977 irq_encoded | IX_IRQ_ENABLE); 978 979 /* Flush all writes to registers */ 980 bus_space_barrier(iot, ioh, 0, ia->ia_iosize, BUS_SPACE_BARRIER_WRITE); 981 982 isc->irq_encoded = irq_encoded; 983 984 i82586_attach(sc, "EtherExpress/16", ethaddr, 985 ix_media, NIX_MEDIA, media); 986 987 if (isc->use_pio) 988 printf("%s: unsupported memory config, using PIO to access %d bytes of memory\n", sc->sc_dev.dv_xname, sc->sc_msize); 989 990 isc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 991 IPL_NET, i82586_intr, sc); 992 if (isc->sc_ih == NULL) 993 DPRINTF(("\n%s: can't establish interrupt\n", 994 sc->sc_dev.dv_xname)); 995 } 996 997 struct cfattach ix_ca = { 998 sizeof(struct ix_softc), ix_match, ix_attach 999 }; 1000
Indexes created Mon Sep 29 21:09:56 GMT 2025