if_iy.c revision 1.36.4.4
1 /* $NetBSD: if_iy.c,v 1.36.4.4 2000/07/21 14:30:54 is Exp $ */ 2 /* #define IYDEBUG */ 3 /* #define IYMEMDEBUG */ 4 5 /*- 6 * Copyright (c) 1996 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Ignatios Souvatzis. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Supported hardware: 43 * 44 * - Intel EtherExpress Pro/10. 45 * - possibly other boards using the i82595 chip and no special tweaks. 46 */ 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/mbuf.h> 56 #include <sys/buf.h> 57 #include <sys/protosw.h> 58 #include <sys/socket.h> 59 #include <sys/ioctl.h> 60 #include <sys/errno.h> 61 #include <sys/syslog.h> 62 #include <sys/device.h> 63 #include <sys/endian.h> 64 #if NRND > 0 65 #include <sys/rnd.h> 66 #endif 67 68 #include <net/if.h> 69 #include <net/if_types.h> 70 #include <net/if_dl.h> 71 72 #include <net/if_ether.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #include <net/bpfdesc.h> 77 #endif 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #ifdef NS 88 #include <netns/ns.h> 89 #include <netns/ns_if.h> 90 #endif 91 92 #if defined(SIOCSIFMEDIA) 93 #include <net/if_media.h> 94 #endif 95 96 #include <vm/vm.h> 97 98 #include <machine/cpu.h> 99 #include <machine/bus.h> 100 #include <machine/intr.h> 101 102 #include <dev/isa/isareg.h> 103 #include <dev/isa/isavar.h> 104 #include <dev/ic/i82595reg.h> 105 106 /* XXX why isn't this centralized? */ 107 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 108 #define bus_space_write_stream_2 bus_space_write_2 109 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 110 #define bus_space_read_stream_2 bus_space_read_2 111 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 112 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 113 114 /* 115 * Ethernet status, per interface. 116 */ 117 struct iy_softc { 118 struct device sc_dev; 119 void *sc_ih; 120 121 bus_space_tag_t sc_iot; 122 bus_space_handle_t sc_ioh; 123 124 struct ethercom sc_ethercom; 125 126 struct ifmedia iy_ifmedia; 127 int iy_media; 128 129 int mappedirq; 130 131 int hard_vers; 132 133 int promisc; 134 135 int sram, tx_size, rx_size; 136 137 int tx_start, tx_end, tx_last; 138 int rx_start; 139 140 int doing_mc_setup; 141 #ifdef IYDEBUG 142 int sc_debug; 143 #endif 144 145 #if NRND > 0 146 rndsource_element_t rnd_source; 147 #endif 148 }; 149 150 void iywatchdog __P((struct ifnet *)); 151 int iyioctl __P((struct ifnet *, u_long, caddr_t)); 152 int iyintr __P((void *)); 153 void iyinit __P((struct iy_softc *)); 154 void iystop __P((struct iy_softc *)); 155 void iystart __P((struct ifnet *)); 156 157 void iy_intr_rx __P((struct iy_softc *)); 158 void iy_intr_tx __P((struct iy_softc *)); 159 160 void iyreset __P((struct iy_softc *)); 161 void iy_readframe __P((struct iy_softc *, int)); 162 void iy_drop_packet_buffer __P((struct iy_softc *)); 163 void iy_find_mem_size __P((struct iy_softc *)); 164 void iyrint __P((struct iy_softc *)); 165 void iytint __P((struct iy_softc *)); 166 void iyxmit __P((struct iy_softc *)); 167 static void iy_mc_setup __P((struct iy_softc *)); 168 static void iy_mc_reset __P((struct iy_softc *)); 169 void iyget __P((struct iy_softc *, bus_space_tag_t, bus_space_handle_t, int)); 170 void iyprobemem __P((struct iy_softc *)); 171 static __inline void eepromwritebit __P((bus_space_tag_t, bus_space_handle_t, 172 int)); 173 static __inline int eepromreadbit __P((bus_space_tag_t, bus_space_handle_t)); 174 175 #ifdef IYDEBUGX 176 void print_rbd __P((volatile struct iy_recv_buf_desc *)); 177 178 int in_ifrint = 0; 179 int in_iftint = 0; 180 #endif 181 182 int iy_mediachange __P((struct ifnet *)); 183 void iy_mediastatus __P((struct ifnet *, struct ifmediareq *)); 184 185 int iyprobe __P((struct device *, struct cfdata *, void *)); 186 void iyattach __P((struct device *, struct device *, void *)); 187 188 static u_int16_t eepromread __P((bus_space_tag_t, bus_space_handle_t, int)); 189 190 static int eepromreadall __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 191 int)); 192 193 struct cfattach iy_ca = { 194 sizeof(struct iy_softc), iyprobe, iyattach 195 }; 196 197 static u_int8_t eepro_irqmap[] = EEPP_INTMAP; 198 static u_int8_t eepro_revirqmap[] = EEPP_RINTMAP; 199 200 int 201 iyprobe(parent, match, aux) 202 struct device *parent; 203 struct cfdata *match; 204 void *aux; 205 { 206 struct isa_attach_args *ia = aux; 207 u_int16_t eaddr[8]; 208 209 bus_space_tag_t iot; 210 bus_space_handle_t ioh; 211 212 u_int8_t c, d; 213 214 iot = ia->ia_iot; 215 216 if (ia->ia_iobase == IOBASEUNK) 217 return 0; 218 219 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) 220 return 0; 221 222 /* try to find the round robin sig: */ 223 224 c = bus_space_read_1(iot, ioh, ID_REG); 225 if ((c & ID_REG_MASK) != ID_REG_SIG) 226 goto out; 227 228 d = bus_space_read_1(iot, ioh, ID_REG); 229 if ((d & ID_REG_MASK) != ID_REG_SIG) 230 goto out; 231 232 if (((d-c) & R_ROBIN_BITS) != 0x40) 233 goto out; 234 235 d = bus_space_read_1(iot, ioh, ID_REG); 236 if ((d & ID_REG_MASK) != ID_REG_SIG) 237 goto out; 238 239 if (((d-c) & R_ROBIN_BITS) != 0x80) 240 goto out; 241 242 d = bus_space_read_1(iot, ioh, ID_REG); 243 if ((d & ID_REG_MASK) != ID_REG_SIG) 244 goto out; 245 246 if (((d-c) & R_ROBIN_BITS) != 0xC0) 247 goto out; 248 249 d = bus_space_read_1(iot, ioh, ID_REG); 250 if ((d & ID_REG_MASK) != ID_REG_SIG) 251 goto out; 252 253 if (((d-c) & R_ROBIN_BITS) != 0x00) 254 goto out; 255 256 #ifdef IYDEBUG 257 printf("iyprobe verified working ID reg.\n"); 258 #endif 259 260 if (eepromreadall(iot, ioh, eaddr, 8)) 261 goto out; 262 263 if (ia->ia_irq == IRQUNK) 264 ia->ia_irq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 265 266 if (ia->ia_irq >= sizeof(eepro_revirqmap)) 267 goto out; 268 269 if (eepro_revirqmap[ia->ia_irq] == 0xff) 270 goto out; 271 272 /* now lets reset the chip */ 273 274 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 275 delay(200); 276 277 ia->ia_iosize = 16; 278 279 bus_space_unmap(iot, ioh, 16); 280 return 1; /* found */ 281 out: 282 bus_space_unmap(iot, ioh, 16); 283 return 0; 284 } 285 286 void 287 iyattach(parent, self, aux) 288 struct device *parent, *self; 289 void *aux; 290 { 291 struct iy_softc *sc = (void *)self; 292 struct isa_attach_args *ia = aux; 293 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 294 bus_space_tag_t iot; 295 bus_space_handle_t ioh; 296 unsigned temp; 297 u_int16_t eaddr[8]; 298 u_int8_t myaddr[ETHER_ADDR_LEN]; 299 int eirq; 300 301 iot = ia->ia_iot; 302 303 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) { 304 printf(": can't map i/o space\n"); 305 return; 306 } 307 308 sc->sc_iot = iot; 309 sc->sc_ioh = ioh; 310 311 sc->mappedirq = eepro_revirqmap[ia->ia_irq]; 312 313 /* now let's reset the chip */ 314 315 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 316 delay(200); 317 318 iyprobemem(sc); 319 320 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 321 ifp->if_softc = sc; 322 ifp->if_start = iystart; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 324 | IFF_MULTICAST; 325 326 sc->doing_mc_setup = 0; 327 328 ifp->if_ioctl = iyioctl; 329 ifp->if_watchdog = iywatchdog; 330 331 (void)eepromreadall(iot, ioh, eaddr, 8); 332 sc->hard_vers = eaddr[EEPW6] & EEPP_BoardRev; 333 334 #ifdef DIAGNOSTICS 335 if ((eaddr[EEPPEther0] != 336 eepromread(iot, ioh, EEPPEther0a)) && 337 (eaddr[EEPPEther1] != 338 eepromread(iot, ioh, EEPPEther1a)) && 339 (eaddr[EEPPEther2] != 340 eepromread(iot, ioh, EEPPEther2a))) 341 342 printf("EEPROM Ethernet address differs from copy\n"); 343 #endif 344 345 myaddr[1] = eaddr[EEPPEther0] & 0xFF; 346 myaddr[0] = eaddr[EEPPEther0] >> 8; 347 myaddr[3] = eaddr[EEPPEther1] & 0xFF; 348 myaddr[2] = eaddr[EEPPEther1] >> 8; 349 myaddr[5] = eaddr[EEPPEther2] & 0xFF; 350 myaddr[4] = eaddr[EEPPEther2] >> 8; 351 352 ifmedia_init(&sc->iy_ifmedia, 0, iy_mediachange, iy_mediastatus); 353 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_2, 0, NULL); 354 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_5, 0, NULL); 355 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 356 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 357 ifmedia_set(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO); 358 /* Attach the interface. */ 359 if_attach(ifp); 360 ether_ifattach(ifp, myaddr); 361 printf(": address %s, rev. %d, %d kB\n", 362 ether_sprintf(myaddr), 363 sc->hard_vers, sc->sram/1024); 364 365 eirq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 366 if (eirq != ia->ia_irq) 367 printf("%s: EEPROM irq setting %d ignored\n", 368 sc->sc_dev.dv_xname, eirq); 369 370 #if NBPFILTER > 0 371 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 372 #endif 373 374 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 375 IPL_NET, iyintr, sc); 376 377 #if NRND > 0 378 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 379 RND_TYPE_NET, 0); 380 #endif 381 382 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 383 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 384 } 385 386 void 387 iystop(sc) 388 struct iy_softc *sc; 389 { 390 bus_space_tag_t iot; 391 bus_space_handle_t ioh; 392 #ifdef IYDEBUG 393 u_int p, v; 394 #endif 395 396 iot = sc->sc_iot; 397 ioh = sc->sc_ioh; 398 399 bus_space_write_1(iot, ioh, COMMAND_REG, RCV_DISABLE_CMD); 400 401 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 402 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); 403 404 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 405 delay(200); 406 #ifdef IYDEBUG 407 printf("%s: dumping tx chain (st 0x%x end 0x%x last 0x%x)\n", 408 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 409 p = sc->tx_last; 410 if (!p) 411 p = sc->tx_start; 412 do { 413 bus_space_write_2(iot, ioh, HOST_ADDR_REG, p); 414 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 415 printf("0x%04x: %b ", p, v, "\020\006Ab\010Dn"); 416 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 417 printf("0x%b", v, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL"); 418 p = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 419 printf(" 0x%04x", p); 420 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 421 printf(" 0x%b\n", v, "\020\020Ch"); 422 423 } while (v & 0x8000); 424 #endif 425 sc->tx_start = sc->tx_end = sc->rx_size; 426 sc->tx_last = 0; 427 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 428 } 429 430 void 431 iyreset(sc) 432 struct iy_softc *sc; 433 { 434 int s; 435 s = splnet(); 436 iystop(sc); 437 iyinit(sc); 438 splx(s); 439 } 440 441 void 442 iyinit(sc) 443 struct iy_softc *sc; 444 { 445 int i; 446 unsigned temp; 447 struct ifnet *ifp; 448 bus_space_tag_t iot; 449 bus_space_handle_t ioh; 450 451 iot = sc->sc_iot; 452 ioh = sc->sc_ioh; 453 454 ifp = &sc->sc_ethercom.ec_if; 455 #ifdef IYDEBUG 456 printf("ifp is %p\n", ifp); 457 #endif 458 459 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 460 461 temp = bus_space_read_1(iot, ioh, EEPROM_REG); 462 if (temp & 0x10) 463 bus_space_write_1(iot, ioh, EEPROM_REG, temp & ~0x10); 464 465 for (i=0; i<6; ++i) { 466 bus_space_write_1(iot, ioh, I_ADD(i), LLADDR(ifp->if_sadl)[i]); 467 } 468 469 temp = bus_space_read_1(iot, ioh, REG1); 470 bus_space_write_1(iot, ioh, REG1, 471 temp | XMT_CHAIN_INT | XMT_CHAIN_ERRSTOP | RCV_DISCARD_BAD); 472 473 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 474 temp = MATCH_ALL; 475 } else if (sc->sc_ethercom.ec_multicnt) { 476 temp = MATCH_MULTI; 477 } else 478 temp = MATCH_ID; 479 480 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 481 482 #ifdef IYDEBUG 483 printf("%s: RECV_MODES set to %b\n", sc->sc_dev.dv_xname, 484 temp, "\020\1PRMSC\2NOBRDST\3SEECRC\4LENGTH\5NOSaIns\6MultiIA"); 485 #endif 486 /* XXX VOODOO */ 487 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 488 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 489 /* XXX END OF VOODOO */ 490 491 492 delay(500000); /* for the hardware to test for the connector */ 493 494 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 495 #ifdef IYDEBUG 496 printf("%s: media select was 0x%b ", sc->sc_dev.dv_xname, 497 temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC"); 498 #endif 499 temp = (temp & TEST_MODE_MASK); 500 501 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 502 case IFM_10_5: 503 temp &= ~ (BNC_BIT | TPE_BIT); 504 break; 505 506 case IFM_10_2: 507 temp = (temp & ~TPE_BIT) | BNC_BIT; 508 break; 509 510 case IFM_10_T: 511 temp = (temp & ~BNC_BIT) | TPE_BIT; 512 break; 513 default: 514 /* nothing; leave as it is */ 515 } 516 switch (temp & (BNC_BIT | TPE_BIT)) { 517 case BNC_BIT: 518 sc->iy_media = IFM_ETHER | IFM_10_2; 519 break; 520 case TPE_BIT: 521 sc->iy_media = IFM_ETHER | IFM_10_T; 522 break; 523 default: 524 sc->iy_media = IFM_ETHER | IFM_10_5; 525 } 526 527 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 528 #ifdef IYDEBUG 529 printf("changed to 0x%b\n", 530 temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC"); 531 #endif 532 533 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 534 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 535 bus_space_write_1(iot, ioh, 0, BANK_SEL(1)); 536 537 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 538 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 539 540 #ifdef IYDEBUG 541 printf("%s: int no was %b\n", sc->sc_dev.dv_xname, 542 temp, "\020\4bad_irq\010flash/boot present"); 543 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 544 printf("%s: int no now 0x%02x\n", sc->sc_dev.dv_xname, 545 temp, "\020\4BAD IRQ\010flash/boot present"); 546 #endif 547 548 549 bus_space_write_1(iot, ioh, RCV_LOWER_LIMIT_REG, 0); 550 bus_space_write_1(iot, ioh, RCV_UPPER_LIMIT_REG, (sc->rx_size - 2) >> 8); 551 bus_space_write_1(iot, ioh, XMT_LOWER_LIMIT_REG, sc->rx_size >> 8); 552 bus_space_write_1(iot, ioh, XMT_UPPER_LIMIT_REG, sc->sram >> 8); 553 554 temp = bus_space_read_1(iot, ioh, REG1); 555 #ifdef IYDEBUG 556 printf("%s: HW access is %b\n", sc->sc_dev.dv_xname, 557 temp, "\020\2WORD_WIDTH\010INT_ENABLE"); 558 #endif 559 bus_space_write_1(iot, ioh, REG1, temp | INT_ENABLE); /* XXX what about WORD_WIDTH? */ 560 561 #ifdef IYDEBUG 562 temp = bus_space_read_1(iot, ioh, REG1); 563 printf("%s: HW access is %b\n", sc->sc_dev.dv_xname, 564 temp, "\020\2WORD_WIDTH\010INT_ENABLE"); 565 #endif 566 567 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 568 569 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS & ~(RX_BIT|TX_BIT)); 570 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); /* clear ints */ 571 572 bus_space_write_2(iot, ioh, RCV_START_LOW, 0); 573 bus_space_write_2(iot, ioh, RCV_STOP_LOW, sc->rx_size - 2); 574 sc->rx_start = 0; 575 576 bus_space_write_1(iot, ioh, 0, SEL_RESET_CMD); 577 delay(200); 578 579 bus_space_write_2(iot, ioh, XMT_ADDR_REG, sc->rx_size); 580 581 sc->tx_start = sc->tx_end = sc->rx_size; 582 sc->tx_last = 0; 583 584 bus_space_write_1(iot, ioh, 0, RCV_ENABLE_CMD); 585 586 ifp->if_flags |= IFF_RUNNING; 587 ifp->if_flags &= ~IFF_OACTIVE; 588 } 589 590 void 591 iystart(ifp) 592 struct ifnet *ifp; 593 { 594 struct iy_softc *sc; 595 596 597 struct mbuf *m0, *m; 598 u_int len, pad, last, end; 599 u_int llen, residual; 600 int avail; 601 caddr_t data; 602 u_int16_t resval, stat; 603 bus_space_tag_t iot; 604 bus_space_handle_t ioh; 605 606 #ifdef IYDEBUG 607 printf("iystart called\n"); 608 #endif 609 sc = ifp->if_softc; 610 611 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 612 return; 613 614 iot = sc->sc_iot; 615 ioh = sc->sc_ioh; 616 617 while ((m0 = ifp->if_snd.ifq_head) != NULL) { 618 #ifdef IYDEBUG 619 printf("%s: trying to write another packet to the hardware\n", 620 sc->sc_dev.dv_xname); 621 #endif 622 623 /* We need to use m->m_pkthdr.len, so require the header */ 624 if ((m0->m_flags & M_PKTHDR) == 0) 625 panic("iystart: no header mbuf"); 626 627 len = m0->m_pkthdr.len; 628 pad = len & 1; 629 630 #ifdef IYDEBUG 631 printf("%s: length is %d.\n", sc->sc_dev.dv_xname, len); 632 #endif 633 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 634 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 635 } 636 637 if (len + pad > ETHER_MAX_LEN) { 638 /* packet is obviously too large: toss it */ 639 ++ifp->if_oerrors; 640 IF_DEQUEUE(&ifp->if_snd, m0); 641 m_freem(m0); 642 continue; 643 } 644 645 #if NBPFILTER > 0 646 if (ifp->if_bpf) 647 bpf_mtap(ifp->if_bpf, m0); 648 #endif 649 650 avail = sc->tx_start - sc->tx_end; 651 if (avail <= 0) 652 avail += sc->tx_size; 653 654 #ifdef IYDEBUG 655 printf("%s: avail is %d.\n", sc->sc_dev.dv_xname, avail); 656 #endif 657 /* 658 * we MUST RUN at splnet here --- 659 * XXX todo: or even turn off the boards ints ??? hm... 660 */ 661 662 /* See if there is room to put another packet in the buffer. */ 663 664 if ((len+pad+2*I595_XMT_HDRLEN) > avail) { 665 #ifdef IYDEBUG 666 printf("%s: len = %d, avail = %d, setting OACTIVE\n", 667 sc->sc_dev.dv_xname, len, avail); 668 #endif 669 ifp->if_flags |= IFF_OACTIVE; 670 return; 671 } 672 673 /* we know it fits in the hardware now, so dequeue it */ 674 IF_DEQUEUE(&ifp->if_snd, m0); 675 676 last = sc->tx_end; 677 end = last + pad + len + I595_XMT_HDRLEN; 678 679 if (end >= sc->sram) { 680 if ((sc->sram - last) <= I595_XMT_HDRLEN) { 681 /* keep header in one piece */ 682 last = sc->rx_size; 683 end = last + pad + len + I595_XMT_HDRLEN; 684 } else 685 end -= sc->tx_size; 686 } 687 688 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 689 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 690 htole16(XMT_CMD)); 691 692 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 693 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 694 695 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 696 htole16(len + pad)); 697 698 residual = resval = 0; 699 700 while ((m = m0)!=0) { 701 data = mtod(m, caddr_t); 702 llen = m->m_len; 703 if (residual) { 704 #ifdef IYDEBUG 705 printf("%s: merging residual with next mbuf.\n", 706 sc->sc_dev.dv_xname); 707 #endif 708 resval |= *data << 8; 709 bus_space_write_stream_2(iot, ioh, 710 MEM_PORT_REG, resval); 711 --llen; 712 ++data; 713 } 714 if (llen > 1) 715 bus_space_write_multi_stream_2(iot, ioh, 716 MEM_PORT_REG, data, llen>>1); 717 residual = llen & 1; 718 if (residual) { 719 resval = *(data + llen - 1); 720 #ifdef IYDEBUG 721 printf("%s: got odd mbuf to send.\n", 722 sc->sc_dev.dv_xname); 723 #endif 724 } 725 726 MFREE(m, m0); 727 } 728 729 if (residual) 730 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 731 resval); 732 733 pad >>= 1; 734 while (pad-- > 0) 735 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 0); 736 737 #ifdef IYDEBUG 738 printf("%s: new last = 0x%x, end = 0x%x.\n", 739 sc->sc_dev.dv_xname, last, end); 740 printf("%s: old start = 0x%x, end = 0x%x, last = 0x%x\n", 741 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 742 #endif 743 744 if (sc->tx_start != sc->tx_end) { 745 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 746 sc->tx_last + XMT_COUNT); 747 748 /* 749 * XXX We keep stat in le order, to potentially save 750 * a byte swap. 751 */ 752 stat = bus_space_read_stream_2(iot, ioh, MEM_PORT_REG); 753 754 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 755 sc->tx_last + XMT_CHAIN); 756 757 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 758 htole16(last)); 759 760 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 761 stat | htole16(CHAIN)); 762 #ifdef IYDEBUG 763 printf("%s: setting 0x%x to 0x%x\n", 764 sc->sc_dev.dv_xname, sc->tx_last + XMT_COUNT, 765 le16toh(stat) | CHAIN); 766 #endif 767 } 768 stat = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 769 770 /* XXX todo: enable ints here if disabled */ 771 772 ++ifp->if_opackets; 773 774 if (sc->tx_start == sc->tx_end) { 775 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 776 bus_space_write_1(iot, ioh, 0, XMT_CMD); 777 sc->tx_start = last; 778 #ifdef IYDEBUG 779 printf("%s: writing 0x%x to XAR and giving XCMD\n", 780 sc->sc_dev.dv_xname, last); 781 #endif 782 } else { 783 bus_space_write_1(iot, ioh, 0, RESUME_XMT_CMD); 784 #ifdef IYDEBUG 785 printf("%s: giving RESUME_XCMD\n", 786 sc->sc_dev.dv_xname); 787 #endif 788 } 789 sc->tx_last = last; 790 sc->tx_end = end; 791 } 792 } 793 794 795 static __inline void 796 eepromwritebit(iot, ioh, what) 797 bus_space_tag_t iot; 798 bus_space_handle_t ioh; 799 int what; 800 { 801 bus_space_write_1(iot, ioh, EEPROM_REG, what); 802 delay(1); 803 bus_space_write_1(iot, ioh, EEPROM_REG, what|EESK); 804 delay(1); 805 bus_space_write_1(iot, ioh, EEPROM_REG, what); 806 delay(1); 807 } 808 809 static __inline int 810 eepromreadbit(iot, ioh) 811 bus_space_tag_t iot; 812 bus_space_handle_t ioh; 813 { 814 int b; 815 816 bus_space_write_1(iot, ioh, EEPROM_REG, EECS|EESK); 817 delay(1); 818 b = bus_space_read_1(iot, ioh, EEPROM_REG); 819 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); 820 delay(1); 821 822 return ((b & EEDO) != 0); 823 } 824 825 static u_int16_t 826 eepromread(iot, ioh, offset) 827 bus_space_tag_t iot; 828 bus_space_handle_t ioh; 829 int offset; 830 { 831 volatile int i; 832 volatile int j; 833 volatile u_int16_t readval; 834 835 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 836 delay(1); 837 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); /* XXXX??? */ 838 delay(1); 839 840 eepromwritebit(iot, ioh, EECS|EEDI); 841 eepromwritebit(iot, ioh, EECS|EEDI); 842 eepromwritebit(iot, ioh, EECS); 843 844 for (j=5; j>=0; --j) { 845 if ((offset>>j) & 1) 846 eepromwritebit(iot, ioh, EECS|EEDI); 847 else 848 eepromwritebit(iot, ioh, EECS); 849 } 850 851 for (readval=0, i=0; i<16; ++i) { 852 readval<<=1; 853 readval |= eepromreadbit(iot, ioh); 854 } 855 856 bus_space_write_1(iot, ioh, EEPROM_REG, 0|EESK); 857 delay(1); 858 bus_space_write_1(iot, ioh, EEPROM_REG, 0); 859 860 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 861 862 return readval; 863 } 864 865 /* 866 * Device timeout/watchdog routine. Entered if the device neglects to generate 867 * an interrupt after a transmit has been started on it. 868 */ 869 void 870 iywatchdog(ifp) 871 struct ifnet *ifp; 872 { 873 struct iy_softc *sc = ifp->if_softc; 874 875 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 876 ++sc->sc_ethercom.ec_if.if_oerrors; 877 iyreset(sc); 878 } 879 880 /* 881 * What to do upon receipt of an interrupt. 882 */ 883 int 884 iyintr(arg) 885 void *arg; 886 { 887 struct iy_softc *sc = arg; 888 bus_space_tag_t iot; 889 bus_space_handle_t ioh; 890 891 u_short status; 892 893 iot = sc->sc_iot; 894 ioh = sc->sc_ioh; 895 896 status = bus_space_read_1(iot, ioh, STATUS_REG); 897 #ifdef IYDEBUG 898 if (status & ALL_INTS) { 899 printf("%s: got interupt %b", sc->sc_dev.dv_xname, status, 900 "\020\1RX_STP\2RX\3TX\4EXEC"); 901 if (status & EXEC_INT) 902 printf(" event %b\n", bus_space_read_1(iot, ioh, 0), 903 "\020\6ABORT"); 904 else 905 printf("\n"); 906 } 907 #endif 908 if ((status & (RX_INT | TX_INT)) == 0) 909 return 0; 910 911 if (status & RX_INT) { 912 iy_intr_rx(sc); 913 bus_space_write_1(iot, ioh, STATUS_REG, RX_INT); 914 } 915 if (status & TX_INT) { 916 iy_intr_tx(sc); 917 bus_space_write_1(iot, ioh, STATUS_REG, TX_INT); 918 } 919 920 #if NRND > 0 921 rnd_add_uint32(&sc->rnd_source, status); 922 #endif 923 924 return 1; 925 } 926 927 void 928 iyget(sc, iot, ioh, rxlen) 929 struct iy_softc *sc; 930 bus_space_tag_t iot; 931 bus_space_handle_t ioh; 932 int rxlen; 933 { 934 struct mbuf *m, *top, **mp; 935 struct ether_header *eh; 936 struct ifnet *ifp; 937 int len; 938 939 ifp = &sc->sc_ethercom.ec_if; 940 941 MGETHDR(m, M_DONTWAIT, MT_DATA); 942 if (m == 0) 943 goto dropped; 944 m->m_pkthdr.rcvif = ifp; 945 m->m_pkthdr.len = rxlen; 946 len = MHLEN; 947 top = 0; 948 mp = ⊤ 949 950 while (rxlen > 0) { 951 if (top) { 952 MGET(m, M_DONTWAIT, MT_DATA); 953 if (m == 0) { 954 m_freem(top); 955 goto dropped; 956 } 957 len = MLEN; 958 } 959 if (rxlen >= MINCLSIZE) { 960 MCLGET(m, M_DONTWAIT); 961 if ((m->m_flags & M_EXT) == 0) { 962 m_free(m); 963 m_freem(top); 964 goto dropped; 965 } 966 len = MCLBYTES; 967 } 968 len = min(rxlen, len); 969 if (len > 1) { 970 len &= ~1; 971 972 bus_space_read_multi_stream_2(iot, ioh, MEM_PORT_REG, 973 mtod(m, caddr_t), len/2); 974 } else { 975 #ifdef IYDEBUG 976 printf("%s: received odd mbuf\n", sc->sc_dev.dv_xname); 977 #endif 978 *(mtod(m, caddr_t)) = bus_space_read_stream_2(iot, ioh, 979 MEM_PORT_REG); 980 } 981 m->m_len = len; 982 rxlen -= len; 983 *mp = m; 984 mp = &m->m_next; 985 } 986 /* XXX receive the top here */ 987 ++ifp->if_ipackets; 988 989 eh = mtod(top, struct ether_header *); 990 991 #if NBPFILTER > 0 992 if (ifp->if_bpf) { 993 bpf_mtap(ifp->if_bpf, top); 994 if ((ifp->if_flags & IFF_PROMISC) && 995 (eh->ether_dhost[0] & 1) == 0 && 996 bcmp(eh->ether_dhost, 997 LLADDR(ifp->if_sadl), sizeof(eh->ether_dhost)) != 0) { 998 999 m_freem(top); 1000 return; 1001 } 1002 } 1003 #endif 1004 (*ifp->if_input)(ifp, top); 1005 return; 1006 1007 dropped: 1008 ++ifp->if_ierrors; 1009 return; 1010 } 1011 1012 void 1013 iy_intr_rx(sc) 1014 struct iy_softc *sc; 1015 { 1016 struct ifnet *ifp; 1017 bus_space_tag_t iot; 1018 bus_space_handle_t ioh; 1019 1020 u_int rxadrs, rxevnt, rxstatus, rxnext, rxlen; 1021 1022 iot = sc->sc_iot; 1023 ioh = sc->sc_ioh; 1024 ifp = &sc->sc_ethercom.ec_if; 1025 1026 rxadrs = sc->rx_start; 1027 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxadrs); 1028 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 1029 rxnext = 0; 1030 1031 while (rxevnt == RCV_DONE) { 1032 rxstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1033 MEM_PORT_REG)); 1034 rxnext = le16toh(bus_space_read_stream_2(iot, ioh, 1035 MEM_PORT_REG)); 1036 rxlen = le16toh(bus_space_read_stream_2(iot, ioh, 1037 MEM_PORT_REG)); 1038 #ifdef IYDEBUG 1039 printf("%s: pck at 0x%04x stat %b next 0x%x len 0x%x\n", 1040 sc->sc_dev.dv_xname, rxadrs, rxstatus, 1041 "\020\1RCLD\2IA_MCH\010SHORT\011OVRN\013ALGERR" 1042 "\014CRCERR\015LENERR\016RCVOK\020TYP", 1043 rxnext, rxlen); 1044 #endif 1045 iyget(sc, iot, ioh, rxlen); 1046 1047 /* move stop address */ 1048 bus_space_write_2(iot, ioh, RCV_STOP_LOW, 1049 rxnext == 0 ? sc->rx_size - 2 : rxnext - 2); 1050 1051 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxnext); 1052 rxadrs = rxnext; 1053 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, 1054 MEM_PORT_REG)); 1055 } 1056 sc->rx_start = rxnext; 1057 } 1058 1059 void 1060 iy_intr_tx(sc) 1061 struct iy_softc *sc; 1062 { 1063 bus_space_tag_t iot; 1064 bus_space_handle_t ioh; 1065 struct ifnet *ifp; 1066 u_int txstatus, txstat2, txlen, txnext; 1067 1068 ifp = &sc->sc_ethercom.ec_if; 1069 iot = sc->sc_iot; 1070 ioh = sc->sc_ioh; 1071 1072 while (sc->tx_start != sc->tx_end) { 1073 bus_space_write_2(iot, ioh, HOST_ADDR_REG, sc->tx_start); 1074 txstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1075 MEM_PORT_REG)); 1076 1077 if ((txstatus & (TX_DONE|CMD_MASK)) != (TX_DONE|XMT_CMD)) 1078 break; 1079 1080 txstat2 = le16toh(bus_space_read_stream_2(iot, ioh, 1081 MEM_PORT_REG)); 1082 txnext = le16toh(bus_space_read_stream_2(iot, ioh, 1083 MEM_PORT_REG)); 1084 txlen = le16toh(bus_space_read_stream_2(iot, ioh, 1085 MEM_PORT_REG)); 1086 #ifdef IYDEBUG 1087 printf("txstat 0x%x stat2 0x%b next 0x%x len 0x%x\n", 1088 txstatus, txstat2, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF" 1089 "\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 1090 txnext, txlen); 1091 #endif 1092 if (txlen & CHAIN) 1093 sc->tx_start = txnext; 1094 else 1095 sc->tx_start = sc->tx_end; 1096 ifp->if_flags &= ~IFF_OACTIVE; 1097 1098 if ((txstat2 & 0x2000) == 0) 1099 ++ifp->if_oerrors; 1100 if (txstat2 & 0x000f) 1101 ifp->if_oerrors += txstat2 & 0x000f; 1102 } 1103 ifp->if_flags &= ~IFF_OACTIVE; 1104 } 1105 1106 int 1107 iyioctl(ifp, cmd, data) 1108 struct ifnet *ifp; 1109 u_long cmd; 1110 caddr_t data; 1111 { 1112 struct iy_softc *sc; 1113 struct ifaddr *ifa; 1114 struct ifreq *ifr; 1115 int s, error = 0; 1116 1117 sc = ifp->if_softc; 1118 ifa = (struct ifaddr *)data; 1119 ifr = (struct ifreq *)data; 1120 1121 #ifdef IYDEBUG 1122 printf("iyioctl called with ifp 0x%p (%s) cmd 0x%x data 0x%p\n", 1123 ifp, ifp->if_xname, cmd, data); 1124 #endif 1125 1126 s = splnet(); 1127 1128 switch (cmd) { 1129 1130 case SIOCSIFADDR: 1131 ifp->if_flags |= IFF_UP; 1132 1133 switch (ifa->ifa_addr->sa_family) { 1134 #ifdef INET 1135 case AF_INET: 1136 iyinit(sc); 1137 arp_ifinit(ifp, ifa); 1138 break; 1139 #endif 1140 #ifdef NS 1141 /* XXX - This code is probably wrong. */ 1142 case AF_NS: 1143 { 1144 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1145 1146 if (ns_nullhost(*ina)) 1147 ina->x_host = *(union ns_host *) 1148 LLADDR(ifp->if_sadl); 1149 else 1150 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1151 ETHER_ADDR_LEN); 1152 /* Set new address. */ 1153 iyinit(sc); 1154 break; 1155 } 1156 #endif /* NS */ 1157 default: 1158 iyinit(sc); 1159 break; 1160 } 1161 break; 1162 1163 case SIOCSIFFLAGS: 1164 sc->promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI); 1165 if ((ifp->if_flags & IFF_UP) == 0 && 1166 (ifp->if_flags & IFF_RUNNING) != 0) { 1167 /* 1168 * If interface is marked down and it is running, then 1169 * stop it. 1170 */ 1171 iystop(sc); 1172 ifp->if_flags &= ~IFF_RUNNING; 1173 } else if ((ifp->if_flags & IFF_UP) != 0 && 1174 (ifp->if_flags & IFF_RUNNING) == 0) { 1175 /* 1176 * If interface is marked up and it is stopped, then 1177 * start it. 1178 */ 1179 iyinit(sc); 1180 } else { 1181 /* 1182 * Reset the interface to pick up changes in any other 1183 * flags that affect hardware registers. 1184 */ 1185 iystop(sc); 1186 iyinit(sc); 1187 } 1188 #ifdef IYDEBUGX 1189 if (ifp->if_flags & IFF_DEBUG) 1190 sc->sc_debug = IFY_ALL; 1191 else 1192 sc->sc_debug = 0; 1193 #endif 1194 break; 1195 1196 case SIOCADDMULTI: 1197 case SIOCDELMULTI: 1198 error = (cmd == SIOCADDMULTI) ? 1199 ether_addmulti(ifr, &sc->sc_ethercom): 1200 ether_delmulti(ifr, &sc->sc_ethercom); 1201 1202 if (error == ENETRESET) { 1203 /* 1204 * Multicast list has changed; set the hardware filter 1205 * accordingly. 1206 */ 1207 iyreset(sc); /* XXX can't make it work otherwise */ 1208 iy_mc_reset(sc); 1209 error = 0; 1210 } 1211 break; 1212 1213 case SIOCSIFMEDIA: 1214 case SIOCGIFMEDIA: 1215 error = ifmedia_ioctl(ifp, ifr, &sc->iy_ifmedia, cmd); 1216 break; 1217 default: 1218 error = EINVAL; 1219 } 1220 splx(s); 1221 return error; 1222 } 1223 1224 int 1225 iy_mediachange(ifp) 1226 struct ifnet *ifp; 1227 { 1228 struct iy_softc *sc = ifp->if_softc; 1229 1230 if (IFM_TYPE(sc->iy_ifmedia.ifm_media) != IFM_ETHER) 1231 return EINVAL; 1232 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 1233 case IFM_10_5: 1234 case IFM_10_2: 1235 case IFM_10_T: 1236 case IFM_AUTO: 1237 iystop(sc); 1238 iyinit(sc); 1239 return 0; 1240 default: 1241 return EINVAL; 1242 } 1243 } 1244 1245 void 1246 iy_mediastatus(ifp, ifmr) 1247 struct ifnet *ifp; 1248 struct ifmediareq *ifmr; 1249 { 1250 struct iy_softc *sc = ifp->if_softc; 1251 1252 ifmr->ifm_active = sc->iy_media; 1253 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1254 } 1255 1256 1257 static void 1258 iy_mc_setup(sc) 1259 struct iy_softc *sc; 1260 { 1261 struct ether_multi *enm; 1262 struct ether_multistep step; 1263 struct ethercom *ecp; 1264 struct ifnet *ifp; 1265 bus_space_tag_t iot; 1266 bus_space_handle_t ioh; 1267 int avail, last /*, end*/ , len; 1268 int timeout; 1269 volatile u_int16_t dum; 1270 u_int8_t temp; 1271 1272 1273 ecp = &sc->sc_ethercom; 1274 ifp = &ecp->ec_if; 1275 1276 iot = sc->sc_iot; 1277 ioh = sc->sc_ioh; 1278 1279 len = 6 * ecp->ec_multicnt + 6; 1280 1281 avail = sc->tx_start - sc->tx_end; 1282 if (avail <= 0) 1283 avail += sc->tx_size; 1284 if (ifp->if_flags & IFF_DEBUG) 1285 printf("%s: iy_mc_setup called, %d addresses, " 1286 "%d/%d bytes needed/avail\n", ifp->if_xname, 1287 ecp->ec_multicnt, len + I595_XMT_HDRLEN, avail); 1288 1289 last = sc->rx_size; 1290 1291 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1292 bus_space_write_1(iot, ioh, RECV_MODES_REG, MATCH_MULTI); 1293 /* XXX VOODOO */ 1294 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1295 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1296 /* XXX END OF VOODOO */ 1297 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1298 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 1299 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(MC_SETUP_CMD)); 1300 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1301 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1302 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(len)); 1303 1304 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1305 LLADDR(ifp->if_sadl), 3); 1306 1307 ETHER_FIRST_MULTI(step, ecp, enm); 1308 while(enm) { 1309 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1310 enm->enm_addrlo, 3); 1311 1312 ETHER_NEXT_MULTI(step, enm); 1313 } 1314 dum = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 1315 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 1316 bus_space_write_1(iot, ioh, 0, MC_SETUP_CMD); 1317 1318 1319 sc->tx_start = sc->rx_size; 1320 sc->tx_end = sc->rx_size + I595_XMT_HDRLEN + len; 1321 1322 for (timeout=0; timeout<100; timeout++) { 1323 DELAY(2); 1324 if ((bus_space_read_1(iot, ioh, STATUS_REG) & EXEC_INT) == 0) 1325 continue; 1326 1327 temp = bus_space_read_1(iot, ioh, 0); 1328 bus_space_write_1(iot, ioh, STATUS_REG, EXEC_INT); 1329 #ifdef DIAGNOSTIC 1330 if (temp & 0x20) { 1331 printf("%s: mc setup failed, %d usec\n", 1332 sc->sc_dev.dv_xname, timeout * 2); 1333 } else if (((temp & 0x0f) == 0x03) && 1334 (ifp->if_flags & IFF_DEBUG)) { 1335 printf("%s: mc setup done, %d usec\n", 1336 sc->sc_dev.dv_xname, timeout * 2); 1337 } 1338 #endif 1339 break; 1340 } 1341 sc->tx_start = sc->tx_end; 1342 ifp->if_flags &= ~IFF_OACTIVE; 1343 1344 } 1345 1346 static void 1347 iy_mc_reset(sc) 1348 struct iy_softc *sc; 1349 { 1350 struct ether_multi *enm; 1351 struct ether_multistep step; 1352 struct ethercom *ecp; 1353 struct ifnet *ifp; 1354 bus_space_tag_t iot; 1355 bus_space_handle_t ioh; 1356 u_int16_t temp; 1357 1358 ecp = &sc->sc_ethercom; 1359 ifp = &ecp->ec_if; 1360 1361 iot = sc->sc_iot; 1362 ioh = sc->sc_ioh; 1363 1364 if (ecp->ec_multicnt > 63) { 1365 ifp->if_flags |= IFF_ALLMULTI; 1366 1367 } else if (ecp->ec_multicnt > 0) { 1368 /* 1369 * Step through the list of addresses. 1370 */ 1371 ETHER_FIRST_MULTI(step, ecp, enm); 1372 while(enm) { 1373 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1374 ifp->if_flags |= IFF_ALLMULTI; 1375 goto setupmulti; 1376 } 1377 ETHER_NEXT_MULTI(step, enm); 1378 } 1379 /* OK, we really need to do it now: */ 1380 #if 0 1381 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) 1382 != IFF_RUNNING) { 1383 ifp->if_flags |= IFF_OACTIVE; 1384 sc->want_mc_setup = 1; 1385 return; 1386 } 1387 #endif 1388 iy_mc_setup(sc); 1389 } else { 1390 ifp->if_flags &= ~IFF_ALLMULTI; 1391 } 1392 1393 setupmulti: 1394 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1395 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 1396 temp = MATCH_ALL; 1397 } else if (sc->sc_ethercom.ec_multicnt) { 1398 temp = MATCH_MULTI; 1399 } else 1400 temp = MATCH_ID; 1401 1402 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 1403 /* XXX VOODOO */ 1404 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1405 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1406 /* XXX END OF VOODOO */ 1407 1408 /* XXX TBD: setup hardware for all multicasts */ 1409 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1410 return; 1411 } 1412 1413 #ifdef IYDEBUG 1414 void 1415 print_rbd(rbd) 1416 volatile struct ie_recv_buf_desc *rbd; 1417 { 1418 1419 printf("RBD at %08lx:\nactual %04x, next %04x, buffer %08x\n" 1420 "length %04x, mbz %04x\n", (u_long)rbd, rbd->ie_rbd_actual, 1421 rbd->ie_rbd_next, rbd->ie_rbd_buffer, rbd->ie_rbd_length, 1422 rbd->mbz); 1423 } 1424 #endif 1425 1426 void 1427 iyprobemem(sc) 1428 struct iy_softc *sc; 1429 { 1430 bus_space_tag_t iot; 1431 bus_space_handle_t ioh; 1432 int testing; 1433 1434 iot = sc->sc_iot; 1435 ioh = sc->sc_ioh; 1436 1437 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 1438 delay(1); 1439 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 4096-2); 1440 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1441 1442 for (testing=65536; testing >= 4096; testing >>= 1) { 1443 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1444 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xdead); 1445 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1446 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xdead) { 1447 #ifdef IYMEMDEBUG 1448 printf("%s: Didn't keep 0xdead at 0x%x\n", 1449 sc->sc_dev.dv_xname, testing-2); 1450 #endif 1451 continue; 1452 } 1453 1454 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1455 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xbeef); 1456 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1457 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xbeef) { 1458 #ifdef IYMEMDEBUG 1459 printf("%s: Didn't keep 0xbeef at 0x%x\n", 1460 sc->sc_dev.dv_xname, testing-2); 1461 #endif 1462 continue; 1463 } 1464 1465 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1466 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1467 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing >> 1); 1468 bus_space_write_2(iot, ioh, MEM_PORT_REG, testing >> 1); 1469 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1470 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) == (testing >> 1)) { 1471 #ifdef IYMEMDEBUG 1472 printf("%s: 0x%x alias of 0x0\n", 1473 sc->sc_dev.dv_xname, testing >> 1); 1474 #endif 1475 continue; 1476 } 1477 1478 break; 1479 } 1480 1481 sc->sram = testing; 1482 1483 switch(testing) { 1484 case 65536: 1485 /* 4 NFS packets + overhead RX, 2 NFS + overhead TX */ 1486 sc->rx_size = 44*1024; 1487 break; 1488 1489 case 32768: 1490 /* 2 NFS packets + overhead RX, 1 NFS + overhead TX */ 1491 sc->rx_size = 22*1024; 1492 break; 1493 1494 case 16384: 1495 /* 1 NFS packet + overhead RX, 4 big packets TX */ 1496 sc->rx_size = 10*1024; 1497 break; 1498 default: 1499 sc->rx_size = testing/2; 1500 break; 1501 } 1502 sc->tx_size = testing - sc->rx_size; 1503 } 1504 1505 static int 1506 eepromreadall(iot, ioh, wordp, maxi) 1507 bus_space_tag_t iot; 1508 bus_space_handle_t ioh; 1509 u_int16_t *wordp; 1510 int maxi; 1511 { 1512 int i; 1513 u_int16_t checksum, tmp; 1514 1515 checksum = 0; 1516 1517 for (i=0; i<EEPP_LENGTH; ++i) { 1518 tmp = eepromread(iot, ioh, i); 1519 checksum += tmp; 1520 if (i<maxi) 1521 wordp[i] = tmp; 1522 } 1523 1524 if (checksum != EEPP_CHKSUM) { 1525 #ifdef IYDEBUG 1526 printf("wrong EEPROM checksum 0x%x should be 0x%x\n", 1527 checksum, EEPP_CHKSUM); 1528 #endif 1529 return 1; 1530 } 1531 return 0; 1532 } 1533
Indexes created Wed Oct 01 15:09:59 GMT 2025