if_iy.c revision 1.36.4.5
1 /* $NetBSD: if_iy.c,v 1.36.4.5 2001/03/16 19:44:04 he Exp $ */ 2 /* #define IYDEBUG */ 3 /* #define IYMEMDEBUG */ 4 5 /*- 6 * Copyright (c) 1996 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Ignatios Souvatzis. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Supported hardware: 43 * 44 * - Intel EtherExpress Pro/10. 45 * - possibly other boards using the i82595 chip and no special tweaks. 46 */ 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/mbuf.h> 56 #include <sys/buf.h> 57 #include <sys/protosw.h> 58 #include <sys/socket.h> 59 #include <sys/ioctl.h> 60 #include <sys/errno.h> 61 #include <sys/syslog.h> 62 #include <sys/device.h> 63 #include <sys/endian.h> 64 #if NRND > 0 65 #include <sys/rnd.h> 66 #endif 67 68 #include <net/if.h> 69 #include <net/if_types.h> 70 #include <net/if_dl.h> 71 72 #include <net/if_ether.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #include <net/bpfdesc.h> 77 #endif 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #ifdef NS 88 #include <netns/ns.h> 89 #include <netns/ns_if.h> 90 #endif 91 92 #if defined(SIOCSIFMEDIA) 93 #include <net/if_media.h> 94 #endif 95 96 #include <vm/vm.h> 97 98 #include <machine/cpu.h> 99 #include <machine/bus.h> 100 #include <machine/intr.h> 101 102 #include <dev/isa/isareg.h> 103 #include <dev/isa/isavar.h> 104 #include <dev/ic/i82595reg.h> 105 106 /* XXX why isn't this centralized? */ 107 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 108 #define bus_space_write_stream_2 bus_space_write_2 109 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 110 #define bus_space_read_stream_2 bus_space_read_2 111 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 112 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 113 114 /* 115 * Ethernet status, per interface. 116 */ 117 struct iy_softc { 118 struct device sc_dev; 119 void *sc_ih; 120 121 bus_space_tag_t sc_iot; 122 bus_space_handle_t sc_ioh; 123 124 struct ethercom sc_ethercom; 125 126 struct ifmedia iy_ifmedia; 127 int iy_media; 128 129 int mappedirq; 130 131 int hard_vers; 132 133 int promisc; 134 135 int sram, tx_size, rx_size; 136 137 int tx_start, tx_end, tx_last; 138 int rx_start; 139 140 int doing_mc_setup; 141 #ifdef IYDEBUG 142 int sc_debug; 143 #endif 144 145 #if NRND > 0 146 rndsource_element_t rnd_source; 147 #endif 148 }; 149 150 void iywatchdog __P((struct ifnet *)); 151 int iyioctl __P((struct ifnet *, u_long, caddr_t)); 152 int iyintr __P((void *)); 153 void iyinit __P((struct iy_softc *)); 154 void iystop __P((struct iy_softc *)); 155 void iystart __P((struct ifnet *)); 156 157 void iy_intr_rx __P((struct iy_softc *)); 158 void iy_intr_tx __P((struct iy_softc *)); 159 160 void iyreset __P((struct iy_softc *)); 161 void iy_readframe __P((struct iy_softc *, int)); 162 void iy_drop_packet_buffer __P((struct iy_softc *)); 163 void iy_find_mem_size __P((struct iy_softc *)); 164 void iyrint __P((struct iy_softc *)); 165 void iytint __P((struct iy_softc *)); 166 void iyxmit __P((struct iy_softc *)); 167 static void iy_mc_setup __P((struct iy_softc *)); 168 static void iy_mc_reset __P((struct iy_softc *)); 169 void iyget __P((struct iy_softc *, bus_space_tag_t, bus_space_handle_t, int)); 170 void iyprobemem __P((struct iy_softc *)); 171 static __inline void eepromwritebit __P((bus_space_tag_t, bus_space_handle_t, 172 int)); 173 static __inline int eepromreadbit __P((bus_space_tag_t, bus_space_handle_t)); 174 175 #ifdef IYDEBUGX 176 void print_rbd __P((volatile struct iy_recv_buf_desc *)); 177 178 int in_ifrint = 0; 179 int in_iftint = 0; 180 #endif 181 182 int iy_mediachange __P((struct ifnet *)); 183 void iy_mediastatus __P((struct ifnet *, struct ifmediareq *)); 184 185 int iyprobe __P((struct device *, struct cfdata *, void *)); 186 void iyattach __P((struct device *, struct device *, void *)); 187 188 static u_int16_t eepromread __P((bus_space_tag_t, bus_space_handle_t, int)); 189 190 static int eepromreadall __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 191 int)); 192 193 struct cfattach iy_ca = { 194 sizeof(struct iy_softc), iyprobe, iyattach 195 }; 196 197 static u_int8_t eepro_irqmap[] = EEPP_INTMAP; 198 static u_int8_t eepro_revirqmap[] = EEPP_RINTMAP; 199 200 int 201 iyprobe(parent, match, aux) 202 struct device *parent; 203 struct cfdata *match; 204 void *aux; 205 { 206 struct isa_attach_args *ia = aux; 207 u_int16_t eaddr[8]; 208 209 bus_space_tag_t iot; 210 bus_space_handle_t ioh; 211 212 u_int8_t c, d; 213 214 iot = ia->ia_iot; 215 216 if (ia->ia_iobase == IOBASEUNK) 217 return 0; 218 219 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) 220 return 0; 221 222 /* try to find the round robin sig: */ 223 224 c = bus_space_read_1(iot, ioh, ID_REG); 225 if ((c & ID_REG_MASK) != ID_REG_SIG) 226 goto out; 227 228 d = bus_space_read_1(iot, ioh, ID_REG); 229 if ((d & ID_REG_MASK) != ID_REG_SIG) 230 goto out; 231 232 if (((d-c) & R_ROBIN_BITS) != 0x40) 233 goto out; 234 235 d = bus_space_read_1(iot, ioh, ID_REG); 236 if ((d & ID_REG_MASK) != ID_REG_SIG) 237 goto out; 238 239 if (((d-c) & R_ROBIN_BITS) != 0x80) 240 goto out; 241 242 d = bus_space_read_1(iot, ioh, ID_REG); 243 if ((d & ID_REG_MASK) != ID_REG_SIG) 244 goto out; 245 246 if (((d-c) & R_ROBIN_BITS) != 0xC0) 247 goto out; 248 249 d = bus_space_read_1(iot, ioh, ID_REG); 250 if ((d & ID_REG_MASK) != ID_REG_SIG) 251 goto out; 252 253 if (((d-c) & R_ROBIN_BITS) != 0x00) 254 goto out; 255 256 #ifdef IYDEBUG 257 printf("iyprobe verified working ID reg.\n"); 258 #endif 259 260 if (eepromreadall(iot, ioh, eaddr, 8)) 261 goto out; 262 263 if (ia->ia_irq == IRQUNK) 264 ia->ia_irq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 265 266 if (ia->ia_irq >= sizeof(eepro_revirqmap)) 267 goto out; 268 269 if (eepro_revirqmap[ia->ia_irq] == 0xff) 270 goto out; 271 272 /* now lets reset the chip */ 273 274 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 275 delay(200); 276 277 ia->ia_iosize = 16; 278 279 bus_space_unmap(iot, ioh, 16); 280 return 1; /* found */ 281 out: 282 bus_space_unmap(iot, ioh, 16); 283 return 0; 284 } 285 286 void 287 iyattach(parent, self, aux) 288 struct device *parent, *self; 289 void *aux; 290 { 291 struct iy_softc *sc = (void *)self; 292 struct isa_attach_args *ia = aux; 293 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 294 bus_space_tag_t iot; 295 bus_space_handle_t ioh; 296 unsigned temp; 297 u_int16_t eaddr[8]; 298 u_int8_t myaddr[ETHER_ADDR_LEN]; 299 int eirq; 300 301 iot = ia->ia_iot; 302 303 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) { 304 printf(": can't map i/o space\n"); 305 return; 306 } 307 308 sc->sc_iot = iot; 309 sc->sc_ioh = ioh; 310 311 sc->mappedirq = eepro_revirqmap[ia->ia_irq]; 312 313 /* now let's reset the chip */ 314 315 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 316 delay(200); 317 318 iyprobemem(sc); 319 320 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 321 ifp->if_softc = sc; 322 ifp->if_start = iystart; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 324 | IFF_MULTICAST; 325 326 sc->doing_mc_setup = 0; 327 328 ifp->if_ioctl = iyioctl; 329 ifp->if_watchdog = iywatchdog; 330 331 (void)eepromreadall(iot, ioh, eaddr, 8); 332 sc->hard_vers = eaddr[EEPW6] & EEPP_BoardRev; 333 334 #ifdef DIAGNOSTICS 335 if ((eaddr[EEPPEther0] != 336 eepromread(iot, ioh, EEPPEther0a)) && 337 (eaddr[EEPPEther1] != 338 eepromread(iot, ioh, EEPPEther1a)) && 339 (eaddr[EEPPEther2] != 340 eepromread(iot, ioh, EEPPEther2a))) 341 342 printf("EEPROM Ethernet address differs from copy\n"); 343 #endif 344 345 myaddr[1] = eaddr[EEPPEther0] & 0xFF; 346 myaddr[0] = eaddr[EEPPEther0] >> 8; 347 myaddr[3] = eaddr[EEPPEther1] & 0xFF; 348 myaddr[2] = eaddr[EEPPEther1] >> 8; 349 myaddr[5] = eaddr[EEPPEther2] & 0xFF; 350 myaddr[4] = eaddr[EEPPEther2] >> 8; 351 352 ifmedia_init(&sc->iy_ifmedia, 0, iy_mediachange, iy_mediastatus); 353 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_2, 0, NULL); 354 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_5, 0, NULL); 355 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 356 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 357 ifmedia_set(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO); 358 /* Attach the interface. */ 359 if_attach(ifp); 360 ether_ifattach(ifp, myaddr); 361 printf(": address %s, rev. %d, %d kB\n", 362 ether_sprintf(myaddr), 363 sc->hard_vers, sc->sram/1024); 364 365 eirq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 366 if (eirq != ia->ia_irq) 367 printf("%s: EEPROM irq setting %d ignored\n", 368 sc->sc_dev.dv_xname, eirq); 369 370 #if NBPFILTER > 0 371 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 372 #endif 373 374 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 375 IPL_NET, iyintr, sc); 376 377 #if NRND > 0 378 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 379 RND_TYPE_NET, 0); 380 #endif 381 382 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 383 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 384 } 385 386 void 387 iystop(sc) 388 struct iy_softc *sc; 389 { 390 bus_space_tag_t iot; 391 bus_space_handle_t ioh; 392 #ifdef IYDEBUG 393 u_int p, v; 394 #endif 395 396 iot = sc->sc_iot; 397 ioh = sc->sc_ioh; 398 399 bus_space_write_1(iot, ioh, COMMAND_REG, RCV_DISABLE_CMD); 400 401 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 402 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); 403 404 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 405 delay(200); 406 #ifdef IYDEBUG 407 printf("%s: dumping tx chain (st 0x%x end 0x%x last 0x%x)\n", 408 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 409 p = sc->tx_last; 410 if (!p) 411 p = sc->tx_start; 412 do { 413 bus_space_write_2(iot, ioh, HOST_ADDR_REG, p); 414 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 415 printf("0x%04x: %b ", p, v, "\020\006Ab\010Dn"); 416 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 417 printf("0x%b", v, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL"); 418 p = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 419 printf(" 0x%04x", p); 420 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 421 printf(" 0x%b\n", v, "\020\020Ch"); 422 423 } while (v & 0x8000); 424 #endif 425 sc->tx_start = sc->tx_end = sc->rx_size; 426 sc->tx_last = 0; 427 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 428 } 429 430 void 431 iyreset(sc) 432 struct iy_softc *sc; 433 { 434 int s; 435 s = splnet(); 436 iystop(sc); 437 iyinit(sc); 438 splx(s); 439 } 440 441 void 442 iyinit(sc) 443 struct iy_softc *sc; 444 { 445 int i; 446 unsigned temp; 447 struct ifnet *ifp; 448 bus_space_tag_t iot; 449 bus_space_handle_t ioh; 450 451 iot = sc->sc_iot; 452 ioh = sc->sc_ioh; 453 454 ifp = &sc->sc_ethercom.ec_if; 455 #ifdef IYDEBUG 456 printf("ifp is %p\n", ifp); 457 #endif 458 459 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 460 461 temp = bus_space_read_1(iot, ioh, EEPROM_REG); 462 if (temp & 0x10) 463 bus_space_write_1(iot, ioh, EEPROM_REG, temp & ~0x10); 464 465 for (i=0; i<6; ++i) { 466 bus_space_write_1(iot, ioh, I_ADD(i), LLADDR(ifp->if_sadl)[i]); 467 } 468 469 temp = bus_space_read_1(iot, ioh, REG1); 470 bus_space_write_1(iot, ioh, REG1, 471 temp | /* XXX XMT_CHAIN_INT | */ XMT_CHAIN_ERRSTOP | RCV_DISCARD_BAD); 472 473 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 474 temp = MATCH_ALL; 475 } else if (sc->sc_ethercom.ec_multicnt) { 476 temp = MATCH_MULTI; 477 } else 478 temp = MATCH_ID; 479 480 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 481 482 #ifdef IYDEBUG 483 printf("%s: RECV_MODES set to %b\n", sc->sc_dev.dv_xname, 484 temp, "\020\1PRMSC\2NOBRDST\3SEECRC\4LENGTH\5NOSaIns\6MultiIA"); 485 #endif 486 /* XXX VOODOO */ 487 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 488 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 489 /* XXX END OF VOODOO */ 490 491 492 delay(500000); /* for the hardware to test for the connector */ 493 494 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 495 #ifdef IYDEBUG 496 printf("%s: media select was 0x%b ", sc->sc_dev.dv_xname, 497 temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC"); 498 #endif 499 temp = (temp & TEST_MODE_MASK); 500 501 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 502 case IFM_10_5: 503 temp &= ~ (BNC_BIT | TPE_BIT); 504 break; 505 506 case IFM_10_2: 507 temp = (temp & ~TPE_BIT) | BNC_BIT; 508 break; 509 510 case IFM_10_T: 511 temp = (temp & ~BNC_BIT) | TPE_BIT; 512 break; 513 default: 514 /* nothing; leave as it is */ 515 } 516 switch (temp & (BNC_BIT | TPE_BIT)) { 517 case BNC_BIT: 518 sc->iy_media = IFM_ETHER | IFM_10_2; 519 break; 520 case TPE_BIT: 521 sc->iy_media = IFM_ETHER | IFM_10_T; 522 break; 523 default: 524 sc->iy_media = IFM_ETHER | IFM_10_5; 525 } 526 527 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 528 #ifdef IYDEBUG 529 printf("changed to 0x%b\n", 530 temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC"); 531 #endif 532 533 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 534 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 535 bus_space_write_1(iot, ioh, 0, BANK_SEL(1)); 536 537 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 538 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 539 540 #ifdef IYDEBUG 541 printf("%s: int no was %b\n", sc->sc_dev.dv_xname, 542 temp, "\020\4bad_irq\010flash/boot present"); 543 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 544 printf("%s: int no now 0x%02x\n", sc->sc_dev.dv_xname, 545 temp, "\020\4BAD IRQ\010flash/boot present"); 546 #endif 547 548 bus_space_write_1(iot, ioh, RCV_LOWER_LIMIT_REG, 0); 549 bus_space_write_1(iot, ioh, RCV_UPPER_LIMIT_REG, (sc->rx_size -2) >>8); 550 bus_space_write_1(iot, ioh, XMT_LOWER_LIMIT_REG, sc->rx_size >>8); 551 bus_space_write_1(iot, ioh, XMT_UPPER_LIMIT_REG, (sc->sram - 2) >>8); 552 553 temp = bus_space_read_1(iot, ioh, REG1); 554 #ifdef IYDEBUG 555 printf("%s: HW access is %b\n", sc->sc_dev.dv_xname, 556 temp, "\020\2WORD_WIDTH\010INT_ENABLE"); 557 #endif 558 bus_space_write_1(iot, ioh, REG1, temp | INT_ENABLE); /* XXX what about WORD_WIDTH? */ 559 560 #ifdef IYDEBUG 561 temp = bus_space_read_1(iot, ioh, REG1); 562 printf("%s: HW access is %b\n", sc->sc_dev.dv_xname, 563 temp, "\020\2WORD_WIDTH\010INT_ENABLE"); 564 #endif 565 566 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 567 568 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS & ~(RX_BIT|TX_BIT)); 569 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); /* clear ints */ 570 571 bus_space_write_2(iot, ioh, RCV_START_LOW, 0); 572 bus_space_write_2(iot, ioh, RCV_STOP_LOW, sc->rx_size - 2); 573 sc->rx_start = 0; 574 575 bus_space_write_1(iot, ioh, 0, SEL_RESET_CMD); 576 delay(200); 577 578 bus_space_write_2(iot, ioh, XMT_ADDR_REG, sc->rx_size); 579 580 sc->tx_start = sc->tx_end = sc->rx_size; 581 sc->tx_last = 0; 582 583 bus_space_write_1(iot, ioh, 0, RCV_ENABLE_CMD); 584 585 ifp->if_flags |= IFF_RUNNING; 586 ifp->if_flags &= ~IFF_OACTIVE; 587 } 588 589 void 590 iystart(ifp) 591 struct ifnet *ifp; 592 { 593 struct iy_softc *sc; 594 595 596 struct mbuf *m0, *m; 597 u_int len, pad, last, end; 598 u_int llen, residual; 599 int avail; 600 caddr_t data; 601 u_int16_t resval, stat; 602 bus_space_tag_t iot; 603 bus_space_handle_t ioh; 604 605 #ifdef IYDEBUG 606 printf("iystart called\n"); 607 #endif 608 sc = ifp->if_softc; 609 610 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 611 return; 612 613 iot = sc->sc_iot; 614 ioh = sc->sc_ioh; 615 616 while ((m0 = ifp->if_snd.ifq_head) != NULL) { 617 #ifdef IYDEBUG 618 printf("%s: trying to write another packet to the hardware\n", 619 sc->sc_dev.dv_xname); 620 #endif 621 622 /* We need to use m->m_pkthdr.len, so require the header */ 623 if ((m0->m_flags & M_PKTHDR) == 0) 624 panic("iystart: no header mbuf"); 625 626 len = m0->m_pkthdr.len; 627 pad = len & 1; 628 629 #ifdef IYDEBUG 630 printf("%s: length is %d.\n", sc->sc_dev.dv_xname, len); 631 #endif 632 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 633 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 634 } 635 636 if (len + pad > ETHER_MAX_LEN) { 637 /* packet is obviously too large: toss it */ 638 ++ifp->if_oerrors; 639 IF_DEQUEUE(&ifp->if_snd, m0); 640 m_freem(m0); 641 continue; 642 } 643 644 #if NBPFILTER > 0 645 if (ifp->if_bpf) 646 bpf_mtap(ifp->if_bpf, m0); 647 #endif 648 649 avail = sc->tx_start - sc->tx_end; 650 if (avail <= 0) 651 avail += sc->tx_size; 652 653 #ifdef IYDEBUG 654 printf("%s: avail is %d.\n", sc->sc_dev.dv_xname, avail); 655 #endif 656 /* 657 * we MUST RUN at splnet here --- 658 * XXX todo: or even turn off the boards ints ??? hm... 659 */ 660 661 /* See if there is room to put another packet in the buffer. */ 662 663 if ((len+pad+2*I595_XMT_HDRLEN) > avail) { 664 #ifdef IYDEBUG 665 printf("%s: len = %d, avail = %d, setting OACTIVE\n", 666 sc->sc_dev.dv_xname, len, avail); 667 #endif 668 ifp->if_flags |= IFF_OACTIVE; 669 return; 670 } 671 672 /* we know it fits in the hardware now, so dequeue it */ 673 IF_DEQUEUE(&ifp->if_snd, m0); 674 675 last = sc->tx_end; 676 end = last + pad + len + I595_XMT_HDRLEN; 677 678 if (end >= sc->sram) { 679 if ((sc->sram - last) <= I595_XMT_HDRLEN) { 680 /* keep header in one piece */ 681 last = sc->rx_size; 682 end = last + pad + len + I595_XMT_HDRLEN; 683 } else 684 end -= sc->tx_size; 685 } 686 687 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 688 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 689 htole16(XMT_CMD)); 690 691 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 692 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 693 694 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 695 htole16(len + pad)); 696 697 residual = resval = 0; 698 699 while ((m = m0)!=0) { 700 data = mtod(m, caddr_t); 701 llen = m->m_len; 702 if (residual) { 703 #ifdef IYDEBUG 704 printf("%s: merging residual with next mbuf.\n", 705 sc->sc_dev.dv_xname); 706 #endif 707 resval |= *data << 8; 708 bus_space_write_stream_2(iot, ioh, 709 MEM_PORT_REG, resval); 710 --llen; 711 ++data; 712 } 713 if (llen > 1) 714 bus_space_write_multi_stream_2(iot, ioh, 715 MEM_PORT_REG, data, llen>>1); 716 residual = llen & 1; 717 if (residual) { 718 resval = *(data + llen - 1); 719 #ifdef IYDEBUG 720 printf("%s: got odd mbuf to send.\n", 721 sc->sc_dev.dv_xname); 722 #endif 723 } 724 725 MFREE(m, m0); 726 } 727 728 if (residual) 729 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 730 resval); 731 732 pad >>= 1; 733 while (pad-- > 0) 734 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 0); 735 736 #ifdef IYDEBUG 737 printf("%s: new last = 0x%x, end = 0x%x.\n", 738 sc->sc_dev.dv_xname, last, end); 739 printf("%s: old start = 0x%x, end = 0x%x, last = 0x%x\n", 740 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 741 #endif 742 743 if (sc->tx_start != sc->tx_end) { 744 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 745 sc->tx_last + XMT_COUNT); 746 747 /* 748 * XXX We keep stat in le order, to potentially save 749 * a byte swap. 750 */ 751 stat = bus_space_read_stream_2(iot, ioh, MEM_PORT_REG); 752 753 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 754 sc->tx_last + XMT_CHAIN); 755 756 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 757 htole16(last)); 758 759 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 760 stat | htole16(CHAIN)); 761 #ifdef IYDEBUG 762 printf("%s: setting 0x%x to 0x%x\n", 763 sc->sc_dev.dv_xname, sc->tx_last + XMT_COUNT, 764 le16toh(stat) | CHAIN); 765 #endif 766 } 767 stat = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 768 769 /* XXX todo: enable ints here if disabled */ 770 771 ++ifp->if_opackets; 772 773 if (sc->tx_start == sc->tx_end) { 774 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 775 bus_space_write_1(iot, ioh, 0, XMT_CMD); 776 sc->tx_start = last; 777 #ifdef IYDEBUG 778 printf("%s: writing 0x%x to XAR and giving XCMD\n", 779 sc->sc_dev.dv_xname, last); 780 #endif 781 } else { 782 bus_space_write_1(iot, ioh, 0, RESUME_XMT_CMD); 783 #ifdef IYDEBUG 784 printf("%s: giving RESUME_XCMD\n", 785 sc->sc_dev.dv_xname); 786 #endif 787 } 788 sc->tx_last = last; 789 sc->tx_end = end; 790 } 791 } 792 793 794 static __inline void 795 eepromwritebit(iot, ioh, what) 796 bus_space_tag_t iot; 797 bus_space_handle_t ioh; 798 int what; 799 { 800 bus_space_write_1(iot, ioh, EEPROM_REG, what); 801 delay(1); 802 bus_space_write_1(iot, ioh, EEPROM_REG, what|EESK); 803 delay(1); 804 bus_space_write_1(iot, ioh, EEPROM_REG, what); 805 delay(1); 806 } 807 808 static __inline int 809 eepromreadbit(iot, ioh) 810 bus_space_tag_t iot; 811 bus_space_handle_t ioh; 812 { 813 int b; 814 815 bus_space_write_1(iot, ioh, EEPROM_REG, EECS|EESK); 816 delay(1); 817 b = bus_space_read_1(iot, ioh, EEPROM_REG); 818 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); 819 delay(1); 820 821 return ((b & EEDO) != 0); 822 } 823 824 static u_int16_t 825 eepromread(iot, ioh, offset) 826 bus_space_tag_t iot; 827 bus_space_handle_t ioh; 828 int offset; 829 { 830 volatile int i; 831 volatile int j; 832 volatile u_int16_t readval; 833 834 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 835 delay(1); 836 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); /* XXXX??? */ 837 delay(1); 838 839 eepromwritebit(iot, ioh, EECS|EEDI); 840 eepromwritebit(iot, ioh, EECS|EEDI); 841 eepromwritebit(iot, ioh, EECS); 842 843 for (j=5; j>=0; --j) { 844 if ((offset>>j) & 1) 845 eepromwritebit(iot, ioh, EECS|EEDI); 846 else 847 eepromwritebit(iot, ioh, EECS); 848 } 849 850 for (readval=0, i=0; i<16; ++i) { 851 readval<<=1; 852 readval |= eepromreadbit(iot, ioh); 853 } 854 855 bus_space_write_1(iot, ioh, EEPROM_REG, 0|EESK); 856 delay(1); 857 bus_space_write_1(iot, ioh, EEPROM_REG, 0); 858 859 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 860 861 return readval; 862 } 863 864 /* 865 * Device timeout/watchdog routine. Entered if the device neglects to generate 866 * an interrupt after a transmit has been started on it. 867 */ 868 void 869 iywatchdog(ifp) 870 struct ifnet *ifp; 871 { 872 struct iy_softc *sc = ifp->if_softc; 873 874 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 875 ++sc->sc_ethercom.ec_if.if_oerrors; 876 iyreset(sc); 877 } 878 879 /* 880 * What to do upon receipt of an interrupt. 881 */ 882 int 883 iyintr(arg) 884 void *arg; 885 { 886 struct iy_softc *sc = arg; 887 bus_space_tag_t iot; 888 bus_space_handle_t ioh; 889 890 u_short status; 891 892 iot = sc->sc_iot; 893 ioh = sc->sc_ioh; 894 895 status = bus_space_read_1(iot, ioh, STATUS_REG); 896 #ifdef IYDEBUG 897 if (status & ALL_INTS) { 898 printf("%s: got interupt %b", sc->sc_dev.dv_xname, status, 899 "\020\1RX_STP\2RX\3TX\4EXEC"); 900 if (status & EXEC_INT) 901 printf(" event %b\n", bus_space_read_1(iot, ioh, 0), 902 "\020\6ABORT"); 903 else 904 printf("\n"); 905 } 906 #endif 907 if ((status & (RX_INT | TX_INT)) == 0) 908 return 0; 909 910 if (status & RX_INT) { 911 iy_intr_rx(sc); 912 bus_space_write_1(iot, ioh, STATUS_REG, RX_INT); 913 } 914 if (status & TX_INT) { 915 iy_intr_tx(sc); 916 bus_space_write_1(iot, ioh, STATUS_REG, TX_INT); 917 } 918 919 #if NRND > 0 920 rnd_add_uint32(&sc->rnd_source, status); 921 #endif 922 923 return 1; 924 } 925 926 void 927 iyget(sc, iot, ioh, rxlen) 928 struct iy_softc *sc; 929 bus_space_tag_t iot; 930 bus_space_handle_t ioh; 931 int rxlen; 932 { 933 struct mbuf *m, *top, **mp; 934 struct ether_header *eh; 935 struct ifnet *ifp; 936 int len; 937 938 ifp = &sc->sc_ethercom.ec_if; 939 940 MGETHDR(m, M_DONTWAIT, MT_DATA); 941 if (m == 0) 942 goto dropped; 943 m->m_pkthdr.rcvif = ifp; 944 m->m_pkthdr.len = rxlen; 945 len = MHLEN; 946 top = 0; 947 mp = ⊤ 948 949 while (rxlen > 0) { 950 if (top) { 951 MGET(m, M_DONTWAIT, MT_DATA); 952 if (m == 0) { 953 m_freem(top); 954 goto dropped; 955 } 956 len = MLEN; 957 } 958 if (rxlen >= MINCLSIZE) { 959 MCLGET(m, M_DONTWAIT); 960 if ((m->m_flags & M_EXT) == 0) { 961 m_free(m); 962 m_freem(top); 963 goto dropped; 964 } 965 len = MCLBYTES; 966 } 967 len = min(rxlen, len); 968 if (len > 1) { 969 len &= ~1; 970 971 bus_space_read_multi_stream_2(iot, ioh, MEM_PORT_REG, 972 mtod(m, caddr_t), len/2); 973 } else { 974 #ifdef IYDEBUG 975 printf("%s: received odd mbuf\n", sc->sc_dev.dv_xname); 976 #endif 977 *(mtod(m, caddr_t)) = bus_space_read_stream_2(iot, ioh, 978 MEM_PORT_REG); 979 } 980 m->m_len = len; 981 rxlen -= len; 982 *mp = m; 983 mp = &m->m_next; 984 } 985 /* XXX receive the top here */ 986 ++ifp->if_ipackets; 987 988 eh = mtod(top, struct ether_header *); 989 990 #if NBPFILTER > 0 991 if (ifp->if_bpf) { 992 bpf_mtap(ifp->if_bpf, top); 993 if ((ifp->if_flags & IFF_PROMISC) && 994 (eh->ether_dhost[0] & 1) == 0 && 995 bcmp(eh->ether_dhost, 996 LLADDR(ifp->if_sadl), sizeof(eh->ether_dhost)) != 0) { 997 998 m_freem(top); 999 return; 1000 } 1001 } 1002 #endif 1003 (*ifp->if_input)(ifp, top); 1004 return; 1005 1006 dropped: 1007 ++ifp->if_ierrors; 1008 return; 1009 } 1010 1011 void 1012 iy_intr_rx(sc) 1013 struct iy_softc *sc; 1014 { 1015 struct ifnet *ifp; 1016 bus_space_tag_t iot; 1017 bus_space_handle_t ioh; 1018 1019 u_int rxadrs, rxevnt, rxstatus, rxnext, rxlen; 1020 1021 iot = sc->sc_iot; 1022 ioh = sc->sc_ioh; 1023 ifp = &sc->sc_ethercom.ec_if; 1024 1025 rxadrs = sc->rx_start; 1026 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxadrs); 1027 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 1028 rxnext = 0; 1029 1030 while (rxevnt == RCV_DONE) { 1031 rxstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1032 MEM_PORT_REG)); 1033 rxnext = le16toh(bus_space_read_stream_2(iot, ioh, 1034 MEM_PORT_REG)); 1035 rxlen = le16toh(bus_space_read_stream_2(iot, ioh, 1036 MEM_PORT_REG)); 1037 #ifdef IYDEBUG 1038 printf("%s: pck at 0x%04x stat %b next 0x%x len 0x%x\n", 1039 sc->sc_dev.dv_xname, rxadrs, rxstatus, 1040 "\020\1RCLD\2IA_MCH\010SHORT\011OVRN\013ALGERR" 1041 "\014CRCERR\015LENERR\016RCVOK\020TYP", 1042 rxnext, rxlen); 1043 #endif 1044 iyget(sc, iot, ioh, rxlen); 1045 1046 /* move stop address */ 1047 bus_space_write_2(iot, ioh, RCV_STOP_LOW, 1048 rxnext == 0 ? sc->rx_size - 2 : rxnext - 2); 1049 1050 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxnext); 1051 rxadrs = rxnext; 1052 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, 1053 MEM_PORT_REG)); 1054 } 1055 sc->rx_start = rxnext; 1056 } 1057 1058 void 1059 iy_intr_tx(sc) 1060 struct iy_softc *sc; 1061 { 1062 bus_space_tag_t iot; 1063 bus_space_handle_t ioh; 1064 struct ifnet *ifp; 1065 u_int txstatus, txstat2, txlen, txnext; 1066 1067 ifp = &sc->sc_ethercom.ec_if; 1068 iot = sc->sc_iot; 1069 ioh = sc->sc_ioh; 1070 1071 while (sc->tx_start != sc->tx_end) { 1072 bus_space_write_2(iot, ioh, HOST_ADDR_REG, sc->tx_start); 1073 txstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1074 MEM_PORT_REG)); 1075 1076 if ((txstatus & (TX_DONE|CMD_MASK)) != (TX_DONE|XMT_CMD)) 1077 break; 1078 1079 txstat2 = le16toh(bus_space_read_stream_2(iot, ioh, 1080 MEM_PORT_REG)); 1081 txnext = le16toh(bus_space_read_stream_2(iot, ioh, 1082 MEM_PORT_REG)); 1083 txlen = le16toh(bus_space_read_stream_2(iot, ioh, 1084 MEM_PORT_REG)); 1085 #ifdef IYDEBUG 1086 printf("txstat 0x%x stat2 0x%b next 0x%x len 0x%x\n", 1087 txstatus, txstat2, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF" 1088 "\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 1089 txnext, txlen); 1090 #endif 1091 if (txlen & CHAIN) 1092 sc->tx_start = txnext; 1093 else 1094 sc->tx_start = sc->tx_end; 1095 ifp->if_flags &= ~IFF_OACTIVE; 1096 1097 if (txstat2 & 0x0020) 1098 ifp->if_collisions += 16; 1099 else 1100 ifp->if_collisions += txstat2 & 0x000f; 1101 1102 if ((txstat2 & 0x2000) == 0) { 1103 ++ifp->if_oerrors; 1104 sc->tx_start = sc->tx_end; 1105 break; /* Fatal errors stop chaining, too */ 1106 } 1107 } 1108 #if 0 1109 if (sc->tx_start != sc->tx_end) { 1110 /* 1111 * This happens when a chain is interupted because of a 1112 * fatal transmission error. Start transmission of the 1113 * remaining part of the chain. 1114 */ 1115 bus_space_write_2(iot, ioh, XMT_ADDR_REG, sc->tx_start); 1116 bus_space_write_1(iot, ioh, 0, XMT_CMD); 1117 } 1118 #endif 1119 /* Nearly done. Tell feeders we may be able to accept more data... */ 1120 ifp->if_flags &= ~IFF_OACTIVE; 1121 1122 /* and get more data. */ 1123 iystart(ifp); 1124 } 1125 1126 int 1127 iyioctl(ifp, cmd, data) 1128 struct ifnet *ifp; 1129 u_long cmd; 1130 caddr_t data; 1131 { 1132 struct iy_softc *sc; 1133 struct ifaddr *ifa; 1134 struct ifreq *ifr; 1135 int s, error = 0; 1136 1137 sc = ifp->if_softc; 1138 ifa = (struct ifaddr *)data; 1139 ifr = (struct ifreq *)data; 1140 1141 #ifdef IYDEBUG 1142 printf("iyioctl called with ifp 0x%p (%s) cmd 0x%x data 0x%p\n", 1143 ifp, ifp->if_xname, cmd, data); 1144 #endif 1145 1146 s = splnet(); 1147 1148 switch (cmd) { 1149 1150 case SIOCSIFADDR: 1151 ifp->if_flags |= IFF_UP; 1152 1153 switch (ifa->ifa_addr->sa_family) { 1154 #ifdef INET 1155 case AF_INET: 1156 iyinit(sc); 1157 arp_ifinit(ifp, ifa); 1158 break; 1159 #endif 1160 #ifdef NS 1161 /* XXX - This code is probably wrong. */ 1162 case AF_NS: 1163 { 1164 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1165 1166 if (ns_nullhost(*ina)) 1167 ina->x_host = *(union ns_host *) 1168 LLADDR(ifp->if_sadl); 1169 else 1170 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1171 ETHER_ADDR_LEN); 1172 /* Set new address. */ 1173 iyinit(sc); 1174 break; 1175 } 1176 #endif /* NS */ 1177 default: 1178 iyinit(sc); 1179 break; 1180 } 1181 break; 1182 1183 case SIOCSIFFLAGS: 1184 sc->promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI); 1185 if ((ifp->if_flags & IFF_UP) == 0 && 1186 (ifp->if_flags & IFF_RUNNING) != 0) { 1187 /* 1188 * If interface is marked down and it is running, then 1189 * stop it. 1190 */ 1191 iystop(sc); 1192 ifp->if_flags &= ~IFF_RUNNING; 1193 } else if ((ifp->if_flags & IFF_UP) != 0 && 1194 (ifp->if_flags & IFF_RUNNING) == 0) { 1195 /* 1196 * If interface is marked up and it is stopped, then 1197 * start it. 1198 */ 1199 iyinit(sc); 1200 } else { 1201 /* 1202 * Reset the interface to pick up changes in any other 1203 * flags that affect hardware registers. 1204 */ 1205 iystop(sc); 1206 iyinit(sc); 1207 } 1208 #ifdef IYDEBUGX 1209 if (ifp->if_flags & IFF_DEBUG) 1210 sc->sc_debug = IFY_ALL; 1211 else 1212 sc->sc_debug = 0; 1213 #endif 1214 break; 1215 1216 case SIOCADDMULTI: 1217 case SIOCDELMULTI: 1218 error = (cmd == SIOCADDMULTI) ? 1219 ether_addmulti(ifr, &sc->sc_ethercom): 1220 ether_delmulti(ifr, &sc->sc_ethercom); 1221 1222 if (error == ENETRESET) { 1223 /* 1224 * Multicast list has changed; set the hardware filter 1225 * accordingly. 1226 */ 1227 iyreset(sc); /* XXX can't make it work otherwise */ 1228 iy_mc_reset(sc); 1229 error = 0; 1230 } 1231 break; 1232 1233 case SIOCSIFMEDIA: 1234 case SIOCGIFMEDIA: 1235 error = ifmedia_ioctl(ifp, ifr, &sc->iy_ifmedia, cmd); 1236 break; 1237 default: 1238 error = EINVAL; 1239 } 1240 splx(s); 1241 return error; 1242 } 1243 1244 int 1245 iy_mediachange(ifp) 1246 struct ifnet *ifp; 1247 { 1248 struct iy_softc *sc = ifp->if_softc; 1249 1250 if (IFM_TYPE(sc->iy_ifmedia.ifm_media) != IFM_ETHER) 1251 return EINVAL; 1252 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 1253 case IFM_10_5: 1254 case IFM_10_2: 1255 case IFM_10_T: 1256 case IFM_AUTO: 1257 iystop(sc); 1258 iyinit(sc); 1259 return 0; 1260 default: 1261 return EINVAL; 1262 } 1263 } 1264 1265 void 1266 iy_mediastatus(ifp, ifmr) 1267 struct ifnet *ifp; 1268 struct ifmediareq *ifmr; 1269 { 1270 struct iy_softc *sc = ifp->if_softc; 1271 1272 ifmr->ifm_active = sc->iy_media; 1273 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1274 } 1275 1276 1277 static void 1278 iy_mc_setup(sc) 1279 struct iy_softc *sc; 1280 { 1281 struct ether_multi *enm; 1282 struct ether_multistep step; 1283 struct ethercom *ecp; 1284 struct ifnet *ifp; 1285 bus_space_tag_t iot; 1286 bus_space_handle_t ioh; 1287 int avail, last /*, end*/ , len; 1288 int timeout; 1289 volatile u_int16_t dum; 1290 u_int8_t temp; 1291 1292 1293 ecp = &sc->sc_ethercom; 1294 ifp = &ecp->ec_if; 1295 1296 iot = sc->sc_iot; 1297 ioh = sc->sc_ioh; 1298 1299 len = 6 * ecp->ec_multicnt + 6; 1300 1301 avail = sc->tx_start - sc->tx_end; 1302 if (avail <= 0) 1303 avail += sc->tx_size; 1304 if (ifp->if_flags & IFF_DEBUG) 1305 printf("%s: iy_mc_setup called, %d addresses, " 1306 "%d/%d bytes needed/avail\n", ifp->if_xname, 1307 ecp->ec_multicnt, len + I595_XMT_HDRLEN, avail); 1308 1309 last = sc->rx_size; 1310 1311 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1312 bus_space_write_1(iot, ioh, RECV_MODES_REG, MATCH_MULTI); 1313 /* XXX VOODOO */ 1314 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1315 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1316 /* XXX END OF VOODOO */ 1317 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1318 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 1319 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(MC_SETUP_CMD)); 1320 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1321 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1322 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(len)); 1323 1324 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1325 LLADDR(ifp->if_sadl), 3); 1326 1327 ETHER_FIRST_MULTI(step, ecp, enm); 1328 while(enm) { 1329 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1330 enm->enm_addrlo, 3); 1331 1332 ETHER_NEXT_MULTI(step, enm); 1333 } 1334 dum = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 1335 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 1336 bus_space_write_1(iot, ioh, 0, MC_SETUP_CMD); 1337 1338 1339 sc->tx_start = sc->rx_size; 1340 sc->tx_end = sc->rx_size + I595_XMT_HDRLEN + len; 1341 1342 for (timeout=0; timeout<100; timeout++) { 1343 DELAY(2); 1344 if ((bus_space_read_1(iot, ioh, STATUS_REG) & EXEC_INT) == 0) 1345 continue; 1346 1347 temp = bus_space_read_1(iot, ioh, 0); 1348 bus_space_write_1(iot, ioh, STATUS_REG, EXEC_INT); 1349 #ifdef DIAGNOSTIC 1350 if (temp & 0x20) { 1351 printf("%s: mc setup failed, %d usec\n", 1352 sc->sc_dev.dv_xname, timeout * 2); 1353 } else if (((temp & 0x0f) == 0x03) && 1354 (ifp->if_flags & IFF_DEBUG)) { 1355 printf("%s: mc setup done, %d usec\n", 1356 sc->sc_dev.dv_xname, timeout * 2); 1357 } 1358 #endif 1359 break; 1360 } 1361 sc->tx_start = sc->tx_end; 1362 ifp->if_flags &= ~IFF_OACTIVE; 1363 1364 } 1365 1366 static void 1367 iy_mc_reset(sc) 1368 struct iy_softc *sc; 1369 { 1370 struct ether_multi *enm; 1371 struct ether_multistep step; 1372 struct ethercom *ecp; 1373 struct ifnet *ifp; 1374 bus_space_tag_t iot; 1375 bus_space_handle_t ioh; 1376 u_int16_t temp; 1377 1378 ecp = &sc->sc_ethercom; 1379 ifp = &ecp->ec_if; 1380 1381 iot = sc->sc_iot; 1382 ioh = sc->sc_ioh; 1383 1384 if (ecp->ec_multicnt > 63) { 1385 ifp->if_flags |= IFF_ALLMULTI; 1386 1387 } else if (ecp->ec_multicnt > 0) { 1388 /* 1389 * Step through the list of addresses. 1390 */ 1391 ETHER_FIRST_MULTI(step, ecp, enm); 1392 while(enm) { 1393 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1394 ifp->if_flags |= IFF_ALLMULTI; 1395 goto setupmulti; 1396 } 1397 ETHER_NEXT_MULTI(step, enm); 1398 } 1399 /* OK, we really need to do it now: */ 1400 #if 0 1401 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) 1402 != IFF_RUNNING) { 1403 ifp->if_flags |= IFF_OACTIVE; 1404 sc->want_mc_setup = 1; 1405 return; 1406 } 1407 #endif 1408 iy_mc_setup(sc); 1409 } else { 1410 ifp->if_flags &= ~IFF_ALLMULTI; 1411 } 1412 1413 setupmulti: 1414 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1415 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 1416 temp = MATCH_ALL; 1417 } else if (sc->sc_ethercom.ec_multicnt) { 1418 temp = MATCH_MULTI; 1419 } else 1420 temp = MATCH_ID; 1421 1422 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 1423 /* XXX VOODOO */ 1424 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1425 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1426 /* XXX END OF VOODOO */ 1427 1428 /* XXX TBD: setup hardware for all multicasts */ 1429 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1430 return; 1431 } 1432 1433 #ifdef IYDEBUG 1434 void 1435 print_rbd(rbd) 1436 volatile struct ie_recv_buf_desc *rbd; 1437 { 1438 1439 printf("RBD at %08lx:\nactual %04x, next %04x, buffer %08x\n" 1440 "length %04x, mbz %04x\n", (u_long)rbd, rbd->ie_rbd_actual, 1441 rbd->ie_rbd_next, rbd->ie_rbd_buffer, rbd->ie_rbd_length, 1442 rbd->mbz); 1443 } 1444 #endif 1445 1446 void 1447 iyprobemem(sc) 1448 struct iy_softc *sc; 1449 { 1450 bus_space_tag_t iot; 1451 bus_space_handle_t ioh; 1452 int testing; 1453 1454 iot = sc->sc_iot; 1455 ioh = sc->sc_ioh; 1456 1457 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 1458 delay(1); 1459 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 4096-2); 1460 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1461 1462 for (testing=65536; testing >= 4096; testing >>= 1) { 1463 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1464 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xdead); 1465 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1466 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xdead) { 1467 #ifdef IYMEMDEBUG 1468 printf("%s: Didn't keep 0xdead at 0x%x\n", 1469 sc->sc_dev.dv_xname, testing-2); 1470 #endif 1471 continue; 1472 } 1473 1474 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1475 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xbeef); 1476 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1477 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xbeef) { 1478 #ifdef IYMEMDEBUG 1479 printf("%s: Didn't keep 0xbeef at 0x%x\n", 1480 sc->sc_dev.dv_xname, testing-2); 1481 #endif 1482 continue; 1483 } 1484 1485 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1486 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1487 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing >> 1); 1488 bus_space_write_2(iot, ioh, MEM_PORT_REG, testing >> 1); 1489 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1490 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) == (testing >> 1)) { 1491 #ifdef IYMEMDEBUG 1492 printf("%s: 0x%x alias of 0x0\n", 1493 sc->sc_dev.dv_xname, testing >> 1); 1494 #endif 1495 continue; 1496 } 1497 1498 break; 1499 } 1500 1501 sc->sram = testing; 1502 1503 switch(testing) { 1504 case 65536: 1505 /* 4 NFS packets + overhead RX, 2 NFS + overhead TX */ 1506 sc->rx_size = 44*1024; 1507 break; 1508 1509 case 32768: 1510 /* 2 NFS packets + overhead RX, 1 NFS + overhead TX */ 1511 sc->rx_size = 22*1024; 1512 break; 1513 1514 case 16384: 1515 /* 1 NFS packet + overhead RX, 4 big packets TX */ 1516 sc->rx_size = 10*1024; 1517 break; 1518 default: 1519 sc->rx_size = testing/2; 1520 break; 1521 } 1522 sc->tx_size = testing - sc->rx_size; 1523 } 1524 1525 static int 1526 eepromreadall(iot, ioh, wordp, maxi) 1527 bus_space_tag_t iot; 1528 bus_space_handle_t ioh; 1529 u_int16_t *wordp; 1530 int maxi; 1531 { 1532 int i; 1533 u_int16_t checksum, tmp; 1534 1535 checksum = 0; 1536 1537 for (i=0; i<EEPP_LENGTH; ++i) { 1538 tmp = eepromread(iot, ioh, i); 1539 checksum += tmp; 1540 if (i<maxi) 1541 wordp[i] = tmp; 1542 } 1543 1544 if (checksum != EEPP_CHKSUM) { 1545 #ifdef IYDEBUG 1546 printf("wrong EEPROM checksum 0x%x should be 0x%x\n", 1547 checksum, EEPP_CHKSUM); 1548 #endif 1549 return 1; 1550 } 1551 return 0; 1552 } 1553
Indexes created Wed Oct 01 15:09:59 GMT 2025