if_iy.c revision 1.41
1 /* $NetBSD: if_iy.c,v 1.41 2000/07/21 13:54:38 is Exp $ */ 2 /* #define IYDEBUG */ 3 /* #define IYMEMDEBUG */ 4 5 /*- 6 * Copyright (c) 1996 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Ignatios Souvatzis. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Supported hardware: 43 * 44 * - Intel EtherExpress Pro/10. 45 * - possibly other boards using the i82595 chip and no special tweaks. 46 */ 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/mbuf.h> 56 #include <sys/buf.h> 57 #include <sys/protosw.h> 58 #include <sys/socket.h> 59 #include <sys/ioctl.h> 60 #include <sys/errno.h> 61 #include <sys/syslog.h> 62 #include <sys/device.h> 63 #include <sys/endian.h> 64 #if NRND > 0 65 #include <sys/rnd.h> 66 #endif 67 68 #include <net/if.h> 69 #include <net/if_types.h> 70 #include <net/if_dl.h> 71 72 #include <net/if_ether.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #include <net/bpfdesc.h> 77 #endif 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #ifdef NS 88 #include <netns/ns.h> 89 #include <netns/ns_if.h> 90 #endif 91 92 #if defined(SIOCSIFMEDIA) 93 #include <net/if_media.h> 94 #endif 95 96 #include <machine/cpu.h> 97 #include <machine/bus.h> 98 #include <machine/intr.h> 99 100 #include <dev/isa/isareg.h> 101 #include <dev/isa/isavar.h> 102 #include <dev/ic/i82595reg.h> 103 104 /* XXX why isn't this centralized? */ 105 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 106 #define bus_space_write_stream_2 bus_space_write_2 107 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 108 #define bus_space_read_stream_2 bus_space_read_2 109 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 110 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 111 112 /* 113 * Ethernet status, per interface. 114 */ 115 struct iy_softc { 116 struct device sc_dev; 117 void *sc_ih; 118 119 bus_space_tag_t sc_iot; 120 bus_space_handle_t sc_ioh; 121 122 struct ethercom sc_ethercom; 123 124 struct ifmedia iy_ifmedia; 125 int iy_media; 126 127 int mappedirq; 128 129 int hard_vers; 130 131 int promisc; 132 133 int sram, tx_size, rx_size; 134 135 int tx_start, tx_end, tx_last; 136 int rx_start; 137 138 int doing_mc_setup; 139 #ifdef IYDEBUG 140 int sc_debug; 141 #endif 142 143 #if NRND > 0 144 rndsource_element_t rnd_source; 145 #endif 146 }; 147 148 void iywatchdog __P((struct ifnet *)); 149 int iyioctl __P((struct ifnet *, u_long, caddr_t)); 150 int iyintr __P((void *)); 151 void iyinit __P((struct iy_softc *)); 152 void iystop __P((struct iy_softc *)); 153 void iystart __P((struct ifnet *)); 154 155 void iy_intr_rx __P((struct iy_softc *)); 156 void iy_intr_tx __P((struct iy_softc *)); 157 158 void iyreset __P((struct iy_softc *)); 159 void iy_readframe __P((struct iy_softc *, int)); 160 void iy_drop_packet_buffer __P((struct iy_softc *)); 161 void iy_find_mem_size __P((struct iy_softc *)); 162 void iyrint __P((struct iy_softc *)); 163 void iytint __P((struct iy_softc *)); 164 void iyxmit __P((struct iy_softc *)); 165 static void iy_mc_setup __P((struct iy_softc *)); 166 static void iy_mc_reset __P((struct iy_softc *)); 167 void iyget __P((struct iy_softc *, bus_space_tag_t, bus_space_handle_t, int)); 168 void iyprobemem __P((struct iy_softc *)); 169 static __inline void eepromwritebit __P((bus_space_tag_t, bus_space_handle_t, 170 int)); 171 static __inline int eepromreadbit __P((bus_space_tag_t, bus_space_handle_t)); 172 173 #ifdef IYDEBUGX 174 void print_rbd __P((volatile struct iy_recv_buf_desc *)); 175 176 int in_ifrint = 0; 177 int in_iftint = 0; 178 #endif 179 180 int iy_mediachange __P((struct ifnet *)); 181 void iy_mediastatus __P((struct ifnet *, struct ifmediareq *)); 182 183 int iyprobe __P((struct device *, struct cfdata *, void *)); 184 void iyattach __P((struct device *, struct device *, void *)); 185 186 static u_int16_t eepromread __P((bus_space_tag_t, bus_space_handle_t, int)); 187 188 static int eepromreadall __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 189 int)); 190 191 struct cfattach iy_ca = { 192 sizeof(struct iy_softc), iyprobe, iyattach 193 }; 194 195 static u_int8_t eepro_irqmap[] = EEPP_INTMAP; 196 static u_int8_t eepro_revirqmap[] = EEPP_RINTMAP; 197 198 int 199 iyprobe(parent, match, aux) 200 struct device *parent; 201 struct cfdata *match; 202 void *aux; 203 { 204 struct isa_attach_args *ia = aux; 205 u_int16_t eaddr[8]; 206 207 bus_space_tag_t iot; 208 bus_space_handle_t ioh; 209 210 u_int8_t c, d; 211 212 iot = ia->ia_iot; 213 214 if (ia->ia_iobase == IOBASEUNK) 215 return 0; 216 217 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) 218 return 0; 219 220 /* try to find the round robin sig: */ 221 222 c = bus_space_read_1(iot, ioh, ID_REG); 223 if ((c & ID_REG_MASK) != ID_REG_SIG) 224 goto out; 225 226 d = bus_space_read_1(iot, ioh, ID_REG); 227 if ((d & ID_REG_MASK) != ID_REG_SIG) 228 goto out; 229 230 if (((d-c) & R_ROBIN_BITS) != 0x40) 231 goto out; 232 233 d = bus_space_read_1(iot, ioh, ID_REG); 234 if ((d & ID_REG_MASK) != ID_REG_SIG) 235 goto out; 236 237 if (((d-c) & R_ROBIN_BITS) != 0x80) 238 goto out; 239 240 d = bus_space_read_1(iot, ioh, ID_REG); 241 if ((d & ID_REG_MASK) != ID_REG_SIG) 242 goto out; 243 244 if (((d-c) & R_ROBIN_BITS) != 0xC0) 245 goto out; 246 247 d = bus_space_read_1(iot, ioh, ID_REG); 248 if ((d & ID_REG_MASK) != ID_REG_SIG) 249 goto out; 250 251 if (((d-c) & R_ROBIN_BITS) != 0x00) 252 goto out; 253 254 #ifdef IYDEBUG 255 printf("iyprobe verified working ID reg.\n"); 256 #endif 257 258 if (eepromreadall(iot, ioh, eaddr, 8)) 259 goto out; 260 261 if (ia->ia_irq == IRQUNK) 262 ia->ia_irq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 263 264 if (ia->ia_irq >= sizeof(eepro_revirqmap)) 265 goto out; 266 267 if (eepro_revirqmap[ia->ia_irq] == 0xff) 268 goto out; 269 270 /* now lets reset the chip */ 271 272 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 273 delay(200); 274 275 ia->ia_iosize = 16; 276 277 bus_space_unmap(iot, ioh, 16); 278 return 1; /* found */ 279 out: 280 bus_space_unmap(iot, ioh, 16); 281 return 0; 282 } 283 284 void 285 iyattach(parent, self, aux) 286 struct device *parent, *self; 287 void *aux; 288 { 289 struct iy_softc *sc = (void *)self; 290 struct isa_attach_args *ia = aux; 291 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 292 bus_space_tag_t iot; 293 bus_space_handle_t ioh; 294 unsigned temp; 295 u_int16_t eaddr[8]; 296 u_int8_t myaddr[ETHER_ADDR_LEN]; 297 int eirq; 298 299 iot = ia->ia_iot; 300 301 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) { 302 printf(": can't map i/o space\n"); 303 return; 304 } 305 306 sc->sc_iot = iot; 307 sc->sc_ioh = ioh; 308 309 sc->mappedirq = eepro_revirqmap[ia->ia_irq]; 310 311 /* now let's reset the chip */ 312 313 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 314 delay(200); 315 316 iyprobemem(sc); 317 318 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 319 ifp->if_softc = sc; 320 ifp->if_start = iystart; 321 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 322 | IFF_MULTICAST; 323 324 sc->doing_mc_setup = 0; 325 326 ifp->if_ioctl = iyioctl; 327 ifp->if_watchdog = iywatchdog; 328 329 (void)eepromreadall(iot, ioh, eaddr, 8); 330 sc->hard_vers = eaddr[EEPW6] & EEPP_BoardRev; 331 332 #ifdef DIAGNOSTICS 333 if ((eaddr[EEPPEther0] != 334 eepromread(iot, ioh, EEPPEther0a)) && 335 (eaddr[EEPPEther1] != 336 eepromread(iot, ioh, EEPPEther1a)) && 337 (eaddr[EEPPEther2] != 338 eepromread(iot, ioh, EEPPEther2a))) 339 340 printf("EEPROM Ethernet address differs from copy\n"); 341 #endif 342 343 myaddr[1] = eaddr[EEPPEther0] & 0xFF; 344 myaddr[0] = eaddr[EEPPEther0] >> 8; 345 myaddr[3] = eaddr[EEPPEther1] & 0xFF; 346 myaddr[2] = eaddr[EEPPEther1] >> 8; 347 myaddr[5] = eaddr[EEPPEther2] & 0xFF; 348 myaddr[4] = eaddr[EEPPEther2] >> 8; 349 350 ifmedia_init(&sc->iy_ifmedia, 0, iy_mediachange, iy_mediastatus); 351 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_2, 0, NULL); 352 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_5, 0, NULL); 353 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 354 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 355 ifmedia_set(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO); 356 /* Attach the interface. */ 357 if_attach(ifp); 358 ether_ifattach(ifp, myaddr); 359 printf(": address %s, rev. %d, %d kB\n", 360 ether_sprintf(myaddr), 361 sc->hard_vers, sc->sram/1024); 362 363 eirq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 364 if (eirq != ia->ia_irq) 365 printf("%s: EEPROM irq setting %d ignored\n", 366 sc->sc_dev.dv_xname, eirq); 367 368 #if NBPFILTER > 0 369 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 370 #endif 371 372 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 373 IPL_NET, iyintr, sc); 374 375 #if NRND > 0 376 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 377 RND_TYPE_NET, 0); 378 #endif 379 380 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 381 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 382 } 383 384 void 385 iystop(sc) 386 struct iy_softc *sc; 387 { 388 bus_space_tag_t iot; 389 bus_space_handle_t ioh; 390 #ifdef IYDEBUG 391 u_int p, v; 392 #endif 393 394 iot = sc->sc_iot; 395 ioh = sc->sc_ioh; 396 397 bus_space_write_1(iot, ioh, COMMAND_REG, RCV_DISABLE_CMD); 398 399 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 400 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); 401 402 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 403 delay(200); 404 #ifdef IYDEBUG 405 printf("%s: dumping tx chain (st 0x%x end 0x%x last 0x%x)\n", 406 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 407 p = sc->tx_last; 408 if (!p) 409 p = sc->tx_start; 410 do { 411 bus_space_write_2(iot, ioh, HOST_ADDR_REG, p); 412 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 413 printf("0x%04x: %b ", p, v, "\020\006Ab\010Dn"); 414 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 415 printf("0x%b", v, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL"); 416 p = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 417 printf(" 0x%04x", p); 418 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 419 printf(" 0x%b\n", v, "\020\020Ch"); 420 421 } while (v & 0x8000); 422 #endif 423 sc->tx_start = sc->tx_end = sc->rx_size; 424 sc->tx_last = 0; 425 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 426 } 427 428 void 429 iyreset(sc) 430 struct iy_softc *sc; 431 { 432 int s; 433 s = splnet(); 434 iystop(sc); 435 iyinit(sc); 436 splx(s); 437 } 438 439 void 440 iyinit(sc) 441 struct iy_softc *sc; 442 { 443 int i; 444 unsigned temp; 445 struct ifnet *ifp; 446 bus_space_tag_t iot; 447 bus_space_handle_t ioh; 448 449 iot = sc->sc_iot; 450 ioh = sc->sc_ioh; 451 452 ifp = &sc->sc_ethercom.ec_if; 453 #ifdef IYDEBUG 454 printf("ifp is %p\n", ifp); 455 #endif 456 457 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 458 459 temp = bus_space_read_1(iot, ioh, EEPROM_REG); 460 if (temp & 0x10) 461 bus_space_write_1(iot, ioh, EEPROM_REG, temp & ~0x10); 462 463 for (i=0; i<6; ++i) { 464 bus_space_write_1(iot, ioh, I_ADD(i), LLADDR(ifp->if_sadl)[i]); 465 } 466 467 temp = bus_space_read_1(iot, ioh, REG1); 468 bus_space_write_1(iot, ioh, REG1, 469 temp | XMT_CHAIN_INT | XMT_CHAIN_ERRSTOP | RCV_DISCARD_BAD); 470 471 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 472 temp = MATCH_ALL; 473 } else if (sc->sc_ethercom.ec_multicnt) { 474 temp = MATCH_MULTI; 475 } else 476 temp = MATCH_ID; 477 478 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 479 480 #ifdef IYDEBUG 481 printf("%s: RECV_MODES set to %b\n", sc->sc_dev.dv_xname, 482 temp, "\020\1PRMSC\2NOBRDST\3SEECRC\4LENGTH\5NOSaIns\6MultiIA"); 483 #endif 484 /* XXX VOODOO */ 485 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 486 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 487 /* XXX END OF VOODOO */ 488 489 490 delay(500000); /* for the hardware to test for the connector */ 491 492 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 493 #ifdef IYDEBUG 494 printf("%s: media select was 0x%b ", sc->sc_dev.dv_xname, 495 temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC"); 496 #endif 497 temp = (temp & TEST_MODE_MASK); 498 499 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 500 case IFM_10_5: 501 temp &= ~ (BNC_BIT | TPE_BIT); 502 break; 503 504 case IFM_10_2: 505 temp = (temp & ~TPE_BIT) | BNC_BIT; 506 break; 507 508 case IFM_10_T: 509 temp = (temp & ~BNC_BIT) | TPE_BIT; 510 break; 511 default: 512 /* nothing; leave as it is */ 513 } 514 switch (temp & (BNC_BIT | TPE_BIT)) { 515 case BNC_BIT: 516 sc->iy_media = IFM_ETHER | IFM_10_2; 517 break; 518 case TPE_BIT: 519 sc->iy_media = IFM_ETHER | IFM_10_T; 520 break; 521 default: 522 sc->iy_media = IFM_ETHER | IFM_10_5; 523 } 524 525 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 526 #ifdef IYDEBUG 527 printf("changed to 0x%b\n", 528 temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC"); 529 #endif 530 531 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 532 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 533 bus_space_write_1(iot, ioh, 0, BANK_SEL(1)); 534 535 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 536 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 537 538 #ifdef IYDEBUG 539 printf("%s: int no was %b\n", sc->sc_dev.dv_xname, 540 temp, "\020\4bad_irq\010flash/boot present"); 541 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 542 printf("%s: int no now 0x%02x\n", sc->sc_dev.dv_xname, 543 temp, "\020\4BAD IRQ\010flash/boot present"); 544 #endif 545 546 547 bus_space_write_1(iot, ioh, RCV_LOWER_LIMIT_REG, 0); 548 bus_space_write_1(iot, ioh, RCV_UPPER_LIMIT_REG, (sc->rx_size - 2) >> 8); 549 bus_space_write_1(iot, ioh, XMT_LOWER_LIMIT_REG, sc->rx_size >> 8); 550 bus_space_write_1(iot, ioh, XMT_UPPER_LIMIT_REG, sc->sram >> 8); 551 552 temp = bus_space_read_1(iot, ioh, REG1); 553 #ifdef IYDEBUG 554 printf("%s: HW access is %b\n", sc->sc_dev.dv_xname, 555 temp, "\020\2WORD_WIDTH\010INT_ENABLE"); 556 #endif 557 bus_space_write_1(iot, ioh, REG1, temp | INT_ENABLE); /* XXX what about WORD_WIDTH? */ 558 559 #ifdef IYDEBUG 560 temp = bus_space_read_1(iot, ioh, REG1); 561 printf("%s: HW access is %b\n", sc->sc_dev.dv_xname, 562 temp, "\020\2WORD_WIDTH\010INT_ENABLE"); 563 #endif 564 565 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 566 567 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS & ~(RX_BIT|TX_BIT)); 568 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); /* clear ints */ 569 570 bus_space_write_2(iot, ioh, RCV_START_LOW, 0); 571 bus_space_write_2(iot, ioh, RCV_STOP_LOW, sc->rx_size - 2); 572 sc->rx_start = 0; 573 574 bus_space_write_1(iot, ioh, 0, SEL_RESET_CMD); 575 delay(200); 576 577 bus_space_write_2(iot, ioh, XMT_ADDR_REG, sc->rx_size); 578 579 sc->tx_start = sc->tx_end = sc->rx_size; 580 sc->tx_last = 0; 581 582 bus_space_write_1(iot, ioh, 0, RCV_ENABLE_CMD); 583 584 ifp->if_flags |= IFF_RUNNING; 585 ifp->if_flags &= ~IFF_OACTIVE; 586 } 587 588 void 589 iystart(ifp) 590 struct ifnet *ifp; 591 { 592 struct iy_softc *sc; 593 594 595 struct mbuf *m0, *m; 596 u_int len, pad, last, end; 597 u_int llen, residual; 598 int avail; 599 caddr_t data; 600 u_int16_t resval, stat; 601 bus_space_tag_t iot; 602 bus_space_handle_t ioh; 603 604 #ifdef IYDEBUG 605 printf("iystart called\n"); 606 #endif 607 sc = ifp->if_softc; 608 609 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 610 return; 611 612 iot = sc->sc_iot; 613 ioh = sc->sc_ioh; 614 615 while ((m0 = ifp->if_snd.ifq_head) != NULL) { 616 #ifdef IYDEBUG 617 printf("%s: trying to write another packet to the hardware\n", 618 sc->sc_dev.dv_xname); 619 #endif 620 621 /* We need to use m->m_pkthdr.len, so require the header */ 622 if ((m0->m_flags & M_PKTHDR) == 0) 623 panic("iystart: no header mbuf"); 624 625 len = m0->m_pkthdr.len; 626 pad = len & 1; 627 628 #ifdef IYDEBUG 629 printf("%s: length is %d.\n", sc->sc_dev.dv_xname, len); 630 #endif 631 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 632 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 633 } 634 635 if (len + pad > ETHER_MAX_LEN) { 636 /* packet is obviously too large: toss it */ 637 ++ifp->if_oerrors; 638 IF_DEQUEUE(&ifp->if_snd, m0); 639 m_freem(m0); 640 continue; 641 } 642 643 #if NBPFILTER > 0 644 if (ifp->if_bpf) 645 bpf_mtap(ifp->if_bpf, m0); 646 #endif 647 648 avail = sc->tx_start - sc->tx_end; 649 if (avail <= 0) 650 avail += sc->tx_size; 651 652 #ifdef IYDEBUG 653 printf("%s: avail is %d.\n", sc->sc_dev.dv_xname, avail); 654 #endif 655 /* 656 * we MUST RUN at splnet here --- 657 * XXX todo: or even turn off the boards ints ??? hm... 658 */ 659 660 /* See if there is room to put another packet in the buffer. */ 661 662 if ((len+pad+2*I595_XMT_HDRLEN) > avail) { 663 #ifdef IYDEBUG 664 printf("%s: len = %d, avail = %d, setting OACTIVE\n", 665 sc->sc_dev.dv_xname, len, avail); 666 #endif 667 ifp->if_flags |= IFF_OACTIVE; 668 return; 669 } 670 671 /* we know it fits in the hardware now, so dequeue it */ 672 IF_DEQUEUE(&ifp->if_snd, m0); 673 674 last = sc->tx_end; 675 end = last + pad + len + I595_XMT_HDRLEN; 676 677 if (end >= sc->sram) { 678 if ((sc->sram - last) <= I595_XMT_HDRLEN) { 679 /* keep header in one piece */ 680 last = sc->rx_size; 681 end = last + pad + len + I595_XMT_HDRLEN; 682 } else 683 end -= sc->tx_size; 684 } 685 686 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 687 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 688 htole16(XMT_CMD)); 689 690 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 691 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 692 693 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 694 htole16(len + pad)); 695 696 residual = resval = 0; 697 698 while ((m = m0)!=0) { 699 data = mtod(m, caddr_t); 700 llen = m->m_len; 701 if (residual) { 702 #ifdef IYDEBUG 703 printf("%s: merging residual with next mbuf.\n", 704 sc->sc_dev.dv_xname); 705 #endif 706 resval |= *data << 8; 707 bus_space_write_stream_2(iot, ioh, 708 MEM_PORT_REG, resval); 709 --llen; 710 ++data; 711 } 712 if (llen > 1) 713 bus_space_write_multi_stream_2(iot, ioh, 714 MEM_PORT_REG, data, llen>>1); 715 residual = llen & 1; 716 if (residual) { 717 resval = *(data + llen - 1); 718 #ifdef IYDEBUG 719 printf("%s: got odd mbuf to send.\n", 720 sc->sc_dev.dv_xname); 721 #endif 722 } 723 724 MFREE(m, m0); 725 } 726 727 if (residual) 728 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 729 resval); 730 731 pad >>= 1; 732 while (pad-- > 0) 733 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 0); 734 735 #ifdef IYDEBUG 736 printf("%s: new last = 0x%x, end = 0x%x.\n", 737 sc->sc_dev.dv_xname, last, end); 738 printf("%s: old start = 0x%x, end = 0x%x, last = 0x%x\n", 739 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 740 #endif 741 742 if (sc->tx_start != sc->tx_end) { 743 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 744 sc->tx_last + XMT_COUNT); 745 746 /* 747 * XXX We keep stat in le order, to potentially save 748 * a byte swap. 749 */ 750 stat = bus_space_read_stream_2(iot, ioh, MEM_PORT_REG); 751 752 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 753 sc->tx_last + XMT_CHAIN); 754 755 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 756 htole16(last)); 757 758 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 759 stat | htole16(CHAIN)); 760 #ifdef IYDEBUG 761 printf("%s: setting 0x%x to 0x%x\n", 762 sc->sc_dev.dv_xname, sc->tx_last + XMT_COUNT, 763 le16toh(stat) | CHAIN); 764 #endif 765 } 766 stat = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 767 768 /* XXX todo: enable ints here if disabled */ 769 770 ++ifp->if_opackets; 771 772 if (sc->tx_start == sc->tx_end) { 773 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 774 bus_space_write_1(iot, ioh, 0, XMT_CMD); 775 sc->tx_start = last; 776 #ifdef IYDEBUG 777 printf("%s: writing 0x%x to XAR and giving XCMD\n", 778 sc->sc_dev.dv_xname, last); 779 #endif 780 } else { 781 bus_space_write_1(iot, ioh, 0, RESUME_XMT_CMD); 782 #ifdef IYDEBUG 783 printf("%s: giving RESUME_XCMD\n", 784 sc->sc_dev.dv_xname); 785 #endif 786 } 787 sc->tx_last = last; 788 sc->tx_end = end; 789 } 790 } 791 792 793 static __inline void 794 eepromwritebit(iot, ioh, what) 795 bus_space_tag_t iot; 796 bus_space_handle_t ioh; 797 int what; 798 { 799 bus_space_write_1(iot, ioh, EEPROM_REG, what); 800 delay(1); 801 bus_space_write_1(iot, ioh, EEPROM_REG, what|EESK); 802 delay(1); 803 bus_space_write_1(iot, ioh, EEPROM_REG, what); 804 delay(1); 805 } 806 807 static __inline int 808 eepromreadbit(iot, ioh) 809 bus_space_tag_t iot; 810 bus_space_handle_t ioh; 811 { 812 int b; 813 814 bus_space_write_1(iot, ioh, EEPROM_REG, EECS|EESK); 815 delay(1); 816 b = bus_space_read_1(iot, ioh, EEPROM_REG); 817 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); 818 delay(1); 819 820 return ((b & EEDO) != 0); 821 } 822 823 static u_int16_t 824 eepromread(iot, ioh, offset) 825 bus_space_tag_t iot; 826 bus_space_handle_t ioh; 827 int offset; 828 { 829 volatile int i; 830 volatile int j; 831 volatile u_int16_t readval; 832 833 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 834 delay(1); 835 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); /* XXXX??? */ 836 delay(1); 837 838 eepromwritebit(iot, ioh, EECS|EEDI); 839 eepromwritebit(iot, ioh, EECS|EEDI); 840 eepromwritebit(iot, ioh, EECS); 841 842 for (j=5; j>=0; --j) { 843 if ((offset>>j) & 1) 844 eepromwritebit(iot, ioh, EECS|EEDI); 845 else 846 eepromwritebit(iot, ioh, EECS); 847 } 848 849 for (readval=0, i=0; i<16; ++i) { 850 readval<<=1; 851 readval |= eepromreadbit(iot, ioh); 852 } 853 854 bus_space_write_1(iot, ioh, EEPROM_REG, 0|EESK); 855 delay(1); 856 bus_space_write_1(iot, ioh, EEPROM_REG, 0); 857 858 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 859 860 return readval; 861 } 862 863 /* 864 * Device timeout/watchdog routine. Entered if the device neglects to generate 865 * an interrupt after a transmit has been started on it. 866 */ 867 void 868 iywatchdog(ifp) 869 struct ifnet *ifp; 870 { 871 struct iy_softc *sc = ifp->if_softc; 872 873 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 874 ++sc->sc_ethercom.ec_if.if_oerrors; 875 iyreset(sc); 876 } 877 878 /* 879 * What to do upon receipt of an interrupt. 880 */ 881 int 882 iyintr(arg) 883 void *arg; 884 { 885 struct iy_softc *sc = arg; 886 bus_space_tag_t iot; 887 bus_space_handle_t ioh; 888 889 u_short status; 890 891 iot = sc->sc_iot; 892 ioh = sc->sc_ioh; 893 894 status = bus_space_read_1(iot, ioh, STATUS_REG); 895 #ifdef IYDEBUG 896 if (status & ALL_INTS) { 897 printf("%s: got interupt %b", sc->sc_dev.dv_xname, status, 898 "\020\1RX_STP\2RX\3TX\4EXEC"); 899 if (status & EXEC_INT) 900 printf(" event %b\n", bus_space_read_1(iot, ioh, 0), 901 "\020\6ABORT"); 902 else 903 printf("\n"); 904 } 905 #endif 906 if ((status & (RX_INT | TX_INT)) == 0) 907 return 0; 908 909 if (status & RX_INT) { 910 iy_intr_rx(sc); 911 bus_space_write_1(iot, ioh, STATUS_REG, RX_INT); 912 } 913 if (status & TX_INT) { 914 iy_intr_tx(sc); 915 bus_space_write_1(iot, ioh, STATUS_REG, TX_INT); 916 } 917 918 #if NRND > 0 919 rnd_add_uint32(&sc->rnd_source, status); 920 #endif 921 922 return 1; 923 } 924 925 void 926 iyget(sc, iot, ioh, rxlen) 927 struct iy_softc *sc; 928 bus_space_tag_t iot; 929 bus_space_handle_t ioh; 930 int rxlen; 931 { 932 struct mbuf *m, *top, **mp; 933 struct ether_header *eh; 934 struct ifnet *ifp; 935 int len; 936 937 ifp = &sc->sc_ethercom.ec_if; 938 939 MGETHDR(m, M_DONTWAIT, MT_DATA); 940 if (m == 0) 941 goto dropped; 942 m->m_pkthdr.rcvif = ifp; 943 m->m_pkthdr.len = rxlen; 944 len = MHLEN; 945 top = 0; 946 mp = ⊤ 947 948 while (rxlen > 0) { 949 if (top) { 950 MGET(m, M_DONTWAIT, MT_DATA); 951 if (m == 0) { 952 m_freem(top); 953 goto dropped; 954 } 955 len = MLEN; 956 } 957 if (rxlen >= MINCLSIZE) { 958 MCLGET(m, M_DONTWAIT); 959 if ((m->m_flags & M_EXT) == 0) { 960 m_free(m); 961 m_freem(top); 962 goto dropped; 963 } 964 len = MCLBYTES; 965 } 966 len = min(rxlen, len); 967 if (len > 1) { 968 len &= ~1; 969 970 bus_space_read_multi_stream_2(iot, ioh, MEM_PORT_REG, 971 mtod(m, caddr_t), len/2); 972 } else { 973 #ifdef IYDEBUG 974 printf("%s: received odd mbuf\n", sc->sc_dev.dv_xname); 975 #endif 976 *(mtod(m, caddr_t)) = bus_space_read_stream_2(iot, ioh, 977 MEM_PORT_REG); 978 } 979 m->m_len = len; 980 rxlen -= len; 981 *mp = m; 982 mp = &m->m_next; 983 } 984 /* XXX receive the top here */ 985 ++ifp->if_ipackets; 986 987 eh = mtod(top, struct ether_header *); 988 989 #if NBPFILTER > 0 990 if (ifp->if_bpf) { 991 bpf_mtap(ifp->if_bpf, top); 992 if ((ifp->if_flags & IFF_PROMISC) && 993 (eh->ether_dhost[0] & 1) == 0 && 994 bcmp(eh->ether_dhost, 995 LLADDR(ifp->if_sadl), sizeof(eh->ether_dhost)) != 0) { 996 997 m_freem(top); 998 return; 999 } 1000 } 1001 #endif 1002 (*ifp->if_input)(ifp, top); 1003 return; 1004 1005 dropped: 1006 ++ifp->if_ierrors; 1007 return; 1008 } 1009 1010 void 1011 iy_intr_rx(sc) 1012 struct iy_softc *sc; 1013 { 1014 struct ifnet *ifp; 1015 bus_space_tag_t iot; 1016 bus_space_handle_t ioh; 1017 1018 u_int rxadrs, rxevnt, rxstatus, rxnext, rxlen; 1019 1020 iot = sc->sc_iot; 1021 ioh = sc->sc_ioh; 1022 ifp = &sc->sc_ethercom.ec_if; 1023 1024 rxadrs = sc->rx_start; 1025 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxadrs); 1026 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 1027 rxnext = 0; 1028 1029 while (rxevnt == RCV_DONE) { 1030 rxstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1031 MEM_PORT_REG)); 1032 rxnext = le16toh(bus_space_read_stream_2(iot, ioh, 1033 MEM_PORT_REG)); 1034 rxlen = le16toh(bus_space_read_stream_2(iot, ioh, 1035 MEM_PORT_REG)); 1036 #ifdef IYDEBUG 1037 printf("%s: pck at 0x%04x stat %b next 0x%x len 0x%x\n", 1038 sc->sc_dev.dv_xname, rxadrs, rxstatus, 1039 "\020\1RCLD\2IA_MCH\010SHORT\011OVRN\013ALGERR" 1040 "\014CRCERR\015LENERR\016RCVOK\020TYP", 1041 rxnext, rxlen); 1042 #endif 1043 iyget(sc, iot, ioh, rxlen); 1044 1045 /* move stop address */ 1046 bus_space_write_2(iot, ioh, RCV_STOP_LOW, 1047 rxnext == 0 ? sc->rx_size - 2 : rxnext - 2); 1048 1049 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxnext); 1050 rxadrs = rxnext; 1051 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, 1052 MEM_PORT_REG)); 1053 } 1054 sc->rx_start = rxnext; 1055 } 1056 1057 void 1058 iy_intr_tx(sc) 1059 struct iy_softc *sc; 1060 { 1061 bus_space_tag_t iot; 1062 bus_space_handle_t ioh; 1063 struct ifnet *ifp; 1064 u_int txstatus, txstat2, txlen, txnext; 1065 1066 ifp = &sc->sc_ethercom.ec_if; 1067 iot = sc->sc_iot; 1068 ioh = sc->sc_ioh; 1069 1070 while (sc->tx_start != sc->tx_end) { 1071 bus_space_write_2(iot, ioh, HOST_ADDR_REG, sc->tx_start); 1072 txstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1073 MEM_PORT_REG)); 1074 1075 if ((txstatus & (TX_DONE|CMD_MASK)) != (TX_DONE|XMT_CMD)) 1076 break; 1077 1078 txstat2 = le16toh(bus_space_read_stream_2(iot, ioh, 1079 MEM_PORT_REG)); 1080 txnext = le16toh(bus_space_read_stream_2(iot, ioh, 1081 MEM_PORT_REG)); 1082 txlen = le16toh(bus_space_read_stream_2(iot, ioh, 1083 MEM_PORT_REG)); 1084 #ifdef IYDEBUG 1085 printf("txstat 0x%x stat2 0x%b next 0x%x len 0x%x\n", 1086 txstatus, txstat2, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF" 1087 "\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 1088 txnext, txlen); 1089 #endif 1090 if (txlen & CHAIN) 1091 sc->tx_start = txnext; 1092 else 1093 sc->tx_start = sc->tx_end; 1094 ifp->if_flags &= ~IFF_OACTIVE; 1095 1096 if ((txstat2 & 0x2000) == 0) 1097 ++ifp->if_oerrors; 1098 if (txstat2 & 0x000f) 1099 ifp->if_oerrors += txstat2 & 0x000f; 1100 } 1101 ifp->if_flags &= ~IFF_OACTIVE; 1102 } 1103 1104 int 1105 iyioctl(ifp, cmd, data) 1106 struct ifnet *ifp; 1107 u_long cmd; 1108 caddr_t data; 1109 { 1110 struct iy_softc *sc; 1111 struct ifaddr *ifa; 1112 struct ifreq *ifr; 1113 int s, error = 0; 1114 1115 sc = ifp->if_softc; 1116 ifa = (struct ifaddr *)data; 1117 ifr = (struct ifreq *)data; 1118 1119 #ifdef IYDEBUG 1120 printf("iyioctl called with ifp 0x%p (%s) cmd 0x%x data 0x%p\n", 1121 ifp, ifp->if_xname, cmd, data); 1122 #endif 1123 1124 s = splnet(); 1125 1126 switch (cmd) { 1127 1128 case SIOCSIFADDR: 1129 ifp->if_flags |= IFF_UP; 1130 1131 switch (ifa->ifa_addr->sa_family) { 1132 #ifdef INET 1133 case AF_INET: 1134 iyinit(sc); 1135 arp_ifinit(ifp, ifa); 1136 break; 1137 #endif 1138 #ifdef NS 1139 /* XXX - This code is probably wrong. */ 1140 case AF_NS: 1141 { 1142 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1143 1144 if (ns_nullhost(*ina)) 1145 ina->x_host = *(union ns_host *) 1146 LLADDR(ifp->if_sadl); 1147 else 1148 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1149 ETHER_ADDR_LEN); 1150 /* Set new address. */ 1151 iyinit(sc); 1152 break; 1153 } 1154 #endif /* NS */ 1155 default: 1156 iyinit(sc); 1157 break; 1158 } 1159 break; 1160 1161 case SIOCSIFFLAGS: 1162 sc->promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI); 1163 if ((ifp->if_flags & IFF_UP) == 0 && 1164 (ifp->if_flags & IFF_RUNNING) != 0) { 1165 /* 1166 * If interface is marked down and it is running, then 1167 * stop it. 1168 */ 1169 iystop(sc); 1170 ifp->if_flags &= ~IFF_RUNNING; 1171 } else if ((ifp->if_flags & IFF_UP) != 0 && 1172 (ifp->if_flags & IFF_RUNNING) == 0) { 1173 /* 1174 * If interface is marked up and it is stopped, then 1175 * start it. 1176 */ 1177 iyinit(sc); 1178 } else { 1179 /* 1180 * Reset the interface to pick up changes in any other 1181 * flags that affect hardware registers. 1182 */ 1183 iystop(sc); 1184 iyinit(sc); 1185 } 1186 #ifdef IYDEBUGX 1187 if (ifp->if_flags & IFF_DEBUG) 1188 sc->sc_debug = IFY_ALL; 1189 else 1190 sc->sc_debug = 0; 1191 #endif 1192 break; 1193 1194 case SIOCADDMULTI: 1195 case SIOCDELMULTI: 1196 error = (cmd == SIOCADDMULTI) ? 1197 ether_addmulti(ifr, &sc->sc_ethercom): 1198 ether_delmulti(ifr, &sc->sc_ethercom); 1199 1200 if (error == ENETRESET) { 1201 /* 1202 * Multicast list has changed; set the hardware filter 1203 * accordingly. 1204 */ 1205 iyreset(sc); /* XXX can't make it work otherwise */ 1206 iy_mc_reset(sc); 1207 error = 0; 1208 } 1209 break; 1210 1211 case SIOCSIFMEDIA: 1212 case SIOCGIFMEDIA: 1213 error = ifmedia_ioctl(ifp, ifr, &sc->iy_ifmedia, cmd); 1214 break; 1215 default: 1216 error = EINVAL; 1217 } 1218 splx(s); 1219 return error; 1220 } 1221 1222 int 1223 iy_mediachange(ifp) 1224 struct ifnet *ifp; 1225 { 1226 struct iy_softc *sc = ifp->if_softc; 1227 1228 if (IFM_TYPE(sc->iy_ifmedia.ifm_media) != IFM_ETHER) 1229 return EINVAL; 1230 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 1231 case IFM_10_5: 1232 case IFM_10_2: 1233 case IFM_10_T: 1234 case IFM_AUTO: 1235 iystop(sc); 1236 iyinit(sc); 1237 return 0; 1238 default: 1239 return EINVAL; 1240 } 1241 } 1242 1243 void 1244 iy_mediastatus(ifp, ifmr) 1245 struct ifnet *ifp; 1246 struct ifmediareq *ifmr; 1247 { 1248 struct iy_softc *sc = ifp->if_softc; 1249 1250 ifmr->ifm_active = sc->iy_media; 1251 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1252 } 1253 1254 1255 static void 1256 iy_mc_setup(sc) 1257 struct iy_softc *sc; 1258 { 1259 struct ether_multi *enm; 1260 struct ether_multistep step; 1261 struct ethercom *ecp; 1262 struct ifnet *ifp; 1263 bus_space_tag_t iot; 1264 bus_space_handle_t ioh; 1265 int avail, last /*, end*/ , len; 1266 int timeout; 1267 volatile u_int16_t dum; 1268 u_int8_t temp; 1269 1270 1271 ecp = &sc->sc_ethercom; 1272 ifp = &ecp->ec_if; 1273 1274 iot = sc->sc_iot; 1275 ioh = sc->sc_ioh; 1276 1277 len = 6 * ecp->ec_multicnt + 6; 1278 1279 avail = sc->tx_start - sc->tx_end; 1280 if (avail <= 0) 1281 avail += sc->tx_size; 1282 if (ifp->if_flags & IFF_DEBUG) 1283 printf("%s: iy_mc_setup called, %d addresses, " 1284 "%d/%d bytes needed/avail\n", ifp->if_xname, 1285 ecp->ec_multicnt, len + I595_XMT_HDRLEN, avail); 1286 1287 last = sc->rx_size; 1288 1289 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1290 bus_space_write_1(iot, ioh, RECV_MODES_REG, MATCH_MULTI); 1291 /* XXX VOODOO */ 1292 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1293 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1294 /* XXX END OF VOODOO */ 1295 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1296 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 1297 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(MC_SETUP_CMD)); 1298 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1299 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1300 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(len)); 1301 1302 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1303 LLADDR(ifp->if_sadl), 3); 1304 1305 ETHER_FIRST_MULTI(step, ecp, enm); 1306 while(enm) { 1307 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1308 enm->enm_addrlo, 3); 1309 1310 ETHER_NEXT_MULTI(step, enm); 1311 } 1312 dum = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 1313 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 1314 bus_space_write_1(iot, ioh, 0, MC_SETUP_CMD); 1315 1316 1317 sc->tx_start = sc->rx_size; 1318 sc->tx_end = sc->rx_size + I595_XMT_HDRLEN + len; 1319 1320 for (timeout=0; timeout<100; timeout++) { 1321 DELAY(2); 1322 if ((bus_space_read_1(iot, ioh, STATUS_REG) & EXEC_INT) == 0) 1323 continue; 1324 1325 temp = bus_space_read_1(iot, ioh, 0); 1326 bus_space_write_1(iot, ioh, STATUS_REG, EXEC_INT); 1327 #ifdef DIAGNOSTIC 1328 if (temp & 0x20) { 1329 printf("%s: mc setup failed, %d usec\n", 1330 sc->sc_dev.dv_xname, timeout * 2); 1331 } else if (((temp & 0x0f) == 0x03) && 1332 (ifp->if_flags & IFF_DEBUG)) { 1333 printf("%s: mc setup done, %d usec\n", 1334 sc->sc_dev.dv_xname, timeout * 2); 1335 } 1336 #endif 1337 break; 1338 } 1339 sc->tx_start = sc->tx_end; 1340 ifp->if_flags &= ~IFF_OACTIVE; 1341 1342 } 1343 1344 static void 1345 iy_mc_reset(sc) 1346 struct iy_softc *sc; 1347 { 1348 struct ether_multi *enm; 1349 struct ether_multistep step; 1350 struct ethercom *ecp; 1351 struct ifnet *ifp; 1352 bus_space_tag_t iot; 1353 bus_space_handle_t ioh; 1354 u_int16_t temp; 1355 1356 ecp = &sc->sc_ethercom; 1357 ifp = &ecp->ec_if; 1358 1359 iot = sc->sc_iot; 1360 ioh = sc->sc_ioh; 1361 1362 if (ecp->ec_multicnt > 63) { 1363 ifp->if_flags |= IFF_ALLMULTI; 1364 1365 } else if (ecp->ec_multicnt > 0) { 1366 /* 1367 * Step through the list of addresses. 1368 */ 1369 ETHER_FIRST_MULTI(step, ecp, enm); 1370 while(enm) { 1371 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1372 ifp->if_flags |= IFF_ALLMULTI; 1373 goto setupmulti; 1374 } 1375 ETHER_NEXT_MULTI(step, enm); 1376 } 1377 /* OK, we really need to do it now: */ 1378 #if 0 1379 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) 1380 != IFF_RUNNING) { 1381 ifp->if_flags |= IFF_OACTIVE; 1382 sc->want_mc_setup = 1; 1383 return; 1384 } 1385 #endif 1386 iy_mc_setup(sc); 1387 } else { 1388 ifp->if_flags &= ~IFF_ALLMULTI; 1389 } 1390 1391 setupmulti: 1392 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1393 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 1394 temp = MATCH_ALL; 1395 } else if (sc->sc_ethercom.ec_multicnt) { 1396 temp = MATCH_MULTI; 1397 } else 1398 temp = MATCH_ID; 1399 1400 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 1401 /* XXX VOODOO */ 1402 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1403 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1404 /* XXX END OF VOODOO */ 1405 1406 /* XXX TBD: setup hardware for all multicasts */ 1407 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1408 return; 1409 } 1410 1411 #ifdef IYDEBUG 1412 void 1413 print_rbd(rbd) 1414 volatile struct ie_recv_buf_desc *rbd; 1415 { 1416 1417 printf("RBD at %08lx:\nactual %04x, next %04x, buffer %08x\n" 1418 "length %04x, mbz %04x\n", (u_long)rbd, rbd->ie_rbd_actual, 1419 rbd->ie_rbd_next, rbd->ie_rbd_buffer, rbd->ie_rbd_length, 1420 rbd->mbz); 1421 } 1422 #endif 1423 1424 void 1425 iyprobemem(sc) 1426 struct iy_softc *sc; 1427 { 1428 bus_space_tag_t iot; 1429 bus_space_handle_t ioh; 1430 int testing; 1431 1432 iot = sc->sc_iot; 1433 ioh = sc->sc_ioh; 1434 1435 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 1436 delay(1); 1437 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 4096-2); 1438 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1439 1440 for (testing=65536; testing >= 4096; testing >>= 1) { 1441 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1442 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xdead); 1443 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1444 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xdead) { 1445 #ifdef IYMEMDEBUG 1446 printf("%s: Didn't keep 0xdead at 0x%x\n", 1447 sc->sc_dev.dv_xname, testing-2); 1448 #endif 1449 continue; 1450 } 1451 1452 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1453 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xbeef); 1454 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1455 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xbeef) { 1456 #ifdef IYMEMDEBUG 1457 printf("%s: Didn't keep 0xbeef at 0x%x\n", 1458 sc->sc_dev.dv_xname, testing-2); 1459 #endif 1460 continue; 1461 } 1462 1463 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1464 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1465 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing >> 1); 1466 bus_space_write_2(iot, ioh, MEM_PORT_REG, testing >> 1); 1467 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1468 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) == (testing >> 1)) { 1469 #ifdef IYMEMDEBUG 1470 printf("%s: 0x%x alias of 0x0\n", 1471 sc->sc_dev.dv_xname, testing >> 1); 1472 #endif 1473 continue; 1474 } 1475 1476 break; 1477 } 1478 1479 sc->sram = testing; 1480 1481 switch(testing) { 1482 case 65536: 1483 /* 4 NFS packets + overhead RX, 2 NFS + overhead TX */ 1484 sc->rx_size = 44*1024; 1485 break; 1486 1487 case 32768: 1488 /* 2 NFS packets + overhead RX, 1 NFS + overhead TX */ 1489 sc->rx_size = 22*1024; 1490 break; 1491 1492 case 16384: 1493 /* 1 NFS packet + overhead RX, 4 big packets TX */ 1494 sc->rx_size = 10*1024; 1495 break; 1496 default: 1497 sc->rx_size = testing/2; 1498 break; 1499 } 1500 sc->tx_size = testing - sc->rx_size; 1501 } 1502 1503 static int 1504 eepromreadall(iot, ioh, wordp, maxi) 1505 bus_space_tag_t iot; 1506 bus_space_handle_t ioh; 1507 u_int16_t *wordp; 1508 int maxi; 1509 { 1510 int i; 1511 u_int16_t checksum, tmp; 1512 1513 checksum = 0; 1514 1515 for (i=0; i<EEPP_LENGTH; ++i) { 1516 tmp = eepromread(iot, ioh, i); 1517 checksum += tmp; 1518 if (i<maxi) 1519 wordp[i] = tmp; 1520 } 1521 1522 if (checksum != EEPP_CHKSUM) { 1523 #ifdef IYDEBUG 1524 printf("wrong EEPROM checksum 0x%x should be 0x%x\n", 1525 checksum, EEPP_CHKSUM); 1526 #endif 1527 return 1; 1528 } 1529 return 0; 1530 } 1531
Indexes created Thu Sep 25 02:09:54 GMT 2025