if_iy.c revision 1.43
1 /* $NetBSD: if_iy.c,v 1.43 2000/10/01 23:32:43 thorpej Exp $ */ 2 /* #define IYDEBUG */ 3 /* #define IYMEMDEBUG */ 4 5 /*- 6 * Copyright (c) 1996 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Ignatios Souvatzis. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Supported hardware: 43 * 44 * - Intel EtherExpress Pro/10. 45 * - possibly other boards using the i82595 chip and no special tweaks. 46 */ 47 48 #include "opt_inet.h" 49 #include "opt_ns.h" 50 #include "bpfilter.h" 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/mbuf.h> 56 #include <sys/buf.h> 57 #include <sys/protosw.h> 58 #include <sys/socket.h> 59 #include <sys/ioctl.h> 60 #include <sys/errno.h> 61 #include <sys/syslog.h> 62 #include <sys/device.h> 63 #include <sys/endian.h> 64 #if NRND > 0 65 #include <sys/rnd.h> 66 #endif 67 68 #include <net/if.h> 69 #include <net/if_types.h> 70 #include <net/if_dl.h> 71 72 #include <net/if_ether.h> 73 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #include <net/bpfdesc.h> 77 #endif 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #ifdef NS 88 #include <netns/ns.h> 89 #include <netns/ns_if.h> 90 #endif 91 92 #if defined(SIOCSIFMEDIA) 93 #include <net/if_media.h> 94 #endif 95 96 #include <machine/cpu.h> 97 #include <machine/bus.h> 98 #include <machine/intr.h> 99 100 #include <dev/isa/isareg.h> 101 #include <dev/isa/isavar.h> 102 #include <dev/ic/i82595reg.h> 103 104 /* XXX why isn't this centralized? */ 105 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 106 #define bus_space_write_stream_2 bus_space_write_2 107 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 108 #define bus_space_read_stream_2 bus_space_read_2 109 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 110 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 111 112 /* 113 * Ethernet status, per interface. 114 */ 115 struct iy_softc { 116 struct device sc_dev; 117 void *sc_ih; 118 119 bus_space_tag_t sc_iot; 120 bus_space_handle_t sc_ioh; 121 122 struct ethercom sc_ethercom; 123 124 struct ifmedia iy_ifmedia; 125 int iy_media; 126 127 int mappedirq; 128 129 int hard_vers; 130 131 int promisc; 132 133 int sram, tx_size, rx_size; 134 135 int tx_start, tx_end, tx_last; 136 int rx_start; 137 138 int doing_mc_setup; 139 #ifdef IYDEBUG 140 int sc_debug; 141 #endif 142 143 #if NRND > 0 144 rndsource_element_t rnd_source; 145 #endif 146 }; 147 148 void iywatchdog __P((struct ifnet *)); 149 int iyioctl __P((struct ifnet *, u_long, caddr_t)); 150 int iyintr __P((void *)); 151 void iyinit __P((struct iy_softc *)); 152 void iystop __P((struct iy_softc *)); 153 void iystart __P((struct ifnet *)); 154 155 void iy_intr_rx __P((struct iy_softc *)); 156 void iy_intr_tx __P((struct iy_softc *)); 157 158 void iyreset __P((struct iy_softc *)); 159 void iy_readframe __P((struct iy_softc *, int)); 160 void iy_drop_packet_buffer __P((struct iy_softc *)); 161 void iy_find_mem_size __P((struct iy_softc *)); 162 void iyrint __P((struct iy_softc *)); 163 void iytint __P((struct iy_softc *)); 164 void iyxmit __P((struct iy_softc *)); 165 static void iy_mc_setup __P((struct iy_softc *)); 166 static void iy_mc_reset __P((struct iy_softc *)); 167 void iyget __P((struct iy_softc *, bus_space_tag_t, bus_space_handle_t, int)); 168 void iyprobemem __P((struct iy_softc *)); 169 static __inline void eepromwritebit __P((bus_space_tag_t, bus_space_handle_t, 170 int)); 171 static __inline int eepromreadbit __P((bus_space_tag_t, bus_space_handle_t)); 172 173 #ifdef IYDEBUGX 174 void print_rbd __P((volatile struct iy_recv_buf_desc *)); 175 176 int in_ifrint = 0; 177 int in_iftint = 0; 178 #endif 179 180 int iy_mediachange __P((struct ifnet *)); 181 void iy_mediastatus __P((struct ifnet *, struct ifmediareq *)); 182 183 int iyprobe __P((struct device *, struct cfdata *, void *)); 184 void iyattach __P((struct device *, struct device *, void *)); 185 186 static u_int16_t eepromread __P((bus_space_tag_t, bus_space_handle_t, int)); 187 188 static int eepromreadall __P((bus_space_tag_t, bus_space_handle_t, u_int16_t *, 189 int)); 190 191 struct cfattach iy_ca = { 192 sizeof(struct iy_softc), iyprobe, iyattach 193 }; 194 195 static u_int8_t eepro_irqmap[] = EEPP_INTMAP; 196 static u_int8_t eepro_revirqmap[] = EEPP_RINTMAP; 197 198 int 199 iyprobe(parent, match, aux) 200 struct device *parent; 201 struct cfdata *match; 202 void *aux; 203 { 204 struct isa_attach_args *ia = aux; 205 u_int16_t eaddr[8]; 206 207 bus_space_tag_t iot; 208 bus_space_handle_t ioh; 209 210 u_int8_t c, d; 211 212 iot = ia->ia_iot; 213 214 if (ia->ia_iobase == IOBASEUNK) 215 return 0; 216 217 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) 218 return 0; 219 220 /* try to find the round robin sig: */ 221 222 c = bus_space_read_1(iot, ioh, ID_REG); 223 if ((c & ID_REG_MASK) != ID_REG_SIG) 224 goto out; 225 226 d = bus_space_read_1(iot, ioh, ID_REG); 227 if ((d & ID_REG_MASK) != ID_REG_SIG) 228 goto out; 229 230 if (((d-c) & R_ROBIN_BITS) != 0x40) 231 goto out; 232 233 d = bus_space_read_1(iot, ioh, ID_REG); 234 if ((d & ID_REG_MASK) != ID_REG_SIG) 235 goto out; 236 237 if (((d-c) & R_ROBIN_BITS) != 0x80) 238 goto out; 239 240 d = bus_space_read_1(iot, ioh, ID_REG); 241 if ((d & ID_REG_MASK) != ID_REG_SIG) 242 goto out; 243 244 if (((d-c) & R_ROBIN_BITS) != 0xC0) 245 goto out; 246 247 d = bus_space_read_1(iot, ioh, ID_REG); 248 if ((d & ID_REG_MASK) != ID_REG_SIG) 249 goto out; 250 251 if (((d-c) & R_ROBIN_BITS) != 0x00) 252 goto out; 253 254 #ifdef IYDEBUG 255 printf("iyprobe verified working ID reg.\n"); 256 #endif 257 258 if (eepromreadall(iot, ioh, eaddr, 8)) 259 goto out; 260 261 if (ia->ia_irq == IRQUNK) 262 ia->ia_irq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 263 264 if (ia->ia_irq >= sizeof(eepro_revirqmap)) 265 goto out; 266 267 if (eepro_revirqmap[ia->ia_irq] == 0xff) 268 goto out; 269 270 /* now lets reset the chip */ 271 272 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 273 delay(200); 274 275 ia->ia_iosize = 16; 276 277 bus_space_unmap(iot, ioh, 16); 278 return 1; /* found */ 279 out: 280 bus_space_unmap(iot, ioh, 16); 281 return 0; 282 } 283 284 void 285 iyattach(parent, self, aux) 286 struct device *parent, *self; 287 void *aux; 288 { 289 struct iy_softc *sc = (void *)self; 290 struct isa_attach_args *ia = aux; 291 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 292 bus_space_tag_t iot; 293 bus_space_handle_t ioh; 294 unsigned temp; 295 u_int16_t eaddr[8]; 296 u_int8_t myaddr[ETHER_ADDR_LEN]; 297 int eirq; 298 299 iot = ia->ia_iot; 300 301 if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh)) { 302 printf(": can't map i/o space\n"); 303 return; 304 } 305 306 sc->sc_iot = iot; 307 sc->sc_ioh = ioh; 308 309 sc->mappedirq = eepro_revirqmap[ia->ia_irq]; 310 311 /* now let's reset the chip */ 312 313 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 314 delay(200); 315 316 iyprobemem(sc); 317 318 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 319 ifp->if_softc = sc; 320 ifp->if_start = iystart; 321 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 322 | IFF_MULTICAST; 323 324 sc->doing_mc_setup = 0; 325 326 ifp->if_ioctl = iyioctl; 327 ifp->if_watchdog = iywatchdog; 328 329 (void)eepromreadall(iot, ioh, eaddr, 8); 330 sc->hard_vers = eaddr[EEPW6] & EEPP_BoardRev; 331 332 #ifdef DIAGNOSTICS 333 if ((eaddr[EEPPEther0] != 334 eepromread(iot, ioh, EEPPEther0a)) && 335 (eaddr[EEPPEther1] != 336 eepromread(iot, ioh, EEPPEther1a)) && 337 (eaddr[EEPPEther2] != 338 eepromread(iot, ioh, EEPPEther2a))) 339 340 printf("EEPROM Ethernet address differs from copy\n"); 341 #endif 342 343 myaddr[1] = eaddr[EEPPEther0] & 0xFF; 344 myaddr[0] = eaddr[EEPPEther0] >> 8; 345 myaddr[3] = eaddr[EEPPEther1] & 0xFF; 346 myaddr[2] = eaddr[EEPPEther1] >> 8; 347 myaddr[5] = eaddr[EEPPEther2] & 0xFF; 348 myaddr[4] = eaddr[EEPPEther2] >> 8; 349 350 ifmedia_init(&sc->iy_ifmedia, 0, iy_mediachange, iy_mediastatus); 351 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_2, 0, NULL); 352 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_5, 0, NULL); 353 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 354 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 355 ifmedia_set(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO); 356 /* Attach the interface. */ 357 if_attach(ifp); 358 ether_ifattach(ifp, myaddr); 359 printf(": address %s, rev. %d, %d kB\n", 360 ether_sprintf(myaddr), 361 sc->hard_vers, sc->sram/1024); 362 363 eirq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 364 if (eirq != ia->ia_irq) 365 printf("%s: EEPROM irq setting %d ignored\n", 366 sc->sc_dev.dv_xname, eirq); 367 368 #if NBPFILTER > 0 369 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 370 #endif 371 372 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 373 IPL_NET, iyintr, sc); 374 375 #if NRND > 0 376 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 377 RND_TYPE_NET, 0); 378 #endif 379 380 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 381 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 382 } 383 384 void 385 iystop(sc) 386 struct iy_softc *sc; 387 { 388 bus_space_tag_t iot; 389 bus_space_handle_t ioh; 390 #ifdef IYDEBUG 391 u_int p, v; 392 #endif 393 394 iot = sc->sc_iot; 395 ioh = sc->sc_ioh; 396 397 bus_space_write_1(iot, ioh, COMMAND_REG, RCV_DISABLE_CMD); 398 399 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 400 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); 401 402 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 403 delay(200); 404 #ifdef IYDEBUG 405 printf("%s: dumping tx chain (st 0x%x end 0x%x last 0x%x)\n", 406 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 407 p = sc->tx_last; 408 if (!p) 409 p = sc->tx_start; 410 do { 411 char sbuf[128]; 412 413 bus_space_write_2(iot, ioh, HOST_ADDR_REG, p); 414 415 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 416 bitmask_snprintf(v, "\020\006Ab\010Dn", sbuf, sizeof(sbuf)); 417 printf("0x%04x: %s ", p, sbuf); 418 419 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 420 bitmask_snprintf(v, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 421 sbuf, sizeof(sbuf)); 422 printf("0x%s", sbuf); 423 424 p = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 425 printf(" 0x%04x", p); 426 427 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 428 bitmask_snprintf(v, "\020\020Ch", sbuf, sizeof(sbuf)); 429 printf(" 0x%s\n", sbuf); 430 431 } while (v & 0x8000); 432 #endif 433 sc->tx_start = sc->tx_end = sc->rx_size; 434 sc->tx_last = 0; 435 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 436 } 437 438 void 439 iyreset(sc) 440 struct iy_softc *sc; 441 { 442 int s; 443 s = splnet(); 444 iystop(sc); 445 iyinit(sc); 446 splx(s); 447 } 448 449 void 450 iyinit(sc) 451 struct iy_softc *sc; 452 { 453 int i; 454 unsigned temp; 455 struct ifnet *ifp; 456 bus_space_tag_t iot; 457 bus_space_handle_t ioh; 458 459 iot = sc->sc_iot; 460 ioh = sc->sc_ioh; 461 462 ifp = &sc->sc_ethercom.ec_if; 463 #ifdef IYDEBUG 464 printf("ifp is %p\n", ifp); 465 #endif 466 467 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 468 469 temp = bus_space_read_1(iot, ioh, EEPROM_REG); 470 if (temp & 0x10) 471 bus_space_write_1(iot, ioh, EEPROM_REG, temp & ~0x10); 472 473 for (i=0; i<6; ++i) { 474 bus_space_write_1(iot, ioh, I_ADD(i), LLADDR(ifp->if_sadl)[i]); 475 } 476 477 temp = bus_space_read_1(iot, ioh, REG1); 478 bus_space_write_1(iot, ioh, REG1, 479 temp | XMT_CHAIN_INT | XMT_CHAIN_ERRSTOP | RCV_DISCARD_BAD); 480 481 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 482 temp = MATCH_ALL; 483 } else if (sc->sc_ethercom.ec_multicnt) { 484 temp = MATCH_MULTI; 485 } else 486 temp = MATCH_ID; 487 488 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 489 490 #ifdef IYDEBUG 491 { 492 char sbuf[128]; 493 494 bitmask_snprintf(temp, "\020\1PRMSC\2NOBRDST\3SEECRC\4LENGTH\5NOSaIns\6MultiIA", 495 sbuf, sizeof(sbuf)); 496 printf("%s: RECV_MODES set to %s\n", sc->sc_dev.dv_xname, sbuf); 497 } 498 #endif 499 /* XXX VOODOO */ 500 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 501 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 502 /* XXX END OF VOODOO */ 503 504 505 delay(500000); /* for the hardware to test for the connector */ 506 507 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 508 #ifdef IYDEBUG 509 { 510 char sbuf[128]; 511 512 bitmask_snprintf(temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC", 513 sbuf, sizeof(sbuf)); 514 printf("%s: media select was 0x%s ", sc->sc_dev.dv_xname, sbuf); 515 } 516 #endif 517 temp = (temp & TEST_MODE_MASK); 518 519 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 520 case IFM_10_5: 521 temp &= ~ (BNC_BIT | TPE_BIT); 522 break; 523 524 case IFM_10_2: 525 temp = (temp & ~TPE_BIT) | BNC_BIT; 526 break; 527 528 case IFM_10_T: 529 temp = (temp & ~BNC_BIT) | TPE_BIT; 530 break; 531 default: 532 /* nothing; leave as it is */ 533 } 534 switch (temp & (BNC_BIT | TPE_BIT)) { 535 case BNC_BIT: 536 sc->iy_media = IFM_ETHER | IFM_10_2; 537 break; 538 case TPE_BIT: 539 sc->iy_media = IFM_ETHER | IFM_10_T; 540 break; 541 default: 542 sc->iy_media = IFM_ETHER | IFM_10_5; 543 } 544 545 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 546 #ifdef IYDEBUG 547 { 548 char sbuf[128]; 549 550 bitmask_snprintf(temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC", 551 sbuf, sizeof(sbuf)); 552 printf("changed to 0x%s\n", sbuf); 553 } 554 #endif 555 556 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 557 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 558 bus_space_write_1(iot, ioh, 0, BANK_SEL(1)); 559 560 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 561 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 562 563 #ifdef IYDEBUG 564 { 565 char sbuf[128]; 566 567 bitmask_snprintf(temp, "\020\4bad_irq\010flash/boot present", 568 sbuf, sizeof(sbuf)); 569 printf("%s: int no was %s\n", sc->sc_dev.dv_xname, sbuf); 570 571 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 572 bitmask_snprintf(temp, "\020\4bad_irq\010flash/boot present", 573 sbuf, sizeof(sbuf)); 574 printf("%s: int no now %s\n", sc->sc_dev.dv_xname, sbuf); 575 } 576 #endif 577 578 579 bus_space_write_1(iot, ioh, RCV_LOWER_LIMIT_REG, 0); 580 bus_space_write_1(iot, ioh, RCV_UPPER_LIMIT_REG, (sc->rx_size - 2) >> 8); 581 bus_space_write_1(iot, ioh, XMT_LOWER_LIMIT_REG, sc->rx_size >> 8); 582 bus_space_write_1(iot, ioh, XMT_UPPER_LIMIT_REG, sc->sram >> 8); 583 584 temp = bus_space_read_1(iot, ioh, REG1); 585 #ifdef IYDEBUG 586 { 587 char sbuf[128]; 588 589 bitmask_snprintf(temp, "\020\2WORD_WIDTH\010INT_ENABLE", 590 sbuf, sizeof(sbuf)); 591 printf("%s: HW access is %s\n", sc->sc_dev.dv_xname, sbuf); 592 } 593 #endif 594 bus_space_write_1(iot, ioh, REG1, temp | INT_ENABLE); /* XXX what about WORD_WIDTH? */ 595 596 #ifdef IYDEBUG 597 { 598 char sbuf[128]; 599 600 temp = bus_space_read_1(iot, ioh, REG1); 601 bitmask_snprintf(temp, "\020\2WORD_WIDTH\010INT_ENABLE", 602 sbuf, sizeof(sbuf)); 603 printf("%s: HW access is %s\n", sc->sc_dev.dv_xname, sbuf); 604 } 605 #endif 606 607 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 608 609 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS & ~(RX_BIT|TX_BIT)); 610 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); /* clear ints */ 611 612 bus_space_write_2(iot, ioh, RCV_START_LOW, 0); 613 bus_space_write_2(iot, ioh, RCV_STOP_LOW, sc->rx_size - 2); 614 sc->rx_start = 0; 615 616 bus_space_write_1(iot, ioh, 0, SEL_RESET_CMD); 617 delay(200); 618 619 bus_space_write_2(iot, ioh, XMT_ADDR_REG, sc->rx_size); 620 621 sc->tx_start = sc->tx_end = sc->rx_size; 622 sc->tx_last = 0; 623 624 bus_space_write_1(iot, ioh, 0, RCV_ENABLE_CMD); 625 626 ifp->if_flags |= IFF_RUNNING; 627 ifp->if_flags &= ~IFF_OACTIVE; 628 } 629 630 void 631 iystart(ifp) 632 struct ifnet *ifp; 633 { 634 struct iy_softc *sc; 635 636 637 struct mbuf *m0, *m; 638 u_int len, pad, last, end; 639 u_int llen, residual; 640 int avail; 641 caddr_t data; 642 u_int16_t resval, stat; 643 bus_space_tag_t iot; 644 bus_space_handle_t ioh; 645 646 #ifdef IYDEBUG 647 printf("iystart called\n"); 648 #endif 649 sc = ifp->if_softc; 650 651 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 652 return; 653 654 iot = sc->sc_iot; 655 ioh = sc->sc_ioh; 656 657 while ((m0 = ifp->if_snd.ifq_head) != NULL) { 658 #ifdef IYDEBUG 659 printf("%s: trying to write another packet to the hardware\n", 660 sc->sc_dev.dv_xname); 661 #endif 662 663 /* We need to use m->m_pkthdr.len, so require the header */ 664 if ((m0->m_flags & M_PKTHDR) == 0) 665 panic("iystart: no header mbuf"); 666 667 len = m0->m_pkthdr.len; 668 pad = len & 1; 669 670 #ifdef IYDEBUG 671 printf("%s: length is %d.\n", sc->sc_dev.dv_xname, len); 672 #endif 673 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 674 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 675 } 676 677 if (len + pad > ETHER_MAX_LEN) { 678 /* packet is obviously too large: toss it */ 679 ++ifp->if_oerrors; 680 IF_DEQUEUE(&ifp->if_snd, m0); 681 m_freem(m0); 682 continue; 683 } 684 685 #if NBPFILTER > 0 686 if (ifp->if_bpf) 687 bpf_mtap(ifp->if_bpf, m0); 688 #endif 689 690 avail = sc->tx_start - sc->tx_end; 691 if (avail <= 0) 692 avail += sc->tx_size; 693 694 #ifdef IYDEBUG 695 printf("%s: avail is %d.\n", sc->sc_dev.dv_xname, avail); 696 #endif 697 /* 698 * we MUST RUN at splnet here --- 699 * XXX todo: or even turn off the boards ints ??? hm... 700 */ 701 702 /* See if there is room to put another packet in the buffer. */ 703 704 if ((len+pad+2*I595_XMT_HDRLEN) > avail) { 705 #ifdef IYDEBUG 706 printf("%s: len = %d, avail = %d, setting OACTIVE\n", 707 sc->sc_dev.dv_xname, len, avail); 708 #endif 709 ifp->if_flags |= IFF_OACTIVE; 710 return; 711 } 712 713 /* we know it fits in the hardware now, so dequeue it */ 714 IF_DEQUEUE(&ifp->if_snd, m0); 715 716 last = sc->tx_end; 717 end = last + pad + len + I595_XMT_HDRLEN; 718 719 if (end >= sc->sram) { 720 if ((sc->sram - last) <= I595_XMT_HDRLEN) { 721 /* keep header in one piece */ 722 last = sc->rx_size; 723 end = last + pad + len + I595_XMT_HDRLEN; 724 } else 725 end -= sc->tx_size; 726 } 727 728 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 729 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 730 htole16(XMT_CMD)); 731 732 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 733 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 734 735 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 736 htole16(len + pad)); 737 738 residual = resval = 0; 739 740 while ((m = m0)!=0) { 741 data = mtod(m, caddr_t); 742 llen = m->m_len; 743 if (residual) { 744 #ifdef IYDEBUG 745 printf("%s: merging residual with next mbuf.\n", 746 sc->sc_dev.dv_xname); 747 #endif 748 resval |= *data << 8; 749 bus_space_write_stream_2(iot, ioh, 750 MEM_PORT_REG, resval); 751 --llen; 752 ++data; 753 } 754 if (llen > 1) 755 bus_space_write_multi_stream_2(iot, ioh, 756 MEM_PORT_REG, data, llen>>1); 757 residual = llen & 1; 758 if (residual) { 759 resval = *(data + llen - 1); 760 #ifdef IYDEBUG 761 printf("%s: got odd mbuf to send.\n", 762 sc->sc_dev.dv_xname); 763 #endif 764 } 765 766 MFREE(m, m0); 767 } 768 769 if (residual) 770 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 771 resval); 772 773 pad >>= 1; 774 while (pad-- > 0) 775 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 0); 776 777 #ifdef IYDEBUG 778 printf("%s: new last = 0x%x, end = 0x%x.\n", 779 sc->sc_dev.dv_xname, last, end); 780 printf("%s: old start = 0x%x, end = 0x%x, last = 0x%x\n", 781 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 782 #endif 783 784 if (sc->tx_start != sc->tx_end) { 785 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 786 sc->tx_last + XMT_COUNT); 787 788 /* 789 * XXX We keep stat in le order, to potentially save 790 * a byte swap. 791 */ 792 stat = bus_space_read_stream_2(iot, ioh, MEM_PORT_REG); 793 794 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 795 sc->tx_last + XMT_CHAIN); 796 797 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 798 htole16(last)); 799 800 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 801 stat | htole16(CHAIN)); 802 #ifdef IYDEBUG 803 printf("%s: setting 0x%x to 0x%x\n", 804 sc->sc_dev.dv_xname, sc->tx_last + XMT_COUNT, 805 le16toh(stat) | CHAIN); 806 #endif 807 } 808 stat = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 809 810 /* XXX todo: enable ints here if disabled */ 811 812 ++ifp->if_opackets; 813 814 if (sc->tx_start == sc->tx_end) { 815 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 816 bus_space_write_1(iot, ioh, 0, XMT_CMD); 817 sc->tx_start = last; 818 #ifdef IYDEBUG 819 printf("%s: writing 0x%x to XAR and giving XCMD\n", 820 sc->sc_dev.dv_xname, last); 821 #endif 822 } else { 823 bus_space_write_1(iot, ioh, 0, RESUME_XMT_CMD); 824 #ifdef IYDEBUG 825 printf("%s: giving RESUME_XCMD\n", 826 sc->sc_dev.dv_xname); 827 #endif 828 } 829 sc->tx_last = last; 830 sc->tx_end = end; 831 } 832 } 833 834 835 static __inline void 836 eepromwritebit(iot, ioh, what) 837 bus_space_tag_t iot; 838 bus_space_handle_t ioh; 839 int what; 840 { 841 bus_space_write_1(iot, ioh, EEPROM_REG, what); 842 delay(1); 843 bus_space_write_1(iot, ioh, EEPROM_REG, what|EESK); 844 delay(1); 845 bus_space_write_1(iot, ioh, EEPROM_REG, what); 846 delay(1); 847 } 848 849 static __inline int 850 eepromreadbit(iot, ioh) 851 bus_space_tag_t iot; 852 bus_space_handle_t ioh; 853 { 854 int b; 855 856 bus_space_write_1(iot, ioh, EEPROM_REG, EECS|EESK); 857 delay(1); 858 b = bus_space_read_1(iot, ioh, EEPROM_REG); 859 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); 860 delay(1); 861 862 return ((b & EEDO) != 0); 863 } 864 865 static u_int16_t 866 eepromread(iot, ioh, offset) 867 bus_space_tag_t iot; 868 bus_space_handle_t ioh; 869 int offset; 870 { 871 volatile int i; 872 volatile int j; 873 volatile u_int16_t readval; 874 875 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 876 delay(1); 877 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); /* XXXX??? */ 878 delay(1); 879 880 eepromwritebit(iot, ioh, EECS|EEDI); 881 eepromwritebit(iot, ioh, EECS|EEDI); 882 eepromwritebit(iot, ioh, EECS); 883 884 for (j=5; j>=0; --j) { 885 if ((offset>>j) & 1) 886 eepromwritebit(iot, ioh, EECS|EEDI); 887 else 888 eepromwritebit(iot, ioh, EECS); 889 } 890 891 for (readval=0, i=0; i<16; ++i) { 892 readval<<=1; 893 readval |= eepromreadbit(iot, ioh); 894 } 895 896 bus_space_write_1(iot, ioh, EEPROM_REG, 0|EESK); 897 delay(1); 898 bus_space_write_1(iot, ioh, EEPROM_REG, 0); 899 900 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 901 902 return readval; 903 } 904 905 /* 906 * Device timeout/watchdog routine. Entered if the device neglects to generate 907 * an interrupt after a transmit has been started on it. 908 */ 909 void 910 iywatchdog(ifp) 911 struct ifnet *ifp; 912 { 913 struct iy_softc *sc = ifp->if_softc; 914 915 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 916 ++sc->sc_ethercom.ec_if.if_oerrors; 917 iyreset(sc); 918 } 919 920 /* 921 * What to do upon receipt of an interrupt. 922 */ 923 int 924 iyintr(arg) 925 void *arg; 926 { 927 struct iy_softc *sc = arg; 928 bus_space_tag_t iot; 929 bus_space_handle_t ioh; 930 931 u_short status; 932 933 iot = sc->sc_iot; 934 ioh = sc->sc_ioh; 935 936 status = bus_space_read_1(iot, ioh, STATUS_REG); 937 #ifdef IYDEBUG 938 if (status & ALL_INTS) { 939 char sbuf[128]; 940 941 bitmask_snprintf(status, "\020\1RX_STP\2RX\3TX\4EXEC", 942 sbuf, sizeof(sbuf)); 943 printf("%s: got interupt %s", sc->sc_dev.dv_xname, sbuf); 944 945 if (status & EXEC_INT) { 946 bitmask_snprintf(bus_space_read_1(iot, ioh, 0), 947 "\020\6ABORT", sbuf, sizeof(sbuf)); 948 printf(" event %s\n", sbuf); 949 } else 950 printf("\n"); 951 } 952 #endif 953 if ((status & (RX_INT | TX_INT)) == 0) 954 return 0; 955 956 if (status & RX_INT) { 957 iy_intr_rx(sc); 958 bus_space_write_1(iot, ioh, STATUS_REG, RX_INT); 959 } 960 if (status & TX_INT) { 961 iy_intr_tx(sc); 962 bus_space_write_1(iot, ioh, STATUS_REG, TX_INT); 963 } 964 965 #if NRND > 0 966 rnd_add_uint32(&sc->rnd_source, status); 967 #endif 968 969 return 1; 970 } 971 972 void 973 iyget(sc, iot, ioh, rxlen) 974 struct iy_softc *sc; 975 bus_space_tag_t iot; 976 bus_space_handle_t ioh; 977 int rxlen; 978 { 979 struct mbuf *m, *top, **mp; 980 struct ifnet *ifp; 981 int len; 982 983 ifp = &sc->sc_ethercom.ec_if; 984 985 MGETHDR(m, M_DONTWAIT, MT_DATA); 986 if (m == 0) 987 goto dropped; 988 m->m_pkthdr.rcvif = ifp; 989 m->m_pkthdr.len = rxlen; 990 len = MHLEN; 991 top = 0; 992 mp = ⊤ 993 994 while (rxlen > 0) { 995 if (top) { 996 MGET(m, M_DONTWAIT, MT_DATA); 997 if (m == 0) { 998 m_freem(top); 999 goto dropped; 1000 } 1001 len = MLEN; 1002 } 1003 if (rxlen >= MINCLSIZE) { 1004 MCLGET(m, M_DONTWAIT); 1005 if ((m->m_flags & M_EXT) == 0) { 1006 m_free(m); 1007 m_freem(top); 1008 goto dropped; 1009 } 1010 len = MCLBYTES; 1011 } 1012 len = min(rxlen, len); 1013 if (len > 1) { 1014 len &= ~1; 1015 1016 bus_space_read_multi_stream_2(iot, ioh, MEM_PORT_REG, 1017 mtod(m, caddr_t), len/2); 1018 } else { 1019 #ifdef IYDEBUG 1020 printf("%s: received odd mbuf\n", sc->sc_dev.dv_xname); 1021 #endif 1022 *(mtod(m, caddr_t)) = bus_space_read_stream_2(iot, ioh, 1023 MEM_PORT_REG); 1024 } 1025 m->m_len = len; 1026 rxlen -= len; 1027 *mp = m; 1028 mp = &m->m_next; 1029 } 1030 /* XXX receive the top here */ 1031 ++ifp->if_ipackets; 1032 1033 #if NBPFILTER > 0 1034 if (ifp->if_bpf) 1035 bpf_mtap(ifp->if_bpf, top); 1036 #endif 1037 (*ifp->if_input)(ifp, top); 1038 return; 1039 1040 dropped: 1041 ++ifp->if_ierrors; 1042 return; 1043 } 1044 1045 void 1046 iy_intr_rx(sc) 1047 struct iy_softc *sc; 1048 { 1049 struct ifnet *ifp; 1050 bus_space_tag_t iot; 1051 bus_space_handle_t ioh; 1052 1053 u_int rxadrs, rxevnt, rxstatus, rxnext, rxlen; 1054 1055 iot = sc->sc_iot; 1056 ioh = sc->sc_ioh; 1057 ifp = &sc->sc_ethercom.ec_if; 1058 1059 rxadrs = sc->rx_start; 1060 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxadrs); 1061 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 1062 rxnext = 0; 1063 1064 while (rxevnt == RCV_DONE) { 1065 rxstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1066 MEM_PORT_REG)); 1067 rxnext = le16toh(bus_space_read_stream_2(iot, ioh, 1068 MEM_PORT_REG)); 1069 rxlen = le16toh(bus_space_read_stream_2(iot, ioh, 1070 MEM_PORT_REG)); 1071 #ifdef IYDEBUG 1072 { 1073 char sbuf[128]; 1074 1075 bitmask_snprintf(rxstatus, "\020\1RCLD\2IA_MCH\010SHORT\011OVRN\013ALGERR\014CRCERR\015LENERR\016RCVOK\020TYP", 1076 sbuf, sizeof(sbuf)); 1077 printf("%s: pck at 0x%04x stat %s next 0x%x len 0x%x\n", 1078 sc->sc_dev.dv_xname, rxadrs, sbuf, rxnext, rxlen); 1079 } 1080 #endif 1081 iyget(sc, iot, ioh, rxlen); 1082 1083 /* move stop address */ 1084 bus_space_write_2(iot, ioh, RCV_STOP_LOW, 1085 rxnext == 0 ? sc->rx_size - 2 : rxnext - 2); 1086 1087 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxnext); 1088 rxadrs = rxnext; 1089 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, 1090 MEM_PORT_REG)); 1091 } 1092 sc->rx_start = rxnext; 1093 } 1094 1095 void 1096 iy_intr_tx(sc) 1097 struct iy_softc *sc; 1098 { 1099 bus_space_tag_t iot; 1100 bus_space_handle_t ioh; 1101 struct ifnet *ifp; 1102 u_int txstatus, txstat2, txlen, txnext; 1103 1104 ifp = &sc->sc_ethercom.ec_if; 1105 iot = sc->sc_iot; 1106 ioh = sc->sc_ioh; 1107 1108 while (sc->tx_start != sc->tx_end) { 1109 bus_space_write_2(iot, ioh, HOST_ADDR_REG, sc->tx_start); 1110 txstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1111 MEM_PORT_REG)); 1112 1113 if ((txstatus & (TX_DONE|CMD_MASK)) != (TX_DONE|XMT_CMD)) 1114 break; 1115 1116 txstat2 = le16toh(bus_space_read_stream_2(iot, ioh, 1117 MEM_PORT_REG)); 1118 txnext = le16toh(bus_space_read_stream_2(iot, ioh, 1119 MEM_PORT_REG)); 1120 txlen = le16toh(bus_space_read_stream_2(iot, ioh, 1121 MEM_PORT_REG)); 1122 #ifdef IYDEBUG 1123 { 1124 char sbuf[128]; 1125 1126 bitmask_snprintf(txstat2, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 1127 sbuf, sizeof(sbuf)); 1128 printf("txstat 0x%x stat2 0x%s next 0x%x len 0x%x\n", 1129 txstatus, sbuf, txnext, txlen); 1130 } 1131 #endif 1132 if (txlen & CHAIN) 1133 sc->tx_start = txnext; 1134 else 1135 sc->tx_start = sc->tx_end; 1136 ifp->if_flags &= ~IFF_OACTIVE; 1137 1138 if ((txstat2 & 0x2000) == 0) 1139 ++ifp->if_oerrors; 1140 if (txstat2 & 0x000f) 1141 ifp->if_oerrors += txstat2 & 0x000f; 1142 } 1143 ifp->if_flags &= ~IFF_OACTIVE; 1144 } 1145 1146 int 1147 iyioctl(ifp, cmd, data) 1148 struct ifnet *ifp; 1149 u_long cmd; 1150 caddr_t data; 1151 { 1152 struct iy_softc *sc; 1153 struct ifaddr *ifa; 1154 struct ifreq *ifr; 1155 int s, error = 0; 1156 1157 sc = ifp->if_softc; 1158 ifa = (struct ifaddr *)data; 1159 ifr = (struct ifreq *)data; 1160 1161 #ifdef IYDEBUG 1162 printf("iyioctl called with ifp 0x%p (%s) cmd 0x%lx data 0x%p\n", 1163 ifp, ifp->if_xname, cmd, data); 1164 #endif 1165 1166 s = splnet(); 1167 1168 switch (cmd) { 1169 1170 case SIOCSIFADDR: 1171 ifp->if_flags |= IFF_UP; 1172 1173 switch (ifa->ifa_addr->sa_family) { 1174 #ifdef INET 1175 case AF_INET: 1176 iyinit(sc); 1177 arp_ifinit(ifp, ifa); 1178 break; 1179 #endif 1180 #ifdef NS 1181 /* XXX - This code is probably wrong. */ 1182 case AF_NS: 1183 { 1184 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1185 1186 if (ns_nullhost(*ina)) 1187 ina->x_host = *(union ns_host *) 1188 LLADDR(ifp->if_sadl); 1189 else 1190 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1191 ETHER_ADDR_LEN); 1192 /* Set new address. */ 1193 iyinit(sc); 1194 break; 1195 } 1196 #endif /* NS */ 1197 default: 1198 iyinit(sc); 1199 break; 1200 } 1201 break; 1202 1203 case SIOCSIFFLAGS: 1204 sc->promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI); 1205 if ((ifp->if_flags & IFF_UP) == 0 && 1206 (ifp->if_flags & IFF_RUNNING) != 0) { 1207 /* 1208 * If interface is marked down and it is running, then 1209 * stop it. 1210 */ 1211 iystop(sc); 1212 ifp->if_flags &= ~IFF_RUNNING; 1213 } else if ((ifp->if_flags & IFF_UP) != 0 && 1214 (ifp->if_flags & IFF_RUNNING) == 0) { 1215 /* 1216 * If interface is marked up and it is stopped, then 1217 * start it. 1218 */ 1219 iyinit(sc); 1220 } else { 1221 /* 1222 * Reset the interface to pick up changes in any other 1223 * flags that affect hardware registers. 1224 */ 1225 iystop(sc); 1226 iyinit(sc); 1227 } 1228 #ifdef IYDEBUGX 1229 if (ifp->if_flags & IFF_DEBUG) 1230 sc->sc_debug = IFY_ALL; 1231 else 1232 sc->sc_debug = 0; 1233 #endif 1234 break; 1235 1236 case SIOCADDMULTI: 1237 case SIOCDELMULTI: 1238 error = (cmd == SIOCADDMULTI) ? 1239 ether_addmulti(ifr, &sc->sc_ethercom): 1240 ether_delmulti(ifr, &sc->sc_ethercom); 1241 1242 if (error == ENETRESET) { 1243 /* 1244 * Multicast list has changed; set the hardware filter 1245 * accordingly. 1246 */ 1247 iyreset(sc); /* XXX can't make it work otherwise */ 1248 iy_mc_reset(sc); 1249 error = 0; 1250 } 1251 break; 1252 1253 case SIOCSIFMEDIA: 1254 case SIOCGIFMEDIA: 1255 error = ifmedia_ioctl(ifp, ifr, &sc->iy_ifmedia, cmd); 1256 break; 1257 default: 1258 error = EINVAL; 1259 } 1260 splx(s); 1261 return error; 1262 } 1263 1264 int 1265 iy_mediachange(ifp) 1266 struct ifnet *ifp; 1267 { 1268 struct iy_softc *sc = ifp->if_softc; 1269 1270 if (IFM_TYPE(sc->iy_ifmedia.ifm_media) != IFM_ETHER) 1271 return EINVAL; 1272 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 1273 case IFM_10_5: 1274 case IFM_10_2: 1275 case IFM_10_T: 1276 case IFM_AUTO: 1277 iystop(sc); 1278 iyinit(sc); 1279 return 0; 1280 default: 1281 return EINVAL; 1282 } 1283 } 1284 1285 void 1286 iy_mediastatus(ifp, ifmr) 1287 struct ifnet *ifp; 1288 struct ifmediareq *ifmr; 1289 { 1290 struct iy_softc *sc = ifp->if_softc; 1291 1292 ifmr->ifm_active = sc->iy_media; 1293 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1294 } 1295 1296 1297 static void 1298 iy_mc_setup(sc) 1299 struct iy_softc *sc; 1300 { 1301 struct ether_multi *enm; 1302 struct ether_multistep step; 1303 struct ethercom *ecp; 1304 struct ifnet *ifp; 1305 bus_space_tag_t iot; 1306 bus_space_handle_t ioh; 1307 int avail, last /*, end*/ , len; 1308 int timeout; 1309 volatile u_int16_t dum; 1310 u_int8_t temp; 1311 1312 1313 ecp = &sc->sc_ethercom; 1314 ifp = &ecp->ec_if; 1315 1316 iot = sc->sc_iot; 1317 ioh = sc->sc_ioh; 1318 1319 len = 6 * ecp->ec_multicnt + 6; 1320 1321 avail = sc->tx_start - sc->tx_end; 1322 if (avail <= 0) 1323 avail += sc->tx_size; 1324 if (ifp->if_flags & IFF_DEBUG) 1325 printf("%s: iy_mc_setup called, %d addresses, " 1326 "%d/%d bytes needed/avail\n", ifp->if_xname, 1327 ecp->ec_multicnt, len + I595_XMT_HDRLEN, avail); 1328 1329 last = sc->rx_size; 1330 1331 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1332 bus_space_write_1(iot, ioh, RECV_MODES_REG, MATCH_MULTI); 1333 /* XXX VOODOO */ 1334 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1335 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1336 /* XXX END OF VOODOO */ 1337 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1338 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 1339 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(MC_SETUP_CMD)); 1340 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1341 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1342 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(len)); 1343 1344 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1345 LLADDR(ifp->if_sadl), 3); 1346 1347 ETHER_FIRST_MULTI(step, ecp, enm); 1348 while(enm) { 1349 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1350 enm->enm_addrlo, 3); 1351 1352 ETHER_NEXT_MULTI(step, enm); 1353 } 1354 dum = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 1355 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 1356 bus_space_write_1(iot, ioh, 0, MC_SETUP_CMD); 1357 1358 1359 sc->tx_start = sc->rx_size; 1360 sc->tx_end = sc->rx_size + I595_XMT_HDRLEN + len; 1361 1362 for (timeout=0; timeout<100; timeout++) { 1363 DELAY(2); 1364 if ((bus_space_read_1(iot, ioh, STATUS_REG) & EXEC_INT) == 0) 1365 continue; 1366 1367 temp = bus_space_read_1(iot, ioh, 0); 1368 bus_space_write_1(iot, ioh, STATUS_REG, EXEC_INT); 1369 #ifdef DIAGNOSTIC 1370 if (temp & 0x20) { 1371 printf("%s: mc setup failed, %d usec\n", 1372 sc->sc_dev.dv_xname, timeout * 2); 1373 } else if (((temp & 0x0f) == 0x03) && 1374 (ifp->if_flags & IFF_DEBUG)) { 1375 printf("%s: mc setup done, %d usec\n", 1376 sc->sc_dev.dv_xname, timeout * 2); 1377 } 1378 #endif 1379 break; 1380 } 1381 sc->tx_start = sc->tx_end; 1382 ifp->if_flags &= ~IFF_OACTIVE; 1383 1384 } 1385 1386 static void 1387 iy_mc_reset(sc) 1388 struct iy_softc *sc; 1389 { 1390 struct ether_multi *enm; 1391 struct ether_multistep step; 1392 struct ethercom *ecp; 1393 struct ifnet *ifp; 1394 bus_space_tag_t iot; 1395 bus_space_handle_t ioh; 1396 u_int16_t temp; 1397 1398 ecp = &sc->sc_ethercom; 1399 ifp = &ecp->ec_if; 1400 1401 iot = sc->sc_iot; 1402 ioh = sc->sc_ioh; 1403 1404 if (ecp->ec_multicnt > 63) { 1405 ifp->if_flags |= IFF_ALLMULTI; 1406 1407 } else if (ecp->ec_multicnt > 0) { 1408 /* 1409 * Step through the list of addresses. 1410 */ 1411 ETHER_FIRST_MULTI(step, ecp, enm); 1412 while(enm) { 1413 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1414 ifp->if_flags |= IFF_ALLMULTI; 1415 goto setupmulti; 1416 } 1417 ETHER_NEXT_MULTI(step, enm); 1418 } 1419 /* OK, we really need to do it now: */ 1420 #if 0 1421 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) 1422 != IFF_RUNNING) { 1423 ifp->if_flags |= IFF_OACTIVE; 1424 sc->want_mc_setup = 1; 1425 return; 1426 } 1427 #endif 1428 iy_mc_setup(sc); 1429 } else { 1430 ifp->if_flags &= ~IFF_ALLMULTI; 1431 } 1432 1433 setupmulti: 1434 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1435 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 1436 temp = MATCH_ALL; 1437 } else if (sc->sc_ethercom.ec_multicnt) { 1438 temp = MATCH_MULTI; 1439 } else 1440 temp = MATCH_ID; 1441 1442 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 1443 /* XXX VOODOO */ 1444 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1445 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1446 /* XXX END OF VOODOO */ 1447 1448 /* XXX TBD: setup hardware for all multicasts */ 1449 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1450 return; 1451 } 1452 1453 #ifdef IYDEBUGX 1454 void 1455 print_rbd(rbd) 1456 volatile struct ie_recv_buf_desc *rbd; 1457 { 1458 printf("RBD at %08lx:\nactual %04x, next %04x, buffer %08x\n" 1459 "length %04x, mbz %04x\n", (u_long)rbd, rbd->ie_rbd_actual, 1460 rbd->ie_rbd_next, rbd->ie_rbd_buffer, rbd->ie_rbd_length, 1461 rbd->mbz); 1462 } 1463 #endif 1464 1465 void 1466 iyprobemem(sc) 1467 struct iy_softc *sc; 1468 { 1469 bus_space_tag_t iot; 1470 bus_space_handle_t ioh; 1471 int testing; 1472 1473 iot = sc->sc_iot; 1474 ioh = sc->sc_ioh; 1475 1476 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 1477 delay(1); 1478 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 4096-2); 1479 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1480 1481 for (testing=65536; testing >= 4096; testing >>= 1) { 1482 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1483 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xdead); 1484 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1485 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xdead) { 1486 #ifdef IYMEMDEBUG 1487 printf("%s: Didn't keep 0xdead at 0x%x\n", 1488 sc->sc_dev.dv_xname, testing-2); 1489 #endif 1490 continue; 1491 } 1492 1493 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1494 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xbeef); 1495 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1496 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xbeef) { 1497 #ifdef IYMEMDEBUG 1498 printf("%s: Didn't keep 0xbeef at 0x%x\n", 1499 sc->sc_dev.dv_xname, testing-2); 1500 #endif 1501 continue; 1502 } 1503 1504 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1505 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1506 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing >> 1); 1507 bus_space_write_2(iot, ioh, MEM_PORT_REG, testing >> 1); 1508 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1509 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) == (testing >> 1)) { 1510 #ifdef IYMEMDEBUG 1511 printf("%s: 0x%x alias of 0x0\n", 1512 sc->sc_dev.dv_xname, testing >> 1); 1513 #endif 1514 continue; 1515 } 1516 1517 break; 1518 } 1519 1520 sc->sram = testing; 1521 1522 switch(testing) { 1523 case 65536: 1524 /* 4 NFS packets + overhead RX, 2 NFS + overhead TX */ 1525 sc->rx_size = 44*1024; 1526 break; 1527 1528 case 32768: 1529 /* 2 NFS packets + overhead RX, 1 NFS + overhead TX */ 1530 sc->rx_size = 22*1024; 1531 break; 1532 1533 case 16384: 1534 /* 1 NFS packet + overhead RX, 4 big packets TX */ 1535 sc->rx_size = 10*1024; 1536 break; 1537 default: 1538 sc->rx_size = testing/2; 1539 break; 1540 } 1541 sc->tx_size = testing - sc->rx_size; 1542 } 1543 1544 static int 1545 eepromreadall(iot, ioh, wordp, maxi) 1546 bus_space_tag_t iot; 1547 bus_space_handle_t ioh; 1548 u_int16_t *wordp; 1549 int maxi; 1550 { 1551 int i; 1552 u_int16_t checksum, tmp; 1553 1554 checksum = 0; 1555 1556 for (i=0; i<EEPP_LENGTH; ++i) { 1557 tmp = eepromread(iot, ioh, i); 1558 checksum += tmp; 1559 if (i<maxi) 1560 wordp[i] = tmp; 1561 } 1562 1563 if (checksum != EEPP_CHKSUM) { 1564 #ifdef IYDEBUG 1565 printf("wrong EEPROM checksum 0x%x should be 0x%x\n", 1566 checksum, EEPP_CHKSUM); 1567 #endif 1568 return 1; 1569 } 1570 return 0; 1571 } 1572
Indexes created Thu Sep 25 08:09:54 GMT 2025