if_iy.c revision 1.72
1 /* $NetBSD: if_iy.c,v 1.72 2006/09/07 02:40:32 dogcow Exp $ */ 2 /* #define IYDEBUG */ 3 /* #define IYMEMDEBUG */ 4 5 /*- 6 * Copyright (c) 1996,2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Ignatios Souvatzis. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Supported hardware: 43 * 44 * - Intel EtherExpress Pro/10. 45 * - possibly other boards using the i82595 chip and no special tweaks. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_iy.c,v 1.72 2006/09/07 02:40:32 dogcow Exp $"); 50 51 #include "opt_inet.h" 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/mbuf.h> 58 #include <sys/buf.h> 59 #include <sys/protosw.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/syslog.h> 64 #include <sys/device.h> 65 #include <sys/endian.h> 66 #if NRND > 0 67 #include <sys/rnd.h> 68 #endif 69 70 #include <net/if.h> 71 #include <net/if_types.h> 72 #include <net/if_dl.h> 73 74 #include <net/if_ether.h> 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #ifdef INET 82 #include <netinet/in.h> 83 #include <netinet/in_systm.h> 84 #include <netinet/in_var.h> 85 #include <netinet/ip.h> 86 #include <netinet/if_inarp.h> 87 #endif 88 89 90 #if defined(SIOCSIFMEDIA) 91 #include <net/if_media.h> 92 #endif 93 94 #include <machine/cpu.h> 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 98 #include <dev/isa/isareg.h> 99 #include <dev/isa/isavar.h> 100 #include <dev/ic/i82595reg.h> 101 102 /* XXX why isn't this centralized? */ 103 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 104 #define bus_space_write_stream_2 bus_space_write_2 105 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 106 #define bus_space_read_stream_2 bus_space_read_2 107 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 108 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 109 110 /* 111 * Ethernet status, per interface. 112 */ 113 struct iy_softc { 114 struct device sc_dev; 115 void *sc_ih; 116 117 bus_space_tag_t sc_iot; 118 bus_space_handle_t sc_ioh; 119 120 struct ethercom sc_ethercom; 121 122 struct ifmedia iy_ifmedia; 123 int iy_media; 124 125 int mappedirq; 126 127 int hard_vers; 128 129 int promisc; 130 131 int sram, tx_size, rx_size; 132 133 int tx_start, tx_end, tx_last; 134 int rx_start; 135 136 int doing_mc_setup; 137 #ifdef IYDEBUG 138 int sc_debug; 139 #endif 140 141 #if NRND > 0 142 rndsource_element_t rnd_source; 143 #endif 144 }; 145 146 void iywatchdog(struct ifnet *); 147 int iyioctl(struct ifnet *, u_long, caddr_t); 148 int iyintr(void *); 149 void iyinit(struct iy_softc *); 150 void iystop(struct iy_softc *); 151 void iystart(struct ifnet *); 152 153 void iy_intr_rx(struct iy_softc *); 154 void iy_intr_tx(struct iy_softc *); 155 156 void iyreset(struct iy_softc *); 157 void iy_readframe(struct iy_softc *, int); 158 void iy_drop_packet_buffer(struct iy_softc *); 159 void iy_find_mem_size(struct iy_softc *); 160 void iyrint(struct iy_softc *); 161 void iytint(struct iy_softc *); 162 void iyxmit(struct iy_softc *); 163 static void iy_mc_setup(struct iy_softc *); 164 static void iy_mc_reset(struct iy_softc *); 165 void iyget(struct iy_softc *, bus_space_tag_t, bus_space_handle_t, int); 166 void iyprobemem(struct iy_softc *); 167 static inline void eepromwritebit(bus_space_tag_t, bus_space_handle_t, int); 168 static inline int eepromreadbit(bus_space_tag_t, bus_space_handle_t); 169 170 #ifdef IYDEBUGX 171 void print_rbd(volatile struct iy_recv_buf_desc *); 172 173 int in_ifrint = 0; 174 int in_iftint = 0; 175 #endif 176 177 int iy_mediachange(struct ifnet *); 178 void iy_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 int iyprobe(struct device *, struct cfdata *, void *); 181 void iyattach(struct device *, struct device *, void *); 182 183 static u_int16_t eepromread(bus_space_tag_t, bus_space_handle_t, int); 184 185 static int eepromreadall(bus_space_tag_t, bus_space_handle_t, u_int16_t *, 186 int); 187 188 CFATTACH_DECL(iy, sizeof(struct iy_softc), 189 iyprobe, iyattach, NULL, NULL); 190 191 static u_int8_t eepro_irqmap[] = EEPP_INTMAP; 192 static u_int8_t eepro_revirqmap[] = EEPP_RINTMAP; 193 194 int 195 iyprobe(parent, match, aux) 196 struct device *parent; 197 struct cfdata *match; 198 void *aux; 199 { 200 struct isa_attach_args *ia = aux; 201 u_int16_t eaddr[8]; 202 bus_space_tag_t iot; 203 bus_space_handle_t ioh; 204 u_int8_t c, d; 205 int irq; 206 207 if (ia->ia_nio < 1) 208 return (0); 209 if (ia->ia_nirq < 1) 210 return (0); 211 212 if (ISA_DIRECT_CONFIG(ia)) 213 return (0); 214 215 iot = ia->ia_iot; 216 217 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 218 return 0; 219 220 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 16, 0, &ioh)) 221 return 0; 222 223 /* try to find the round robin sig: */ 224 225 c = bus_space_read_1(iot, ioh, ID_REG); 226 if ((c & ID_REG_MASK) != ID_REG_SIG) 227 goto out; 228 229 d = bus_space_read_1(iot, ioh, ID_REG); 230 if ((d & ID_REG_MASK) != ID_REG_SIG) 231 goto out; 232 233 if (((d-c) & R_ROBIN_BITS) != 0x40) 234 goto out; 235 236 d = bus_space_read_1(iot, ioh, ID_REG); 237 if ((d & ID_REG_MASK) != ID_REG_SIG) 238 goto out; 239 240 if (((d-c) & R_ROBIN_BITS) != 0x80) 241 goto out; 242 243 d = bus_space_read_1(iot, ioh, ID_REG); 244 if ((d & ID_REG_MASK) != ID_REG_SIG) 245 goto out; 246 247 if (((d-c) & R_ROBIN_BITS) != 0xC0) 248 goto out; 249 250 d = bus_space_read_1(iot, ioh, ID_REG); 251 if ((d & ID_REG_MASK) != ID_REG_SIG) 252 goto out; 253 254 if (((d-c) & R_ROBIN_BITS) != 0x00) 255 goto out; 256 257 #ifdef IYDEBUG 258 printf("iyprobe verified working ID reg.\n"); 259 #endif 260 261 if (eepromreadall(iot, ioh, eaddr, 8)) 262 goto out; 263 264 if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ) 265 irq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 266 else 267 irq = ia->ia_irq[0].ir_irq; 268 269 if (irq >= sizeof(eepro_revirqmap)) 270 goto out; 271 272 if (eepro_revirqmap[irq] == 0xff) 273 goto out; 274 275 /* now lets reset the chip */ 276 277 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 278 delay(200); 279 280 ia->ia_nio = 1; 281 ia->ia_io[0].ir_size = 16; 282 283 ia->ia_nirq = 1; 284 ia->ia_irq[0].ir_irq = irq; 285 286 ia->ia_niomem = 0; 287 ia->ia_ndrq = 0; 288 289 bus_space_unmap(iot, ioh, 16); 290 return 1; /* found */ 291 out: 292 bus_space_unmap(iot, ioh, 16); 293 return 0; 294 } 295 296 void 297 iyattach(parent, self, aux) 298 struct device *parent, *self; 299 void *aux; 300 { 301 struct iy_softc *sc = (void *)self; 302 struct isa_attach_args *ia = aux; 303 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 304 bus_space_tag_t iot; 305 bus_space_handle_t ioh; 306 unsigned temp; 307 u_int16_t eaddr[8]; 308 u_int8_t myaddr[ETHER_ADDR_LEN]; 309 int eirq; 310 311 iot = ia->ia_iot; 312 313 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 16, 0, &ioh)) { 314 printf(": can't map i/o space\n"); 315 return; 316 } 317 318 sc->sc_iot = iot; 319 sc->sc_ioh = ioh; 320 321 sc->mappedirq = eepro_revirqmap[ia->ia_irq[0].ir_irq]; 322 323 /* now let's reset the chip */ 324 325 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 326 delay(200); 327 328 iyprobemem(sc); 329 330 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 331 ifp->if_softc = sc; 332 ifp->if_start = iystart; 333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 334 | IFF_MULTICAST; 335 336 sc->doing_mc_setup = 0; 337 338 ifp->if_ioctl = iyioctl; 339 ifp->if_watchdog = iywatchdog; 340 341 IFQ_SET_READY(&ifp->if_snd); 342 343 (void)eepromreadall(iot, ioh, eaddr, 8); 344 sc->hard_vers = eaddr[EEPW6] & EEPP_BoardRev; 345 346 #ifdef DIAGNOSTICS 347 if ((eaddr[EEPPEther0] != 348 eepromread(iot, ioh, EEPPEther0a)) && 349 (eaddr[EEPPEther1] != 350 eepromread(iot, ioh, EEPPEther1a)) && 351 (eaddr[EEPPEther2] != 352 eepromread(iot, ioh, EEPPEther2a))) 353 354 printf("EEPROM Ethernet address differs from copy\n"); 355 #endif 356 357 myaddr[1] = eaddr[EEPPEther0] & 0xFF; 358 myaddr[0] = eaddr[EEPPEther0] >> 8; 359 myaddr[3] = eaddr[EEPPEther1] & 0xFF; 360 myaddr[2] = eaddr[EEPPEther1] >> 8; 361 myaddr[5] = eaddr[EEPPEther2] & 0xFF; 362 myaddr[4] = eaddr[EEPPEther2] >> 8; 363 364 ifmedia_init(&sc->iy_ifmedia, 0, iy_mediachange, iy_mediastatus); 365 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_2, 0, NULL); 366 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_5, 0, NULL); 367 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 368 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 369 ifmedia_set(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO); 370 /* Attach the interface. */ 371 if_attach(ifp); 372 ether_ifattach(ifp, myaddr); 373 printf(": address %s, rev. %d, %d kB\n", 374 ether_sprintf(myaddr), 375 sc->hard_vers, sc->sram/1024); 376 377 eirq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 378 if (eirq != ia->ia_irq[0].ir_irq) 379 printf("%s: EEPROM irq setting %d ignored\n", 380 sc->sc_dev.dv_xname, eirq); 381 382 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 383 IST_EDGE, IPL_NET, iyintr, sc); 384 385 #if NRND > 0 386 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 387 RND_TYPE_NET, 0); 388 #endif 389 390 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 391 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 392 } 393 394 void 395 iystop(sc) 396 struct iy_softc *sc; 397 { 398 bus_space_tag_t iot; 399 bus_space_handle_t ioh; 400 #ifdef IYDEBUG 401 u_int p, v; 402 #endif 403 404 iot = sc->sc_iot; 405 ioh = sc->sc_ioh; 406 407 bus_space_write_1(iot, ioh, COMMAND_REG, RCV_DISABLE_CMD); 408 409 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 410 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); 411 412 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 413 delay(200); 414 #ifdef IYDEBUG 415 printf("%s: dumping tx chain (st 0x%x end 0x%x last 0x%x)\n", 416 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 417 p = sc->tx_last; 418 if (!p) 419 p = sc->tx_start; 420 do { 421 char sbuf[128]; 422 423 bus_space_write_2(iot, ioh, HOST_ADDR_REG, p); 424 425 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 426 bitmask_snprintf(v, "\020\006Ab\010Dn", sbuf, sizeof(sbuf)); 427 printf("0x%04x: %s ", p, sbuf); 428 429 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 430 bitmask_snprintf(v, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 431 sbuf, sizeof(sbuf)); 432 printf("0x%s", sbuf); 433 434 p = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 435 printf(" 0x%04x", p); 436 437 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 438 bitmask_snprintf(v, "\020\020Ch", sbuf, sizeof(sbuf)); 439 printf(" 0x%s\n", sbuf); 440 441 } while (v & 0x8000); 442 #endif 443 sc->tx_start = sc->tx_end = sc->rx_size; 444 sc->tx_last = 0; 445 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 446 } 447 448 void 449 iyreset(sc) 450 struct iy_softc *sc; 451 { 452 int s; 453 s = splnet(); 454 iystop(sc); 455 iyinit(sc); 456 splx(s); 457 } 458 459 void 460 iyinit(sc) 461 struct iy_softc *sc; 462 { 463 int i; 464 unsigned temp; 465 struct ifnet *ifp; 466 bus_space_tag_t iot; 467 bus_space_handle_t ioh; 468 469 iot = sc->sc_iot; 470 ioh = sc->sc_ioh; 471 472 ifp = &sc->sc_ethercom.ec_if; 473 #ifdef IYDEBUG 474 printf("ifp is %p\n", ifp); 475 #endif 476 477 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 478 479 temp = bus_space_read_1(iot, ioh, EEPROM_REG); 480 if (temp & 0x10) 481 bus_space_write_1(iot, ioh, EEPROM_REG, temp & ~0x10); 482 483 for (i=0; i<6; ++i) { 484 bus_space_write_1(iot, ioh, I_ADD(i), LLADDR(ifp->if_sadl)[i]); 485 } 486 487 temp = bus_space_read_1(iot, ioh, REG1); 488 bus_space_write_1(iot, ioh, REG1, 489 temp | /* XMT_CHAIN_INT | XMT_CHAIN_ERRSTOP | */ RCV_DISCARD_BAD); 490 491 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 492 temp = MATCH_ALL; 493 } else 494 temp = MATCH_BRDCST; 495 496 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 497 498 #ifdef IYDEBUG 499 { 500 char sbuf[128]; 501 502 bitmask_snprintf(temp, "\020\1PRMSC\2NOBRDST\3SEECRC\4LENGTH\5NOSaIns\6MultiIA", 503 sbuf, sizeof(sbuf)); 504 printf("%s: RECV_MODES set to %s\n", sc->sc_dev.dv_xname, sbuf); 505 } 506 #endif 507 /* XXX VOODOO */ 508 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 509 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 510 /* XXX END OF VOODOO */ 511 512 513 delay(500000); /* for the hardware to test for the connector */ 514 515 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 516 #ifdef IYDEBUG 517 { 518 char sbuf[128]; 519 520 bitmask_snprintf(temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC", 521 sbuf, sizeof(sbuf)); 522 printf("%s: media select was 0x%s ", sc->sc_dev.dv_xname, sbuf); 523 } 524 #endif 525 temp = (temp & TEST_MODE_MASK); 526 527 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 528 case IFM_10_5: 529 temp &= ~ (BNC_BIT | TPE_BIT); 530 break; 531 532 case IFM_10_2: 533 temp = (temp & ~TPE_BIT) | BNC_BIT; 534 break; 535 536 case IFM_10_T: 537 temp = (temp & ~BNC_BIT) | TPE_BIT; 538 break; 539 default: 540 ; 541 /* nothing; leave as it is */ 542 } 543 switch (temp & (BNC_BIT | TPE_BIT)) { 544 case BNC_BIT: 545 sc->iy_media = IFM_ETHER | IFM_10_2; 546 break; 547 case TPE_BIT: 548 sc->iy_media = IFM_ETHER | IFM_10_T; 549 break; 550 default: 551 sc->iy_media = IFM_ETHER | IFM_10_5; 552 } 553 554 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 555 #ifdef IYDEBUG 556 { 557 char sbuf[128]; 558 559 bitmask_snprintf(temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC", 560 sbuf, sizeof(sbuf)); 561 printf("changed to 0x%s\n", sbuf); 562 } 563 #endif 564 565 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 566 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 567 bus_space_write_1(iot, ioh, 0, BANK_SEL(1)); 568 569 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 570 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 571 572 #ifdef IYDEBUG 573 { 574 char sbuf[128]; 575 576 bitmask_snprintf(temp, "\020\4bad_irq\010flash/boot present", 577 sbuf, sizeof(sbuf)); 578 printf("%s: int no was %s\n", sc->sc_dev.dv_xname, sbuf); 579 580 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 581 bitmask_snprintf(temp, "\020\4bad_irq\010flash/boot present", 582 sbuf, sizeof(sbuf)); 583 printf("%s: int no now %s\n", sc->sc_dev.dv_xname, sbuf); 584 } 585 #endif 586 587 bus_space_write_1(iot, ioh, RCV_LOWER_LIMIT_REG, 0); 588 bus_space_write_1(iot, ioh, RCV_UPPER_LIMIT_REG, (sc->rx_size -2) >>8); 589 bus_space_write_1(iot, ioh, XMT_LOWER_LIMIT_REG, sc->rx_size >>8); 590 bus_space_write_1(iot, ioh, XMT_UPPER_LIMIT_REG, (sc->sram - 2) >>8); 591 592 temp = bus_space_read_1(iot, ioh, REG1); 593 #ifdef IYDEBUG 594 { 595 char sbuf[128]; 596 597 bitmask_snprintf(temp, "\020\2WORD_WIDTH\010INT_ENABLE", 598 sbuf, sizeof(sbuf)); 599 printf("%s: HW access is %s\n", sc->sc_dev.dv_xname, sbuf); 600 } 601 #endif 602 bus_space_write_1(iot, ioh, REG1, temp | INT_ENABLE); /* XXX what about WORD_WIDTH? */ 603 604 #ifdef IYDEBUG 605 { 606 char sbuf[128]; 607 608 temp = bus_space_read_1(iot, ioh, REG1); 609 bitmask_snprintf(temp, "\020\2WORD_WIDTH\010INT_ENABLE", 610 sbuf, sizeof(sbuf)); 611 printf("%s: HW access is %s\n", sc->sc_dev.dv_xname, sbuf); 612 } 613 #endif 614 615 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 616 617 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS & ~(RX_BIT|TX_BIT)); 618 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); /* clear ints */ 619 620 bus_space_write_1(iot, ioh, RCV_COPY_THRESHOLD, 0); 621 622 bus_space_write_2(iot, ioh, RCV_START_LOW, 0); 623 bus_space_write_2(iot, ioh, RCV_STOP_LOW, sc->rx_size - 2); 624 sc->rx_start = 0; 625 626 bus_space_write_1(iot, ioh, 0, SEL_RESET_CMD); 627 delay(200); 628 629 bus_space_write_2(iot, ioh, XMT_ADDR_REG, sc->rx_size); 630 631 sc->tx_start = sc->tx_end = sc->rx_size; 632 sc->tx_last = 0; 633 634 bus_space_write_1(iot, ioh, 0, RCV_ENABLE_CMD); 635 636 ifp->if_flags |= IFF_RUNNING; 637 ifp->if_flags &= ~IFF_OACTIVE; 638 } 639 640 void 641 iystart(ifp) 642 struct ifnet *ifp; 643 { 644 struct iy_softc *sc; 645 646 647 struct mbuf *m0, *m; 648 u_int len, pad, last, end; 649 u_int llen, residual; 650 int avail; 651 caddr_t data; 652 unsigned temp; 653 u_int16_t resval, stat; 654 bus_space_tag_t iot; 655 bus_space_handle_t ioh; 656 657 #ifdef IYDEBUG 658 printf("iystart called\n"); 659 #endif 660 sc = ifp->if_softc; 661 662 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 663 return; 664 665 iy_intr_tx(sc); 666 667 iot = sc->sc_iot; 668 ioh = sc->sc_ioh; 669 670 for (;;) { 671 IFQ_POLL(&ifp->if_snd, m0); 672 if (m0 == NULL) 673 break; 674 #ifdef IYDEBUG 675 printf("%s: trying to write another packet to the hardware\n", 676 sc->sc_dev.dv_xname); 677 #endif 678 679 /* We need to use m->m_pkthdr.len, so require the header */ 680 if ((m0->m_flags & M_PKTHDR) == 0) 681 panic("iystart: no header mbuf"); 682 683 len = m0->m_pkthdr.len; 684 pad = len & 1; 685 686 #ifdef IYDEBUG 687 printf("%s: length is %d.\n", sc->sc_dev.dv_xname, len); 688 #endif 689 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 690 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 691 } 692 693 if (len + pad > ETHER_MAX_LEN) { 694 /* packet is obviously too large: toss it */ 695 ++ifp->if_oerrors; 696 IFQ_DEQUEUE(&ifp->if_snd, m0); 697 m_freem(m0); 698 continue; 699 } 700 701 #if NBPFILTER > 0 702 if (ifp->if_bpf) 703 bpf_mtap(ifp->if_bpf, m0); 704 #endif 705 706 avail = sc->tx_start - sc->tx_end; 707 if (avail <= 0) 708 avail += sc->tx_size; 709 710 #ifdef IYDEBUG 711 printf("%s: avail is %d.\n", sc->sc_dev.dv_xname, avail); 712 #endif 713 /* 714 * we MUST RUN at splnet here --- 715 * XXX todo: or even turn off the boards ints ??? hm... 716 */ 717 718 /* See if there is room to put another packet in the buffer. */ 719 720 if ((len+pad+2*I595_XMT_HDRLEN) > avail) { 721 #ifdef IYDEBUG 722 printf("%s: len = %d, avail = %d, setting OACTIVE\n", 723 sc->sc_dev.dv_xname, len, avail); 724 #endif 725 /* mark interface as full ... */ 726 ifp->if_flags |= IFF_OACTIVE; 727 728 /* and wait for any transmission result */ 729 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 730 731 temp = bus_space_read_1(iot, ioh, REG1); 732 bus_space_write_1(iot, ioh, REG1, 733 temp & ~XMT_CHAIN_INT); 734 735 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 736 737 return; 738 } 739 740 /* we know it fits in the hardware now, so dequeue it */ 741 IFQ_DEQUEUE(&ifp->if_snd, m0); 742 743 last = sc->tx_end; 744 end = last + pad + len + I595_XMT_HDRLEN; 745 746 if (end >= sc->sram) { 747 if ((sc->sram - last) <= I595_XMT_HDRLEN) { 748 /* keep header in one piece */ 749 last = sc->rx_size; 750 end = last + pad + len + I595_XMT_HDRLEN; 751 } else 752 end -= sc->tx_size; 753 } 754 755 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 756 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 757 htole16(XMT_CMD)); 758 759 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 760 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 761 762 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 763 htole16(len + pad)); 764 765 residual = resval = 0; 766 767 while ((m = m0)!=0) { 768 data = mtod(m, caddr_t); 769 llen = m->m_len; 770 if (residual) { 771 #ifdef IYDEBUG 772 printf("%s: merging residual with next mbuf.\n", 773 sc->sc_dev.dv_xname); 774 #endif 775 resval |= *data << 8; 776 bus_space_write_stream_2(iot, ioh, 777 MEM_PORT_REG, resval); 778 --llen; 779 ++data; 780 } 781 /* 782 * XXX ALIGNMENT LOSSAGE HERE. 783 */ 784 if (llen > 1) 785 bus_space_write_multi_stream_2(iot, ioh, 786 MEM_PORT_REG, (u_int16_t *) data, 787 llen>>1); 788 residual = llen & 1; 789 if (residual) { 790 resval = *(data + llen - 1); 791 #ifdef IYDEBUG 792 printf("%s: got odd mbuf to send.\n", 793 sc->sc_dev.dv_xname); 794 #endif 795 } 796 797 MFREE(m, m0); 798 } 799 800 if (residual) 801 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 802 resval); 803 804 pad >>= 1; 805 while (pad-- > 0) 806 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 0); 807 808 #ifdef IYDEBUG 809 printf("%s: new last = 0x%x, end = 0x%x.\n", 810 sc->sc_dev.dv_xname, last, end); 811 printf("%s: old start = 0x%x, end = 0x%x, last = 0x%x\n", 812 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 813 #endif 814 815 if (sc->tx_start != sc->tx_end) { 816 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 817 sc->tx_last + XMT_COUNT); 818 819 /* 820 * XXX We keep stat in le order, to potentially save 821 * a byte swap. 822 */ 823 stat = bus_space_read_stream_2(iot, ioh, MEM_PORT_REG); 824 825 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 826 sc->tx_last + XMT_CHAIN); 827 828 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 829 htole16(last)); 830 831 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 832 stat | htole16(CHAIN)); 833 #ifdef IYDEBUG 834 printf("%s: setting 0x%x to 0x%x\n", 835 sc->sc_dev.dv_xname, sc->tx_last + XMT_COUNT, 836 le16toh(stat) | CHAIN); 837 #endif 838 } 839 stat = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 840 841 /* XXX todo: enable ints here if disabled */ 842 843 ++ifp->if_opackets; 844 845 if (sc->tx_start == sc->tx_end) { 846 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 847 bus_space_write_1(iot, ioh, 0, XMT_CMD); 848 sc->tx_start = last; 849 #ifdef IYDEBUG 850 printf("%s: writing 0x%x to XAR and giving XCMD\n", 851 sc->sc_dev.dv_xname, last); 852 #endif 853 } else { 854 bus_space_write_1(iot, ioh, 0, RESUME_XMT_CMD); 855 #ifdef IYDEBUG 856 printf("%s: giving RESUME_XCMD\n", 857 sc->sc_dev.dv_xname); 858 #endif 859 } 860 sc->tx_last = last; 861 sc->tx_end = end; 862 } 863 /* and wait only for end of transmission chain */ 864 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 865 866 temp = bus_space_read_1(iot, ioh, REG1); 867 bus_space_write_1(iot, ioh, REG1, temp | XMT_CHAIN_INT); 868 869 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 870 } 871 872 873 static inline void 874 eepromwritebit(iot, ioh, what) 875 bus_space_tag_t iot; 876 bus_space_handle_t ioh; 877 int what; 878 { 879 bus_space_write_1(iot, ioh, EEPROM_REG, what); 880 delay(1); 881 bus_space_write_1(iot, ioh, EEPROM_REG, what|EESK); 882 delay(1); 883 bus_space_write_1(iot, ioh, EEPROM_REG, what); 884 delay(1); 885 } 886 887 static inline int 888 eepromreadbit(iot, ioh) 889 bus_space_tag_t iot; 890 bus_space_handle_t ioh; 891 { 892 int b; 893 894 bus_space_write_1(iot, ioh, EEPROM_REG, EECS|EESK); 895 delay(1); 896 b = bus_space_read_1(iot, ioh, EEPROM_REG); 897 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); 898 delay(1); 899 900 return ((b & EEDO) != 0); 901 } 902 903 static u_int16_t 904 eepromread(iot, ioh, offset) 905 bus_space_tag_t iot; 906 bus_space_handle_t ioh; 907 int offset; 908 { 909 volatile int i; 910 volatile int j; 911 volatile u_int16_t readval; 912 913 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 914 delay(1); 915 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); /* XXXX??? */ 916 delay(1); 917 918 eepromwritebit(iot, ioh, EECS|EEDI); 919 eepromwritebit(iot, ioh, EECS|EEDI); 920 eepromwritebit(iot, ioh, EECS); 921 922 for (j=5; j>=0; --j) { 923 if ((offset>>j) & 1) 924 eepromwritebit(iot, ioh, EECS|EEDI); 925 else 926 eepromwritebit(iot, ioh, EECS); 927 } 928 929 for (readval=0, i=0; i<16; ++i) { 930 readval<<=1; 931 readval |= eepromreadbit(iot, ioh); 932 } 933 934 bus_space_write_1(iot, ioh, EEPROM_REG, 0|EESK); 935 delay(1); 936 bus_space_write_1(iot, ioh, EEPROM_REG, 0); 937 938 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 939 940 return readval; 941 } 942 943 /* 944 * Device timeout/watchdog routine. Entered if the device neglects to generate 945 * an interrupt after a transmit has been started on it. 946 */ 947 void 948 iywatchdog(ifp) 949 struct ifnet *ifp; 950 { 951 struct iy_softc *sc = ifp->if_softc; 952 953 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 954 ++sc->sc_ethercom.ec_if.if_oerrors; 955 iyreset(sc); 956 } 957 958 /* 959 * What to do upon receipt of an interrupt. 960 */ 961 int 962 iyintr(arg) 963 void *arg; 964 { 965 struct iy_softc *sc; 966 struct ifnet *ifp; 967 bus_space_tag_t iot; 968 bus_space_handle_t ioh; 969 970 u_short status; 971 972 sc = arg; 973 iot = sc->sc_iot; 974 ioh = sc->sc_ioh; 975 976 ifp = &sc->sc_ethercom.ec_if; 977 978 status = bus_space_read_1(iot, ioh, STATUS_REG); 979 #ifdef IYDEBUG 980 if (status & ALL_INTS) { 981 char sbuf[128]; 982 983 bitmask_snprintf(status, "\020\1RX_STP\2RX\3TX\4EXEC", 984 sbuf, sizeof(sbuf)); 985 printf("%s: got interrupt %s", sc->sc_dev.dv_xname, sbuf); 986 987 if (status & EXEC_INT) { 988 bitmask_snprintf(bus_space_read_1(iot, ioh, 0), 989 "\020\6ABORT", sbuf, sizeof(sbuf)); 990 printf(" event %s\n", sbuf); 991 } else 992 printf("\n"); 993 } 994 #endif 995 if ((status & (RX_INT | TX_INT)) == 0) 996 return 0; 997 998 if (status & RX_INT) { 999 iy_intr_rx(sc); 1000 bus_space_write_1(iot, ioh, STATUS_REG, RX_INT); 1001 } 1002 if (status & TX_INT) { 1003 /* Tell feeders we may be able to accept more data... */ 1004 ifp->if_flags &= ~IFF_OACTIVE; 1005 /* and get more data. */ 1006 iystart(ifp); 1007 bus_space_write_1(iot, ioh, STATUS_REG, TX_INT); 1008 } 1009 1010 #if NRND > 0 1011 rnd_add_uint32(&sc->rnd_source, status); 1012 #endif 1013 1014 return 1; 1015 } 1016 1017 void 1018 iyget(sc, iot, ioh, rxlen) 1019 struct iy_softc *sc; 1020 bus_space_tag_t iot; 1021 bus_space_handle_t ioh; 1022 int rxlen; 1023 { 1024 struct mbuf *m, *top, **mp; 1025 struct ifnet *ifp; 1026 int len; 1027 1028 ifp = &sc->sc_ethercom.ec_if; 1029 1030 MGETHDR(m, M_DONTWAIT, MT_DATA); 1031 if (m == 0) 1032 goto dropped; 1033 m->m_pkthdr.rcvif = ifp; 1034 m->m_pkthdr.len = rxlen; 1035 len = MHLEN; 1036 top = 0; 1037 mp = ⊤ 1038 1039 while (rxlen > 0) { 1040 if (top) { 1041 MGET(m, M_DONTWAIT, MT_DATA); 1042 if (m == 0) { 1043 m_freem(top); 1044 goto dropped; 1045 } 1046 len = MLEN; 1047 } 1048 if (rxlen >= MINCLSIZE) { 1049 MCLGET(m, M_DONTWAIT); 1050 if ((m->m_flags & M_EXT) == 0) { 1051 m_free(m); 1052 m_freem(top); 1053 goto dropped; 1054 } 1055 len = MCLBYTES; 1056 } 1057 len = min(rxlen, len); 1058 /* 1059 * XXX ALIGNMENT LOSSAGE HERE. 1060 */ 1061 if (len > 1) { 1062 len &= ~1; 1063 1064 bus_space_read_multi_stream_2(iot, ioh, MEM_PORT_REG, 1065 mtod(m, u_int16_t *), len/2); 1066 } else { 1067 #ifdef IYDEBUG 1068 printf("%s: received odd mbuf\n", sc->sc_dev.dv_xname); 1069 #endif 1070 *(mtod(m, caddr_t)) = bus_space_read_stream_2(iot, ioh, 1071 MEM_PORT_REG); 1072 } 1073 m->m_len = len; 1074 rxlen -= len; 1075 *mp = m; 1076 mp = &m->m_next; 1077 } 1078 1079 if (top == NULL) 1080 return; 1081 1082 /* XXX receive the top here */ 1083 ++ifp->if_ipackets; 1084 1085 1086 #if NBPFILTER > 0 1087 if (ifp->if_bpf) 1088 bpf_mtap(ifp->if_bpf, top); 1089 #endif 1090 (*ifp->if_input)(ifp, top); 1091 return; 1092 1093 dropped: 1094 ++ifp->if_ierrors; 1095 return; 1096 } 1097 1098 void 1099 iy_intr_rx(sc) 1100 struct iy_softc *sc; 1101 { 1102 bus_space_tag_t iot; 1103 bus_space_handle_t ioh; 1104 1105 u_int rxadrs, rxevnt, rxstatus, rxnext, rxlen; 1106 1107 iot = sc->sc_iot; 1108 ioh = sc->sc_ioh; 1109 1110 rxadrs = sc->rx_start; 1111 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxadrs); 1112 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 1113 rxnext = 0; 1114 1115 while (rxevnt == RCV_DONE) { 1116 rxstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1117 MEM_PORT_REG)); 1118 rxnext = le16toh(bus_space_read_stream_2(iot, ioh, 1119 MEM_PORT_REG)); 1120 rxlen = le16toh(bus_space_read_stream_2(iot, ioh, 1121 MEM_PORT_REG)); 1122 #ifdef IYDEBUG 1123 { 1124 char sbuf[128]; 1125 1126 bitmask_snprintf(rxstatus, "\020\1RCLD\2IA_MCH\010SHORT\011OVRN\013ALGERR\014CRCERR\015LENERR\016RCVOK\020TYP", 1127 sbuf, sizeof(sbuf)); 1128 printf("%s: pck at 0x%04x stat %s next 0x%x len 0x%x\n", 1129 sc->sc_dev.dv_xname, rxadrs, sbuf, rxnext, rxlen); 1130 } 1131 #endif 1132 iyget(sc, iot, ioh, rxlen); 1133 1134 /* move stop address */ 1135 bus_space_write_2(iot, ioh, RCV_STOP_LOW, 1136 rxnext == 0 ? sc->rx_size - 2 : rxnext - 2); 1137 1138 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxnext); 1139 rxadrs = rxnext; 1140 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, 1141 MEM_PORT_REG)); 1142 } 1143 sc->rx_start = rxnext; 1144 } 1145 1146 void 1147 iy_intr_tx(sc) 1148 struct iy_softc *sc; 1149 { 1150 bus_space_tag_t iot; 1151 bus_space_handle_t ioh; 1152 struct ifnet *ifp; 1153 u_int txstatus, txstat2, txlen, txnext; 1154 1155 ifp = &sc->sc_ethercom.ec_if; 1156 iot = sc->sc_iot; 1157 ioh = sc->sc_ioh; 1158 1159 while (sc->tx_start != sc->tx_end) { 1160 bus_space_write_2(iot, ioh, HOST_ADDR_REG, sc->tx_start); 1161 txstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1162 MEM_PORT_REG)); 1163 1164 if ((txstatus & (TX_DONE|CMD_MASK)) != (TX_DONE|XMT_CMD)) 1165 break; 1166 1167 txstat2 = le16toh(bus_space_read_stream_2(iot, ioh, 1168 MEM_PORT_REG)); 1169 txnext = le16toh(bus_space_read_stream_2(iot, ioh, 1170 MEM_PORT_REG)); 1171 txlen = le16toh(bus_space_read_stream_2(iot, ioh, 1172 MEM_PORT_REG)); 1173 #ifdef IYDEBUG 1174 { 1175 char sbuf[128]; 1176 1177 bitmask_snprintf(txstat2, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 1178 sbuf, sizeof(sbuf)); 1179 printf("txstat 0x%x stat2 0x%s next 0x%x len 0x%x\n", 1180 txstatus, sbuf, txnext, txlen); 1181 } 1182 #endif 1183 if (txlen & CHAIN) 1184 sc->tx_start = txnext; 1185 else 1186 sc->tx_start = sc->tx_end; 1187 ifp->if_flags &= ~IFF_OACTIVE; 1188 1189 if (txstat2 & 0x0020) 1190 ifp->if_collisions += 16; 1191 else 1192 ifp->if_collisions += txstat2 & 0x000f; 1193 1194 if ((txstat2 & 0x2000) == 0) 1195 ++ifp->if_oerrors; 1196 } 1197 } 1198 1199 int 1200 iyioctl(ifp, cmd, data) 1201 struct ifnet *ifp; 1202 u_long cmd; 1203 caddr_t data; 1204 { 1205 struct iy_softc *sc; 1206 struct ifaddr *ifa; 1207 struct ifreq *ifr; 1208 int s, error = 0; 1209 1210 sc = ifp->if_softc; 1211 ifa = (struct ifaddr *)data; 1212 ifr = (struct ifreq *)data; 1213 1214 #ifdef IYDEBUG 1215 printf("iyioctl called with ifp %p (%s) cmd 0x%lx data %p\n", 1216 ifp, ifp->if_xname, cmd, data); 1217 #endif 1218 1219 s = splnet(); 1220 1221 switch (cmd) { 1222 1223 case SIOCSIFADDR: 1224 ifp->if_flags |= IFF_UP; 1225 1226 switch (ifa->ifa_addr->sa_family) { 1227 #ifdef INET 1228 case AF_INET: 1229 iyinit(sc); 1230 arp_ifinit(ifp, ifa); 1231 break; 1232 #endif 1233 default: 1234 iyinit(sc); 1235 break; 1236 } 1237 break; 1238 1239 case SIOCSIFFLAGS: 1240 sc->promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI); 1241 if ((ifp->if_flags & IFF_UP) == 0 && 1242 (ifp->if_flags & IFF_RUNNING) != 0) { 1243 /* 1244 * If interface is marked down and it is running, then 1245 * stop it. 1246 */ 1247 iystop(sc); 1248 ifp->if_flags &= ~IFF_RUNNING; 1249 } else if ((ifp->if_flags & IFF_UP) != 0 && 1250 (ifp->if_flags & IFF_RUNNING) == 0) { 1251 /* 1252 * If interface is marked up and it is stopped, then 1253 * start it. 1254 */ 1255 iyinit(sc); 1256 } else { 1257 /* 1258 * Reset the interface to pick up changes in any other 1259 * flags that affect hardware registers. 1260 */ 1261 iystop(sc); 1262 iyinit(sc); 1263 } 1264 #ifdef IYDEBUGX 1265 if (ifp->if_flags & IFF_DEBUG) 1266 sc->sc_debug = IFY_ALL; 1267 else 1268 sc->sc_debug = 0; 1269 #endif 1270 break; 1271 1272 case SIOCADDMULTI: 1273 case SIOCDELMULTI: 1274 error = (cmd == SIOCADDMULTI) ? 1275 ether_addmulti(ifr, &sc->sc_ethercom): 1276 ether_delmulti(ifr, &sc->sc_ethercom); 1277 1278 if (error == ENETRESET) { 1279 /* 1280 * Multicast list has changed; set the hardware filter 1281 * accordingly. 1282 */ 1283 if (ifp->if_flags & IFF_RUNNING) { 1284 /* XXX can't make it work otherwise */ 1285 iyreset(sc); 1286 iy_mc_reset(sc); 1287 } 1288 error = 0; 1289 } 1290 break; 1291 1292 case SIOCSIFMEDIA: 1293 case SIOCGIFMEDIA: 1294 error = ifmedia_ioctl(ifp, ifr, &sc->iy_ifmedia, cmd); 1295 break; 1296 default: 1297 error = EINVAL; 1298 } 1299 splx(s); 1300 return error; 1301 } 1302 1303 int 1304 iy_mediachange(ifp) 1305 struct ifnet *ifp; 1306 { 1307 struct iy_softc *sc = ifp->if_softc; 1308 1309 if (IFM_TYPE(sc->iy_ifmedia.ifm_media) != IFM_ETHER) 1310 return EINVAL; 1311 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 1312 case IFM_10_5: 1313 case IFM_10_2: 1314 case IFM_10_T: 1315 case IFM_AUTO: 1316 iystop(sc); 1317 iyinit(sc); 1318 return 0; 1319 default: 1320 return EINVAL; 1321 } 1322 } 1323 1324 void 1325 iy_mediastatus(ifp, ifmr) 1326 struct ifnet *ifp; 1327 struct ifmediareq *ifmr; 1328 { 1329 struct iy_softc *sc = ifp->if_softc; 1330 1331 ifmr->ifm_active = sc->iy_media; 1332 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1333 } 1334 1335 1336 static void 1337 iy_mc_setup(sc) 1338 struct iy_softc *sc; 1339 { 1340 struct ether_multi *enm; 1341 struct ether_multistep step; 1342 struct ethercom *ecp; 1343 struct ifnet *ifp; 1344 bus_space_tag_t iot; 1345 bus_space_handle_t ioh; 1346 int avail, last /*, end*/ , len; 1347 int timeout; 1348 volatile u_int16_t dum; 1349 u_int8_t temp; 1350 1351 1352 ecp = &sc->sc_ethercom; 1353 ifp = &ecp->ec_if; 1354 1355 iot = sc->sc_iot; 1356 ioh = sc->sc_ioh; 1357 1358 len = 6 * ecp->ec_multicnt; 1359 1360 avail = sc->tx_start - sc->tx_end; 1361 if (avail <= 0) 1362 avail += sc->tx_size; 1363 if (ifp->if_flags & IFF_DEBUG) 1364 printf("%s: iy_mc_setup called, %d addresses, " 1365 "%d/%d bytes needed/avail\n", ifp->if_xname, 1366 ecp->ec_multicnt, len + I595_XMT_HDRLEN, avail); 1367 1368 last = sc->rx_size; 1369 1370 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1371 bus_space_write_1(iot, ioh, RECV_MODES_REG, MATCH_BRDCST); 1372 /* XXX VOODOO */ 1373 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1374 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1375 /* XXX END OF VOODOO */ 1376 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1377 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 1378 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(MC_SETUP_CMD)); 1379 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1380 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1381 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(len)); 1382 1383 ETHER_FIRST_MULTI(step, ecp, enm); 1384 while(enm) { 1385 /* 1386 * XXX ALIGNMENT LOSSAGE HERE? 1387 */ 1388 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1389 (u_int16_t *) enm->enm_addrlo, 3); 1390 1391 ETHER_NEXT_MULTI(step, enm); 1392 } 1393 dum = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 1394 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 1395 bus_space_write_1(iot, ioh, 0, MC_SETUP_CMD); 1396 1397 1398 sc->tx_start = sc->rx_size; 1399 sc->tx_end = sc->rx_size + I595_XMT_HDRLEN + len; 1400 1401 for (timeout=0; timeout<100; timeout++) { 1402 DELAY(2); 1403 if ((bus_space_read_1(iot, ioh, STATUS_REG) & EXEC_INT) == 0) 1404 continue; 1405 1406 temp = bus_space_read_1(iot, ioh, 0); 1407 bus_space_write_1(iot, ioh, STATUS_REG, EXEC_INT); 1408 #ifdef DIAGNOSTIC 1409 if (temp & 0x20) { 1410 printf("%s: mc setup failed, %d usec\n", 1411 sc->sc_dev.dv_xname, timeout * 2); 1412 } else if (((temp & 0x0f) == 0x03) && 1413 (ifp->if_flags & IFF_DEBUG)) { 1414 printf("%s: mc setup done, %d usec\n", 1415 sc->sc_dev.dv_xname, timeout * 2); 1416 } 1417 #endif 1418 break; 1419 } 1420 sc->tx_start = sc->tx_end; 1421 ifp->if_flags &= ~IFF_OACTIVE; 1422 1423 } 1424 1425 static void 1426 iy_mc_reset(sc) 1427 struct iy_softc *sc; 1428 { 1429 struct ether_multi *enm; 1430 struct ether_multistep step; 1431 struct ethercom *ecp; 1432 struct ifnet *ifp; 1433 bus_space_tag_t iot; 1434 bus_space_handle_t ioh; 1435 u_int16_t temp; 1436 1437 ecp = &sc->sc_ethercom; 1438 ifp = &ecp->ec_if; 1439 1440 iot = sc->sc_iot; 1441 ioh = sc->sc_ioh; 1442 1443 if (ecp->ec_multicnt > 63) { 1444 ifp->if_flags |= IFF_ALLMULTI; 1445 1446 } else if (ecp->ec_multicnt > 0) { 1447 /* 1448 * Step through the list of addresses. 1449 */ 1450 ETHER_FIRST_MULTI(step, ecp, enm); 1451 while(enm) { 1452 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1453 ifp->if_flags |= IFF_ALLMULTI; 1454 goto setupmulti; 1455 } 1456 ETHER_NEXT_MULTI(step, enm); 1457 } 1458 /* OK, we really need to do it now: */ 1459 #if 0 1460 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) 1461 != IFF_RUNNING) { 1462 ifp->if_flags |= IFF_OACTIVE; 1463 sc->want_mc_setup = 1; 1464 return; 1465 } 1466 #endif 1467 iy_mc_setup(sc); 1468 } else { 1469 ifp->if_flags &= ~IFF_ALLMULTI; 1470 } 1471 1472 setupmulti: 1473 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1474 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 1475 temp = MATCH_ALL; 1476 } else 1477 temp = MATCH_BRDCST; 1478 1479 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 1480 /* XXX VOODOO */ 1481 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1482 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1483 /* XXX END OF VOODOO */ 1484 1485 /* XXX TBD: setup hardware for all multicasts */ 1486 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1487 return; 1488 } 1489 1490 #ifdef IYDEBUGX 1491 void 1492 print_rbd(rbd) 1493 volatile struct ie_recv_buf_desc *rbd; 1494 { 1495 printf("RBD at %08lx:\nactual %04x, next %04x, buffer %08x\n" 1496 "length %04x, mbz %04x\n", (u_long)rbd, rbd->ie_rbd_actual, 1497 rbd->ie_rbd_next, rbd->ie_rbd_buffer, rbd->ie_rbd_length, 1498 rbd->mbz); 1499 } 1500 #endif 1501 1502 void 1503 iyprobemem(sc) 1504 struct iy_softc *sc; 1505 { 1506 bus_space_tag_t iot; 1507 bus_space_handle_t ioh; 1508 int testing; 1509 1510 iot = sc->sc_iot; 1511 ioh = sc->sc_ioh; 1512 1513 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 1514 delay(1); 1515 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 4096-2); 1516 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1517 1518 for (testing=65536; testing >= 4096; testing >>= 1) { 1519 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1520 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xdead); 1521 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1522 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xdead) { 1523 #ifdef IYMEMDEBUG 1524 printf("%s: Didn't keep 0xdead at 0x%x\n", 1525 sc->sc_dev.dv_xname, testing-2); 1526 #endif 1527 continue; 1528 } 1529 1530 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1531 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xbeef); 1532 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1533 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xbeef) { 1534 #ifdef IYMEMDEBUG 1535 printf("%s: Didn't keep 0xbeef at 0x%x\n", 1536 sc->sc_dev.dv_xname, testing-2); 1537 #endif 1538 continue; 1539 } 1540 1541 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1542 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1543 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing >> 1); 1544 bus_space_write_2(iot, ioh, MEM_PORT_REG, testing >> 1); 1545 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1546 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) == (testing >> 1)) { 1547 #ifdef IYMEMDEBUG 1548 printf("%s: 0x%x alias of 0x0\n", 1549 sc->sc_dev.dv_xname, testing >> 1); 1550 #endif 1551 continue; 1552 } 1553 1554 break; 1555 } 1556 1557 sc->sram = testing; 1558 1559 switch(testing) { 1560 case 65536: 1561 /* 4 NFS packets + overhead RX, 2 NFS + overhead TX */ 1562 sc->rx_size = 44*1024; 1563 break; 1564 1565 case 32768: 1566 /* 2 NFS packets + overhead RX, 1 NFS + overhead TX */ 1567 sc->rx_size = 22*1024; 1568 break; 1569 1570 case 16384: 1571 /* 1 NFS packet + overhead RX, 4 big packets TX */ 1572 sc->rx_size = 10*1024; 1573 break; 1574 default: 1575 sc->rx_size = testing/2; 1576 break; 1577 } 1578 sc->tx_size = testing - sc->rx_size; 1579 } 1580 1581 static int 1582 eepromreadall(iot, ioh, wordp, maxi) 1583 bus_space_tag_t iot; 1584 bus_space_handle_t ioh; 1585 u_int16_t *wordp; 1586 int maxi; 1587 { 1588 int i; 1589 u_int16_t checksum, tmp; 1590 1591 checksum = 0; 1592 1593 for (i=0; i<EEPP_LENGTH; ++i) { 1594 tmp = eepromread(iot, ioh, i); 1595 checksum += tmp; 1596 if (i<maxi) 1597 wordp[i] = tmp; 1598 } 1599 1600 if (checksum != EEPP_CHKSUM) { 1601 #ifdef IYDEBUG 1602 printf("wrong EEPROM checksum 0x%x should be 0x%x\n", 1603 checksum, EEPP_CHKSUM); 1604 #endif 1605 return 1; 1606 } 1607 return 0; 1608 } 1609
Indexes created Wed Oct 01 15:09:59 GMT 2025