if_we_isa.c revision 1.1.4.5
1 /* $NetBSD: if_we_isa.c,v 1.1.4.5 2002/01/11 23:39:08 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 42 * adapters. 43 * 44 * Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved. 45 * 46 * Copyright (C) 1993, David Greenman. This software may be used, modified, 47 * copied, distributed, and sold, in both source and binary form provided that 48 * the above copyright and these terms are retained. Under no circumstances is 49 * the author responsible for the proper functioning of this software, nor does 50 * the author assume any responsibility for damages incurred with its use. 51 */ 52 53 /* 54 * Device driver for the Western Digital/SMC 8003 and 8013 series, 55 * and the SMC Elite Ultra (8216). 56 */ 57 58 #include <sys/cdefs.h> 59 __KERNEL_RCSID(0, "$NetBSD: if_we_isa.c,v 1.1.4.5 2002/01/11 23:39:08 nathanw Exp $"); 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/device.h> 64 #include <sys/socket.h> 65 #include <sys/mbuf.h> 66 #include <sys/syslog.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_types.h> 71 #include <net/if_media.h> 72 73 #include <net/if_ether.h> 74 75 #include <machine/bus.h> 76 #include <machine/bswap.h> 77 #include <machine/intr.h> 78 79 #include <dev/isa/isareg.h> 80 #include <dev/isa/isavar.h> 81 82 #include <dev/ic/dp8390reg.h> 83 #include <dev/ic/dp8390var.h> 84 #include <dev/ic/wereg.h> 85 #include <dev/ic/wevar.h> 86 87 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 88 #define bus_space_read_region_stream_2 bus_space_read_region_2 89 #define bus_space_write_stream_2 bus_space_write_2 90 #define bus_space_write_region_stream_2 bus_space_write_region_2 91 #endif 92 93 int we_isa_probe __P((struct device *, struct cfdata *, void *)); 94 void we_isa_attach __P((struct device *, struct device *, void *)); 95 96 struct cfattach we_isa_ca = { 97 sizeof(struct we_softc), we_isa_probe, we_isa_attach 98 }; 99 100 extern struct cfdriver we_cd; 101 102 static const char *we_params __P((bus_space_tag_t, bus_space_handle_t, 103 u_int8_t *, bus_size_t *, int *, int *)); 104 105 static const int we_584_irq[] = { 106 9, 3, 5, 7, 10, 11, 15, 4, 107 }; 108 #define NWE_584_IRQ (sizeof(we_584_irq) / sizeof(we_584_irq[0])) 109 110 static const int we_790_irq[] = { 111 ISACF_IRQ_DEFAULT, 9, 3, 5, 7, 10, 11, 15, 112 }; 113 #define NWE_790_IRQ (sizeof(we_790_irq) / sizeof(we_790_irq[0])) 114 115 /* 116 * Delay needed when switching 16-bit access to shared memory. 117 */ 118 #define WE_DELAY(wsc) delay(3) 119 120 /* 121 * Enable card RAM, and 16-bit access. 122 */ 123 #define WE_MEM_ENABLE(wsc) \ 124 do { \ 125 if ((wsc)->sc_16bitp) \ 126 bus_space_write_1((wsc)->sc_asict, (wsc)->sc_asich, \ 127 WE_LAAR, (wsc)->sc_laar_proto | WE_LAAR_M16EN); \ 128 bus_space_write_1((wsc)->sc_asict, (wsc)->sc_asich, \ 129 WE_MSR, wsc->sc_msr_proto | WE_MSR_MENB); \ 130 WE_DELAY((wsc)); \ 131 } while (0) 132 133 /* 134 * Disable card RAM, and 16-bit access. 135 */ 136 #define WE_MEM_DISABLE(wsc) \ 137 do { \ 138 bus_space_write_1((wsc)->sc_asict, (wsc)->sc_asich, \ 139 WE_MSR, (wsc)->sc_msr_proto); \ 140 if ((wsc)->sc_16bitp) \ 141 bus_space_write_1((wsc)->sc_asict, (wsc)->sc_asich, \ 142 WE_LAAR, (wsc)->sc_laar_proto); \ 143 WE_DELAY((wsc)); \ 144 } while (0) 145 146 int 147 we_isa_probe(parent, cf, aux) 148 struct device *parent; 149 struct cfdata *cf; 150 void *aux; 151 { 152 struct isa_attach_args *ia = aux; 153 bus_space_tag_t asict, memt; 154 bus_space_handle_t asich, memh; 155 bus_size_t memsize; 156 int asich_valid, memh_valid; 157 int i, is790, rv = 0; 158 u_int8_t x, type; 159 160 asict = ia->ia_iot; 161 memt = ia->ia_memt; 162 163 asich_valid = memh_valid = 0; 164 165 if (ia->ia_nio < 1) 166 return (0); 167 if (ia->ia_niomem < 1) 168 return (0); 169 if (ia->ia_nirq < 1) 170 return (0); 171 172 if (ISA_DIRECT_CONFIG(ia)) 173 return (0); 174 175 /* Disallow wildcarded i/o addresses. */ 176 if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT) 177 return (0); 178 179 /* Disallow wildcarded mem address. */ 180 if (ia->ia_iomem[0].ir_addr == ISACF_IOMEM_DEFAULT) 181 return (0); 182 183 /* Attempt to map the device. */ 184 if (bus_space_map(asict, ia->ia_io[0].ir_addr, WE_NPORTS, 0, &asich)) 185 goto out; 186 asich_valid = 1; 187 188 #ifdef TOSH_ETHER 189 bus_space_write_1(asict, asich, WE_MSR, WE_MSR_POW); 190 #endif 191 192 /* 193 * Attempt to do a checksum over the station address PROM. 194 * If it fails, it's probably not a WD/SMC board. There is 195 * a problem with this, though. Some clone WD8003E boards 196 * (e.g. Danpex) won't pass the checksum. In this case, 197 * the checksum byte always seems to be 0. 198 */ 199 for (x = 0, i = 0; i < 8; i++) 200 x += bus_space_read_1(asict, asich, WE_PROM + i); 201 202 if (x != WE_ROM_CHECKSUM_TOTAL) { 203 /* Make sure it's an 8003E clone... */ 204 if (bus_space_read_1(asict, asich, WE_CARD_ID) != 205 WE_TYPE_WD8003E) 206 goto out; 207 208 /* Check the checksum byte. */ 209 if (bus_space_read_1(asict, asich, WE_PROM + 7) != 0) 210 goto out; 211 } 212 213 /* 214 * Reset the card to force it into a known state. 215 */ 216 #ifdef TOSH_ETHER 217 bus_space_write_1(asict, asich, WE_MSR, WE_MSR_RST | WE_MSR_POW); 218 #else 219 bus_space_write_1(asict, asich, WE_MSR, WE_MSR_RST); 220 #endif 221 delay(100); 222 223 bus_space_write_1(asict, asich, WE_MSR, 224 bus_space_read_1(asict, asich, WE_MSR) & ~WE_MSR_RST); 225 226 /* Wait in case the card is reading it's EEPROM. */ 227 delay(5000); 228 229 /* 230 * Get parameters. 231 */ 232 if (we_params(asict, asich, &type, &memsize, NULL, &is790) == NULL) 233 goto out; 234 235 /* Allow user to override probed value. */ 236 if (ia->ia_iomem[0].ir_size) 237 memsize = ia->ia_iomem[0].ir_size; 238 239 /* Attempt to map the memory space. */ 240 if (bus_space_map(memt, ia->ia_iomem[0].ir_addr, memsize, 0, &memh)) 241 goto out; 242 memh_valid = 1; 243 244 /* 245 * If possible, get the assigned interrupt number from the card 246 * and use it. 247 */ 248 if (is790) { 249 u_int8_t hwr; 250 251 /* Assemble together the encoded interrupt number. */ 252 hwr = bus_space_read_1(asict, asich, WE790_HWR); 253 bus_space_write_1(asict, asich, WE790_HWR, 254 hwr | WE790_HWR_SWH); 255 256 x = bus_space_read_1(asict, asich, WE790_GCR); 257 i = ((x & WE790_GCR_IR2) >> 4) | 258 ((x & (WE790_GCR_IR1|WE790_GCR_IR0)) >> 2); 259 bus_space_write_1(asict, asich, WE790_HWR, 260 hwr & ~WE790_HWR_SWH); 261 262 if (ia->ia_irq[0].ir_irq != ISACF_IRQ_DEFAULT && 263 ia->ia_irq[0].ir_irq != we_790_irq[i]) 264 printf("%s%d: overriding configured IRQ %d to %d\n", 265 we_cd.cd_name, cf->cf_unit, ia->ia_irq[0].ir_irq, 266 we_790_irq[i]); 267 ia->ia_irq[0].ir_irq = we_790_irq[i]; 268 } else if (type & WE_SOFTCONFIG) { 269 /* Assemble together the encoded interrupt number. */ 270 i = (bus_space_read_1(asict, asich, WE_ICR) & WE_ICR_IR2) | 271 ((bus_space_read_1(asict, asich, WE_IRR) & 272 (WE_IRR_IR0 | WE_IRR_IR1)) >> 5); 273 274 if (ia->ia_irq[0].ir_irq != ISACF_IRQ_DEFAULT && 275 ia->ia_irq[0].ir_irq != we_584_irq[i]) 276 printf("%s%d: overriding configured IRQ %d to %d\n", 277 we_cd.cd_name, cf->cf_unit, ia->ia_irq[0].ir_irq, 278 we_584_irq[i]); 279 ia->ia_irq[0].ir_irq = we_584_irq[i]; 280 } 281 282 /* So, we say we've found it! */ 283 ia->ia_nio = 1; 284 ia->ia_io[0].ir_size = WE_NPORTS; 285 286 ia->ia_niomem = 1; 287 ia->ia_iomem[0].ir_size = memsize; 288 289 ia->ia_nirq = 1; 290 291 ia->ia_ndrq = 0; 292 293 rv = 1; 294 295 out: 296 if (asich_valid) 297 bus_space_unmap(asict, asich, WE_NPORTS); 298 if (memh_valid) 299 bus_space_unmap(memt, memh, memsize); 300 return (rv); 301 } 302 303 void 304 we_isa_attach(parent, self, aux) 305 struct device *parent, *self; 306 void *aux; 307 { 308 struct we_softc *wsc = (struct we_softc *)self; 309 struct dp8390_softc *sc = &wsc->sc_dp8390; 310 struct isa_attach_args *ia = aux; 311 bus_space_tag_t nict, asict, memt; 312 bus_space_handle_t nich, asich, memh; 313 const char *typestr; 314 315 printf("\n"); 316 317 nict = asict = ia->ia_iot; 318 memt = ia->ia_memt; 319 320 /* Map the device. */ 321 if (bus_space_map(asict, ia->ia_io[0].ir_addr, WE_NPORTS, 0, &asich)) { 322 printf("%s: can't map nic i/o space\n", 323 sc->sc_dev.dv_xname); 324 return; 325 } 326 327 if (bus_space_subregion(asict, asich, WE_NIC_OFFSET, WE_NIC_NPORTS, 328 &nich)) { 329 printf("%s: can't subregion i/o space\n", 330 sc->sc_dev.dv_xname); 331 return; 332 } 333 334 typestr = we_params(asict, asich, &wsc->sc_type, NULL, 335 &wsc->sc_16bitp, &sc->is790); 336 if (typestr == NULL) { 337 printf("%s: where did the card go?\n", sc->sc_dev.dv_xname); 338 return; 339 } 340 341 /* 342 * Map memory space. Note we use the size that might have 343 * been overridden by the user. 344 */ 345 if (bus_space_map(memt, ia->ia_iomem[0].ir_addr, 346 ia->ia_iomem[0].ir_size, 0, &memh)) { 347 printf("%s: can't map shared memory\n", 348 sc->sc_dev.dv_xname); 349 return; 350 } 351 352 wsc->sc_asict = asict; 353 wsc->sc_asich = asich; 354 355 sc->sc_regt = nict; 356 sc->sc_regh = nich; 357 358 sc->sc_buft = memt; 359 sc->sc_bufh = memh; 360 361 wsc->sc_maddr = ia->ia_iomem[0].ir_addr; 362 sc->mem_size = ia->ia_iomem[0].ir_size; 363 364 /* Interface is always enabled. */ 365 sc->sc_enabled = 1; 366 367 if (we_config(self, wsc, typestr)) 368 return; 369 370 /* 371 * Enable the configured interrupt. 372 */ 373 if (sc->is790) 374 bus_space_write_1(asict, asich, WE790_ICR, 375 bus_space_read_1(asict, asich, WE790_ICR) | 376 WE790_ICR_EIL); 377 else if (wsc->sc_type & WE_SOFTCONFIG) 378 bus_space_write_1(asict, asich, WE_IRR, 379 bus_space_read_1(asict, asich, WE_IRR) | WE_IRR_IEN); 380 else if (ia->ia_irq[0].ir_irq == ISACF_IRQ_DEFAULT) { 381 printf("%s: can't wildcard IRQ on a %s\n", 382 sc->sc_dev.dv_xname, typestr); 383 return; 384 } 385 386 /* Establish interrupt handler. */ 387 wsc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 388 IST_EDGE, IPL_NET, dp8390_intr, sc); 389 if (wsc->sc_ih == NULL) 390 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 391 } 392 393 static const char * 394 we_params(asict, asich, typep, memsizep, is16bitp, is790p) 395 bus_space_tag_t asict; 396 bus_space_handle_t asich; 397 u_int8_t *typep; 398 bus_size_t *memsizep; 399 int *is16bitp, *is790p; 400 { 401 const char *typestr; 402 bus_size_t memsize; 403 int is16bit, is790; 404 u_int8_t type; 405 406 memsize = 8192; 407 is16bit = is790 = 0; 408 409 type = bus_space_read_1(asict, asich, WE_CARD_ID); 410 switch (type) { 411 case WE_TYPE_WD8003S: 412 typestr = "WD8003S"; 413 break; 414 case WE_TYPE_WD8003E: 415 typestr = "WD8003E"; 416 break; 417 case WE_TYPE_WD8003EB: 418 typestr = "WD8003EB"; 419 break; 420 case WE_TYPE_WD8003W: 421 typestr = "WD8003W"; 422 break; 423 case WE_TYPE_WD8013EBT: 424 typestr = "WD8013EBT"; 425 memsize = 16384; 426 is16bit = 1; 427 break; 428 case WE_TYPE_WD8013W: 429 typestr = "WD8013W"; 430 memsize = 16384; 431 is16bit = 1; 432 break; 433 case WE_TYPE_WD8013EP: /* also WD8003EP */ 434 if (bus_space_read_1(asict, asich, WE_ICR) & WE_ICR_16BIT) { 435 is16bit = 1; 436 memsize = 16384; 437 typestr = "WD8013EP"; 438 } else 439 typestr = "WD8003EP"; 440 break; 441 case WE_TYPE_WD8013WC: 442 typestr = "WD8013WC"; 443 memsize = 16384; 444 is16bit = 1; 445 break; 446 case WE_TYPE_WD8013EBP: 447 typestr = "WD8013EBP"; 448 memsize = 16384; 449 is16bit = 1; 450 break; 451 case WE_TYPE_WD8013EPC: 452 typestr = "WD8013EPC"; 453 memsize = 16384; 454 is16bit = 1; 455 break; 456 case WE_TYPE_SMC8216C: 457 case WE_TYPE_SMC8216T: 458 { 459 u_int8_t hwr; 460 461 typestr = (type == WE_TYPE_SMC8216C) ? 462 "SMC8216/SMC8216C" : "SMC8216T"; 463 464 hwr = bus_space_read_1(asict, asich, WE790_HWR); 465 bus_space_write_1(asict, asich, WE790_HWR, 466 hwr | WE790_HWR_SWH); 467 switch (bus_space_read_1(asict, asich, WE790_RAR) & 468 WE790_RAR_SZ64) { 469 case WE790_RAR_SZ64: 470 memsize = 65536; 471 break; 472 case WE790_RAR_SZ32: 473 memsize = 32768; 474 break; 475 case WE790_RAR_SZ16: 476 memsize = 16384; 477 break; 478 case WE790_RAR_SZ8: 479 /* 8216 has 16K shared mem -- 8416 has 8K */ 480 typestr = (type == WE_TYPE_SMC8216C) ? 481 "SMC8416C/SMC8416BT" : "SMC8416T"; 482 memsize = 8192; 483 break; 484 } 485 bus_space_write_1(asict, asich, WE790_HWR, hwr); 486 487 is16bit = 1; 488 is790 = 1; 489 break; 490 } 491 #ifdef TOSH_ETHER 492 case WE_TYPE_TOSHIBA1: 493 typestr = "Toshiba1"; 494 memsize = 32768; 495 is16bit = 1; 496 break; 497 case WE_TYPE_TOSHIBA4: 498 typestr = "Toshiba4"; 499 memsize = 32768; 500 is16bit = 1; 501 break; 502 #endif 503 default: 504 /* Not one we recognize. */ 505 return (NULL); 506 } 507 508 /* 509 * Make some adjustments to initial values depending on what is 510 * found in the ICR. 511 */ 512 if (is16bit && (type != WE_TYPE_WD8013EBT) && 513 #ifdef TOSH_ETHER 514 (type != WE_TYPE_TOSHIBA1 && type != WE_TYPE_TOSHIBA4) && 515 #endif 516 (bus_space_read_1(asict, asich, WE_ICR) & WE_ICR_16BIT) == 0) { 517 is16bit = 0; 518 memsize = 8192; 519 } 520 521 #ifdef WE_DEBUG 522 { 523 int i; 524 525 printf("we_params: type = 0x%x, typestr = %s, is16bit = %d, " 526 "memsize = %d\n", type, typestr, is16bit, memsize); 527 for (i = 0; i < 8; i++) 528 printf(" %d -> 0x%x\n", i, 529 bus_space_read_1(asict, asich, i)); 530 } 531 #endif 532 533 if (typep != NULL) 534 *typep = type; 535 if (memsizep != NULL) 536 *memsizep = memsize; 537 if (is16bitp != NULL) 538 *is16bitp = is16bit; 539 if (is790p != NULL) 540 *is790p = is790; 541 return (typestr); 542 } 543
Indexes created Thu Oct 02 14:10:14 GMT 2025