isa.c revision 1.30 1 1.1 cgd /*-
2 1.1 cgd * Copyright (c) 1991 The Regents of the University of California.
3 1.1 cgd * All rights reserved.
4 1.1 cgd *
5 1.1 cgd * This code is derived from software contributed to Berkeley by
6 1.1 cgd * William Jolitz.
7 1.1 cgd *
8 1.1 cgd * Redistribution and use in source and binary forms, with or without
9 1.1 cgd * modification, are permitted provided that the following conditions
10 1.1 cgd * are met:
11 1.1 cgd * 1. Redistributions of source code must retain the above copyright
12 1.1 cgd * notice, this list of conditions and the following disclaimer.
13 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 cgd * notice, this list of conditions and the following disclaimer in the
15 1.1 cgd * documentation and/or other materials provided with the distribution.
16 1.1 cgd * 3. All advertising materials mentioning features or use of this software
17 1.1 cgd * must display the following acknowledgement:
18 1.1 cgd * This product includes software developed by the University of
19 1.1 cgd * California, Berkeley and its contributors.
20 1.1 cgd * 4. Neither the name of the University nor the names of its contributors
21 1.1 cgd * may be used to endorse or promote products derived from this software
22 1.1 cgd * without specific prior written permission.
23 1.1 cgd *
24 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 1.1 cgd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 1.1 cgd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 1.1 cgd * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 1.1 cgd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 1.1 cgd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 1.1 cgd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 1.1 cgd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 1.1 cgd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 1.1 cgd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 1.1 cgd * SUCH DAMAGE.
35 1.1 cgd *
36 1.13 cgd * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
37 1.30 mycroft * $Id: isa.c,v 1.30 1993/12/17 00:11:48 mycroft Exp $
38 1.1 cgd */
39 1.1 cgd
40 1.1 cgd /*
41 1.1 cgd * code to manage AT bus
42 1.2 cgd *
43 1.2 cgd * 92/08/18 Frank P. MacLachlan (fpm (at) crash.cts.com):
44 1.2 cgd * Fixed uninitialized variable problem and added code to deal
45 1.2 cgd * with DMA page boundaries in isa_dmarangecheck(). Fixed word
46 1.2 cgd * mode DMA count compution and reorganized DMA setup code in
47 1.2 cgd * isa_dmastart()
48 1.1 cgd */
49 1.1 cgd
50 1.1 cgd #include "param.h"
51 1.1 cgd #include "systm.h"
52 1.1 cgd #include "conf.h"
53 1.1 cgd #include "file.h"
54 1.1 cgd #include "buf.h"
55 1.1 cgd #include "uio.h"
56 1.1 cgd #include "syslog.h"
57 1.1 cgd #include "malloc.h"
58 1.1 cgd #include "machine/segments.h"
59 1.21 andrew #include "machine/cpufunc.h"
60 1.1 cgd #include "vm/vm.h"
61 1.1 cgd #include "i386/isa/isa_device.h"
62 1.1 cgd #include "i386/isa/isa.h"
63 1.1 cgd #include "i386/isa/icu.h"
64 1.1 cgd #include "i386/isa/ic/i8237.h"
65 1.1 cgd #include "i386/isa/ic/i8042.h"
66 1.16 mycroft #include "i386/isa/timerreg.h"
67 1.28 brezak #include "i386/isa/spkr_reg.h"
68 1.14 deraadt
69 1.14 deraadt /* sorry, has to be here, no place else really suitable */
70 1.14 deraadt #include "machine/pc/display.h"
71 1.14 deraadt u_short *Crtat = (u_short *)MONO_BUF;
72 1.1 cgd
73 1.2 cgd /*
74 1.2 cgd ** Register definitions for DMA controller 1 (channels 0..3):
75 1.2 cgd */
76 1.2 cgd #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
77 1.2 cgd #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
78 1.2 cgd #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
79 1.2 cgd #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
80 1.2 cgd
81 1.2 cgd /*
82 1.2 cgd ** Register definitions for DMA controller 2 (channels 4..7):
83 1.2 cgd */
84 1.30 mycroft #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
85 1.2 cgd #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
86 1.2 cgd #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
87 1.2 cgd #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
88 1.2 cgd
89 1.15 cgd int config_isadev(struct isa_device *, u_int *);
90 1.6 deraadt void config_attach(struct isa_driver *, struct isa_device *);
91 1.21 andrew static void sysbeepstop(int);
92 1.1 cgd
93 1.1 cgd /*
94 1.1 cgd * Configure all ISA devices
95 1.1 cgd */
96 1.21 andrew void
97 1.30 mycroft isa_configure()
98 1.30 mycroft {
99 1.1 cgd struct isa_device *dvp;
100 1.1 cgd struct isa_driver *dp;
101 1.1 cgd
102 1.1 cgd splhigh();
103 1.1 cgd INTREN(IRQ_SLAVE);
104 1.30 mycroft enable_intr();
105 1.30 mycroft
106 1.6 deraadt for (dvp = isa_devtab_tty; config_isadev(dvp,&ttymask); dvp++)
107 1.6 deraadt ;
108 1.6 deraadt for (dvp = isa_devtab_bio; config_isadev(dvp,&biomask); dvp++)
109 1.6 deraadt ;
110 1.6 deraadt for (dvp = isa_devtab_net; config_isadev(dvp,&netmask); dvp++)
111 1.6 deraadt ;
112 1.15 cgd for (dvp = isa_devtab_null; config_isadev(dvp, (u_int *) NULL); dvp++)
113 1.6 deraadt ;
114 1.7 cgd
115 1.30 mycroft printf("biomask %x ttymask %x netmask %x\n",
116 1.30 mycroft biomask, ttymask, netmask);
117 1.30 mycroft
118 1.30 mycroft biomask |= astmask;
119 1.30 mycroft ttymask |= astmask;
120 1.30 mycroft netmask |= astmask;
121 1.30 mycroft impmask = netmask | ttymask;
122 1.26 mycroft
123 1.30 mycroft spl0();
124 1.1 cgd }
125 1.1 cgd
126 1.1 cgd /*
127 1.1 cgd * Configure an ISA device.
128 1.1 cgd */
129 1.21 andrew int
130 1.1 cgd config_isadev(isdp, mp)
131 1.1 cgd struct isa_device *isdp;
132 1.15 cgd u_int *mp;
133 1.1 cgd {
134 1.1 cgd struct isa_driver *dp;
135 1.1 cgd
136 1.1 cgd if (dp = isdp->id_driver) {
137 1.1 cgd if (isdp->id_maddr) {
138 1.1 cgd extern u_int atdevbase;
139 1.1 cgd
140 1.15 cgd isdp->id_maddr -= 0xa0000; /* XXX should be a define */
141 1.1 cgd isdp->id_maddr += atdevbase;
142 1.1 cgd }
143 1.1 cgd isdp->id_alive = (*dp->probe)(isdp);
144 1.11 deraadt if (isdp->id_irq == (u_short)-1)
145 1.11 deraadt isdp->id_alive = 0;
146 1.15 cgd /*
147 1.15 cgd * Only print the I/O address range if id_alive != -1
148 1.15 cgd * Right now this is a temporary fix just for the new
149 1.15 cgd * NPX code so that if it finds a 486 that can use trap
150 1.15 cgd * 16 it will not report I/O addresses.
151 1.15 cgd * Rod Grimes 04/26/94
152 1.15 cgd *
153 1.15 cgd * XXX -- cgd
154 1.15 cgd */
155 1.1 cgd if (isdp->id_alive) {
156 1.1 cgd printf("%s%d", dp->name, isdp->id_unit);
157 1.27 cgd if (isdp->id_iobase) {
158 1.27 cgd printf(" at 0x%x", isdp->id_iobase);
159 1.27 cgd if ((isdp->id_iobase + isdp->id_alive - 1) !=
160 1.27 cgd isdp->id_iobase)
161 1.27 cgd printf("-0x%x", isdp->id_iobase +
162 1.27 cgd isdp->id_alive - 1);
163 1.27 cgd }
164 1.11 deraadt if (isdp->id_irq != 0)
165 1.15 cgd printf(" irq %d", ffs(isdp->id_irq)-1);
166 1.3 deraadt if (isdp->id_drq != -1)
167 1.15 cgd printf(" drq %d", isdp->id_drq);
168 1.4 cgd if (isdp->id_maddr != 0)
169 1.15 cgd printf(" maddr 0x%x", kvtop(isdp->id_maddr));
170 1.4 cgd if (isdp->id_msize != 0)
171 1.20 deraadt printf("-0x%x", kvtop(isdp->id_maddr) +
172 1.20 deraadt isdp->id_msize - 1);
173 1.4 cgd if (isdp->id_flags != 0)
174 1.15 cgd printf(" flags 0x%x", isdp->id_flags);
175 1.15 cgd printf(" on isa\n");
176 1.3 deraadt
177 1.6 deraadt config_attach(dp, isdp);
178 1.6 deraadt
179 1.12 deraadt if (isdp->id_irq) {
180 1.1 cgd int intrno;
181 1.1 cgd
182 1.1 cgd intrno = ffs(isdp->id_irq)-1;
183 1.15 cgd setidt(ICU_OFFSET+intrno, isdp->id_intr,
184 1.15 cgd SDT_SYS386IGT, SEL_KPL);
185 1.3 deraadt if(mp)
186 1.3 deraadt INTRMASK(*mp,isdp->id_irq);
187 1.15 cgd INTREN(isdp->id_irq);
188 1.1 cgd }
189 1.1 cgd }
190 1.1 cgd return (1);
191 1.1 cgd } else return(0);
192 1.1 cgd }
193 1.6 deraadt
194 1.6 deraadt void
195 1.6 deraadt config_attach(struct isa_driver *dp, struct isa_device *isdp)
196 1.6 deraadt {
197 1.6 deraadt extern struct isa_device isa_subdev[];
198 1.6 deraadt struct isa_device *dvp;
199 1.6 deraadt
200 1.6 deraadt if(isdp->id_masunit==-1) {
201 1.8 deraadt (void)(*dp->attach)(isdp);
202 1.6 deraadt return;
203 1.6 deraadt }
204 1.6 deraadt
205 1.6 deraadt if(isdp->id_masunit==0) {
206 1.6 deraadt for(dvp = isa_subdev; dvp->id_driver; dvp++) {
207 1.6 deraadt if (dvp->id_driver != dp)
208 1.6 deraadt continue;
209 1.10 deraadt if (dvp->id_masunit != isdp->id_unit)
210 1.6 deraadt continue;
211 1.6 deraadt if (dvp->id_physid == -1)
212 1.6 deraadt continue;
213 1.8 deraadt dvp->id_alive = (*dp->attach)(dvp);
214 1.6 deraadt }
215 1.6 deraadt for(dvp = isa_subdev; dvp->id_driver; dvp++) {
216 1.6 deraadt if (dvp->id_driver != dp)
217 1.6 deraadt continue;
218 1.10 deraadt if (dvp->id_masunit != isdp->id_unit)
219 1.6 deraadt continue;
220 1.6 deraadt if (dvp->id_physid != -1)
221 1.6 deraadt continue;
222 1.8 deraadt dvp->id_alive = (*dp->attach)(dvp);
223 1.6 deraadt }
224 1.6 deraadt return;
225 1.6 deraadt }
226 1.6 deraadt printf("id_masunit has weird value\n");
227 1.6 deraadt }
228 1.6 deraadt
229 1.1 cgd
230 1.1 cgd #define IDTVEC(name) __CONCAT(X,name)
231 1.1 cgd /* default interrupt vector table entries */
232 1.1 cgd extern IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
233 1.1 cgd IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
234 1.1 cgd IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
235 1.1 cgd IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
236 1.1 cgd
237 1.1 cgd static *defvec[16] = {
238 1.1 cgd &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
239 1.1 cgd &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
240 1.1 cgd &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
241 1.1 cgd &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15) };
242 1.1 cgd
243 1.1 cgd /* out of range default interrupt vector gate entry */
244 1.1 cgd extern IDTVEC(intrdefault);
245 1.15 cgd
246 1.1 cgd /*
247 1.1 cgd * Fill in default interrupt table (in case of spuruious interrupt
248 1.1 cgd * during configuration of kernel, setup interrupt control unit
249 1.1 cgd */
250 1.21 andrew void
251 1.1 cgd isa_defaultirq() {
252 1.1 cgd int i;
253 1.1 cgd
254 1.1 cgd /* icu vectors */
255 1.1 cgd for (i = NRSVIDT ; i < NRSVIDT+ICU_LEN ; i++)
256 1.1 cgd setidt(i, defvec[i], SDT_SYS386IGT, SEL_KPL);
257 1.15 cgd
258 1.1 cgd /* out of range vectors */
259 1.1 cgd for (i = NRSVIDT; i < NIDT; i++)
260 1.1 cgd setidt(i, &IDTVEC(intrdefault), SDT_SYS386IGT, SEL_KPL);
261 1.1 cgd
262 1.1 cgd /* initialize 8259's */
263 1.1 cgd outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
264 1.1 cgd outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */
265 1.1 cgd outb(IO_ICU1+1, 1<<2); /* slave on line 2 */
266 1.15 cgd #ifdef AUTO_EOI_1
267 1.15 cgd outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
268 1.15 cgd #else
269 1.1 cgd outb(IO_ICU1+1, 1); /* 8086 mode */
270 1.15 cgd #endif
271 1.1 cgd outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
272 1.15 cgd outb(IO_ICU1, 0x0a); /* default to IRR on read */
273 1.21 andrew #ifdef REORDER_IRQ
274 1.15 cgd outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
275 1.21 andrew #endif
276 1.1 cgd
277 1.1 cgd outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
278 1.1 cgd outb(IO_ICU2+1, NRSVIDT+8); /* staring at this vector index */
279 1.1 cgd outb(IO_ICU2+1,2); /* my slave id is 2 */
280 1.15 cgd #ifdef AUTO_EOI_2
281 1.15 cgd outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
282 1.15 cgd #else
283 1.1 cgd outb(IO_ICU2+1,1); /* 8086 mode */
284 1.15 cgd #endif
285 1.1 cgd outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
286 1.15 cgd outb(IO_ICU2, 0x0a); /* default to IRR on read */
287 1.1 cgd }
288 1.1 cgd
289 1.1 cgd /* region of physical memory known to be contiguous */
290 1.1 cgd vm_offset_t isaphysmem;
291 1.1 cgd static caddr_t dma_bounce[8]; /* XXX */
292 1.1 cgd static char bounced[8]; /* XXX */
293 1.1 cgd #define MAXDMASZ 512 /* XXX */
294 1.1 cgd
295 1.1 cgd /* high byte of address is stored in this port for i-th dma channel */
296 1.1 cgd static short dmapageport[8] =
297 1.1 cgd { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
298 1.1 cgd
299 1.1 cgd /*
300 1.1 cgd * isa_dmacascade(): program 8237 DMA controller channel to accept
301 1.1 cgd * external dma control by a board.
302 1.1 cgd */
303 1.21 andrew void
304 1.21 andrew isa_dmacascade(unsigned chan)
305 1.2 cgd {
306 1.1 cgd if (chan > 7)
307 1.1 cgd panic("isa_dmacascade: impossible request");
308 1.1 cgd
309 1.1 cgd /* set dma channel mode, and set dma channel mode */
310 1.2 cgd if ((chan & 4) == 0) {
311 1.2 cgd outb(DMA1_MODE, DMA37MD_CASCADE | chan);
312 1.2 cgd outb(DMA1_SMSK, chan);
313 1.2 cgd } else {
314 1.2 cgd outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
315 1.2 cgd outb(DMA2_SMSK, chan & 3);
316 1.2 cgd }
317 1.1 cgd }
318 1.1 cgd
319 1.1 cgd /*
320 1.1 cgd * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
321 1.1 cgd * problems by using a bounce buffer.
322 1.1 cgd */
323 1.21 andrew void
324 1.21 andrew isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
325 1.1 cgd { vm_offset_t phys;
326 1.2 cgd int waport;
327 1.1 cgd caddr_t newaddr;
328 1.1 cgd
329 1.2 cgd if ( chan > 7
330 1.2 cgd || (chan < 4 && nbytes > (1<<16))
331 1.2 cgd || (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
332 1.1 cgd panic("isa_dmastart: impossible request");
333 1.1 cgd
334 1.2 cgd if (isa_dmarangecheck(addr, nbytes, chan)) {
335 1.1 cgd if (dma_bounce[chan] == 0)
336 1.1 cgd dma_bounce[chan] =
337 1.1 cgd /*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
338 1.1 cgd (caddr_t) isaphysmem + NBPG*chan;
339 1.1 cgd bounced[chan] = 1;
340 1.1 cgd newaddr = dma_bounce[chan];
341 1.1 cgd *(int *) newaddr = 0; /* XXX */
342 1.1 cgd
343 1.1 cgd /* copy bounce buffer on write */
344 1.1 cgd if (!(flags & B_READ))
345 1.1 cgd bcopy(addr, newaddr, nbytes);
346 1.1 cgd addr = newaddr;
347 1.1 cgd }
348 1.1 cgd
349 1.1 cgd /* translate to physical */
350 1.1 cgd phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
351 1.1 cgd
352 1.2 cgd if ((chan & 4) == 0) {
353 1.2 cgd /*
354 1.2 cgd * Program one of DMA channels 0..3. These are
355 1.2 cgd * byte mode channels.
356 1.2 cgd */
357 1.2 cgd /* set dma channel mode, and reset address ff */
358 1.2 cgd if (flags & B_READ)
359 1.2 cgd outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
360 1.2 cgd else
361 1.2 cgd outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
362 1.2 cgd outb(DMA1_FFC, 0);
363 1.1 cgd
364 1.2 cgd /* send start address */
365 1.2 cgd waport = DMA1_CHN(chan);
366 1.1 cgd outb(waport, phys);
367 1.1 cgd outb(waport, phys>>8);
368 1.2 cgd outb(dmapageport[chan], phys>>16);
369 1.2 cgd
370 1.2 cgd /* send count */
371 1.2 cgd outb(waport + 1, --nbytes);
372 1.2 cgd outb(waport + 1, nbytes>>8);
373 1.2 cgd
374 1.2 cgd /* unmask channel */
375 1.2 cgd outb(DMA1_SMSK, chan);
376 1.1 cgd } else {
377 1.2 cgd /*
378 1.2 cgd * Program one of DMA channels 4..7. These are
379 1.2 cgd * word mode channels.
380 1.2 cgd */
381 1.2 cgd /* set dma channel mode, and reset address ff */
382 1.2 cgd if (flags & B_READ)
383 1.2 cgd outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
384 1.2 cgd else
385 1.2 cgd outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
386 1.2 cgd outb(DMA2_FFC, 0);
387 1.2 cgd
388 1.2 cgd /* send start address */
389 1.2 cgd waport = DMA2_CHN(chan - 4);
390 1.1 cgd outb(waport, phys>>1);
391 1.1 cgd outb(waport, phys>>9);
392 1.2 cgd outb(dmapageport[chan], phys>>16);
393 1.1 cgd
394 1.2 cgd /* send count */
395 1.2 cgd nbytes >>= 1;
396 1.1 cgd outb(waport + 2, --nbytes);
397 1.1 cgd outb(waport + 2, nbytes>>8);
398 1.2 cgd
399 1.2 cgd /* unmask channel */
400 1.2 cgd outb(DMA2_SMSK, chan & 3);
401 1.1 cgd }
402 1.1 cgd }
403 1.1 cgd
404 1.21 andrew void
405 1.21 andrew isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
406 1.1 cgd {
407 1.1 cgd
408 1.1 cgd /* copy bounce buffer on read */
409 1.1 cgd /*if ((flags & (B_PHYS|B_READ)) == (B_PHYS|B_READ))*/
410 1.1 cgd if (bounced[chan]) {
411 1.1 cgd bcopy(dma_bounce[chan], addr, nbytes);
412 1.1 cgd bounced[chan] = 0;
413 1.1 cgd }
414 1.1 cgd }
415 1.1 cgd
416 1.1 cgd /*
417 1.1 cgd * Check for problems with the address range of a DMA transfer
418 1.2 cgd * (non-contiguous physical pages, outside of bus address space,
419 1.2 cgd * crossing DMA page boundaries).
420 1.1 cgd * Return true if special handling needed.
421 1.1 cgd */
422 1.1 cgd
423 1.21 andrew int
424 1.2 cgd isa_dmarangecheck(caddr_t va, unsigned length, unsigned chan) {
425 1.2 cgd vm_offset_t phys, priorpage = 0, endva;
426 1.2 cgd u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
427 1.1 cgd
428 1.1 cgd endva = (vm_offset_t)round_page(va + length);
429 1.1 cgd for (; va < (caddr_t) endva ; va += NBPG) {
430 1.1 cgd phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va));
431 1.1 cgd #define ISARAM_END RAM_END
432 1.1 cgd if (phys == 0)
433 1.1 cgd panic("isa_dmacheck: no physical page present");
434 1.1 cgd if (phys > ISARAM_END)
435 1.1 cgd return (1);
436 1.2 cgd if (priorpage) {
437 1.2 cgd if (priorpage + NBPG != phys)
438 1.2 cgd return (1);
439 1.2 cgd /* check if crossing a DMA page boundary */
440 1.2 cgd if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
441 1.2 cgd return (1);
442 1.2 cgd }
443 1.1 cgd priorpage = phys;
444 1.1 cgd }
445 1.1 cgd return (0);
446 1.1 cgd }
447 1.1 cgd
448 1.1 cgd /* head of queue waiting for physmem to become available */
449 1.1 cgd struct buf isa_physmemq;
450 1.1 cgd
451 1.1 cgd /* blocked waiting for resource to become free for exclusive use */
452 1.1 cgd static isaphysmemflag;
453 1.1 cgd /* if waited for and call requested when free (B_CALL) */
454 1.1 cgd static void (*isaphysmemunblock)(); /* needs to be a list */
455 1.1 cgd
456 1.1 cgd /*
457 1.1 cgd * Allocate contiguous physical memory for transfer, returning
458 1.1 cgd * a *virtual* address to region. May block waiting for resource.
459 1.1 cgd * (assumed to be called at splbio())
460 1.1 cgd */
461 1.1 cgd caddr_t
462 1.1 cgd isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) {
463 1.1 cgd
464 1.1 cgd isaphysmemunblock = func;
465 1.1 cgd while (isaphysmemflag & B_BUSY) {
466 1.1 cgd isaphysmemflag |= B_WANTED;
467 1.24 deraadt sleep((caddr_t)&isaphysmemflag, PRIBIO);
468 1.1 cgd }
469 1.1 cgd isaphysmemflag |= B_BUSY;
470 1.1 cgd
471 1.1 cgd return((caddr_t)isaphysmem);
472 1.1 cgd }
473 1.1 cgd
474 1.1 cgd /*
475 1.1 cgd * Free contiguous physical memory used for transfer.
476 1.1 cgd * (assumed to be called at splbio())
477 1.1 cgd */
478 1.1 cgd void
479 1.1 cgd isa_freephysmem(caddr_t va, unsigned length) {
480 1.1 cgd
481 1.1 cgd isaphysmemflag &= ~B_BUSY;
482 1.1 cgd if (isaphysmemflag & B_WANTED) {
483 1.1 cgd isaphysmemflag &= B_WANTED;
484 1.24 deraadt wakeup((caddr_t)&isaphysmemflag);
485 1.1 cgd if (isaphysmemunblock)
486 1.1 cgd (*isaphysmemunblock)();
487 1.1 cgd }
488 1.1 cgd }
489 1.1 cgd
490 1.1 cgd /*
491 1.1 cgd * Handle a NMI, possibly a machine check.
492 1.1 cgd * return true to panic system, false to ignore.
493 1.1 cgd */
494 1.21 andrew int
495 1.1 cgd isa_nmi(cd) {
496 1.1 cgd
497 1.1 cgd log(LOG_CRIT, "\nNMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70));
498 1.1 cgd return(0);
499 1.1 cgd }
500 1.1 cgd
501 1.1 cgd /*
502 1.1 cgd * Caught a stray interrupt, notify
503 1.1 cgd */
504 1.21 andrew void
505 1.1 cgd isa_strayintr(d) {
506 1.1 cgd
507 1.1 cgd /* DON'T BOTHER FOR NOW! */
508 1.1 cgd /* for some reason, we get bursts of intr #7, even if not enabled! */
509 1.4 cgd /*
510 1.4 cgd * Well the reason you got bursts of intr #7 is because someone
511 1.4 cgd * raised an interrupt line and dropped it before the 8259 could
512 1.4 cgd * prioritize it. This is documented in the intel data book. This
513 1.4 cgd * means you have BAD hardware! I have changed this so that only
514 1.15 cgd * the first 5 get logged, then it quits logging them, and puts
515 1.4 cgd * out a special message. rgrimes 3/25/1993
516 1.4 cgd */
517 1.15 cgd extern u_long intrcnt_stray;
518 1.4 cgd
519 1.15 cgd intrcnt_stray++;
520 1.15 cgd if (intrcnt_stray <= 5)
521 1.4 cgd log(LOG_ERR,"ISA strayintr %x\n", d);
522 1.15 cgd if (intrcnt_stray == 5)
523 1.4 cgd log(LOG_CRIT,"Too many ISA strayintr not logging any more\n");
524 1.1 cgd }
525 1.1 cgd
526 1.1 cgd /*
527 1.15 cgd * Wait "n" microseconds.
528 1.15 cgd * Relies on timer 1 counting down from (TIMER_FREQ / hz) at
529 1.17 mycroft * (1 * TIMER_FREQ) Hz.
530 1.15 cgd * Note: timer had better have been programmed before this is first used!
531 1.17 mycroft * (Note that we use `rate generator' mode, which counts at 1:1; `square
532 1.17 mycroft * wave' mode counts at 2:1).
533 1.15 cgd */
534 1.17 mycroft #define CF (1 * TIMER_FREQ)
535 1.15 cgd
536 1.15 cgd extern int hz; /* XXX - should be elsewhere */
537 1.15 cgd
538 1.21 andrew void
539 1.21 andrew DELAY(n)
540 1.15 cgd int n;
541 1.15 cgd {
542 1.15 cgd int counter_limit;
543 1.15 cgd int prev_tick;
544 1.15 cgd int tick;
545 1.15 cgd int ticks_left;
546 1.15 cgd int sec;
547 1.15 cgd int usec;
548 1.15 cgd
549 1.15 cgd #ifdef DELAYDEBUG
550 1.16 mycroft int gettick_calls = 1;
551 1.15 cgd int n1;
552 1.15 cgd static int state = 0;
553 1.15 cgd
554 1.15 cgd if (state == 0) {
555 1.15 cgd state = 1;
556 1.15 cgd for (n1 = 1; n1 <= 10000000; n1 *= 10)
557 1.15 cgd DELAY(n1);
558 1.15 cgd state = 2;
559 1.15 cgd }
560 1.15 cgd if (state == 1)
561 1.15 cgd printf("DELAY(%d)...", n);
562 1.15 cgd #endif
563 1.15 cgd
564 1.15 cgd /*
565 1.15 cgd * Read the counter first, so that the rest of the setup overhead is
566 1.15 cgd * counted. Guess the initial overhead is 20 usec (on most systems it
567 1.16 mycroft * takes about 1.5 usec for each of the i/o's in gettick(). The loop
568 1.15 cgd * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
569 1.15 cgd * multiplications and divisions to scale the count take a while).
570 1.15 cgd */
571 1.16 mycroft prev_tick = gettick();
572 1.15 cgd n -= 20;
573 1.15 cgd
574 1.15 cgd /*
575 1.15 cgd * Calculate (n * (CF / 1e6)) without using floating point and without
576 1.15 cgd * any avoidable overflows.
577 1.15 cgd */
578 1.15 cgd sec = n / 1000000;
579 1.15 cgd usec = n - sec * 1000000;
580 1.15 cgd ticks_left = sec * CF
581 1.15 cgd + usec * (CF / 1000000)
582 1.15 cgd + usec * ((CF % 1000000) / 1000) / 1000
583 1.15 cgd + usec * (CF % 1000) / 1000000;
584 1.15 cgd
585 1.15 cgd counter_limit = TIMER_FREQ / hz;
586 1.15 cgd while (ticks_left > 0) {
587 1.16 mycroft tick = gettick();
588 1.15 cgd #ifdef DELAYDEBUG
589 1.16 mycroft ++gettick_calls;
590 1.15 cgd #endif
591 1.15 cgd if (tick > prev_tick)
592 1.15 cgd ticks_left -= prev_tick - (tick - counter_limit);
593 1.15 cgd else
594 1.15 cgd ticks_left -= prev_tick - tick;
595 1.15 cgd prev_tick = tick;
596 1.1 cgd }
597 1.15 cgd #ifdef DELAYDEBUG
598 1.15 cgd if (state == 1)
599 1.16 mycroft printf(" %d calls to gettick() at %d usec each\n",
600 1.16 mycroft gettick_calls, (n + 5) / gettick_calls);
601 1.15 cgd #endif
602 1.1 cgd }
603 1.1 cgd
604 1.21 andrew int
605 1.16 mycroft gettick() {
606 1.15 cgd int high;
607 1.15 cgd int low;
608 1.15 cgd
609 1.15 cgd /*
610 1.15 cgd * Protect ourself against interrupts.
611 1.15 cgd */
612 1.15 cgd disable_intr();
613 1.15 cgd /*
614 1.15 cgd * Latch the count for 'timer' (cc00xxxx, c = counter, x = any).
615 1.15 cgd */
616 1.16 mycroft outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
617 1.16 mycroft low = inb(TIMER_CNTR0);
618 1.16 mycroft high = inb(TIMER_CNTR0);
619 1.15 cgd enable_intr();
620 1.15 cgd return ((high << 8) | low);
621 1.1 cgd }
622 1.1 cgd
623 1.1 cgd static beeping;
624 1.21 andrew static void
625 1.21 andrew sysbeepstop(int f)
626 1.1 cgd {
627 1.16 mycroft int s = splhigh();
628 1.16 mycroft
629 1.1 cgd /* disable counter 2 */
630 1.16 mycroft disable_intr();
631 1.28 brezak outb(PITAUX_PORT, inb(PITAUX_PORT) & ~PIT_SPKR);
632 1.16 mycroft enable_intr();
633 1.1 cgd if (f)
634 1.24 deraadt timeout((timeout_t)sysbeepstop, (caddr_t)0, f);
635 1.1 cgd else
636 1.1 cgd beeping = 0;
637 1.16 mycroft
638 1.16 mycroft splx(s);
639 1.1 cgd }
640 1.1 cgd
641 1.21 andrew void
642 1.21 andrew sysbeep(int pitch, int period)
643 1.1 cgd {
644 1.16 mycroft int s = splhigh();
645 1.16 mycroft static int last_pitch, last_period;
646 1.1 cgd
647 1.16 mycroft if (beeping) {
648 1.24 deraadt untimeout((timeout_t)sysbeepstop, (caddr_t)(last_period/2));
649 1.24 deraadt untimeout((timeout_t)sysbeepstop, (caddr_t)0);
650 1.1 cgd }
651 1.16 mycroft if (!beeping || last_pitch != pitch) {
652 1.16 mycroft /*
653 1.16 mycroft * XXX - move timer stuff to clock.c.
654 1.16 mycroft */
655 1.16 mycroft disable_intr();
656 1.16 mycroft outb(TIMER_MODE, TIMER_SEL2|TIMER_16BIT|TIMER_SQWAVE);
657 1.19 mycroft outb(TIMER_CNTR2, TIMER_DIV(pitch)%256);
658 1.19 mycroft outb(TIMER_CNTR2, TIMER_DIV(pitch)/256);
659 1.28 brezak outb(PITAUX_PORT, inb(PITAUX_PORT) | PIT_SPKR); /* enable counter 2 */
660 1.16 mycroft enable_intr();
661 1.16 mycroft }
662 1.16 mycroft last_pitch = pitch;
663 1.16 mycroft beeping = last_period = period;
664 1.24 deraadt timeout((timeout_t)sysbeepstop, (caddr_t)(period/2), period);
665 1.16 mycroft
666 1.16 mycroft splx(s);
667 1.1 cgd }
668 1.1 cgd
669 1.1 cgd /*
670 1.1 cgd * Pass command to keyboard controller (8042)
671 1.1 cgd */
672 1.21 andrew unsigned
673 1.21 andrew kbc_8042cmd(int val)
674 1.21 andrew {
675 1.1 cgd while (inb(KBSTATP)&KBS_IBF);
676 1.1 cgd if (val) outb(KBCMDP, val);
677 1.1 cgd while (inb(KBSTATP)&KBS_IBF);
678 1.1 cgd return (inb(KBDATAP));
679 1.28 brezak }
680 1.28 brezak
681 1.28 brezak /*
682 1.28 brezak * find an ISA device in a given isa_devtab_* table, given
683 1.28 brezak * the table to search, the expected id_driver entry, and the unit number.
684 1.28 brezak *
685 1.28 brezak * this function is defined in isa_device.h, and this location is debatable;
686 1.28 brezak * i put it there because it's useless w/o, and directly operates on
687 1.28 brezak * the other stuff in that file.
688 1.28 brezak *
689 1.28 brezak */
690 1.28 brezak
691 1.28 brezak struct isa_device *find_isadev(table, driverp, unit)
692 1.28 brezak struct isa_device *table;
693 1.28 brezak struct isa_driver *driverp;
694 1.28 brezak int unit;
695 1.28 brezak {
696 1.28 brezak if (driverp == NULL) /* sanity check */
697 1.28 brezak return NULL;
698 1.28 brezak
699 1.28 brezak while ((table->id_driver != driverp) || (table->id_unit != unit)) {
700 1.28 brezak if (table->id_driver == 0)
701 1.28 brezak return NULL;
702 1.28 brezak
703 1.28 brezak table++;
704 1.28 brezak }
705 1.28 brezak
706 1.28 brezak return table;
707 1.15 cgd }
708 1.15 cgd
709 1.15 cgd /*
710 1.15 cgd * Return nonzero if a (masked) irq is pending for a given device.
711 1.15 cgd */
712 1.15 cgd int
713 1.15 cgd isa_irq_pending(dvp)
714 1.15 cgd struct isa_device *dvp;
715 1.15 cgd {
716 1.15 cgd unsigned id_irq;
717 1.15 cgd
718 1.15 cgd id_irq = (unsigned short) dvp->id_irq; /* XXX silly type in struct */
719 1.15 cgd if (id_irq & 0xff)
720 1.15 cgd return (inb(IO_ICU1) & id_irq);
721 1.15 cgd return (inb(IO_ICU2) & (id_irq >> 8));
722 1.1 cgd }
723