isa.c revision 1.38
1 /*- 2 * Copyright (c) 1994 Charles Hannum. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 38 * $Id: isa.c,v 1.38 1994/03/01 18:22:52 mycroft Exp $ 39 */ 40 41 /* 42 * code to manage AT bus 43 * 44 * 92/08/18 Frank P. MacLachlan (fpm (at) crash.cts.com): 45 * Fixed uninitialized variable problem and added code to deal 46 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 47 * mode DMA count compution and reorganized DMA setup code in 48 * isa_dmastart() 49 */ 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/conf.h> 54 #include <sys/file.h> 55 #include <sys/buf.h> 56 #include <sys/uio.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 60 #include <vm/vm.h> 61 62 #include <machine/segments.h> 63 #include <machine/pio.h> 64 #include <machine/cpufunc.h> 65 66 #include <i386/isa/isa_device.h> 67 #include <i386/isa/isa.h> 68 #include <i386/isa/icu.h> 69 #include <i386/isa/ic/i8237.h> 70 #include <i386/isa/ic/i8042.h> 71 #include <i386/isa/timerreg.h> 72 #include <i386/isa/spkr_reg.h> 73 74 /* sorry, has to be here, no place else really suitable */ 75 #include <machine/pc/display.h> 76 u_short *Crtat = (u_short *)MONO_BUF; 77 78 /* 79 * Register definitions for DMA controller 1 (channels 0..3): 80 */ 81 #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 82 #define DMA1_SR (IO_DMA1 + 1*8) /* status register */ 83 #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 84 #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 85 #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 86 87 /* 88 * Register definitions for DMA controller 2 (channels 4..7): 89 */ 90 #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 91 #define DMA2_SR (IO_DMA2 + 2*8) /* status register */ 92 #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 93 #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 94 #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 95 96 int config_isadev(struct isa_device *, u_int *); 97 void config_attach(struct isa_driver *, struct isa_device *); 98 static void sysbeepstop(int); 99 100 /* 101 * Configure all ISA devices 102 */ 103 void 104 isa_configure() 105 { 106 struct isa_device *dvp; 107 struct isa_driver *dp; 108 109 splhigh(); 110 INTREN(IRQ_SLAVE); 111 enable_intr(); 112 113 for (dvp = isa_devtab_tty; config_isadev(dvp, &ttymask); dvp++) 114 ; 115 for (dvp = isa_devtab_bio; config_isadev(dvp, &biomask); dvp++) 116 ; 117 for (dvp = isa_devtab_net; config_isadev(dvp, &netmask); dvp++) 118 ; 119 for (dvp = isa_devtab_null; config_isadev(dvp, (u_int *) NULL); dvp++) 120 ; 121 122 printf("biomask %x ttymask %x netmask %x\n", 123 biomask, ttymask, netmask); 124 125 clockmask |= astmask; 126 biomask |= astmask; 127 ttymask |= astmask; 128 netmask |= astmask; 129 impmask = netmask | ttymask; 130 131 spl0(); 132 } 133 134 /* 135 * Configure an ISA device. 136 */ 137 int 138 config_isadev(isdp, mp) 139 struct isa_device *isdp; 140 u_int *mp; 141 { 142 struct isa_driver *dp; 143 144 if (dp = isdp->id_driver) { 145 if (isdp->id_maddr) { 146 extern u_int atdevbase; 147 148 isdp->id_maddr -= 0xa0000; /* XXX should be a define */ 149 isdp->id_maddr += atdevbase; 150 } 151 isdp->id_alive = (*dp->probe)(isdp); 152 if (isdp->id_irq == (u_short)-1) 153 isdp->id_alive = 0; 154 /* 155 * Only print the I/O address range if id_alive != -1 156 * Right now this is a temporary fix just for the new 157 * NPX code so that if it finds a 486 that can use trap 158 * 16 it will not report I/O addresses. 159 * Rod Grimes 04/26/94 160 * 161 * XXX -- cgd 162 */ 163 if (isdp->id_alive) { 164 printf("%s%d", dp->name, isdp->id_unit); 165 if (isdp->id_iobase) { 166 printf(" at 0x%x", isdp->id_iobase); 167 if ((isdp->id_iobase + isdp->id_alive - 1) != 168 isdp->id_iobase) 169 printf("-0x%x", isdp->id_iobase + 170 isdp->id_alive - 1); 171 } 172 if (isdp->id_irq != 0) 173 printf(" irq %d", ffs(isdp->id_irq)-1); 174 if (isdp->id_drq != -1) 175 printf(" drq %d", isdp->id_drq); 176 if (isdp->id_maddr != 0) 177 printf(" maddr 0x%x", kvtop(isdp->id_maddr)); 178 if (isdp->id_msize != 0) 179 printf("-0x%x", kvtop(isdp->id_maddr) + 180 isdp->id_msize - 1); 181 if (isdp->id_flags != 0) 182 printf(" flags 0x%x", isdp->id_flags); 183 printf(" on isa\n"); 184 185 config_attach(dp, isdp); 186 187 if (isdp->id_irq) { 188 int intrno; 189 190 intrno = ffs(isdp->id_irq)-1; 191 setidt(ICU_OFFSET+intrno, isdp->id_intr, 192 SDT_SYS386IGT, SEL_KPL); 193 if(mp) 194 INTRMASK(*mp,isdp->id_irq); 195 INTREN(isdp->id_irq); 196 } 197 } 198 return (1); 199 } else return(0); 200 } 201 202 void 203 config_attach(struct isa_driver *dp, struct isa_device *isdp) 204 { 205 extern struct isa_device isa_subdev[]; 206 struct isa_device *dvp; 207 208 if(isdp->id_masunit==-1) { 209 (void)(*dp->attach)(isdp); 210 return; 211 } 212 213 if(isdp->id_masunit==0) { 214 for(dvp = isa_subdev; dvp->id_driver; dvp++) { 215 if (dvp->id_driver != dp) 216 continue; 217 if (dvp->id_masunit != isdp->id_unit) 218 continue; 219 if (dvp->id_physid == -1) 220 continue; 221 dvp->id_alive = (*dp->attach)(dvp); 222 } 223 for(dvp = isa_subdev; dvp->id_driver; dvp++) { 224 if (dvp->id_driver != dp) 225 continue; 226 if (dvp->id_masunit != isdp->id_unit) 227 continue; 228 if (dvp->id_physid != -1) 229 continue; 230 dvp->id_alive = (*dp->attach)(dvp); 231 } 232 return; 233 } 234 printf("id_masunit has weird value\n"); 235 } 236 237 238 #define IDTVEC(name) __CONCAT(X,name) 239 /* default interrupt vector table entries */ 240 extern IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3), 241 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7), 242 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11), 243 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15); 244 245 static *defvec[16] = { 246 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), 247 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), 248 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), 249 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15) }; 250 251 /* out of range default interrupt vector gate entry */ 252 extern IDTVEC(intrdefault); 253 254 /* 255 * Fill in default interrupt table (in case of spuruious interrupt 256 * during configuration of kernel, setup interrupt control unit 257 */ 258 void 259 isa_defaultirq() { 260 int i; 261 262 /* icu vectors */ 263 for (i = NRSVIDT ; i < NRSVIDT+ICU_LEN ; i++) 264 setidt(i, defvec[i], SDT_SYS386IGT, SEL_KPL); 265 266 /* out of range vectors */ 267 for (i = NRSVIDT; i < NIDT; i++) 268 setidt(i, &IDTVEC(intrdefault), SDT_SYS386IGT, SEL_KPL); 269 270 /* initialize 8259's */ 271 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 272 outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */ 273 outb(IO_ICU1+1, 1<<2); /* slave on line 2 */ 274 #ifdef AUTO_EOI_1 275 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ 276 #else 277 outb(IO_ICU1+1, 1); /* 8086 mode */ 278 #endif 279 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 280 outb(IO_ICU1, 0x0a); /* default to IRR on read */ 281 #ifdef REORDER_IRQ 282 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 283 #endif 284 285 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 286 outb(IO_ICU2+1, NRSVIDT+8); /* staring at this vector index */ 287 outb(IO_ICU2+1,2); /* my slave id is 2 */ 288 #ifdef AUTO_EOI_2 289 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ 290 #else 291 outb(IO_ICU2+1,1); /* 8086 mode */ 292 #endif 293 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 294 outb(IO_ICU2, 0x0a); /* default to IRR on read */ 295 } 296 297 /* region of physical memory known to be contiguous */ 298 vm_offset_t isaphysmem; 299 static caddr_t dma_bounce[8]; /* XXX */ 300 static char bounced[8]; /* XXX */ 301 #define MAXDMASZ 512 /* XXX */ 302 303 /* high byte of address is stored in this port for i-th dma channel */ 304 static short dmapageport[8] = 305 { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 306 307 /* 308 * isa_dmacascade(): program 8237 DMA controller channel to accept 309 * external dma control by a board. 310 */ 311 void 312 isa_dmacascade(chan) 313 int chan; 314 { 315 316 #ifdef DIAGNOSTIC 317 if (chan < 0 || chan > 7) 318 panic("isa_dmacascade: impossible request"); 319 #endif 320 321 /* set dma channel mode, and set dma channel mode */ 322 if ((chan & 4) == 0) { 323 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 324 outb(DMA1_SMSK, chan); 325 } else { 326 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 327 outb(DMA2_SMSK, chan & 3); 328 } 329 } 330 331 /* 332 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 333 * problems by using a bounce buffer. 334 */ 335 void 336 isa_dmastart(flags, addr, nbytes, chan) 337 int flags; 338 caddr_t addr; 339 vm_size_t nbytes; 340 int chan; 341 { 342 vm_offset_t phys; 343 int waport; 344 caddr_t newaddr; 345 346 #ifdef DIAGNOSTIC 347 if (chan < 0 || chan > 7 || 348 ((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) : 349 (nbytes >= (1<<16)))) 350 panic("isa_dmastart: impossible request"); 351 #endif 352 353 if (isa_dmarangecheck(addr, nbytes, chan)) { 354 if (dma_bounce[chan] == 0) 355 dma_bounce[chan] = 356 /*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/ 357 (caddr_t) isaphysmem + NBPG*chan; 358 bounced[chan] = 1; 359 newaddr = dma_bounce[chan]; 360 *(int *) newaddr = 0; /* XXX */ 361 /* copy bounce buffer on write */ 362 if ((flags & B_READ) == 0) 363 bcopy(addr, newaddr, nbytes); 364 addr = newaddr; 365 } 366 367 /* translate to physical */ 368 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 369 370 if ((chan & 4) == 0) { 371 /* 372 * Program one of DMA channels 0..3. These are 373 * byte mode channels. 374 */ 375 /* set dma channel mode, and reset address ff */ 376 if (flags & B_READ) 377 outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE); 378 else 379 outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ); 380 outb(DMA1_FFC, 0); 381 382 /* send start address */ 383 waport = DMA1_CHN(chan); 384 outb(waport, phys); 385 outb(waport, phys>>8); 386 outb(dmapageport[chan], phys>>16); 387 388 /* send count */ 389 outb(waport + 1, --nbytes); 390 outb(waport + 1, nbytes>>8); 391 392 /* unmask channel */ 393 outb(DMA1_SMSK, chan | DMA37SM_CLEAR); 394 } else { 395 /* 396 * Program one of DMA channels 4..7. These are 397 * word mode channels. 398 */ 399 /* set dma channel mode, and reset address ff */ 400 if (flags & B_READ) 401 outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE); 402 else 403 outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ); 404 outb(DMA2_FFC, 0); 405 406 /* send start address */ 407 waport = DMA2_CHN(chan & 3); 408 outb(waport, phys>>1); 409 outb(waport, phys>>9); 410 outb(dmapageport[chan], phys>>16); 411 412 /* send count */ 413 nbytes >>= 1; 414 outb(waport + 2, --nbytes); 415 outb(waport + 2, nbytes>>8); 416 417 /* unmask channel */ 418 outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR); 419 } 420 } 421 422 void 423 isa_dmadone(flags, addr, nbytes, chan) 424 int flags; 425 caddr_t addr; 426 vm_size_t nbytes; 427 int chan; 428 { 429 u_char tc; 430 431 #ifdef DIAGNOSTIC 432 if (chan < 0 || chan > 7) 433 panic("isa_dmadone: impossible request"); 434 #endif 435 436 /* check that the terminal count was reached */ 437 if ((chan & 4) == 0) 438 tc = inb(DMA1_SR) & (1 << chan); 439 else 440 tc = inb(DMA2_SR) & (1 << (chan & 3)); 441 if (tc == 0) 442 /* XXX probably should panic or something */ 443 log(LOG_ERR, "dma channel %d not finished\n", chan); 444 445 /* copy bounce buffer on read */ 446 if (bounced[chan]) { 447 bcopy(dma_bounce[chan], addr, nbytes); 448 bounced[chan] = 0; 449 } 450 451 /* mask channel */ 452 if ((chan & 4) == 0) 453 outb(DMA1_SMSK, DMA37SM_SET | chan); 454 else 455 outb(DMA2_SMSK, DMA37SM_SET | (chan & 3)); 456 } 457 458 /* 459 * Check for problems with the address range of a DMA transfer 460 * (non-contiguous physical pages, outside of bus address space, 461 * crossing DMA page boundaries). 462 * Return true if special handling needed. 463 */ 464 int 465 isa_dmarangecheck(va, length, chan) 466 vm_offset_t va; 467 u_long length; 468 int chan; 469 { 470 vm_offset_t phys, priorpage = 0, endva; 471 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 472 473 endva = round_page(va + length); 474 for (; va < endva ; va += NBPG) { 475 phys = trunc_page(pmap_extract(pmap_kernel(), va)); 476 if (phys == 0) 477 panic("isa_dmacheck: no physical page present"); 478 if (phys >= (1<<24)) 479 return 1; 480 if (priorpage) { 481 if (priorpage + NBPG != phys) 482 return 1; 483 /* check if crossing a DMA page boundary */ 484 if ((priorpage ^ phys) & dma_pgmsk) 485 return 1; 486 } 487 priorpage = phys; 488 } 489 return 0; 490 } 491 492 /* head of queue waiting for physmem to become available */ 493 struct buf isa_physmemq; 494 495 /* blocked waiting for resource to become free for exclusive use */ 496 static isaphysmemflag; 497 /* if waited for and call requested when free (B_CALL) */ 498 static void (*isaphysmemunblock)(); /* needs to be a list */ 499 500 /* 501 * Allocate contiguous physical memory for transfer, returning 502 * a *virtual* address to region. May block waiting for resource. 503 * (assumed to be called at splbio()) 504 */ 505 caddr_t 506 isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) { 507 508 isaphysmemunblock = func; 509 while (isaphysmemflag & B_BUSY) { 510 isaphysmemflag |= B_WANTED; 511 sleep((caddr_t)&isaphysmemflag, PRIBIO); 512 } 513 isaphysmemflag |= B_BUSY; 514 515 return((caddr_t)isaphysmem); 516 } 517 518 /* 519 * Free contiguous physical memory used for transfer. 520 * (assumed to be called at splbio()) 521 */ 522 void 523 isa_freephysmem(caddr_t va, unsigned length) { 524 525 isaphysmemflag &= ~B_BUSY; 526 if (isaphysmemflag & B_WANTED) { 527 isaphysmemflag &= B_WANTED; 528 wakeup((caddr_t)&isaphysmemflag); 529 if (isaphysmemunblock) 530 (*isaphysmemunblock)(); 531 } 532 } 533 534 /* 535 * Handle a NMI, possibly a machine check. 536 * return true to panic system, false to ignore. 537 */ 538 int 539 isa_nmi(cd) { 540 541 log(LOG_CRIT, "\nNMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70)); 542 return(0); 543 } 544 545 /* 546 * Caught a stray interrupt, notify 547 */ 548 void 549 isa_strayintr(d) { 550 551 /* DON'T BOTHER FOR NOW! */ 552 /* for some reason, we get bursts of intr #7, even if not enabled! */ 553 /* 554 * Well the reason you got bursts of intr #7 is because someone 555 * raised an interrupt line and dropped it before the 8259 could 556 * prioritize it. This is documented in the intel data book. This 557 * means you have BAD hardware! I have changed this so that only 558 * the first 5 get logged, then it quits logging them, and puts 559 * out a special message. rgrimes 3/25/1993 560 */ 561 extern u_long intrcnt_stray; 562 563 intrcnt_stray++; 564 if (intrcnt_stray <= 5) 565 log(LOG_ERR,"ISA strayintr %x\n", d); 566 if (intrcnt_stray == 5) 567 log(LOG_CRIT,"Too many ISA strayintr not logging any more\n"); 568 } 569 570 /* 571 * Wait "n" microseconds. 572 * Relies on timer 1 counting down from (TIMER_FREQ / hz) at 573 * (1 * TIMER_FREQ) Hz. 574 * Note: timer had better have been programmed before this is first used! 575 * (Note that we use `rate generator' mode, which counts at 1:1; `square 576 * wave' mode counts at 2:1). 577 */ 578 #define CF (1 * TIMER_FREQ) 579 580 extern int hz; /* XXX - should be elsewhere */ 581 582 void 583 DELAY(n) 584 int n; 585 { 586 int counter_limit; 587 int prev_tick; 588 int tick; 589 int ticks_left; 590 int sec; 591 int usec; 592 593 #ifdef DELAYDEBUG 594 int gettick_calls = 1; 595 int n1; 596 static int state = 0; 597 598 if (state == 0) { 599 state = 1; 600 for (n1 = 1; n1 <= 10000000; n1 *= 10) 601 DELAY(n1); 602 state = 2; 603 } 604 if (state == 1) 605 printf("DELAY(%d)...", n); 606 #endif 607 608 /* 609 * Read the counter first, so that the rest of the setup overhead is 610 * counted. Guess the initial overhead is 20 usec (on most systems it 611 * takes about 1.5 usec for each of the i/o's in gettick(). The loop 612 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 613 * multiplications and divisions to scale the count take a while). 614 */ 615 prev_tick = gettick(); 616 n -= 20; 617 618 /* 619 * Calculate (n * (CF / 1e6)) without using floating point and without 620 * any avoidable overflows. 621 */ 622 sec = n / 1000000; 623 usec = n - sec * 1000000; 624 ticks_left = sec * CF 625 + usec * (CF / 1000000) 626 + usec * ((CF % 1000000) / 1000) / 1000 627 + usec * (CF % 1000) / 1000000; 628 629 counter_limit = TIMER_FREQ / hz; 630 while (ticks_left > 0) { 631 tick = gettick(); 632 #ifdef DELAYDEBUG 633 ++gettick_calls; 634 #endif 635 if (tick > prev_tick) 636 ticks_left -= prev_tick - (tick - counter_limit); 637 else 638 ticks_left -= prev_tick - tick; 639 prev_tick = tick; 640 } 641 #ifdef DELAYDEBUG 642 if (state == 1) 643 printf(" %d calls to gettick() at %d usec each\n", 644 gettick_calls, (n + 5) / gettick_calls); 645 #endif 646 } 647 648 int 649 gettick() { 650 int high; 651 int low; 652 653 /* 654 * Protect ourself against interrupts. 655 */ 656 disable_intr(); 657 /* 658 * Latch the count for 'timer' (cc00xxxx, c = counter, x = any). 659 */ 660 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 661 low = inb(TIMER_CNTR0); 662 high = inb(TIMER_CNTR0); 663 enable_intr(); 664 return ((high << 8) | low); 665 } 666 667 static beeping; 668 static void 669 sysbeepstop(int f) 670 { 671 int s = splhigh(); 672 673 /* disable counter 2 */ 674 disable_intr(); 675 outb(PITAUX_PORT, inb(PITAUX_PORT) & ~PIT_SPKR); 676 enable_intr(); 677 if (f) 678 timeout((timeout_t)sysbeepstop, (caddr_t)0, f); 679 else 680 beeping = 0; 681 682 splx(s); 683 } 684 685 void 686 sysbeep(int pitch, int period) 687 { 688 int s = splhigh(); 689 static int last_pitch, last_period; 690 691 if (beeping) { 692 untimeout((timeout_t)sysbeepstop, (caddr_t)(last_period/2)); 693 untimeout((timeout_t)sysbeepstop, (caddr_t)0); 694 } 695 if (!beeping || last_pitch != pitch) { 696 /* 697 * XXX - move timer stuff to clock.c. 698 */ 699 disable_intr(); 700 outb(TIMER_MODE, TIMER_SEL2|TIMER_16BIT|TIMER_SQWAVE); 701 outb(TIMER_CNTR2, TIMER_DIV(pitch)%256); 702 outb(TIMER_CNTR2, TIMER_DIV(pitch)/256); 703 outb(PITAUX_PORT, inb(PITAUX_PORT) | PIT_SPKR); /* enable counter 2 */ 704 enable_intr(); 705 } 706 last_pitch = pitch; 707 beeping = last_period = period; 708 timeout((timeout_t)sysbeepstop, (caddr_t)(period/2), period); 709 710 splx(s); 711 } 712 713 /* 714 * find an ISA device in a given isa_devtab_* table, given 715 * the table to search, the expected id_driver entry, and the unit number. 716 * 717 * this function is defined in isa_device.h, and this location is debatable; 718 * i put it there because it's useless w/o, and directly operates on 719 * the other stuff in that file. 720 * 721 */ 722 723 struct isa_device *find_isadev(table, driverp, unit) 724 struct isa_device *table; 725 struct isa_driver *driverp; 726 int unit; 727 { 728 if (driverp == NULL) /* sanity check */ 729 return NULL; 730 731 while ((table->id_driver != driverp) || (table->id_unit != unit)) { 732 if (table->id_driver == 0) 733 return NULL; 734 735 table++; 736 } 737 738 return table; 739 } 740 741 /* 742 * Return nonzero if a (masked) irq is pending for a given device. 743 */ 744 int 745 isa_irq_pending(dvp) 746 struct isa_device *dvp; 747 { 748 unsigned id_irq; 749 750 id_irq = (unsigned short) dvp->id_irq; /* XXX silly type in struct */ 751 if (id_irq & 0xff) 752 return (inb(IO_ICU1) & id_irq); 753 return (inb(IO_ICU2) & (id_irq >> 8)); 754 } 755
Indexes created Tue Sep 30 17:09:57 GMT 2025