isa.c revision 1.44
1 /*- 2 * Copyright (c) 1993, 1994 Charles Hannum. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 38 * $Id: isa.c,v 1.44 1994/03/10 21:38:46 mycroft Exp $ 39 */ 40 41 /* 42 * code to manage AT bus 43 * 44 * 92/08/18 Frank P. MacLachlan (fpm (at) crash.cts.com): 45 * Fixed uninitialized variable problem and added code to deal 46 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 47 * mode DMA count compution and reorganized DMA setup code in 48 * isa_dmastart() 49 */ 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/conf.h> 55 #include <sys/file.h> 56 #include <sys/buf.h> 57 #include <sys/uio.h> 58 #include <sys/syslog.h> 59 #include <sys/malloc.h> 60 61 #include <vm/vm.h> 62 63 #include <machine/segments.h> 64 #include <machine/pio.h> 65 #include <machine/cpufunc.h> 66 67 #include <i386/isa/isa_device.h> 68 #include <i386/isa/isa.h> 69 #include <i386/isa/icu.h> 70 #include <i386/isa/ic/i8237.h> 71 #include <i386/isa/ic/i8042.h> 72 #include <i386/isa/timerreg.h> 73 #include <i386/isa/spkr_reg.h> 74 75 /* sorry, has to be here, no place else really suitable */ 76 #include <machine/pc/display.h> 77 u_short *Crtat = (u_short *)MONO_BUF; 78 79 /* 80 * Register definitions for DMA controller 1 (channels 0..3): 81 */ 82 #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 83 #define DMA1_SR (IO_DMA1 + 1*8) /* status register */ 84 #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 85 #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 86 #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 87 88 /* 89 * Register definitions for DMA controller 2 (channels 4..7): 90 */ 91 #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 92 #define DMA2_SR (IO_DMA2 + 2*8) /* status register */ 93 #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 94 #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 95 #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 96 97 int config_isadev(struct isa_device *, u_int *); 98 void config_attach(struct isa_driver *, struct isa_device *); 99 static void sysbeepstop(int); 100 101 /* 102 * Configure all ISA devices 103 */ 104 void 105 isa_configure() 106 { 107 struct isa_device *dvp; 108 struct isa_driver *dp; 109 110 splhigh(); 111 INTREN(IRQ_SLAVE); 112 enable_intr(); 113 114 for (dvp = isa_devtab_tty; dvp->id_driver; dvp++) 115 config_isadev(dvp, &ttymask); 116 for (dvp = isa_devtab_bio; dvp->id_driver; dvp++) 117 config_isadev(dvp, &biomask); 118 for (dvp = isa_devtab_net; dvp->id_driver; dvp++) 119 config_isadev(dvp, &netmask); 120 for (dvp = isa_devtab_null; dvp->id_driver; dvp++) 121 config_isadev(dvp, (u_int *) NULL); 122 123 printf("biomask %x ttymask %x netmask %x\n", 124 biomask, ttymask, netmask); 125 126 clockmask |= astmask; 127 biomask |= astmask; 128 ttymask |= astmask; 129 netmask |= astmask; 130 impmask = netmask | ttymask; 131 132 spl0(); 133 } 134 135 /* 136 * Configure an ISA device. 137 */ 138 config_isadev(isdp, mp) 139 struct isa_device *isdp; 140 u_int *mp; 141 { 142 struct isa_driver *dp = isdp->id_driver; 143 144 if (isdp->id_masunit != -1) { 145 /* Not really an ISA device; just call the probe and attach. */ 146 isdp->id_alive = (*dp->probe)(isdp); 147 if (isdp->id_alive) 148 config_attach(dp, isdp); 149 return; 150 } 151 152 if (isdp->id_maddr) { 153 extern u_int atdevbase; 154 155 isdp->id_maddr -= 0xa0000; /* XXX should be a define */ 156 isdp->id_maddr += atdevbase; 157 } 158 isdp->id_alive = (*dp->probe)(isdp); 159 if (isdp->id_irq == (u_short)-1) 160 isdp->id_alive = 0; 161 /* 162 * Only print the I/O address range if id_alive != -1 163 * Right now this is a temporary fix just for the new 164 * NPX code so that if it finds a 486 that can use trap 165 * 16 it will not report I/O addresses. 166 * Rod Grimes 04/26/94 167 * 168 * XXX -- cgd 169 */ 170 if (isdp->id_alive) { 171 printf("%s%d", dp->name, isdp->id_unit); 172 if (isdp->id_iobase) { 173 printf(" at 0x%x", isdp->id_iobase); 174 if ((isdp->id_iobase + isdp->id_alive - 1) != 175 isdp->id_iobase) 176 printf("-0x%x", isdp->id_iobase + 177 isdp->id_alive - 1); 178 } 179 if (isdp->id_irq != 0) 180 printf(" irq %d", ffs(isdp->id_irq)-1); 181 if (isdp->id_drq != -1) 182 printf(" drq %d", isdp->id_drq); 183 if (isdp->id_maddr != 0) 184 printf(" maddr 0x%x", kvtop(isdp->id_maddr)); 185 if (isdp->id_msize != 0) 186 printf("-0x%x", kvtop(isdp->id_maddr) + 187 isdp->id_msize - 1); 188 if (isdp->id_flags != 0) 189 printf(" flags 0x%x", isdp->id_flags); 190 printf(" on isa\n"); 191 192 config_attach(dp, isdp); 193 194 if (isdp->id_irq) { 195 int intrno; 196 197 intrno = ffs(isdp->id_irq)-1; 198 setidt(ICU_OFFSET+intrno, isdp->id_intr, 199 SDT_SYS386IGT, SEL_KPL); 200 if(mp) 201 INTRMASK(*mp,isdp->id_irq); 202 INTREN(isdp->id_irq); 203 } 204 } 205 } 206 207 void 208 config_attach(struct isa_driver *dp, struct isa_device *isdp) 209 { 210 extern struct isa_device isa_subdev[]; 211 struct isa_device *dvp; 212 213 (void)(*dp->attach)(isdp); 214 215 /* XXXX This is for SCSI controllers, and it sucks. */ 216 for (dvp = isa_subdev; dvp->id_driver; dvp++) { 217 if (dvp->id_driver != dp) 218 continue; 219 if (dvp->id_masunit != isdp->id_unit) 220 continue; 221 if (dvp->id_physid == -1) 222 continue; 223 dvp->id_alive = (*dp->attach)(dvp); 224 } 225 for (dvp = isa_subdev; dvp->id_driver; dvp++) { 226 if (dvp->id_driver != dp) 227 continue; 228 if (dvp->id_masunit != isdp->id_unit) 229 continue; 230 if (dvp->id_physid != -1) 231 continue; 232 dvp->id_alive = (*dp->attach)(dvp); 233 } 234 } 235 236 237 #define IDTVEC(name) __CONCAT(X,name) 238 /* default interrupt vector table entries */ 239 extern IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3), 240 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7), 241 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11), 242 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15); 243 244 static *defvec[16] = { 245 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), 246 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), 247 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), 248 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15) }; 249 250 /* out of range default interrupt vector gate entry */ 251 extern IDTVEC(intrdefault); 252 253 /* 254 * Fill in default interrupt table (in case of spuruious interrupt 255 * during configuration of kernel, setup interrupt control unit 256 */ 257 void 258 isa_defaultirq() { 259 int i; 260 261 /* icu vectors */ 262 for (i = NRSVIDT ; i < NRSVIDT+ICU_LEN ; i++) 263 setidt(i, defvec[i], SDT_SYS386IGT, SEL_KPL); 264 265 /* out of range vectors */ 266 for (i = NRSVIDT; i < NIDT; i++) 267 setidt(i, &IDTVEC(intrdefault), SDT_SYS386IGT, SEL_KPL); 268 269 /* initialize 8259's */ 270 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 271 outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */ 272 outb(IO_ICU1+1, 1<<2); /* slave on line 2 */ 273 #ifdef AUTO_EOI_1 274 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ 275 #else 276 outb(IO_ICU1+1, 1); /* 8086 mode */ 277 #endif 278 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 279 outb(IO_ICU1, 0x0a); /* default to IRR on read */ 280 #ifdef REORDER_IRQ 281 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 282 #endif 283 284 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 285 outb(IO_ICU2+1, NRSVIDT+8); /* staring at this vector index */ 286 outb(IO_ICU2+1,2); /* my slave id is 2 */ 287 #ifdef AUTO_EOI_2 288 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ 289 #else 290 outb(IO_ICU2+1,1); /* 8086 mode */ 291 #endif 292 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 293 outb(IO_ICU2, 0x0a); /* default to IRR on read */ 294 } 295 296 /* region of physical memory known to be contiguous */ 297 vm_offset_t isaphysmem; 298 static caddr_t dma_bounce[8]; /* XXX */ 299 static char bounced[8]; /* XXX */ 300 #define MAXDMASZ 512 /* XXX */ 301 302 /* high byte of address is stored in this port for i-th dma channel */ 303 static short dmapageport[8] = 304 { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 305 306 /* 307 * isa_dmacascade(): program 8237 DMA controller channel to accept 308 * external dma control by a board. 309 */ 310 void 311 isa_dmacascade(chan) 312 int chan; 313 { 314 315 #ifdef DIAGNOSTIC 316 if (chan < 0 || chan > 7) 317 panic("isa_dmacascade: impossible request"); 318 #endif 319 320 /* set dma channel mode, and set dma channel mode */ 321 if ((chan & 4) == 0) { 322 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 323 outb(DMA1_SMSK, chan); 324 } else { 325 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 326 outb(DMA2_SMSK, chan & 3); 327 } 328 } 329 330 /* 331 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 332 * problems by using a bounce buffer. 333 */ 334 void 335 isa_dmastart(flags, addr, nbytes, chan) 336 int flags; 337 caddr_t addr; 338 vm_size_t nbytes; 339 int chan; 340 { 341 vm_offset_t phys; 342 int waport; 343 caddr_t newaddr; 344 345 #ifdef DIAGNOSTIC 346 if (chan < 0 || chan > 7 || 347 ((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) : 348 (nbytes >= (1<<16)))) 349 panic("isa_dmastart: impossible request"); 350 #endif 351 352 if (isa_dmarangecheck(addr, nbytes, chan)) { 353 if (dma_bounce[chan] == 0) 354 dma_bounce[chan] = 355 /*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/ 356 (caddr_t) isaphysmem + NBPG*chan; 357 bounced[chan] = 1; 358 newaddr = dma_bounce[chan]; 359 *(int *) newaddr = 0; /* XXX */ 360 /* copy bounce buffer on write */ 361 if ((flags & B_READ) == 0) 362 bcopy(addr, newaddr, nbytes); 363 addr = newaddr; 364 } 365 366 /* translate to physical */ 367 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 368 369 if ((chan & 4) == 0) { 370 /* 371 * Program one of DMA channels 0..3. These are 372 * byte mode channels. 373 */ 374 /* set dma channel mode, and reset address ff */ 375 if (flags & B_READ) 376 outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE); 377 else 378 outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ); 379 outb(DMA1_FFC, 0); 380 381 /* send start address */ 382 waport = DMA1_CHN(chan); 383 outb(waport, phys); 384 outb(waport, phys>>8); 385 outb(dmapageport[chan], phys>>16); 386 387 /* send count */ 388 outb(waport + 1, --nbytes); 389 outb(waport + 1, nbytes>>8); 390 391 /* unmask channel */ 392 outb(DMA1_SMSK, chan | DMA37SM_CLEAR); 393 } else { 394 /* 395 * Program one of DMA channels 4..7. These are 396 * word mode channels. 397 */ 398 /* set dma channel mode, and reset address ff */ 399 if (flags & B_READ) 400 outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE); 401 else 402 outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ); 403 outb(DMA2_FFC, 0); 404 405 /* send start address */ 406 waport = DMA2_CHN(chan & 3); 407 outb(waport, phys>>1); 408 outb(waport, phys>>9); 409 outb(dmapageport[chan], phys>>16); 410 411 /* send count */ 412 nbytes >>= 1; 413 outb(waport + 2, --nbytes); 414 outb(waport + 2, nbytes>>8); 415 416 /* unmask channel */ 417 outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR); 418 } 419 } 420 421 void 422 isa_dmaabort(chan) 423 int chan; 424 { 425 426 #ifdef DIAGNOSTIC 427 if (chan < 0 || chan > 7) 428 panic("isa_dmadone: impossible request"); 429 #endif 430 431 bounced[chan] = 0; 432 433 /* mask channel */ 434 if ((chan & 4) == 0) 435 outb(DMA1_SMSK, DMA37SM_SET | chan); 436 else 437 outb(DMA2_SMSK, DMA37SM_SET | (chan & 3)); 438 } 439 440 void 441 isa_dmadone(flags, addr, nbytes, chan) 442 int flags; 443 caddr_t addr; 444 vm_size_t nbytes; 445 int chan; 446 { 447 u_char tc; 448 449 #ifdef DIAGNOSTIC 450 if (chan < 0 || chan > 7) 451 panic("isa_dmadone: impossible request"); 452 #endif 453 454 /* check that the terminal count was reached */ 455 if ((chan & 4) == 0) 456 tc = inb(DMA1_SR) & (1 << chan); 457 else 458 tc = inb(DMA2_SR) & (1 << (chan & 3)); 459 if (tc == 0) 460 /* XXX probably should panic or something */ 461 log(LOG_ERR, "dma channel %d not finished\n", chan); 462 463 /* copy bounce buffer on read */ 464 if (bounced[chan]) { 465 bcopy(dma_bounce[chan], addr, nbytes); 466 bounced[chan] = 0; 467 } 468 469 /* mask channel */ 470 if ((chan & 4) == 0) 471 outb(DMA1_SMSK, DMA37SM_SET | chan); 472 else 473 outb(DMA2_SMSK, DMA37SM_SET | (chan & 3)); 474 } 475 476 /* 477 * Check for problems with the address range of a DMA transfer 478 * (non-contiguous physical pages, outside of bus address space, 479 * crossing DMA page boundaries). 480 * Return true if special handling needed. 481 */ 482 int 483 isa_dmarangecheck(va, length, chan) 484 vm_offset_t va; 485 u_long length; 486 int chan; 487 { 488 vm_offset_t phys, priorpage = 0, endva; 489 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 490 491 endva = round_page(va + length); 492 for (; va < endva ; va += NBPG) { 493 phys = trunc_page(pmap_extract(pmap_kernel(), va)); 494 if (phys == 0) 495 panic("isa_dmacheck: no physical page present"); 496 if (phys >= (1<<24)) 497 return 1; 498 if (priorpage) { 499 if (priorpage + NBPG != phys) 500 return 1; 501 /* check if crossing a DMA page boundary */ 502 if ((priorpage ^ phys) & dma_pgmsk) 503 return 1; 504 } 505 priorpage = phys; 506 } 507 return 0; 508 } 509 510 /* head of queue waiting for physmem to become available */ 511 struct buf isa_physmemq; 512 513 /* blocked waiting for resource to become free for exclusive use */ 514 static isaphysmemflag; 515 /* if waited for and call requested when free (B_CALL) */ 516 static void (*isaphysmemunblock)(); /* needs to be a list */ 517 518 /* 519 * Allocate contiguous physical memory for transfer, returning 520 * a *virtual* address to region. May block waiting for resource. 521 * (assumed to be called at splbio()) 522 */ 523 caddr_t 524 isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) { 525 526 isaphysmemunblock = func; 527 while (isaphysmemflag & B_BUSY) { 528 isaphysmemflag |= B_WANTED; 529 sleep((caddr_t)&isaphysmemflag, PRIBIO); 530 } 531 isaphysmemflag |= B_BUSY; 532 533 return((caddr_t)isaphysmem); 534 } 535 536 /* 537 * Free contiguous physical memory used for transfer. 538 * (assumed to be called at splbio()) 539 */ 540 void 541 isa_freephysmem(caddr_t va, unsigned length) { 542 543 isaphysmemflag &= ~B_BUSY; 544 if (isaphysmemflag & B_WANTED) { 545 isaphysmemflag &= B_WANTED; 546 wakeup((caddr_t)&isaphysmemflag); 547 if (isaphysmemunblock) 548 (*isaphysmemunblock)(); 549 } 550 } 551 552 /* 553 * Handle a NMI, possibly a machine check. 554 * return true to panic system, false to ignore. 555 */ 556 int 557 isa_nmi(cd) { 558 559 log(LOG_CRIT, "\nNMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70)); 560 return(0); 561 } 562 563 /* 564 * Caught a stray interrupt, notify 565 */ 566 void 567 isa_strayintr(d) { 568 569 /* DON'T BOTHER FOR NOW! */ 570 /* for some reason, we get bursts of intr #7, even if not enabled! */ 571 /* 572 * Well the reason you got bursts of intr #7 is because someone 573 * raised an interrupt line and dropped it before the 8259 could 574 * prioritize it. This is documented in the intel data book. This 575 * means you have BAD hardware! I have changed this so that only 576 * the first 5 get logged, then it quits logging them, and puts 577 * out a special message. rgrimes 3/25/1993 578 */ 579 extern u_long intrcnt_stray; 580 581 intrcnt_stray++; 582 if (intrcnt_stray <= 5) 583 log(LOG_ERR,"ISA strayintr %x\n", d); 584 if (intrcnt_stray == 5) 585 log(LOG_CRIT,"Too many ISA strayintr not logging any more\n"); 586 } 587 588 /* 589 * Wait "n" microseconds. 590 * Relies on timer 1 counting down from (TIMER_FREQ / hz) at TIMER_FREQ Hz. 591 * Note: timer had better have been programmed before this is first used! 592 * (Note that we use `rate generator' mode, which counts at 1:1; `square 593 * wave' mode counts at 2:1). 594 */ 595 void 596 delay(n) 597 int n; 598 { 599 int limit, tick, otick; 600 601 /* 602 * Read the counter first, so that the rest of the setup overhead is 603 * counted. 604 */ 605 otick = gettick(); 606 607 #ifdef __GNUC__ 608 /* 609 * Calculate ((n * TIMER_FREQ) / 1e6) using explicit assembler code so 610 * we can take advantage of the intermediate 64-bit quantity to prevent 611 * loss of significance. 612 */ 613 n -= 5; 614 if (n < 0) 615 return; 616 {register int m; 617 __asm __volatile("mul %3" 618 : "=a" (n), "=d" (m) 619 : "0" (n), "r" (TIMER_FREQ)); 620 __asm __volatile("div %3" 621 : "=a" (n) 622 : "0" (n), "d" (m), "r" (1000000) 623 : "%edx");} 624 #else 625 /* 626 * Calculate ((n * TIMER_FREQ) / 1e6) without using floating point and 627 * without any avoidable overflows. 628 */ 629 n -= 20; 630 { 631 int sec = n / 1000000, 632 usec = n % 1000000; 633 n = sec * TIMER_FREQ + 634 usec * (TIMER_FREQ / 1000000) + 635 usec * ((TIMER_FREQ % 1000000) / 1000) / 1000 + 636 usec * (TIMER_FREQ % 1000) / 1000000; 637 } 638 #endif 639 640 limit = TIMER_FREQ / hz; 641 642 while (n > 0) { 643 tick = gettick(); 644 if (tick > otick) 645 n -= limit - (tick - otick); 646 else 647 n -= otick - tick; 648 otick = tick; 649 } 650 } 651 652 int 653 gettick() 654 { 655 u_char lo, hi; 656 657 /* Don't want someone screwing with the counter while we're here. */ 658 disable_intr(); 659 /* Select counter 0 and latch it. */ 660 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 661 lo = inb(TIMER_CNTR0); 662 hi = inb(TIMER_CNTR0); 663 enable_intr(); 664 return ((hi << 8) | lo); 665 } 666 667 static beeping; 668 static void 669 sysbeepstop(int f) 670 { 671 int s = splhigh(); 672 673 /* disable counter 2 */ 674 disable_intr(); 675 outb(PITAUX_PORT, inb(PITAUX_PORT) & ~PIT_SPKR); 676 enable_intr(); 677 if (f) 678 timeout((timeout_t)sysbeepstop, (caddr_t)0, f); 679 else 680 beeping = 0; 681 682 splx(s); 683 } 684 685 void 686 sysbeep(int pitch, int period) 687 { 688 int s = splhigh(); 689 static int last_pitch, last_period; 690 691 if (beeping) { 692 untimeout((timeout_t)sysbeepstop, (caddr_t)(last_period/2)); 693 untimeout((timeout_t)sysbeepstop, (caddr_t)0); 694 } 695 if (!beeping || last_pitch != pitch) { 696 /* 697 * XXX - move timer stuff to clock.c. 698 */ 699 disable_intr(); 700 outb(TIMER_MODE, TIMER_SEL2|TIMER_16BIT|TIMER_SQWAVE); 701 outb(TIMER_CNTR2, TIMER_DIV(pitch)%256); 702 outb(TIMER_CNTR2, TIMER_DIV(pitch)/256); 703 outb(PITAUX_PORT, inb(PITAUX_PORT) | PIT_SPKR); /* enable counter 2 */ 704 enable_intr(); 705 } 706 last_pitch = pitch; 707 beeping = last_period = period; 708 timeout((timeout_t)sysbeepstop, (caddr_t)(period/2), period); 709 710 splx(s); 711 } 712 713 /* 714 * find an ISA device in a given isa_devtab_* table, given 715 * the table to search, the expected id_driver entry, and the unit number. 716 * 717 * this function is defined in isa_device.h, and this location is debatable; 718 * i put it there because it's useless w/o, and directly operates on 719 * the other stuff in that file. 720 * 721 */ 722 723 struct isa_device *find_isadev(table, driverp, unit) 724 struct isa_device *table; 725 struct isa_driver *driverp; 726 int unit; 727 { 728 if (driverp == NULL) /* sanity check */ 729 return NULL; 730 731 while ((table->id_driver != driverp) || (table->id_unit != unit)) { 732 if (table->id_driver == 0) 733 return NULL; 734 735 table++; 736 } 737 738 return table; 739 } 740 741 /* 742 * Return nonzero if a (masked) irq is pending for a given device. 743 */ 744 int 745 isa_irq_pending(dvp) 746 struct isa_device *dvp; 747 { 748 unsigned id_irq; 749 750 id_irq = (unsigned short) dvp->id_irq; /* XXX silly type in struct */ 751 if (id_irq & 0xff) 752 return (inb(IO_ICU1) & id_irq); 753 return (inb(IO_ICU2) & (id_irq >> 8)); 754 } 755
Indexes created Thu Oct 02 01:09:59 GMT 2025