isa.c revision 1.47
1 /*- 2 * Copyright (c) 1993, 1994 Charles Hannum. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 38 * $Id: isa.c,v 1.47 1994/03/31 16:59:04 mycroft Exp $ 39 */ 40 41 /* 42 * code to manage AT bus 43 * 44 * 92/08/18 Frank P. MacLachlan (fpm (at) crash.cts.com): 45 * Fixed uninitialized variable problem and added code to deal 46 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 47 * mode DMA count compution and reorganized DMA setup code in 48 * isa_dmastart() 49 */ 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/conf.h> 55 #include <sys/file.h> 56 #include <sys/buf.h> 57 #include <sys/uio.h> 58 #include <sys/syslog.h> 59 #include <sys/malloc.h> 60 #include <sys/device.h> 61 62 #include <vm/vm.h> 63 64 #include <machine/segments.h> 65 #include <machine/pio.h> 66 #include <machine/cpufunc.h> 67 68 #include <i386/isa/isa.h> 69 #include <i386/isa/isa_device.h> 70 #include <i386/isa/isavar.h> 71 #include <i386/isa/icu.h> 72 #include <i386/isa/ic/i8237.h> 73 #include <i386/isa/ic/i8042.h> 74 #include <i386/isa/timerreg.h> 75 #include <i386/isa/spkr_reg.h> 76 77 /* sorry, has to be here, no place else really suitable */ 78 #include <machine/pc/display.h> 79 u_short *Crtat = (u_short *)MONO_BUF; 80 81 /* 82 * Register definitions for DMA controller 1 (channels 0..3): 83 */ 84 #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 85 #define DMA1_SR (IO_DMA1 + 1*8) /* status register */ 86 #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 87 #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 88 #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 89 90 /* 91 * Register definitions for DMA controller 2 (channels 4..7): 92 */ 93 #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 94 #define DMA2_SR (IO_DMA2 + 2*8) /* status register */ 95 #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 96 #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 97 #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 98 99 static void sysbeepstop(int); 100 101 /* 102 * Configure all ISA devices 103 * 104 * XXX This code is a hack. It wants to be new config, but can't be until the 105 * interrupt system is redone. For now, we do some gross hacks to make it look 106 * 99% like new config. 107 */ 108 static char *msgs[3] = { "", " not configured\n", " unsupported\n" }; 109 110 struct cfdata * 111 config_search(fn, parent, aux) 112 cfmatch_t fn; 113 struct device *parent; 114 void *aux; 115 { 116 struct cfdata *cf = 0; 117 struct device *dv = 0; 118 size_t devsize; 119 struct cfdriver *cd; 120 struct isa_device *id, 121 *idp = parent ? (void *)parent->dv_cfdata->cf_loc : 0; 122 123 for (id = isa_devtab; id->id_driver; id++) { 124 if (id->id_state == FSTATE_FOUND) 125 continue; 126 if (id->id_parent != idp) 127 continue; 128 cd = id->id_driver; 129 if (id->id_unit < cd->cd_ndevs) { 130 if (cd->cd_devs[id->id_unit] != 0) 131 continue; 132 } else { 133 int old = cd->cd_ndevs, new; 134 void **nsp; 135 136 if (old == 0) { 137 nsp = malloc(MINALLOCSIZE, M_DEVBUF, M_NOWAIT); 138 if (!nsp) 139 panic("config_search: creating dev array"); 140 bzero(nsp, MINALLOCSIZE); 141 cd->cd_ndevs = MINALLOCSIZE / sizeof(void *); 142 } else { 143 new = old; 144 do { 145 new *= 2; 146 } while (new <= id->id_unit); 147 cd->cd_ndevs = new; 148 nsp = malloc(new * sizeof(void *), M_DEVBUF, 149 M_NOWAIT); 150 if (!nsp) 151 panic("config_search: expanding dev array"); 152 bzero(nsp, new * sizeof(void *)); 153 bcopy(cd->cd_devs, nsp, old * sizeof(void *)); 154 free(cd->cd_devs, M_DEVBUF); 155 } 156 cd->cd_devs = nsp; 157 } 158 if (!cf) { 159 cf = malloc(sizeof(struct cfdata), M_DEVBUF, M_NOWAIT); if (!cf) 160 panic("config_search: creating cfdata"); 161 } 162 cf->cf_driver = cd; 163 cf->cf_unit = id->id_unit; 164 cf->cf_fstate = 0; 165 cf->cf_loc = (void *)id; 166 cf->cf_flags = id->id_flags; 167 cf->cf_parents = 0; 168 cf->cf_ivstubs = 0; 169 if (dv && devsize != cd->cd_devsize) { 170 free(dv, M_DEVBUF); 171 dv = 0; 172 } 173 if (!dv) { 174 devsize = cd->cd_devsize; 175 dv = malloc(devsize, M_DEVBUF, M_NOWAIT); 176 if (!dv) 177 panic("config_search: creating softc"); 178 } 179 bzero(dv, cd->cd_devsize); 180 dv->dv_class = cd->cd_class; 181 dv->dv_cfdata = cf; 182 dv->dv_unit = id->id_unit; 183 sprintf(dv->dv_xname, "%s%d", cd->cd_name, id->id_unit); 184 dv->dv_parent = parent; 185 cd->cd_devs[id->id_unit] = dv; 186 if (fn) { 187 if ((*fn)(parent, dv, aux)) 188 return cf; 189 } else { 190 if ((*cd->cd_match)(parent, dv, aux)) 191 return cf; 192 } 193 cd->cd_devs[id->id_unit] = 0; 194 } 195 if (cf) 196 free(cf, M_DEVBUF); 197 if (dv) 198 free(dv, M_DEVBUF); 199 return 0; 200 } 201 202 void 203 config_attach(parent, cf, aux, print) 204 struct device *parent; 205 struct cfdata *cf; 206 void *aux; 207 cfprint_t print; 208 { 209 struct isa_device *id = (void *)cf->cf_loc; 210 struct cfdriver *cd = cf->cf_driver; 211 struct device *dv = cd->cd_devs[id->id_unit]; 212 213 cf->cf_fstate = id->id_state = FSTATE_FOUND; 214 printf("%s at %s", dv->dv_xname, parent ? parent->dv_xname : "isa0"); 215 if (print) 216 (void) (*print)(aux, (char *)0); 217 (*cd->cd_attach)(parent, dv, aux); 218 } 219 220 int 221 config_found(parent, aux, print) 222 struct device *parent; 223 void *aux; 224 cfprint_t print; 225 { 226 struct cfdata *cf; 227 228 if ((cf = config_search((cfmatch_t)NULL, parent, aux)) != NULL) { 229 config_attach(parent, cf, aux, print); 230 return 1; 231 } 232 if (print) 233 printf(msgs[(*print)(aux, parent->dv_xname)]); 234 return 0; 235 } 236 237 int 238 isaprint(aux, isa) 239 void *aux; 240 char *isa; 241 { 242 struct isa_attach_args *ia = aux; 243 244 if (ia->ia_iosize) 245 printf(" port 0x%x", ia->ia_iobase); 246 if (ia->ia_iosize > 1) 247 printf("-0x%x", ia->ia_iobase + ia->ia_iosize - 1); 248 if (ia->ia_msize) 249 printf(" iomem 0x%x", ia->ia_maddr - atdevbase + 0xa0000); 250 if (ia->ia_msize > 1) 251 printf("-0x%x", 252 ia->ia_maddr - atdevbase + 0xa0000 + ia->ia_msize - 1); 253 if (ia->ia_irq) 254 printf(" irq %d", ffs(ia->ia_irq) - 1); 255 if (ia->ia_drq != (u_short)-1) 256 printf(" drq %d", ia->ia_drq); 257 /* XXXX print flags */ 258 return QUIET; 259 } 260 261 int 262 isasubmatch(parent, self, aux) 263 struct device *parent, *self; 264 void *aux; 265 { 266 struct isa_device *id = (void *)self->dv_cfdata->cf_loc; 267 struct isa_attach_args ia; 268 269 ia.ia_iobase = id->id_iobase; 270 ia.ia_iosize = 0x666; 271 ia.ia_irq = id->id_irq; 272 ia.ia_drq = id->id_drq; 273 ia.ia_maddr = id->id_maddr - 0xa0000 + atdevbase; 274 ia.ia_msize = id->id_msize; 275 276 if (!(*id->id_driver->cd_match)(parent, self, &ia)) { 277 /* 278 * If we don't do this, isa_configure() will repeatedly try to 279 * probe devices that weren't found. But we need to be careful 280 * to do it only for the ISA bus, or we would cause things like 281 * `com0 at ast? slave ?' to not probe on the second ast. 282 */ 283 if (!parent) 284 id->id_state = FSTATE_FOUND; 285 286 return 0; 287 } 288 289 config_attach(parent, self->dv_cfdata, &ia, isaprint); 290 291 if (id->id_irq) { 292 int intrno; 293 294 intrno = ffs(id->id_irq) - 1; 295 setidt(ICU_OFFSET+intrno, id->id_intr, SDT_SYS386IGT, SEL_KPL); 296 if (id->id_mask) 297 INTRMASK(*id->id_mask, id->id_irq); 298 INTREN(id->id_irq); 299 } 300 301 return 1; 302 } 303 304 void 305 isa_configure() 306 { 307 308 splhigh(); 309 INTREN(IRQ_SLAVE); 310 enable_intr(); 311 312 while (config_search(isasubmatch, NULL, NULL)); 313 314 printf("biomask %x ttymask %x netmask %x\n", 315 biomask, ttymask, netmask); 316 317 clockmask |= astmask; 318 biomask |= astmask; 319 ttymask |= astmask; 320 netmask |= astmask; 321 impmask = netmask | ttymask; 322 323 spl0(); 324 } 325 326 #define IDTVEC(name) __CONCAT(X,name) 327 /* default interrupt vector table entries */ 328 extern IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3), 329 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7), 330 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11), 331 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15); 332 333 static *defvec[16] = { 334 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), 335 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), 336 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), 337 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15) }; 338 339 /* out of range default interrupt vector gate entry */ 340 extern IDTVEC(intrdefault); 341 342 /* 343 * Fill in default interrupt table (in case of spuruious interrupt 344 * during configuration of kernel, setup interrupt control unit 345 */ 346 void 347 isa_defaultirq() { 348 int i; 349 350 /* icu vectors */ 351 for (i = NRSVIDT ; i < NRSVIDT+ICU_LEN ; i++) 352 setidt(i, defvec[i], SDT_SYS386IGT, SEL_KPL); 353 354 /* out of range vectors */ 355 for (i = NRSVIDT; i < NIDT; i++) 356 setidt(i, &IDTVEC(intrdefault), SDT_SYS386IGT, SEL_KPL); 357 358 /* initialize 8259's */ 359 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 360 outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */ 361 outb(IO_ICU1+1, 1<<2); /* slave on line 2 */ 362 #ifdef AUTO_EOI_1 363 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ 364 #else 365 outb(IO_ICU1+1, 1); /* 8086 mode */ 366 #endif 367 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 368 outb(IO_ICU1, 0x0a); /* default to IRR on read */ 369 #ifdef REORDER_IRQ 370 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 371 #endif 372 373 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 374 outb(IO_ICU2+1, NRSVIDT+8); /* staring at this vector index */ 375 outb(IO_ICU2+1,2); /* my slave id is 2 */ 376 #ifdef AUTO_EOI_2 377 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ 378 #else 379 outb(IO_ICU2+1,1); /* 8086 mode */ 380 #endif 381 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 382 outb(IO_ICU2, 0x0a); /* default to IRR on read */ 383 } 384 385 /* region of physical memory known to be contiguous */ 386 vm_offset_t isaphysmem; 387 static caddr_t dma_bounce[8]; /* XXX */ 388 static char bounced[8]; /* XXX */ 389 #define MAXDMASZ 512 /* XXX */ 390 391 /* high byte of address is stored in this port for i-th dma channel */ 392 static short dmapageport[8] = 393 { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; 394 395 /* 396 * isa_dmacascade(): program 8237 DMA controller channel to accept 397 * external dma control by a board. 398 */ 399 void 400 isa_dmacascade(chan) 401 int chan; 402 { 403 404 #ifdef DIAGNOSTIC 405 if (chan < 0 || chan > 7) 406 panic("isa_dmacascade: impossible request"); 407 #endif 408 409 /* set dma channel mode, and set dma channel mode */ 410 if ((chan & 4) == 0) { 411 outb(DMA1_MODE, DMA37MD_CASCADE | chan); 412 outb(DMA1_SMSK, chan); 413 } else { 414 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); 415 outb(DMA2_SMSK, chan & 3); 416 } 417 } 418 419 /* 420 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment 421 * problems by using a bounce buffer. 422 */ 423 void 424 isa_dmastart(flags, addr, nbytes, chan) 425 int flags; 426 caddr_t addr; 427 vm_size_t nbytes; 428 int chan; 429 { 430 vm_offset_t phys; 431 int waport; 432 caddr_t newaddr; 433 434 #ifdef DIAGNOSTIC 435 if (chan < 0 || chan > 7 || 436 ((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) : 437 (nbytes >= (1<<16)))) 438 panic("isa_dmastart: impossible request"); 439 #endif 440 441 if (isa_dmarangecheck(addr, nbytes, chan)) { 442 if (dma_bounce[chan] == 0) 443 dma_bounce[chan] = 444 /*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/ 445 (caddr_t) isaphysmem + NBPG*chan; 446 bounced[chan] = 1; 447 newaddr = dma_bounce[chan]; 448 *(int *) newaddr = 0; /* XXX */ 449 /* copy bounce buffer on write */ 450 if ((flags & B_READ) == 0) 451 bcopy(addr, newaddr, nbytes); 452 addr = newaddr; 453 } 454 455 /* translate to physical */ 456 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 457 458 if ((chan & 4) == 0) { 459 /* 460 * Program one of DMA channels 0..3. These are 461 * byte mode channels. 462 */ 463 /* set dma channel mode, and reset address ff */ 464 if (flags & B_READ) 465 outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_WRITE); 466 else 467 outb(DMA1_MODE, chan | DMA37MD_SINGLE | DMA37MD_READ); 468 outb(DMA1_FFC, 0); 469 470 /* send start address */ 471 waport = DMA1_CHN(chan); 472 outb(waport, phys); 473 outb(waport, phys>>8); 474 outb(dmapageport[chan], phys>>16); 475 476 /* send count */ 477 outb(waport + 1, --nbytes); 478 outb(waport + 1, nbytes>>8); 479 480 /* unmask channel */ 481 outb(DMA1_SMSK, chan | DMA37SM_CLEAR); 482 } else { 483 /* 484 * Program one of DMA channels 4..7. These are 485 * word mode channels. 486 */ 487 /* set dma channel mode, and reset address ff */ 488 if (flags & B_READ) 489 outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_WRITE); 490 else 491 outb(DMA2_MODE, (chan & 3) | DMA37MD_SINGLE | DMA37MD_READ); 492 outb(DMA2_FFC, 0); 493 494 /* send start address */ 495 waport = DMA2_CHN(chan & 3); 496 outb(waport, phys>>1); 497 outb(waport, phys>>9); 498 outb(dmapageport[chan], phys>>16); 499 500 /* send count */ 501 nbytes >>= 1; 502 outb(waport + 2, --nbytes); 503 outb(waport + 2, nbytes>>8); 504 505 /* unmask channel */ 506 outb(DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR); 507 } 508 } 509 510 void 511 isa_dmaabort(chan) 512 int chan; 513 { 514 515 #ifdef DIAGNOSTIC 516 if (chan < 0 || chan > 7) 517 panic("isa_dmadone: impossible request"); 518 #endif 519 520 bounced[chan] = 0; 521 522 /* mask channel */ 523 if ((chan & 4) == 0) 524 outb(DMA1_SMSK, DMA37SM_SET | chan); 525 else 526 outb(DMA2_SMSK, DMA37SM_SET | (chan & 3)); 527 } 528 529 void 530 isa_dmadone(flags, addr, nbytes, chan) 531 int flags; 532 caddr_t addr; 533 vm_size_t nbytes; 534 int chan; 535 { 536 u_char tc; 537 538 #ifdef DIAGNOSTIC 539 if (chan < 0 || chan > 7) 540 panic("isa_dmadone: impossible request"); 541 #endif 542 543 /* check that the terminal count was reached */ 544 if ((chan & 4) == 0) 545 tc = inb(DMA1_SR) & (1 << chan); 546 else 547 tc = inb(DMA2_SR) & (1 << (chan & 3)); 548 if (tc == 0) 549 /* XXX probably should panic or something */ 550 log(LOG_ERR, "dma channel %d not finished\n", chan); 551 552 /* copy bounce buffer on read */ 553 if (bounced[chan]) { 554 bcopy(dma_bounce[chan], addr, nbytes); 555 bounced[chan] = 0; 556 } 557 558 /* mask channel */ 559 if ((chan & 4) == 0) 560 outb(DMA1_SMSK, DMA37SM_SET | chan); 561 else 562 outb(DMA2_SMSK, DMA37SM_SET | (chan & 3)); 563 } 564 565 /* 566 * Check for problems with the address range of a DMA transfer 567 * (non-contiguous physical pages, outside of bus address space, 568 * crossing DMA page boundaries). 569 * Return true if special handling needed. 570 */ 571 int 572 isa_dmarangecheck(va, length, chan) 573 vm_offset_t va; 574 u_long length; 575 int chan; 576 { 577 vm_offset_t phys, priorpage = 0, endva; 578 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); 579 580 endva = round_page(va + length); 581 for (; va < endva ; va += NBPG) { 582 phys = trunc_page(pmap_extract(pmap_kernel(), va)); 583 if (phys == 0) 584 panic("isa_dmacheck: no physical page present"); 585 if (phys >= (1<<24)) 586 return 1; 587 if (priorpage) { 588 if (priorpage + NBPG != phys) 589 return 1; 590 /* check if crossing a DMA page boundary */ 591 if ((priorpage ^ phys) & dma_pgmsk) 592 return 1; 593 } 594 priorpage = phys; 595 } 596 return 0; 597 } 598 599 /* head of queue waiting for physmem to become available */ 600 struct buf isa_physmemq; 601 602 /* blocked waiting for resource to become free for exclusive use */ 603 static isaphysmemflag; 604 /* if waited for and call requested when free (B_CALL) */ 605 static void (*isaphysmemunblock)(); /* needs to be a list */ 606 607 /* 608 * Allocate contiguous physical memory for transfer, returning 609 * a *virtual* address to region. May block waiting for resource. 610 * (assumed to be called at splbio()) 611 */ 612 caddr_t 613 isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) { 614 615 isaphysmemunblock = func; 616 while (isaphysmemflag & B_BUSY) { 617 isaphysmemflag |= B_WANTED; 618 sleep((caddr_t)&isaphysmemflag, PRIBIO); 619 } 620 isaphysmemflag |= B_BUSY; 621 622 return((caddr_t)isaphysmem); 623 } 624 625 /* 626 * Free contiguous physical memory used for transfer. 627 * (assumed to be called at splbio()) 628 */ 629 void 630 isa_freephysmem(caddr_t va, unsigned length) { 631 632 isaphysmemflag &= ~B_BUSY; 633 if (isaphysmemflag & B_WANTED) { 634 isaphysmemflag &= B_WANTED; 635 wakeup((caddr_t)&isaphysmemflag); 636 if (isaphysmemunblock) 637 (*isaphysmemunblock)(); 638 } 639 } 640 641 /* 642 * Handle a NMI, possibly a machine check. 643 * return true to panic system, false to ignore. 644 */ 645 int 646 isa_nmi(cd) { 647 648 log(LOG_CRIT, "\nNMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70)); 649 return(0); 650 } 651 652 /* 653 * Caught a stray interrupt, notify 654 */ 655 void 656 isa_strayintr(d) { 657 658 /* DON'T BOTHER FOR NOW! */ 659 /* for some reason, we get bursts of intr #7, even if not enabled! */ 660 /* 661 * Well the reason you got bursts of intr #7 is because someone 662 * raised an interrupt line and dropped it before the 8259 could 663 * prioritize it. This is documented in the intel data book. This 664 * means you have BAD hardware! I have changed this so that only 665 * the first 5 get logged, then it quits logging them, and puts 666 * out a special message. rgrimes 3/25/1993 667 */ 668 extern u_long intrcnt_stray; 669 670 intrcnt_stray++; 671 if (intrcnt_stray <= 5) 672 log(LOG_ERR,"ISA strayintr %x\n", d); 673 if (intrcnt_stray == 5) 674 log(LOG_CRIT,"Too many ISA strayintr not logging any more\n"); 675 } 676 677 static beeping; 678 static void 679 sysbeepstop(int f) 680 { 681 int s = splhigh(); 682 683 /* disable counter 2 */ 684 disable_intr(); 685 outb(PITAUX_PORT, inb(PITAUX_PORT) & ~PIT_SPKR); 686 enable_intr(); 687 if (f) 688 timeout((timeout_t)sysbeepstop, (caddr_t)0, f); 689 else 690 beeping = 0; 691 692 splx(s); 693 } 694 695 void 696 sysbeep(int pitch, int period) 697 { 698 int s = splhigh(); 699 static int last_pitch, last_period; 700 701 if (beeping) { 702 untimeout((timeout_t)sysbeepstop, (caddr_t)(last_period/2)); 703 untimeout((timeout_t)sysbeepstop, (caddr_t)0); 704 } 705 if (!beeping || last_pitch != pitch) { 706 /* 707 * XXX - move timer stuff to clock.c. 708 */ 709 disable_intr(); 710 outb(TIMER_MODE, TIMER_SEL2|TIMER_16BIT|TIMER_SQWAVE); 711 outb(TIMER_CNTR2, TIMER_DIV(pitch)%256); 712 outb(TIMER_CNTR2, TIMER_DIV(pitch)/256); 713 outb(PITAUX_PORT, inb(PITAUX_PORT) | PIT_SPKR); /* enable counter 2 */ 714 enable_intr(); 715 } 716 last_pitch = pitch; 717 beeping = last_period = period; 718 timeout((timeout_t)sysbeepstop, (caddr_t)(period/2), period); 719 720 splx(s); 721 } 722 723 /* 724 * Return nonzero if a (masked) irq is pending for a given device. 725 */ 726 int 727 isa_irq_pending(dvp) 728 struct isa_device *dvp; 729 { 730 unsigned id_irq; 731 732 id_irq = (unsigned short) dvp->id_irq; /* XXX silly type in struct */ 733 if (id_irq & 0xff) 734 return (inb(IO_ICU1) & id_irq); 735 return (inb(IO_ICU2) & (id_irq >> 8)); 736 } 737
Indexes created Tue Sep 30 17:09:57 GMT 2025