isadma.c revision 1.36
1 /* $NetBSD: isadma.c,v 1.36 1998/06/25 19:18:06 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the ISA on-board DMA controller. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/proc.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 50 #include <vm/vm.h> 51 52 #include <machine/bus.h> 53 54 #include <dev/isa/isareg.h> 55 #include <dev/isa/isavar.h> 56 #include <dev/isa/isadmavar.h> 57 #include <dev/isa/isadmareg.h> 58 59 struct isa_mem *isa_mem_head; 60 61 /* 62 * High byte of DMA address is stored in this DMAPG register for 63 * the Nth DMA channel. 64 */ 65 static int dmapageport[2][4] = { 66 {0x7, 0x3, 0x1, 0x2}, 67 {0xf, 0xb, 0x9, 0xa} 68 }; 69 70 static u_int8_t dmamode[4] = { 71 DMA37MD_READ | DMA37MD_SINGLE, 72 DMA37MD_WRITE | DMA37MD_SINGLE, 73 DMA37MD_READ | DMA37MD_SINGLE | DMA37MD_LOOP, 74 DMA37MD_WRITE | DMA37MD_SINGLE | DMA37MD_LOOP 75 }; 76 77 static inline void _isa_dmaunmask __P((struct isa_dma_state *, int)); 78 static inline void _isa_dmamask __P((struct isa_dma_state *, int)); 79 80 static inline void 81 _isa_dmaunmask(ids, chan) 82 struct isa_dma_state *ids; 83 int chan; 84 { 85 int ochan = chan & 3; 86 87 ISA_DMA_MASK_CLR(ids, chan); 88 89 /* 90 * If DMA is frozen, don't unmask it now. It will be 91 * unmasked when DMA is thawed again. 92 */ 93 if (ids->ids_frozen) 94 return; 95 96 /* set dma channel mode, and set dma channel mode */ 97 if ((chan & 4) == 0) 98 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 99 DMA1_SMSK, ochan | DMA37SM_CLEAR); 100 else 101 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 102 DMA2_SMSK, ochan | DMA37SM_CLEAR); 103 } 104 105 static inline void 106 _isa_dmamask(ids, chan) 107 struct isa_dma_state *ids; 108 int chan; 109 { 110 int ochan = chan & 3; 111 112 ISA_DMA_MASK_SET(ids, chan); 113 114 /* 115 * XXX Should we avoid masking the channel if DMA is 116 * XXX frozen? It seems like what we're doing should 117 * XXX be safe, and we do need to reset FFC... 118 */ 119 120 /* set dma channel mode, and set dma channel mode */ 121 if ((chan & 4) == 0) { 122 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 123 DMA1_SMSK, ochan | DMA37SM_SET); 124 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 125 DMA1_FFC, 0); 126 } else { 127 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 128 DMA2_SMSK, ochan | DMA37SM_SET); 129 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 130 DMA2_FFC, 0); 131 } 132 } 133 134 /* 135 * _isa_dmainit(): Initialize the isa_dma_state for this chipset. 136 */ 137 void 138 _isa_dmainit(ids, bst, dmat, dev) 139 struct isa_dma_state *ids; 140 bus_space_tag_t bst; 141 bus_dma_tag_t dmat; 142 struct device *dev; 143 { 144 145 ids->ids_dev = dev; 146 147 if (ids->ids_initialized) { 148 /* 149 * Some systems may have e.g. `ofisa' (OpenFirmware 150 * configuration of ISA bus) and a regular `isa'. 151 * We allow both to call the initialization function, 152 * and take the device name from the last caller 153 * (assuming it will be the indirect ISA bus). Since 154 * `ofisa' and `isa' are the same bus with different 155 * configuration mechanisms, the space and dma tags 156 * must be the same! 157 */ 158 if (ids->ids_bst != bst || ids->ids_dmat != dmat) 159 panic("_isa_dmainit: inconsistent ISA tags"); 160 } else { 161 ids->ids_bst = bst; 162 ids->ids_dmat = dmat; 163 164 /* 165 * Map the registers used by the ISA DMA controller. 166 */ 167 if (bus_space_map(ids->ids_bst, IO_DMA1, DMA1_IOSIZE, 0, 168 &ids->ids_dma1h)) 169 panic("_isa_dmainit: unable to map DMA controller #1"); 170 if (bus_space_map(ids->ids_bst, IO_DMA2, DMA2_IOSIZE, 0, 171 &ids->ids_dma2h)) 172 panic("_isa_dmainit: unable to map DMA controller #2"); 173 if (bus_space_map(ids->ids_bst, IO_DMAPG, 0xf, 0, 174 &ids->ids_dmapgh)) 175 panic("_isa_dmainit: unable to map DMA page registers"); 176 177 /* 178 * All 8 DMA channels start out "masked". 179 */ 180 ids->ids_masked = 0xff; 181 182 ids->ids_initialized = 1; 183 } 184 } 185 186 /* 187 * _isa_dmacascade(): program 8237 DMA controller channel to accept 188 * external dma control by a board. 189 */ 190 int 191 _isa_dmacascade(ids, chan) 192 struct isa_dma_state *ids; 193 int chan; 194 { 195 int ochan = chan & 3; 196 197 if (chan < 0 || chan > 7) { 198 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 199 return (EINVAL); 200 } 201 202 if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) { 203 printf("%s: DRQ %d is not free\n", ids->ids_dev->dv_xname, 204 chan); 205 return (EAGAIN); 206 } 207 208 ISA_DMA_DRQ_ALLOC(ids, chan); 209 210 /* set dma channel mode, and set dma channel mode */ 211 if ((chan & 4) == 0) 212 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 213 DMA1_MODE, ochan | DMA37MD_CASCADE); 214 else 215 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 216 DMA2_MODE, ochan | DMA37MD_CASCADE); 217 218 _isa_dmaunmask(ids, chan); 219 return (0); 220 } 221 222 int 223 _isa_dmamap_create(ids, chan, size, flags) 224 struct isa_dma_state *ids; 225 int chan; 226 bus_size_t size; 227 int flags; 228 { 229 bus_size_t maxsize; 230 231 if (chan < 0 || chan > 7) { 232 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 233 return (EINVAL); 234 } 235 236 if (chan & 4) 237 maxsize = (1 << 17); 238 else 239 maxsize = (1 << 16); 240 241 if (size > maxsize) 242 return (EINVAL); 243 244 if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) { 245 printf("%s: drq %d is not free\n", ids->ids_dev->dv_xname, 246 chan); 247 return (EAGAIN); 248 } 249 250 ISA_DMA_DRQ_ALLOC(ids, chan); 251 252 return (bus_dmamap_create(ids->ids_dmat, size, 1, size, maxsize, 253 flags, &ids->ids_dmamaps[chan])); 254 } 255 256 void 257 _isa_dmamap_destroy(ids, chan) 258 struct isa_dma_state *ids; 259 int chan; 260 { 261 262 if (chan < 0 || chan > 7) { 263 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 264 goto lose; 265 } 266 267 if (ISA_DMA_DRQ_ISFREE(ids, chan)) { 268 printf("%s: drq %d is already free\n", 269 ids->ids_dev->dv_xname, chan); 270 goto lose; 271 } 272 273 ISA_DMA_DRQ_FREE(ids, chan); 274 275 bus_dmamap_destroy(ids->ids_dmat, ids->ids_dmamaps[chan]); 276 return; 277 278 lose: 279 panic("_isa_dmamap_destroy"); 280 } 281 282 /* 283 * _isa_dmastart(): program 8237 DMA controller channel and set it 284 * in motion. 285 */ 286 int 287 _isa_dmastart(ids, chan, addr, nbytes, p, flags, busdmaflags) 288 struct isa_dma_state *ids; 289 int chan; 290 void *addr; 291 bus_size_t nbytes; 292 struct proc *p; 293 int flags; 294 int busdmaflags; 295 { 296 bus_dmamap_t dmam; 297 bus_addr_t dmaaddr; 298 int waport; 299 int ochan = chan & 3; 300 int error; 301 302 if (chan < 0 || chan > 7) { 303 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 304 goto lose; 305 } 306 307 #ifdef ISADMA_DEBUG 308 printf("_isa_dmastart: drq %d, addr %p, nbytes 0x%lx, p %p, " 309 "flags 0x%x, dmaflags 0x%x\n", 310 chan, addr, nbytes, p, flags, busdmaflags); 311 #endif 312 313 if (chan & 4) { 314 if (nbytes > (1 << 17) || nbytes & 1 || (u_long)addr & 1) { 315 printf("%s: drq %d, nbytes 0x%lx, addr %p\n", 316 ids->ids_dev->dv_xname, chan, nbytes, addr); 317 goto lose; 318 } 319 } else { 320 if (nbytes > (1 << 16)) { 321 printf("%s: drq %d, nbytes 0x%lx\n", 322 ids->ids_dev->dv_xname, chan, nbytes); 323 goto lose; 324 } 325 } 326 327 dmam = ids->ids_dmamaps[chan]; 328 if (dmam == NULL) 329 panic("_isa_dmastart: no DMA map for chan %d\n", chan); 330 331 error = bus_dmamap_load(ids->ids_dmat, dmam, addr, nbytes, 332 p, busdmaflags); 333 if (error) 334 return (error); 335 336 #ifdef ISADMA_DEBUG 337 __asm(".globl isa_dmastart_afterload ; isa_dmastart_afterload:"); 338 #endif 339 340 if (flags & DMAMODE_READ) { 341 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 342 BUS_DMASYNC_PREREAD); 343 ids->ids_dmareads |= (1 << chan); 344 } else { 345 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 346 BUS_DMASYNC_PREWRITE); 347 ids->ids_dmareads &= ~(1 << chan); 348 } 349 350 dmaaddr = dmam->dm_segs[0].ds_addr; 351 352 #ifdef ISADMA_DEBUG 353 printf(" dmaaddr 0x%lx\n", dmaaddr); 354 355 __asm(".globl isa_dmastart_aftersync ; isa_dmastart_aftersync:"); 356 #endif 357 358 ids->ids_dmalength[chan] = nbytes; 359 360 _isa_dmamask(ids, chan); 361 ids->ids_dmafinished &= ~(1 << chan); 362 363 if ((chan & 4) == 0) { 364 /* set dma channel mode */ 365 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, DMA1_MODE, 366 ochan | dmamode[flags]); 367 368 /* send start address */ 369 waport = DMA1_CHN(ochan); 370 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 371 dmapageport[0][ochan], (dmaaddr >> 16) & 0xff); 372 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 373 dmaaddr & 0xff); 374 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 375 (dmaaddr >> 8) & 0xff); 376 377 /* send count */ 378 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 379 (--nbytes) & 0xff); 380 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 381 (nbytes >> 8) & 0xff); 382 } else { 383 /* set dma channel mode */ 384 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, DMA2_MODE, 385 ochan | dmamode[flags]); 386 387 /* send start address */ 388 waport = DMA2_CHN(ochan); 389 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 390 dmapageport[1][ochan], (dmaaddr >> 16) & 0xff); 391 dmaaddr >>= 1; 392 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 393 dmaaddr & 0xff); 394 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 395 (dmaaddr >> 8) & 0xff); 396 397 /* send count */ 398 nbytes >>= 1; 399 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 400 (--nbytes) & 0xff); 401 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 402 (nbytes >> 8) & 0xff); 403 } 404 405 _isa_dmaunmask(ids, chan); 406 return (0); 407 408 lose: 409 panic("_isa_dmastart"); 410 } 411 412 void 413 _isa_dmaabort(ids, chan) 414 struct isa_dma_state *ids; 415 int chan; 416 { 417 418 if (chan < 0 || chan > 7) { 419 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 420 panic("_isa_dmaabort"); 421 } 422 423 _isa_dmamask(ids, chan); 424 bus_dmamap_unload(ids->ids_dmat, ids->ids_dmamaps[chan]); 425 ids->ids_dmareads &= ~(1 << chan); 426 } 427 428 bus_size_t 429 _isa_dmacount(ids, chan) 430 struct isa_dma_state *ids; 431 int chan; 432 { 433 int waport; 434 bus_size_t nbytes; 435 int ochan = chan & 3; 436 437 if (chan < 0 || chan > 7) { 438 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 439 panic("isa_dmacount"); 440 } 441 442 _isa_dmamask(ids, chan); 443 444 /* 445 * We have to shift the byte count by 1. If we're in auto-initialize 446 * mode, the count may have wrapped around to the initial value. We 447 * can't use the TC bit to check for this case, so instead we compare 448 * against the original byte count. 449 * If we're not in auto-initialize mode, then the count will wrap to 450 * -1, so we also handle that case. 451 */ 452 if ((chan & 4) == 0) { 453 waport = DMA1_CHN(ochan); 454 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 455 waport + 1) + 1; 456 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 457 waport + 1) << 8; 458 nbytes &= 0xffff; 459 } else { 460 waport = DMA2_CHN(ochan); 461 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 462 waport + 2) + 1; 463 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 464 waport + 2) << 8; 465 nbytes <<= 1; 466 nbytes &= 0x1ffff; 467 } 468 469 if (nbytes == ids->ids_dmalength[chan]) 470 nbytes = 0; 471 472 _isa_dmaunmask(ids, chan); 473 return (nbytes); 474 } 475 476 int 477 _isa_dmafinished(ids, chan) 478 struct isa_dma_state *ids; 479 int chan; 480 { 481 482 if (chan < 0 || chan > 7) { 483 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 484 panic("_isa_dmafinished"); 485 } 486 487 /* check that the terminal count was reached */ 488 if ((chan & 4) == 0) 489 ids->ids_dmafinished |= bus_space_read_1(ids->ids_bst, 490 ids->ids_dma1h, DMA1_SR) & 0x0f; 491 else 492 ids->ids_dmafinished |= (bus_space_read_1(ids->ids_bst, 493 ids->ids_dma2h, DMA2_SR) & 0x0f) << 4; 494 495 return ((ids->ids_dmafinished & (1 << chan)) != 0); 496 } 497 498 void 499 _isa_dmadone(ids, chan) 500 struct isa_dma_state *ids; 501 int chan; 502 { 503 bus_dmamap_t dmam; 504 505 if (chan < 0 || chan > 7) { 506 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 507 panic("_isa_dmadone"); 508 } 509 510 dmam = ids->ids_dmamaps[chan]; 511 512 _isa_dmamask(ids, chan); 513 514 if (_isa_dmafinished(ids, chan) == 0) 515 printf("%s: _isa_dmadone: channel %d not finished\n", 516 ids->ids_dev->dv_xname, chan); 517 518 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 519 (ids->ids_dmareads & (1 << chan)) ? BUS_DMASYNC_POSTREAD : 520 BUS_DMASYNC_POSTWRITE); 521 522 bus_dmamap_unload(ids->ids_dmat, dmam); 523 ids->ids_dmareads &= ~(1 << chan); 524 } 525 526 void 527 _isa_dmafreeze(ids) 528 struct isa_dma_state *ids; 529 { 530 int s; 531 532 s = splhigh(); 533 534 if (ids->ids_frozen == 0) { 535 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 536 DMA1_MASK, 0x0f); 537 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 538 DMA2_MASK, 0x0f); 539 } 540 541 ids->ids_frozen++; 542 if (ids->ids_frozen < 1) 543 panic("_isa_dmafreeze: overflow"); 544 545 splx(s); 546 } 547 548 void 549 _isa_dmathaw(ids) 550 struct isa_dma_state *ids; 551 { 552 int s; 553 554 s = splhigh(); 555 556 ids->ids_frozen--; 557 if (ids->ids_frozen < 0) 558 panic("_isa_dmathaw: underflow"); 559 560 if (ids->ids_frozen == 0) { 561 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 562 DMA1_MASK, ids->ids_masked & 0x0f); 563 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 564 DMA2_MASK, (ids->ids_masked >> 4) & 0x0f); 565 } 566 567 splx(s); 568 } 569 570 int 571 _isa_dmamem_alloc(ids, chan, size, addrp, flags) 572 struct isa_dma_state *ids; 573 int chan; 574 bus_size_t size; 575 bus_addr_t *addrp; 576 int flags; 577 { 578 bus_dma_segment_t seg; 579 int error, boundary, rsegs; 580 581 if (chan < 0 || chan > 7) { 582 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 583 panic("_isa_dmamem_alloc"); 584 } 585 586 boundary = (chan & 4) ? (1 << 17) : (1 << 16); 587 588 size = round_page(size); 589 590 error = bus_dmamem_alloc(ids->ids_dmat, size, NBPG, boundary, 591 &seg, 1, &rsegs, flags); 592 if (error) 593 return (error); 594 595 *addrp = seg.ds_addr; 596 return (0); 597 } 598 599 void 600 _isa_dmamem_free(ids, chan, addr, size) 601 struct isa_dma_state *ids; 602 int chan; 603 bus_addr_t addr; 604 bus_size_t size; 605 { 606 bus_dma_segment_t seg; 607 608 if (chan < 0 || chan > 7) { 609 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 610 panic("_isa_dmamem_free"); 611 } 612 613 seg.ds_addr = addr; 614 seg.ds_len = size; 615 616 bus_dmamem_free(ids->ids_dmat, &seg, 1); 617 } 618 619 int 620 _isa_dmamem_map(ids, chan, addr, size, kvap, flags) 621 struct isa_dma_state *ids; 622 int chan; 623 bus_addr_t addr; 624 bus_size_t size; 625 caddr_t *kvap; 626 int flags; 627 { 628 bus_dma_segment_t seg; 629 630 if (chan < 0 || chan > 7) { 631 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 632 panic("_isa_dmamem_map"); 633 } 634 635 seg.ds_addr = addr; 636 seg.ds_len = size; 637 638 return (bus_dmamem_map(ids->ids_dmat, &seg, 1, size, kvap, flags)); 639 } 640 641 void 642 _isa_dmamem_unmap(ids, chan, kva, size) 643 struct isa_dma_state *ids; 644 int chan; 645 caddr_t kva; 646 size_t size; 647 { 648 649 if (chan < 0 || chan > 7) { 650 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 651 panic("_isa_dmamem_unmap"); 652 } 653 654 bus_dmamem_unmap(ids->ids_dmat, kva, size); 655 } 656 657 int 658 _isa_dmamem_mmap(ids, chan, addr, size, off, prot, flags) 659 struct isa_dma_state *ids; 660 int chan; 661 bus_addr_t addr; 662 bus_size_t size; 663 int off, prot, flags; 664 { 665 bus_dma_segment_t seg; 666 667 if (chan < 0 || chan > 7) { 668 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 669 panic("_isa_dmamem_mmap"); 670 } 671 672 seg.ds_addr = addr; 673 seg.ds_len = size; 674 675 return (bus_dmamem_mmap(ids->ids_dmat, &seg, 1, off, prot, flags)); 676 } 677 678 int 679 _isa_drq_isfree(ids, chan) 680 struct isa_dma_state *ids; 681 int chan; 682 { 683 684 if (chan < 0 || chan > 7) { 685 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 686 panic("_isa_drq_isfree"); 687 } 688 689 return ISA_DMA_DRQ_ISFREE(ids, chan); 690 } 691 692 void * 693 _isa_malloc(ids, chan, size, pool, flags) 694 struct isa_dma_state *ids; 695 int chan; 696 size_t size; 697 int pool; 698 int flags; 699 { 700 bus_addr_t addr; 701 caddr_t kva; 702 int bflags; 703 struct isa_mem *m; 704 705 bflags = flags & M_WAITOK ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT; 706 707 if (_isa_dmamem_alloc(ids, chan, size, &addr, bflags)) 708 return 0; 709 if (_isa_dmamem_map(ids, chan, addr, size, &kva, bflags)) { 710 _isa_dmamem_free(ids, chan, addr, size); 711 return 0; 712 } 713 m = malloc(sizeof(*m), pool, flags); 714 if (m == 0) { 715 _isa_dmamem_unmap(ids, chan, kva, size); 716 _isa_dmamem_free(ids, chan, addr, size); 717 return 0; 718 } 719 m->ids = ids; 720 m->chan = chan; 721 m->size = size; 722 m->addr = addr; 723 m->kva = kva; 724 m->next = isa_mem_head; 725 isa_mem_head = m; 726 return (void *)kva; 727 } 728 729 void 730 _isa_free(addr, pool) 731 void *addr; 732 int pool; 733 { 734 struct isa_mem **mp, *m; 735 caddr_t kva = (caddr_t)addr; 736 737 for(mp = &isa_mem_head; *mp && (*mp)->kva != kva; 738 mp = &(*mp)->next) 739 ; 740 m = *mp; 741 if (!m) { 742 printf("_isa_free: freeing unallocted memory\n"); 743 return; 744 } 745 *mp = m->next; 746 _isa_dmamem_unmap(m->ids, m->chan, kva, m->size); 747 _isa_dmamem_free(m->ids, m->chan, m->addr, m->size); 748 free(m, pool); 749 } 750 751 int 752 _isa_mappage(mem, off, prot) 753 void *mem; 754 int off; 755 int prot; 756 { 757 struct isa_mem *m; 758 759 for(m = isa_mem_head; m && m->kva != (caddr_t)mem; m = m->next) 760 ; 761 if (!m) { 762 printf("_isa_mappage: mapping unallocted memory\n"); 763 return -1; 764 } 765 return _isa_dmamem_mmap(m->ids, m->chan, m->addr, 766 m->size, off, prot, BUS_DMA_WAITOK); 767 } 768
Indexes created Mon Sep 22 21:09:42 GMT 2025