isadma.c revision 1.40
1 /* $NetBSD: isadma.c,v 1.40 1999/02/22 02:32:43 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the ISA on-board DMA controller. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/proc.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 50 #include <vm/vm.h> 51 52 #include <machine/bus.h> 53 54 #include <dev/isa/isareg.h> 55 #include <dev/isa/isavar.h> 56 #include <dev/isa/isadmavar.h> 57 #include <dev/isa/isadmareg.h> 58 59 struct isa_mem *isa_mem_head; 60 61 /* 62 * High byte of DMA address is stored in this DMAPG register for 63 * the Nth DMA channel. 64 */ 65 static int dmapageport[2][4] = { 66 {0x7, 0x3, 0x1, 0x2}, 67 {0xf, 0xb, 0x9, 0xa} 68 }; 69 70 static u_int8_t dmamode[] = { 71 /* write to device/read from device */ 72 DMA37MD_READ | DMA37MD_SINGLE, 73 DMA37MD_WRITE | DMA37MD_SINGLE, 74 75 /* write to device/read from device */ 76 DMA37MD_READ | DMA37MD_DEMAND, 77 DMA37MD_WRITE | DMA37MD_DEMAND, 78 79 /* write to device/read from device - DMAMODE_LOOP */ 80 DMA37MD_READ | DMA37MD_SINGLE | DMA37MD_LOOP, 81 DMA37MD_WRITE | DMA37MD_SINGLE | DMA37MD_LOOP, 82 83 /* write to device/read from device - DMAMODE_LOOPDEMAND */ 84 DMA37MD_READ | DMA37MD_DEMAND | DMA37MD_LOOP, 85 DMA37MD_WRITE | DMA37MD_DEMAND | DMA37MD_LOOP, 86 }; 87 88 static inline void _isa_dmaunmask __P((struct isa_dma_state *, int)); 89 static inline void _isa_dmamask __P((struct isa_dma_state *, int)); 90 91 static inline void 92 _isa_dmaunmask(ids, chan) 93 struct isa_dma_state *ids; 94 int chan; 95 { 96 int ochan = chan & 3; 97 98 ISA_DMA_MASK_CLR(ids, chan); 99 100 /* 101 * If DMA is frozen, don't unmask it now. It will be 102 * unmasked when DMA is thawed again. 103 */ 104 if (ids->ids_frozen) 105 return; 106 107 /* set dma channel mode, and set dma channel mode */ 108 if ((chan & 4) == 0) 109 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 110 DMA1_SMSK, ochan | DMA37SM_CLEAR); 111 else 112 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 113 DMA2_SMSK, ochan | DMA37SM_CLEAR); 114 } 115 116 static inline void 117 _isa_dmamask(ids, chan) 118 struct isa_dma_state *ids; 119 int chan; 120 { 121 int ochan = chan & 3; 122 123 ISA_DMA_MASK_SET(ids, chan); 124 125 /* 126 * XXX Should we avoid masking the channel if DMA is 127 * XXX frozen? It seems like what we're doing should 128 * XXX be safe, and we do need to reset FFC... 129 */ 130 131 /* set dma channel mode, and set dma channel mode */ 132 if ((chan & 4) == 0) { 133 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 134 DMA1_SMSK, ochan | DMA37SM_SET); 135 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 136 DMA1_FFC, 0); 137 } else { 138 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 139 DMA2_SMSK, ochan | DMA37SM_SET); 140 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 141 DMA2_FFC, 0); 142 } 143 } 144 145 /* 146 * _isa_dmainit(): Initialize the isa_dma_state for this chipset. 147 */ 148 void 149 _isa_dmainit(ids, bst, dmat, dev) 150 struct isa_dma_state *ids; 151 bus_space_tag_t bst; 152 bus_dma_tag_t dmat; 153 struct device *dev; 154 { 155 156 ids->ids_dev = dev; 157 158 if (ids->ids_initialized) { 159 /* 160 * Some systems may have e.g. `ofisa' (OpenFirmware 161 * configuration of ISA bus) and a regular `isa'. 162 * We allow both to call the initialization function, 163 * and take the device name from the last caller 164 * (assuming it will be the indirect ISA bus). Since 165 * `ofisa' and `isa' are the same bus with different 166 * configuration mechanisms, the space and dma tags 167 * must be the same! 168 */ 169 if (ids->ids_bst != bst || ids->ids_dmat != dmat) 170 panic("_isa_dmainit: inconsistent ISA tags"); 171 } else { 172 ids->ids_bst = bst; 173 ids->ids_dmat = dmat; 174 175 /* 176 * Map the registers used by the ISA DMA controller. 177 */ 178 if (bus_space_map(ids->ids_bst, IO_DMA1, DMA1_IOSIZE, 0, 179 &ids->ids_dma1h)) 180 panic("_isa_dmainit: unable to map DMA controller #1"); 181 if (bus_space_map(ids->ids_bst, IO_DMA2, DMA2_IOSIZE, 0, 182 &ids->ids_dma2h)) 183 panic("_isa_dmainit: unable to map DMA controller #2"); 184 if (bus_space_map(ids->ids_bst, IO_DMAPG, 0xf, 0, 185 &ids->ids_dmapgh)) 186 panic("_isa_dmainit: unable to map DMA page registers"); 187 188 /* 189 * All 8 DMA channels start out "masked". 190 */ 191 ids->ids_masked = 0xff; 192 193 ids->ids_initialized = 1; 194 195 /* 196 * DRQ 4 is used to chain the two 8237s together; make 197 * sure it's always cascaded, and that it will be unmasked 198 * when DMA is thawed. 199 */ 200 _isa_dmacascade(ids, 4); 201 } 202 } 203 204 /* 205 * _isa_dmacascade(): program 8237 DMA controller channel to accept 206 * external dma control by a board. 207 */ 208 int 209 _isa_dmacascade(ids, chan) 210 struct isa_dma_state *ids; 211 int chan; 212 { 213 int ochan = chan & 3; 214 215 if (chan < 0 || chan > 7) { 216 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 217 return (EINVAL); 218 } 219 220 if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) { 221 printf("%s: DRQ %d is not free\n", ids->ids_dev->dv_xname, 222 chan); 223 return (EAGAIN); 224 } 225 226 ISA_DMA_DRQ_ALLOC(ids, chan); 227 228 /* set dma channel mode, and set dma channel mode */ 229 if ((chan & 4) == 0) 230 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 231 DMA1_MODE, ochan | DMA37MD_CASCADE); 232 else 233 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 234 DMA2_MODE, ochan | DMA37MD_CASCADE); 235 236 _isa_dmaunmask(ids, chan); 237 return (0); 238 } 239 240 int 241 _isa_dmamap_create(ids, chan, size, flags) 242 struct isa_dma_state *ids; 243 int chan; 244 bus_size_t size; 245 int flags; 246 { 247 bus_size_t maxsize; 248 249 if (chan < 0 || chan > 7) { 250 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 251 return (EINVAL); 252 } 253 254 if (chan & 4) 255 maxsize = (1 << 17); 256 else 257 maxsize = (1 << 16); 258 259 if (size > maxsize) 260 return (EINVAL); 261 262 if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) { 263 printf("%s: drq %d is not free\n", ids->ids_dev->dv_xname, 264 chan); 265 return (EAGAIN); 266 } 267 268 ISA_DMA_DRQ_ALLOC(ids, chan); 269 270 return (bus_dmamap_create(ids->ids_dmat, size, 1, size, maxsize, 271 flags, &ids->ids_dmamaps[chan])); 272 } 273 274 void 275 _isa_dmamap_destroy(ids, chan) 276 struct isa_dma_state *ids; 277 int chan; 278 { 279 280 if (chan < 0 || chan > 7) { 281 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 282 goto lose; 283 } 284 285 if (ISA_DMA_DRQ_ISFREE(ids, chan)) { 286 printf("%s: drq %d is already free\n", 287 ids->ids_dev->dv_xname, chan); 288 goto lose; 289 } 290 291 ISA_DMA_DRQ_FREE(ids, chan); 292 293 bus_dmamap_destroy(ids->ids_dmat, ids->ids_dmamaps[chan]); 294 return; 295 296 lose: 297 panic("_isa_dmamap_destroy"); 298 } 299 300 /* 301 * _isa_dmastart(): program 8237 DMA controller channel and set it 302 * in motion. 303 */ 304 int 305 _isa_dmastart(ids, chan, addr, nbytes, p, flags, busdmaflags) 306 struct isa_dma_state *ids; 307 int chan; 308 void *addr; 309 bus_size_t nbytes; 310 struct proc *p; 311 int flags; 312 int busdmaflags; 313 { 314 bus_dmamap_t dmam; 315 bus_addr_t dmaaddr; 316 int waport; 317 int ochan = chan & 3; 318 int error; 319 320 if (chan < 0 || chan > 7) { 321 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 322 goto lose; 323 } 324 325 #ifdef ISADMA_DEBUG 326 printf("_isa_dmastart: drq %d, addr %p, nbytes 0x%lx, p %p, " 327 "flags 0x%x, dmaflags 0x%x\n", 328 chan, addr, nbytes, p, flags, busdmaflags); 329 #endif 330 331 /* Can't specify LOOP and LOOPDEMAND together. */ 332 if ((flags & (DMAMODE_LOOP|DMAMODE_LOOPDEMAND)) == 333 (DMAMODE_LOOP|DMAMODE_LOOPDEMAND)) 334 return (EINVAL); 335 336 if (chan & 4) { 337 if (nbytes > (1 << 17) || nbytes & 1 || (u_long)addr & 1) { 338 printf("%s: drq %d, nbytes 0x%lx, addr %p\n", 339 ids->ids_dev->dv_xname, chan, nbytes, addr); 340 goto lose; 341 } 342 } else { 343 if (nbytes > (1 << 16)) { 344 printf("%s: drq %d, nbytes 0x%lx\n", 345 ids->ids_dev->dv_xname, chan, nbytes); 346 goto lose; 347 } 348 } 349 350 dmam = ids->ids_dmamaps[chan]; 351 if (dmam == NULL) 352 panic("_isa_dmastart: no DMA map for chan %d\n", chan); 353 354 error = bus_dmamap_load(ids->ids_dmat, dmam, addr, nbytes, 355 p, busdmaflags); 356 if (error) 357 return (error); 358 359 #ifdef ISADMA_DEBUG 360 __asm(".globl isa_dmastart_afterload ; isa_dmastart_afterload:"); 361 #endif 362 363 if (flags & DMAMODE_READ) { 364 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 365 BUS_DMASYNC_PREREAD); 366 ids->ids_dmareads |= (1 << chan); 367 } else { 368 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 369 BUS_DMASYNC_PREWRITE); 370 ids->ids_dmareads &= ~(1 << chan); 371 } 372 373 dmaaddr = dmam->dm_segs[0].ds_addr; 374 375 #ifdef ISADMA_DEBUG 376 printf(" dmaaddr 0x%lx\n", dmaaddr); 377 378 __asm(".globl isa_dmastart_aftersync ; isa_dmastart_aftersync:"); 379 #endif 380 381 ids->ids_dmalength[chan] = nbytes; 382 383 _isa_dmamask(ids, chan); 384 ids->ids_dmafinished &= ~(1 << chan); 385 386 if ((chan & 4) == 0) { 387 /* set dma channel mode */ 388 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, DMA1_MODE, 389 ochan | dmamode[flags]); 390 391 /* send start address */ 392 waport = DMA1_CHN(ochan); 393 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 394 dmapageport[0][ochan], (dmaaddr >> 16) & 0xff); 395 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 396 dmaaddr & 0xff); 397 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 398 (dmaaddr >> 8) & 0xff); 399 400 /* send count */ 401 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 402 (--nbytes) & 0xff); 403 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 404 (nbytes >> 8) & 0xff); 405 } else { 406 /* set dma channel mode */ 407 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, DMA2_MODE, 408 ochan | dmamode[flags]); 409 410 /* send start address */ 411 waport = DMA2_CHN(ochan); 412 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 413 dmapageport[1][ochan], (dmaaddr >> 16) & 0xff); 414 dmaaddr >>= 1; 415 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 416 dmaaddr & 0xff); 417 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 418 (dmaaddr >> 8) & 0xff); 419 420 /* send count */ 421 nbytes >>= 1; 422 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 423 (--nbytes) & 0xff); 424 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 425 (nbytes >> 8) & 0xff); 426 } 427 428 _isa_dmaunmask(ids, chan); 429 return (0); 430 431 lose: 432 panic("_isa_dmastart"); 433 } 434 435 void 436 _isa_dmaabort(ids, chan) 437 struct isa_dma_state *ids; 438 int chan; 439 { 440 441 if (chan < 0 || chan > 7) { 442 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 443 panic("_isa_dmaabort"); 444 } 445 446 _isa_dmamask(ids, chan); 447 bus_dmamap_unload(ids->ids_dmat, ids->ids_dmamaps[chan]); 448 ids->ids_dmareads &= ~(1 << chan); 449 } 450 451 bus_size_t 452 _isa_dmacount(ids, chan) 453 struct isa_dma_state *ids; 454 int chan; 455 { 456 int waport; 457 bus_size_t nbytes; 458 int ochan = chan & 3; 459 460 if (chan < 0 || chan > 7) { 461 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 462 panic("isa_dmacount"); 463 } 464 465 _isa_dmamask(ids, chan); 466 467 /* 468 * We have to shift the byte count by 1. If we're in auto-initialize 469 * mode, the count may have wrapped around to the initial value. We 470 * can't use the TC bit to check for this case, so instead we compare 471 * against the original byte count. 472 * If we're not in auto-initialize mode, then the count will wrap to 473 * -1, so we also handle that case. 474 */ 475 if ((chan & 4) == 0) { 476 waport = DMA1_CHN(ochan); 477 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 478 waport + 1) + 1; 479 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 480 waport + 1) << 8; 481 nbytes &= 0xffff; 482 } else { 483 waport = DMA2_CHN(ochan); 484 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 485 waport + 2) + 1; 486 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 487 waport + 2) << 8; 488 nbytes <<= 1; 489 nbytes &= 0x1ffff; 490 } 491 492 if (nbytes == ids->ids_dmalength[chan]) 493 nbytes = 0; 494 495 _isa_dmaunmask(ids, chan); 496 return (nbytes); 497 } 498 499 int 500 _isa_dmafinished(ids, chan) 501 struct isa_dma_state *ids; 502 int chan; 503 { 504 505 if (chan < 0 || chan > 7) { 506 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 507 panic("_isa_dmafinished"); 508 } 509 510 /* check that the terminal count was reached */ 511 if ((chan & 4) == 0) 512 ids->ids_dmafinished |= bus_space_read_1(ids->ids_bst, 513 ids->ids_dma1h, DMA1_SR) & 0x0f; 514 else 515 ids->ids_dmafinished |= (bus_space_read_1(ids->ids_bst, 516 ids->ids_dma2h, DMA2_SR) & 0x0f) << 4; 517 518 return ((ids->ids_dmafinished & (1 << chan)) != 0); 519 } 520 521 void 522 _isa_dmadone(ids, chan) 523 struct isa_dma_state *ids; 524 int chan; 525 { 526 bus_dmamap_t dmam; 527 528 if (chan < 0 || chan > 7) { 529 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 530 panic("_isa_dmadone"); 531 } 532 533 dmam = ids->ids_dmamaps[chan]; 534 535 _isa_dmamask(ids, chan); 536 537 if (_isa_dmafinished(ids, chan) == 0) 538 printf("%s: _isa_dmadone: channel %d not finished\n", 539 ids->ids_dev->dv_xname, chan); 540 541 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 542 (ids->ids_dmareads & (1 << chan)) ? BUS_DMASYNC_POSTREAD : 543 BUS_DMASYNC_POSTWRITE); 544 545 bus_dmamap_unload(ids->ids_dmat, dmam); 546 ids->ids_dmareads &= ~(1 << chan); 547 } 548 549 void 550 _isa_dmafreeze(ids) 551 struct isa_dma_state *ids; 552 { 553 int s; 554 555 s = splhigh(); 556 557 if (ids->ids_frozen == 0) { 558 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 559 DMA1_MASK, 0x0f); 560 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 561 DMA2_MASK, 0x0f); 562 } 563 564 ids->ids_frozen++; 565 if (ids->ids_frozen < 1) 566 panic("_isa_dmafreeze: overflow"); 567 568 splx(s); 569 } 570 571 void 572 _isa_dmathaw(ids) 573 struct isa_dma_state *ids; 574 { 575 int s; 576 577 s = splhigh(); 578 579 ids->ids_frozen--; 580 if (ids->ids_frozen < 0) 581 panic("_isa_dmathaw: underflow"); 582 583 if (ids->ids_frozen == 0) { 584 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 585 DMA1_MASK, ids->ids_masked & 0x0f); 586 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 587 DMA2_MASK, (ids->ids_masked >> 4) & 0x0f); 588 } 589 590 splx(s); 591 } 592 593 int 594 _isa_dmamem_alloc(ids, chan, size, addrp, flags) 595 struct isa_dma_state *ids; 596 int chan; 597 bus_size_t size; 598 bus_addr_t *addrp; 599 int flags; 600 { 601 bus_dma_segment_t seg; 602 int error, boundary, rsegs; 603 604 if (chan < 0 || chan > 7) { 605 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 606 panic("_isa_dmamem_alloc"); 607 } 608 609 boundary = (chan & 4) ? (1 << 17) : (1 << 16); 610 611 size = round_page(size); 612 613 error = bus_dmamem_alloc(ids->ids_dmat, size, NBPG, boundary, 614 &seg, 1, &rsegs, flags); 615 if (error) 616 return (error); 617 618 *addrp = seg.ds_addr; 619 return (0); 620 } 621 622 void 623 _isa_dmamem_free(ids, chan, addr, size) 624 struct isa_dma_state *ids; 625 int chan; 626 bus_addr_t addr; 627 bus_size_t size; 628 { 629 bus_dma_segment_t seg; 630 631 if (chan < 0 || chan > 7) { 632 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 633 panic("_isa_dmamem_free"); 634 } 635 636 seg.ds_addr = addr; 637 seg.ds_len = size; 638 639 bus_dmamem_free(ids->ids_dmat, &seg, 1); 640 } 641 642 int 643 _isa_dmamem_map(ids, chan, addr, size, kvap, flags) 644 struct isa_dma_state *ids; 645 int chan; 646 bus_addr_t addr; 647 bus_size_t size; 648 caddr_t *kvap; 649 int flags; 650 { 651 bus_dma_segment_t seg; 652 653 if (chan < 0 || chan > 7) { 654 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 655 panic("_isa_dmamem_map"); 656 } 657 658 seg.ds_addr = addr; 659 seg.ds_len = size; 660 661 return (bus_dmamem_map(ids->ids_dmat, &seg, 1, size, kvap, flags)); 662 } 663 664 void 665 _isa_dmamem_unmap(ids, chan, kva, size) 666 struct isa_dma_state *ids; 667 int chan; 668 caddr_t kva; 669 size_t size; 670 { 671 672 if (chan < 0 || chan > 7) { 673 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 674 panic("_isa_dmamem_unmap"); 675 } 676 677 bus_dmamem_unmap(ids->ids_dmat, kva, size); 678 } 679 680 int 681 _isa_dmamem_mmap(ids, chan, addr, size, off, prot, flags) 682 struct isa_dma_state *ids; 683 int chan; 684 bus_addr_t addr; 685 bus_size_t size; 686 int off, prot, flags; 687 { 688 bus_dma_segment_t seg; 689 690 if (chan < 0 || chan > 7) { 691 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 692 panic("_isa_dmamem_mmap"); 693 } 694 695 if (off < 0) 696 return (-1); 697 698 seg.ds_addr = addr; 699 seg.ds_len = size; 700 701 return (bus_dmamem_mmap(ids->ids_dmat, &seg, 1, off, prot, flags)); 702 } 703 704 int 705 _isa_drq_isfree(ids, chan) 706 struct isa_dma_state *ids; 707 int chan; 708 { 709 710 if (chan < 0 || chan > 7) { 711 printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan); 712 panic("_isa_drq_isfree"); 713 } 714 715 return ISA_DMA_DRQ_ISFREE(ids, chan); 716 } 717 718 void * 719 _isa_malloc(ids, chan, size, pool, flags) 720 struct isa_dma_state *ids; 721 int chan; 722 size_t size; 723 int pool; 724 int flags; 725 { 726 bus_addr_t addr; 727 caddr_t kva; 728 int bflags; 729 struct isa_mem *m; 730 731 bflags = flags & M_WAITOK ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT; 732 733 if (_isa_dmamem_alloc(ids, chan, size, &addr, bflags)) 734 return 0; 735 if (_isa_dmamem_map(ids, chan, addr, size, &kva, bflags)) { 736 _isa_dmamem_free(ids, chan, addr, size); 737 return 0; 738 } 739 m = malloc(sizeof(*m), pool, flags); 740 if (m == 0) { 741 _isa_dmamem_unmap(ids, chan, kva, size); 742 _isa_dmamem_free(ids, chan, addr, size); 743 return 0; 744 } 745 m->ids = ids; 746 m->chan = chan; 747 m->size = size; 748 m->addr = addr; 749 m->kva = kva; 750 m->next = isa_mem_head; 751 isa_mem_head = m; 752 return (void *)kva; 753 } 754 755 void 756 _isa_free(addr, pool) 757 void *addr; 758 int pool; 759 { 760 struct isa_mem **mp, *m; 761 caddr_t kva = (caddr_t)addr; 762 763 for(mp = &isa_mem_head; *mp && (*mp)->kva != kva; 764 mp = &(*mp)->next) 765 ; 766 m = *mp; 767 if (!m) { 768 printf("_isa_free: freeing unallocted memory\n"); 769 return; 770 } 771 *mp = m->next; 772 _isa_dmamem_unmap(m->ids, m->chan, kva, m->size); 773 _isa_dmamem_free(m->ids, m->chan, m->addr, m->size); 774 free(m, pool); 775 } 776 777 int 778 _isa_mappage(mem, off, prot) 779 void *mem; 780 int off; 781 int prot; 782 { 783 struct isa_mem *m; 784 785 for(m = isa_mem_head; m && m->kva != (caddr_t)mem; m = m->next) 786 ; 787 if (!m) { 788 printf("_isa_mappage: mapping unallocted memory\n"); 789 return -1; 790 } 791 return _isa_dmamem_mmap(m->ids, m->chan, m->addr, 792 m->size, off, prot, BUS_DMA_WAITOK); 793 } 794
Indexes created Thu Sep 25 08:09:54 GMT 2025