isadma.c revision 1.64
1 /* $NetBSD: isadma.c,v 1.64 2010/04/19 18:24:26 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the ISA on-board DMA controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: isadma.c,v 1.64 2010/04/19 18:24:26 dyoung Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/proc.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #include <sys/bus.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <dev/isa/isareg.h> 51 #include <dev/isa/isavar.h> 52 #include <dev/isa/isadmavar.h> 53 #include <dev/isa/isadmareg.h> 54 55 struct isa_mem *isa_mem_head; 56 57 /* 58 * High byte of DMA address is stored in this DMAPG register for 59 * the Nth DMA channel. 60 */ 61 static int dmapageport[2][4] = { 62 {0x7, 0x3, 0x1, 0x2}, 63 {0xf, 0xb, 0x9, 0xa} 64 }; 65 66 static u_int8_t dmamode[] = { 67 /* write to device/read from device */ 68 DMA37MD_READ | DMA37MD_SINGLE, 69 DMA37MD_WRITE | DMA37MD_SINGLE, 70 71 /* write to device/read from device */ 72 DMA37MD_READ | DMA37MD_DEMAND, 73 DMA37MD_WRITE | DMA37MD_DEMAND, 74 75 /* write to device/read from device - DMAMODE_LOOP */ 76 DMA37MD_READ | DMA37MD_SINGLE | DMA37MD_LOOP, 77 DMA37MD_WRITE | DMA37MD_SINGLE | DMA37MD_LOOP, 78 79 /* write to device/read from device - DMAMODE_LOOPDEMAND */ 80 DMA37MD_READ | DMA37MD_DEMAND | DMA37MD_LOOP, 81 DMA37MD_WRITE | DMA37MD_DEMAND | DMA37MD_LOOP, 82 }; 83 84 static inline void _isa_dmaunmask(struct isa_dma_state *, int); 85 static inline void _isa_dmamask(struct isa_dma_state *, int); 86 87 static inline void 88 _isa_dmaunmask(struct isa_dma_state *ids, int chan) 89 { 90 int ochan = chan & 3; 91 92 ISA_DMA_MASK_CLR(ids, chan); 93 94 /* 95 * If DMA is frozen, don't unmask it now. It will be 96 * unmasked when DMA is thawed again. 97 */ 98 if (ids->ids_frozen) 99 return; 100 101 /* set dma channel mode, and set dma channel mode */ 102 if ((chan & 4) == 0) 103 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 104 DMA1_SMSK, ochan | DMA37SM_CLEAR); 105 else 106 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 107 DMA2_SMSK, ochan | DMA37SM_CLEAR); 108 } 109 110 static inline void 111 _isa_dmamask(struct isa_dma_state *ids, int chan) 112 { 113 int ochan = chan & 3; 114 115 ISA_DMA_MASK_SET(ids, chan); 116 117 /* 118 * XXX Should we avoid masking the channel if DMA is 119 * XXX frozen? It seems like what we're doing should 120 * XXX be safe, and we do need to reset FFC... 121 */ 122 123 /* set dma channel mode, and set dma channel mode */ 124 if ((chan & 4) == 0) { 125 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 126 DMA1_SMSK, ochan | DMA37SM_SET); 127 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 128 DMA1_FFC, 0); 129 } else { 130 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 131 DMA2_SMSK, ochan | DMA37SM_SET); 132 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 133 DMA2_FFC, 0); 134 } 135 } 136 137 /* 138 * _isa_dmainit(): Initialize the isa_dma_state for this chipset. 139 */ 140 void 141 _isa_dmainit(struct isa_dma_state *ids, bus_space_tag_t bst, bus_dma_tag_t dmat, device_t dev) 142 { 143 int chan; 144 145 ids->ids_dev = dev; 146 147 if (ids->ids_initialized) { 148 /* 149 * Some systems may have e.g. `ofisa' (OpenFirmware 150 * configuration of ISA bus) and a regular `isa'. 151 * We allow both to call the initialization function, 152 * and take the device name from the last caller 153 * (assuming it will be the indirect ISA bus). Since 154 * `ofisa' and `isa' are the same bus with different 155 * configuration mechanisms, the space and dma tags 156 * must be the same! 157 */ 158 if (!bus_space_is_equal(ids->ids_bst, bst) || 159 ids->ids_dmat != dmat) 160 panic("_isa_dmainit: inconsistent ISA tags"); 161 } else { 162 ids->ids_bst = bst; 163 ids->ids_dmat = dmat; 164 165 /* 166 * Map the registers used by the ISA DMA controller. 167 */ 168 if (bus_space_map(ids->ids_bst, IO_DMA1, DMA1_IOSIZE, 0, 169 &ids->ids_dma1h)) 170 panic("_isa_dmainit: unable to map DMA controller #1"); 171 if (bus_space_map(ids->ids_bst, IO_DMA2, DMA2_IOSIZE, 0, 172 &ids->ids_dma2h)) 173 panic("_isa_dmainit: unable to map DMA controller #2"); 174 if (bus_space_map(ids->ids_bst, IO_DMAPG, 0xf, 0, 175 &ids->ids_dmapgh)) 176 panic("_isa_dmainit: unable to map DMA page registers"); 177 178 /* 179 * All 8 DMA channels start out "masked". 180 */ 181 ids->ids_masked = 0xff; 182 183 /* 184 * Initialize the max transfer size for each channel, if 185 * it is not initialized already (i.e. by a bus-dependent 186 * front-end). 187 */ 188 for (chan = 0; chan < 8; chan++) { 189 if (ids->ids_maxsize[chan] == 0) 190 ids->ids_maxsize[chan] = 191 ISA_DMA_MAXSIZE_DEFAULT(chan); 192 } 193 194 ids->ids_initialized = 1; 195 196 /* 197 * DRQ 4 is used to chain the two 8237s together; make 198 * sure it's always cascaded, and that it will be unmasked 199 * when DMA is thawed. 200 */ 201 _isa_dmacascade(ids, 4); 202 } 203 } 204 205 void 206 _isa_dmadestroy(struct isa_dma_state *ids) 207 { 208 if (!ids->ids_initialized) 209 return; 210 211 _isa_dmacascade_stop(ids, 4); 212 213 /* 214 * Unmap the registers used by the ISA DMA controller. 215 */ 216 bus_space_unmap(ids->ids_bst, ids->ids_dmapgh, 0xf); 217 bus_space_unmap(ids->ids_bst, ids->ids_dma2h, DMA2_IOSIZE); 218 bus_space_unmap(ids->ids_bst, ids->ids_dma1h, DMA1_IOSIZE); 219 220 ids->ids_initialized = 0; 221 } 222 223 /* 224 * _isa_dmacascade(): program 8237 DMA controller channel to accept 225 * external dma control by a board. 226 */ 227 int 228 _isa_dmacascade(struct isa_dma_state *ids, int chan) 229 { 230 int ochan = chan & 3; 231 232 if (chan < 0 || chan > 7) { 233 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 234 return (EINVAL); 235 } 236 237 if (!ISA_DMA_DRQ_ISFREE(ids, chan)) { 238 printf("%s: DRQ %d is not free\n", device_xname(ids->ids_dev), 239 chan); 240 return (EAGAIN); 241 } 242 243 ISA_DMA_DRQ_ALLOC(ids, chan); 244 245 /* set dma channel mode, and set dma channel mode */ 246 if ((chan & 4) == 0) 247 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 248 DMA1_MODE, ochan | DMA37MD_CASCADE); 249 else 250 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 251 DMA2_MODE, ochan | DMA37MD_CASCADE); 252 253 _isa_dmaunmask(ids, chan); 254 return (0); 255 } 256 257 /* 258 * _isa_dmacascade_stop(): turn off cascading on the 8237 DMA controller channel 259 * external dma control by a board. 260 */ 261 int 262 _isa_dmacascade_stop(struct isa_dma_state *ids, int chan) 263 { 264 if (chan < 0 || chan > 7) { 265 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 266 return EINVAL; 267 } 268 269 if (ISA_DMA_DRQ_ISFREE(ids, chan)) 270 return 0; 271 272 _isa_dmamask(ids, chan); 273 274 ISA_DMA_DRQ_FREE(ids, chan); 275 276 return 0; 277 } 278 279 int 280 _isa_drq_alloc(struct isa_dma_state *ids, int chan) 281 { 282 if (!ISA_DMA_DRQ_ISFREE(ids, chan)) 283 return EBUSY; 284 ISA_DMA_DRQ_ALLOC(ids, chan); 285 return 0; 286 } 287 288 int 289 _isa_drq_free(struct isa_dma_state *ids, int chan) 290 { 291 if (ISA_DMA_DRQ_ISFREE(ids, chan)) 292 return EINVAL; 293 ISA_DMA_DRQ_FREE(ids, chan); 294 return 0; 295 } 296 297 bus_size_t 298 _isa_dmamaxsize(struct isa_dma_state *ids, int chan) 299 { 300 301 if (chan < 0 || chan > 7) { 302 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 303 return (0); 304 } 305 306 return (ids->ids_maxsize[chan]); 307 } 308 309 int 310 _isa_dmamap_create(struct isa_dma_state *ids, int chan, bus_size_t size, int flags) 311 { 312 int error; 313 314 if (chan < 0 || chan > 7) { 315 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 316 return (EINVAL); 317 } 318 319 if (size > ids->ids_maxsize[chan]) 320 return (EINVAL); 321 322 error = bus_dmamap_create(ids->ids_dmat, size, 1, size, 323 ids->ids_maxsize[chan], flags, &ids->ids_dmamaps[chan]); 324 325 return (error); 326 } 327 328 void 329 _isa_dmamap_destroy(struct isa_dma_state *ids, int chan) 330 { 331 332 if (chan < 0 || chan > 7) { 333 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 334 goto lose; 335 } 336 337 bus_dmamap_destroy(ids->ids_dmat, ids->ids_dmamaps[chan]); 338 return; 339 340 lose: 341 panic("_isa_dmamap_destroy"); 342 } 343 344 /* 345 * _isa_dmastart(): program 8237 DMA controller channel and set it 346 * in motion. 347 */ 348 int 349 _isa_dmastart(struct isa_dma_state *ids, int chan, void *addr, bus_size_t nbytes, struct proc *p, int flags, int busdmaflags) 350 { 351 bus_dmamap_t dmam; 352 bus_addr_t dmaaddr; 353 int waport; 354 int ochan = chan & 3; 355 int error; 356 357 if (chan < 0 || chan > 7) { 358 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 359 goto lose; 360 } 361 362 #ifdef ISADMA_DEBUG 363 printf("_isa_dmastart: drq %d, addr %p, nbytes 0x%lx, p %p, " 364 "flags 0x%x, dmaflags 0x%x\n", 365 chan, addr, (u_long)nbytes, p, flags, busdmaflags); 366 #endif 367 368 if (ISA_DMA_DRQ_ISFREE(ids, chan)) { 369 printf("%s: dma start on free channel %d\n", 370 device_xname(ids->ids_dev), chan); 371 goto lose; 372 } 373 374 if (chan & 4) { 375 if (nbytes > (1 << 17) || nbytes & 1 || (u_long)addr & 1) { 376 printf("%s: drq %d, nbytes 0x%lx, addr %p\n", 377 device_xname(ids->ids_dev), chan, 378 (unsigned long) nbytes, addr); 379 goto lose; 380 } 381 } else { 382 if (nbytes > (1 << 16)) { 383 printf("%s: drq %d, nbytes 0x%lx\n", 384 device_xname(ids->ids_dev), chan, 385 (unsigned long) nbytes); 386 goto lose; 387 } 388 } 389 390 dmam = ids->ids_dmamaps[chan]; 391 if (dmam == NULL) 392 panic("_isa_dmastart: no DMA map for chan %d", chan); 393 394 error = bus_dmamap_load(ids->ids_dmat, dmam, addr, nbytes, 395 p, busdmaflags | 396 ((flags & DMAMODE_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 397 if (error) 398 return (error); 399 400 #ifdef ISADMA_DEBUG 401 __asm(".globl isa_dmastart_afterload ; isa_dmastart_afterload:"); 402 #endif 403 404 if (flags & DMAMODE_READ) { 405 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 406 BUS_DMASYNC_PREREAD); 407 ids->ids_dmareads |= (1 << chan); 408 } else { 409 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 410 BUS_DMASYNC_PREWRITE); 411 ids->ids_dmareads &= ~(1 << chan); 412 } 413 414 dmaaddr = dmam->dm_segs[0].ds_addr; 415 416 #ifdef ISADMA_DEBUG 417 printf(" dmaaddr 0x%lx\n", dmaaddr); 418 419 __asm(".globl isa_dmastart_aftersync ; isa_dmastart_aftersync:"); 420 #endif 421 422 ids->ids_dmalength[chan] = nbytes; 423 424 _isa_dmamask(ids, chan); 425 ids->ids_dmafinished &= ~(1 << chan); 426 427 if ((chan & 4) == 0) { 428 /* set dma channel mode */ 429 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, DMA1_MODE, 430 ochan | dmamode[flags]); 431 432 /* send start address */ 433 waport = DMA1_CHN(ochan); 434 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 435 dmapageport[0][ochan], (dmaaddr >> 16) & 0xff); 436 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 437 dmaaddr & 0xff); 438 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport, 439 (dmaaddr >> 8) & 0xff); 440 441 /* send count */ 442 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 443 (--nbytes) & 0xff); 444 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1, 445 (nbytes >> 8) & 0xff); 446 } else { 447 /* set dma channel mode */ 448 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, DMA2_MODE, 449 ochan | dmamode[flags]); 450 451 /* send start address */ 452 waport = DMA2_CHN(ochan); 453 bus_space_write_1(ids->ids_bst, ids->ids_dmapgh, 454 dmapageport[1][ochan], (dmaaddr >> 16) & 0xff); 455 dmaaddr >>= 1; 456 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 457 dmaaddr & 0xff); 458 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport, 459 (dmaaddr >> 8) & 0xff); 460 461 /* send count */ 462 nbytes >>= 1; 463 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 464 (--nbytes) & 0xff); 465 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2, 466 (nbytes >> 8) & 0xff); 467 } 468 469 _isa_dmaunmask(ids, chan); 470 return (0); 471 472 lose: 473 panic("_isa_dmastart"); 474 } 475 476 void 477 _isa_dmaabort(struct isa_dma_state *ids, int chan) 478 { 479 480 if (chan < 0 || chan > 7) { 481 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 482 panic("_isa_dmaabort"); 483 } 484 485 _isa_dmamask(ids, chan); 486 bus_dmamap_unload(ids->ids_dmat, ids->ids_dmamaps[chan]); 487 ids->ids_dmareads &= ~(1 << chan); 488 } 489 490 bus_size_t 491 _isa_dmacount(struct isa_dma_state *ids, int chan) 492 { 493 int waport; 494 bus_size_t nbytes; 495 int ochan = chan & 3; 496 497 if (chan < 0 || chan > 7) { 498 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 499 panic("isa_dmacount"); 500 } 501 502 _isa_dmamask(ids, chan); 503 504 /* 505 * We have to shift the byte count by 1. If we're in auto-initialize 506 * mode, the count may have wrapped around to the initial value. We 507 * can't use the TC bit to check for this case, so instead we compare 508 * against the original byte count. 509 * If we're not in auto-initialize mode, then the count will wrap to 510 * -1, so we also handle that case. 511 */ 512 if ((chan & 4) == 0) { 513 waport = DMA1_CHN(ochan); 514 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 515 waport + 1) + 1; 516 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma1h, 517 waport + 1) << 8; 518 nbytes &= 0xffff; 519 } else { 520 waport = DMA2_CHN(ochan); 521 nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 522 waport + 2) + 1; 523 nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma2h, 524 waport + 2) << 8; 525 nbytes <<= 1; 526 nbytes &= 0x1ffff; 527 } 528 529 if (nbytes == ids->ids_dmalength[chan]) 530 nbytes = 0; 531 532 _isa_dmaunmask(ids, chan); 533 return (nbytes); 534 } 535 536 int 537 _isa_dmafinished(struct isa_dma_state *ids, int chan) 538 { 539 540 if (chan < 0 || chan > 7) { 541 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 542 panic("_isa_dmafinished"); 543 } 544 545 /* check that the terminal count was reached */ 546 if ((chan & 4) == 0) 547 ids->ids_dmafinished |= bus_space_read_1(ids->ids_bst, 548 ids->ids_dma1h, DMA1_SR) & 0x0f; 549 else 550 ids->ids_dmafinished |= (bus_space_read_1(ids->ids_bst, 551 ids->ids_dma2h, DMA2_SR) & 0x0f) << 4; 552 553 return ((ids->ids_dmafinished & (1 << chan)) != 0); 554 } 555 556 void 557 _isa_dmadone(struct isa_dma_state *ids, int chan) 558 { 559 bus_dmamap_t dmam; 560 561 if (chan < 0 || chan > 7) { 562 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 563 panic("_isa_dmadone"); 564 } 565 566 dmam = ids->ids_dmamaps[chan]; 567 568 _isa_dmamask(ids, chan); 569 570 if (_isa_dmafinished(ids, chan) == 0) 571 printf("%s: _isa_dmadone: channel %d not finished\n", 572 device_xname(ids->ids_dev), chan); 573 574 bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize, 575 (ids->ids_dmareads & (1 << chan)) ? BUS_DMASYNC_POSTREAD : 576 BUS_DMASYNC_POSTWRITE); 577 578 bus_dmamap_unload(ids->ids_dmat, dmam); 579 ids->ids_dmareads &= ~(1 << chan); 580 } 581 582 void 583 _isa_dmafreeze(struct isa_dma_state *ids) 584 { 585 int s; 586 587 s = splhigh(); 588 589 if (ids->ids_frozen == 0) { 590 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 591 DMA1_MASK, 0x0f); 592 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 593 DMA2_MASK, 0x0f); 594 } 595 596 ids->ids_frozen++; 597 if (ids->ids_frozen < 1) 598 panic("_isa_dmafreeze: overflow"); 599 600 splx(s); 601 } 602 603 void 604 _isa_dmathaw(struct isa_dma_state *ids) 605 { 606 int s; 607 608 s = splhigh(); 609 610 ids->ids_frozen--; 611 if (ids->ids_frozen < 0) 612 panic("_isa_dmathaw: underflow"); 613 614 if (ids->ids_frozen == 0) { 615 bus_space_write_1(ids->ids_bst, ids->ids_dma1h, 616 DMA1_MASK, ids->ids_masked & 0x0f); 617 bus_space_write_1(ids->ids_bst, ids->ids_dma2h, 618 DMA2_MASK, (ids->ids_masked >> 4) & 0x0f); 619 } 620 621 splx(s); 622 } 623 624 int 625 _isa_dmamem_alloc(struct isa_dma_state *ids, int chan, bus_size_t size, bus_addr_t *addrp, int flags) 626 { 627 bus_dma_segment_t seg; 628 int error, boundary, rsegs; 629 630 if (chan < 0 || chan > 7) { 631 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 632 panic("_isa_dmamem_alloc"); 633 } 634 635 boundary = (chan & 4) ? (1 << 17) : (1 << 16); 636 637 size = round_page(size); 638 639 error = bus_dmamem_alloc(ids->ids_dmat, size, PAGE_SIZE, boundary, 640 &seg, 1, &rsegs, flags); 641 if (error) 642 return (error); 643 644 *addrp = seg.ds_addr; 645 return (0); 646 } 647 648 void 649 _isa_dmamem_free(struct isa_dma_state *ids, int chan, bus_addr_t addr, bus_size_t size) 650 { 651 bus_dma_segment_t seg; 652 653 if (chan < 0 || chan > 7) { 654 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 655 panic("_isa_dmamem_free"); 656 } 657 658 seg.ds_addr = addr; 659 seg.ds_len = size; 660 661 bus_dmamem_free(ids->ids_dmat, &seg, 1); 662 } 663 664 int 665 _isa_dmamem_map(struct isa_dma_state *ids, int chan, bus_addr_t addr, bus_size_t size, void **kvap, int flags) 666 { 667 bus_dma_segment_t seg; 668 669 if (chan < 0 || chan > 7) { 670 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 671 panic("_isa_dmamem_map"); 672 } 673 674 seg.ds_addr = addr; 675 seg.ds_len = size; 676 677 return (bus_dmamem_map(ids->ids_dmat, &seg, 1, size, kvap, flags)); 678 } 679 680 void 681 _isa_dmamem_unmap(struct isa_dma_state *ids, int chan, void *kva, size_t size) 682 { 683 684 if (chan < 0 || chan > 7) { 685 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 686 panic("_isa_dmamem_unmap"); 687 } 688 689 bus_dmamem_unmap(ids->ids_dmat, kva, size); 690 } 691 692 paddr_t 693 _isa_dmamem_mmap(struct isa_dma_state *ids, int chan, bus_addr_t addr, bus_size_t size, off_t off, int prot, int flags) 694 { 695 bus_dma_segment_t seg; 696 697 if (chan < 0 || chan > 7) { 698 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 699 panic("_isa_dmamem_mmap"); 700 } 701 702 if (off < 0) 703 return (-1); 704 705 seg.ds_addr = addr; 706 seg.ds_len = size; 707 708 return (bus_dmamem_mmap(ids->ids_dmat, &seg, 1, off, prot, flags)); 709 } 710 711 int 712 _isa_drq_isfree(struct isa_dma_state *ids, int chan) 713 { 714 715 if (chan < 0 || chan > 7) { 716 printf("%s: bogus drq %d\n", device_xname(ids->ids_dev), chan); 717 panic("_isa_drq_isfree"); 718 } 719 720 return ISA_DMA_DRQ_ISFREE(ids, chan); 721 } 722 723 void * 724 _isa_malloc(struct isa_dma_state *ids, int chan, size_t size, struct malloc_type *pool, int flags) 725 { 726 bus_addr_t addr; 727 void *kva; 728 int bflags; 729 struct isa_mem *m; 730 731 bflags = flags & M_WAITOK ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT; 732 733 if (_isa_dmamem_alloc(ids, chan, size, &addr, bflags)) 734 return 0; 735 if (_isa_dmamem_map(ids, chan, addr, size, &kva, bflags)) { 736 _isa_dmamem_free(ids, chan, addr, size); 737 return 0; 738 } 739 m = malloc(sizeof(*m), pool, flags); 740 if (m == 0) { 741 _isa_dmamem_unmap(ids, chan, kva, size); 742 _isa_dmamem_free(ids, chan, addr, size); 743 return 0; 744 } 745 m->ids = ids; 746 m->chan = chan; 747 m->size = size; 748 m->addr = addr; 749 m->kva = kva; 750 m->next = isa_mem_head; 751 isa_mem_head = m; 752 return (void *)kva; 753 } 754 755 void 756 _isa_free(void *addr, struct malloc_type *pool) 757 { 758 struct isa_mem **mp, *m; 759 void *kva = (void *)addr; 760 761 for(mp = &isa_mem_head; *mp && (*mp)->kva != kva; 762 mp = &(*mp)->next) 763 ; 764 m = *mp; 765 if (!m) { 766 printf("_isa_free: freeing unallocted memory\n"); 767 return; 768 } 769 *mp = m->next; 770 _isa_dmamem_unmap(m->ids, m->chan, kva, m->size); 771 _isa_dmamem_free(m->ids, m->chan, m->addr, m->size); 772 free(m, pool); 773 } 774 775 paddr_t 776 _isa_mappage(void *mem, off_t off, int prot) 777 { 778 struct isa_mem *m; 779 780 for(m = isa_mem_head; m && m->kva != (void *)mem; m = m->next) 781 ; 782 if (!m) { 783 printf("_isa_mappage: mapping unallocted memory\n"); 784 return -1; 785 } 786 return _isa_dmamem_mmap(m->ids, m->chan, m->addr, 787 m->size, off, prot, BUS_DMA_WAITOK); 788 } 789
Indexes created Wed Sep 24 15:09:51 GMT 2025